2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
278 if ((size & 15) || size > MBOX_LEN)
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
285 if (adap->pdev->error_state != pci_channel_io_normal)
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
304 for (i = 0; i < timeout; i += ms) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
349 static int t4_edc_err_read(struct adapter *adap, int idx)
351 u32 edc_ecc_err_addr_reg;
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
410 /* Argument sanity checks ...
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
424 /* Offset into the region of memory which is being accessed
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
462 pos = addr & ~(mem_aperture-1);
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
478 * A note on Endianness issues:
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
488 * Then a read of the adapter memory via the PCI-E Memory Window
493 * [ b3 | b2 | b1 | b0 ]
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
498 * ( ..., b0, b1, b2, b3, ... )
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
503 * ( ..., b3, b2, b1, b0, ... )
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
525 if (offset == mem_aperture) {
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
558 for (i = resid; i < 4; i++)
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
575 u32 val, ldst_addrspace;
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
580 struct fw_ldst_cmd ldst_cmd;
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
606 t4_hw_pci_read_cfg4(adap, reg, &val);
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
619 if (is_t4(adap->params.chip)) {
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
633 adap->t4_bar0 = bar0;
635 ret = bar0 + memwin_base;
637 /* For T5, only relative offset inside the PCIe BAR is passed */
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
668 * Returns the size of the chip's BAR0 register space.
670 unsigned int t4_get_regs_len(struct adapter *adapter)
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
674 switch (chip_version) {
676 return T4_REGMAP_SIZE;
680 return T5_REGMAP_SIZE;
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
689 * t4_get_regs - read chip registers into provided buffer
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
700 static const unsigned int t4_reg_ranges[] = {
1158 static const unsigned int t5_reg_ranges[] = {
1933 static const unsigned int t6_reg_ranges[] = {
2510 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511 const unsigned int *reg_ranges;
2512 int reg_ranges_size, range;
2513 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2515 /* Select the right set of register ranges to dump depending on the
2516 * adapter chip type.
2518 switch (chip_version) {
2520 reg_ranges = t4_reg_ranges;
2521 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2525 reg_ranges = t5_reg_ranges;
2526 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2530 reg_ranges = t6_reg_ranges;
2531 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2535 dev_err(adap->pdev_dev,
2536 "Unsupported chip version %d\n", chip_version);
2540 /* Clear the register buffer and insert the appropriate register
2541 * values selected by the above register ranges.
2543 memset(buf, 0, buf_size);
2544 for (range = 0; range < reg_ranges_size; range += 2) {
2545 unsigned int reg = reg_ranges[range];
2546 unsigned int last_reg = reg_ranges[range + 1];
2547 u32 *bufp = (u32 *)((char *)buf + reg);
2549 /* Iterate across the register range filling in the register
2550 * buffer but don't write past the end of the register buffer.
2552 while (reg <= last_reg && bufp < buf_end) {
2553 *bufp++ = t4_read_reg(adap, reg);
2559 #define EEPROM_STAT_ADDR 0x7bfc
2560 #define VPD_BASE 0x400
2561 #define VPD_BASE_OLD 0
2562 #define VPD_LEN 1024
2563 #define CHELSIO_VPD_UNIQUE_ID 0x82
2566 * t4_seeprom_wp - enable/disable EEPROM write protection
2567 * @adapter: the adapter
2568 * @enable: whether to enable or disable write protection
2570 * Enables or disables write protection on the serial EEPROM.
2572 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2574 unsigned int v = enable ? 0xc : 0;
2575 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2576 return ret < 0 ? ret : 0;
2580 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2581 * @adapter: adapter to read
2582 * @p: where to store the parameters
2584 * Reads card parameters stored in VPD EEPROM.
2586 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2588 int i, ret = 0, addr;
2591 unsigned int vpdr_len, kw_offset, id_len;
2593 vpd = vmalloc(VPD_LEN);
2597 /* Card information normally starts at VPD_BASE but early cards had
2600 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2604 /* The VPD shall have a unique identifier specified by the PCI SIG.
2605 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2606 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2607 * is expected to automatically put this entry at the
2608 * beginning of the VPD.
2610 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2612 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2616 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2617 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2622 id_len = pci_vpd_lrdt_size(vpd);
2623 if (id_len > ID_LEN)
2626 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2628 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2633 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2634 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2635 if (vpdr_len + kw_offset > VPD_LEN) {
2636 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2641 #define FIND_VPD_KW(var, name) do { \
2642 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2644 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2648 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2651 FIND_VPD_KW(i, "RV");
2652 for (csum = 0; i >= 0; i--)
2656 dev_err(adapter->pdev_dev,
2657 "corrupted VPD EEPROM, actual csum %u\n", csum);
2662 FIND_VPD_KW(ec, "EC");
2663 FIND_VPD_KW(sn, "SN");
2664 FIND_VPD_KW(pn, "PN");
2665 FIND_VPD_KW(na, "NA");
2668 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2670 memcpy(p->ec, vpd + ec, EC_LEN);
2672 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2673 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2675 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2676 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2678 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2679 strim((char *)p->na);
2687 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2688 * @adapter: adapter to read
2689 * @p: where to store the parameters
2691 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2692 * Clock. This can only be called after a connection to the firmware
2695 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2697 u32 cclk_param, cclk_val;
2700 /* Grab the raw VPD parameters.
2702 ret = t4_get_raw_vpd_params(adapter, p);
2706 /* Ask firmware for the Core Clock since it knows how to translate the
2707 * Reference Clock ('V2') VPD field into a Core Clock value ...
2709 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2710 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2711 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2712 1, &cclk_param, &cclk_val);
2721 /* serial flash and firmware constants */
2723 SF_ATTEMPTS = 10, /* max retries for SF operations */
2725 /* flash command opcodes */
2726 SF_PROG_PAGE = 2, /* program page */
2727 SF_WR_DISABLE = 4, /* disable writes */
2728 SF_RD_STATUS = 5, /* read status register */
2729 SF_WR_ENABLE = 6, /* enable writes */
2730 SF_RD_DATA_FAST = 0xb, /* read flash */
2731 SF_RD_ID = 0x9f, /* read ID */
2732 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2734 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2738 * sf1_read - read data from the serial flash
2739 * @adapter: the adapter
2740 * @byte_cnt: number of bytes to read
2741 * @cont: whether another operation will be chained
2742 * @lock: whether to lock SF for PL access only
2743 * @valp: where to store the read data
2745 * Reads up to 4 bytes of data from the serial flash. The location of
2746 * the read needs to be specified prior to calling this by issuing the
2747 * appropriate commands to the serial flash.
2749 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2750 int lock, u32 *valp)
2754 if (!byte_cnt || byte_cnt > 4)
2756 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2758 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2759 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2760 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2762 *valp = t4_read_reg(adapter, SF_DATA_A);
2767 * sf1_write - write data to the serial flash
2768 * @adapter: the adapter
2769 * @byte_cnt: number of bytes to write
2770 * @cont: whether another operation will be chained
2771 * @lock: whether to lock SF for PL access only
2772 * @val: value to write
2774 * Writes up to 4 bytes of data to the serial flash. The location of
2775 * the write needs to be specified prior to calling this by issuing the
2776 * appropriate commands to the serial flash.
2778 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2781 if (!byte_cnt || byte_cnt > 4)
2783 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2785 t4_write_reg(adapter, SF_DATA_A, val);
2786 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2787 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2788 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2792 * flash_wait_op - wait for a flash operation to complete
2793 * @adapter: the adapter
2794 * @attempts: max number of polls of the status register
2795 * @delay: delay between polls in ms
2797 * Wait for a flash operation to complete by polling the status register.
2799 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2805 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2806 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2810 if (--attempts == 0)
2818 * t4_read_flash - read words from serial flash
2819 * @adapter: the adapter
2820 * @addr: the start address for the read
2821 * @nwords: how many 32-bit words to read
2822 * @data: where to store the read data
2823 * @byte_oriented: whether to store data as bytes or as words
2825 * Read the specified number of 32-bit words from the serial flash.
2826 * If @byte_oriented is set the read data is stored as a byte array
2827 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2828 * natural endianness.
2830 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2831 unsigned int nwords, u32 *data, int byte_oriented)
2835 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2838 addr = swab32(addr) | SF_RD_DATA_FAST;
2840 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2841 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2844 for ( ; nwords; nwords--, data++) {
2845 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2847 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2851 *data = (__force __u32)(cpu_to_be32(*data));
2857 * t4_write_flash - write up to a page of data to the serial flash
2858 * @adapter: the adapter
2859 * @addr: the start address to write
2860 * @n: length of data to write in bytes
2861 * @data: the data to write
2863 * Writes up to a page of data (256 bytes) to the serial flash starting
2864 * at the given address. All the data must be written to the same page.
2866 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2867 unsigned int n, const u8 *data)
2871 unsigned int i, c, left, val, offset = addr & 0xff;
2873 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2876 val = swab32(addr) | SF_PROG_PAGE;
2878 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2879 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2882 for (left = n; left; left -= c) {
2884 for (val = 0, i = 0; i < c; ++i)
2885 val = (val << 8) + *data++;
2887 ret = sf1_write(adapter, c, c != left, 1, val);
2891 ret = flash_wait_op(adapter, 8, 1);
2895 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2897 /* Read the page to verify the write succeeded */
2898 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2902 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2903 dev_err(adapter->pdev_dev,
2904 "failed to correctly write the flash page at %#x\n",
2911 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2916 * t4_get_fw_version - read the firmware version
2917 * @adapter: the adapter
2918 * @vers: where to place the version
2920 * Reads the FW version from flash.
2922 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2924 return t4_read_flash(adapter, FLASH_FW_START +
2925 offsetof(struct fw_hdr, fw_ver), 1,
2930 * t4_get_tp_version - read the TP microcode version
2931 * @adapter: the adapter
2932 * @vers: where to place the version
2934 * Reads the TP microcode version from flash.
2936 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2938 return t4_read_flash(adapter, FLASH_FW_START +
2939 offsetof(struct fw_hdr, tp_microcode_ver),
2944 * t4_get_exprom_version - return the Expansion ROM version (if any)
2945 * @adapter: the adapter
2946 * @vers: where to place the version
2948 * Reads the Expansion ROM header from FLASH and returns the version
2949 * number (if present) through the @vers return value pointer. We return
2950 * this in the Firmware Version Format since it's convenient. Return
2951 * 0 on success, -ENOENT if no Expansion ROM is present.
2953 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2955 struct exprom_header {
2956 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2957 unsigned char hdr_ver[4]; /* Expansion ROM version */
2959 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2963 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2964 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2969 hdr = (struct exprom_header *)exprom_header_buf;
2970 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2973 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2974 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2975 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2976 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2981 * t4_check_fw_version - check if the FW is supported with this driver
2982 * @adap: the adapter
2984 * Checks if an adapter's FW is compatible with the driver. Returns 0
2985 * if there's exact match, a negative error if the version could not be
2986 * read or there's a major version mismatch
2988 int t4_check_fw_version(struct adapter *adap)
2990 int i, ret, major, minor, micro;
2991 int exp_major, exp_minor, exp_micro;
2992 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2994 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
2995 /* Try multiple times before returning error */
2996 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
2997 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3002 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3003 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3004 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3006 switch (chip_version) {
3008 exp_major = T4FW_MIN_VERSION_MAJOR;
3009 exp_minor = T4FW_MIN_VERSION_MINOR;
3010 exp_micro = T4FW_MIN_VERSION_MICRO;
3013 exp_major = T5FW_MIN_VERSION_MAJOR;
3014 exp_minor = T5FW_MIN_VERSION_MINOR;
3015 exp_micro = T5FW_MIN_VERSION_MICRO;
3018 exp_major = T6FW_MIN_VERSION_MAJOR;
3019 exp_minor = T6FW_MIN_VERSION_MINOR;
3020 exp_micro = T6FW_MIN_VERSION_MICRO;
3023 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3028 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3029 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3030 dev_err(adap->pdev_dev,
3031 "Card has firmware version %u.%u.%u, minimum "
3032 "supported firmware is %u.%u.%u.\n", major, minor,
3033 micro, exp_major, exp_minor, exp_micro);
3039 /* Is the given firmware API compatible with the one the driver was compiled
3042 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3045 /* short circuit if it's the exact same firmware version */
3046 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3049 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3050 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3051 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3058 /* The firmware in the filesystem is usable, but should it be installed?
3059 * This routine explains itself in detail if it indicates the filesystem
3060 * firmware should be installed.
3062 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3067 if (!card_fw_usable) {
3068 reason = "incompatible or unusable";
3073 reason = "older than the version supported with this driver";
3080 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3081 "installing firmware %u.%u.%u.%u on card.\n",
3082 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3083 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3084 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3085 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3090 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3091 const u8 *fw_data, unsigned int fw_size,
3092 struct fw_hdr *card_fw, enum dev_state state,
3095 int ret, card_fw_usable, fs_fw_usable;
3096 const struct fw_hdr *fs_fw;
3097 const struct fw_hdr *drv_fw;
3099 drv_fw = &fw_info->fw_hdr;
3101 /* Read the header of the firmware on the card */
3102 ret = -t4_read_flash(adap, FLASH_FW_START,
3103 sizeof(*card_fw) / sizeof(uint32_t),
3104 (uint32_t *)card_fw, 1);
3106 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3108 dev_err(adap->pdev_dev,
3109 "Unable to read card's firmware header: %d\n", ret);
3113 if (fw_data != NULL) {
3114 fs_fw = (const void *)fw_data;
3115 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3121 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3122 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3123 /* Common case: the firmware on the card is an exact match and
3124 * the filesystem one is an exact match too, or the filesystem
3125 * one is absent/incompatible.
3127 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3128 should_install_fs_fw(adap, card_fw_usable,
3129 be32_to_cpu(fs_fw->fw_ver),
3130 be32_to_cpu(card_fw->fw_ver))) {
3131 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3134 dev_err(adap->pdev_dev,
3135 "failed to install firmware: %d\n", ret);
3139 /* Installed successfully, update the cached header too. */
3142 *reset = 0; /* already reset as part of load_fw */
3145 if (!card_fw_usable) {
3148 d = be32_to_cpu(drv_fw->fw_ver);
3149 c = be32_to_cpu(card_fw->fw_ver);
3150 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3152 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3154 "driver compiled with %d.%d.%d.%d, "
3155 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3157 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3158 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3159 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3160 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3161 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3162 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3167 /* We're using whatever's on the card and it's known to be good. */
3168 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3169 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3176 * t4_flash_erase_sectors - erase a range of flash sectors
3177 * @adapter: the adapter
3178 * @start: the first sector to erase
3179 * @end: the last sector to erase
3181 * Erases the sectors in the given inclusive range.
3183 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3187 if (end >= adapter->params.sf_nsec)
3190 while (start <= end) {
3191 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3192 (ret = sf1_write(adapter, 4, 0, 1,
3193 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3194 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3195 dev_err(adapter->pdev_dev,
3196 "erase of flash sector %d failed, error %d\n",
3202 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3207 * t4_flash_cfg_addr - return the address of the flash configuration file
3208 * @adapter: the adapter
3210 * Return the address within the flash where the Firmware Configuration
3213 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3215 if (adapter->params.sf_size == 0x100000)
3216 return FLASH_FPGA_CFG_START;
3218 return FLASH_CFG_START;
3221 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3222 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3223 * and emit an error message for mismatched firmware to save our caller the
3226 static bool t4_fw_matches_chip(const struct adapter *adap,
3227 const struct fw_hdr *hdr)
3229 /* The expression below will return FALSE for any unsupported adapter
3230 * which will keep us "honest" in the future ...
3232 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3233 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3234 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3237 dev_err(adap->pdev_dev,
3238 "FW image (%d) is not suitable for this adapter (%d)\n",
3239 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3244 * t4_load_fw - download firmware
3245 * @adap: the adapter
3246 * @fw_data: the firmware image to write
3249 * Write the supplied firmware image to the card's serial flash.
3251 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3256 u8 first_page[SF_PAGE_SIZE];
3257 const __be32 *p = (const __be32 *)fw_data;
3258 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3259 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3260 unsigned int fw_img_start = adap->params.sf_fw_start;
3261 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3264 dev_err(adap->pdev_dev, "FW image has no data\n");
3268 dev_err(adap->pdev_dev,
3269 "FW image size not multiple of 512 bytes\n");
3272 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3273 dev_err(adap->pdev_dev,
3274 "FW image size differs from size in FW header\n");
3277 if (size > FW_MAX_SIZE) {
3278 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3282 if (!t4_fw_matches_chip(adap, hdr))
3285 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3286 csum += be32_to_cpu(p[i]);
3288 if (csum != 0xffffffff) {
3289 dev_err(adap->pdev_dev,
3290 "corrupted firmware image, checksum %#x\n", csum);
3294 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3295 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3300 * We write the correct version at the end so the driver can see a bad
3301 * version if the FW write fails. Start by writing a copy of the
3302 * first page with a bad version.
3304 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3305 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3306 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3310 addr = fw_img_start;
3311 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3312 addr += SF_PAGE_SIZE;
3313 fw_data += SF_PAGE_SIZE;
3314 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3319 ret = t4_write_flash(adap,
3320 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3321 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3324 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3327 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3332 * t4_phy_fw_ver - return current PHY firmware version
3333 * @adap: the adapter
3334 * @phy_fw_ver: return value buffer for PHY firmware version
3336 * Returns the current version of external PHY firmware on the
3339 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3344 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3345 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3346 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3347 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3348 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3357 * t4_load_phy_fw - download port PHY firmware
3358 * @adap: the adapter
3359 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3360 * @win_lock: the lock to use to guard the memory copy
3361 * @phy_fw_version: function to check PHY firmware versions
3362 * @phy_fw_data: the PHY firmware image to write
3363 * @phy_fw_size: image size
3365 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3366 * @phy_fw_version is supplied, then it will be used to determine if
3367 * it's necessary to perform the transfer by comparing the version
3368 * of any existing adapter PHY firmware with that of the passed in
3369 * PHY firmware image. If @win_lock is non-NULL then it will be used
3370 * around the call to t4_memory_rw() which transfers the PHY firmware
3373 * A negative error number will be returned if an error occurs. If
3374 * version number support is available and there's no need to upgrade
3375 * the firmware, 0 will be returned. If firmware is successfully
3376 * transferred to the adapter, 1 will be retured.
3378 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3379 * a result, a RESET of the adapter would cause that RAM to lose its
3380 * contents. Thus, loading PHY firmware on such adapters must happen
3381 * after any FW_RESET_CMDs ...
3383 int t4_load_phy_fw(struct adapter *adap,
3384 int win, spinlock_t *win_lock,
3385 int (*phy_fw_version)(const u8 *, size_t),
3386 const u8 *phy_fw_data, size_t phy_fw_size)
3388 unsigned long mtype = 0, maddr = 0;
3390 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3393 /* If we have version number support, then check to see if the adapter
3394 * already has up-to-date PHY firmware loaded.
3396 if (phy_fw_version) {
3397 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3398 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3402 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3403 CH_WARN(adap, "PHY Firmware already up-to-date, "
3404 "version %#x\n", cur_phy_fw_ver);
3409 /* Ask the firmware where it wants us to copy the PHY firmware image.
3410 * The size of the file requires a special version of the READ coommand
3411 * which will pass the file size via the values field in PARAMS_CMD and
3412 * retrieve the return value from firmware and place it in the same
3415 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3416 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3417 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3418 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3420 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3425 maddr = (val & 0xff) << 16;
3427 /* Copy the supplied PHY Firmware image to the adapter memory location
3428 * allocated by the adapter firmware.
3431 spin_lock_bh(win_lock);
3432 ret = t4_memory_rw(adap, win, mtype, maddr,
3433 phy_fw_size, (__be32 *)phy_fw_data,
3436 spin_unlock_bh(win_lock);
3440 /* Tell the firmware that the PHY firmware image has been written to
3441 * RAM and it can now start copying it over to the PHYs. The chip
3442 * firmware will RESET the affected PHYs as part of this operation
3443 * leaving them running the new PHY firmware image.
3445 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3446 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3447 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3448 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3449 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3450 ¶m, &val, 30000);
3452 /* If we have version number support, then check to see that the new
3453 * firmware got loaded properly.
3455 if (phy_fw_version) {
3456 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3460 if (cur_phy_fw_ver != new_phy_fw_vers) {
3461 CH_WARN(adap, "PHY Firmware did not update: "
3462 "version on adapter %#x, "
3463 "version flashed %#x\n",
3464 cur_phy_fw_ver, new_phy_fw_vers);
3473 * t4_fwcache - firmware cache operation
3474 * @adap: the adapter
3475 * @op : the operation (flush or flush and invalidate)
3477 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3479 struct fw_params_cmd c;
3481 memset(&c, 0, sizeof(c));
3483 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3484 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3485 FW_PARAMS_CMD_PFN_V(adap->pf) |
3486 FW_PARAMS_CMD_VFN_V(0));
3487 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3489 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3490 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3491 c.param[0].val = (__force __be32)op;
3493 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3496 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3497 unsigned int *pif_req_wrptr,
3498 unsigned int *pif_rsp_wrptr)
3501 u32 cfg, val, req, rsp;
3503 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3504 if (cfg & LADBGEN_F)
3505 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3507 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3508 req = POLADBGWRPTR_G(val);
3509 rsp = PILADBGWRPTR_G(val);
3511 *pif_req_wrptr = req;
3513 *pif_rsp_wrptr = rsp;
3515 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3516 for (j = 0; j < 6; j++) {
3517 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3518 PILADBGRDPTR_V(rsp));
3519 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3520 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3524 req = (req + 2) & POLADBGRDPTR_M;
3525 rsp = (rsp + 2) & PILADBGRDPTR_M;
3527 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3530 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3535 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3536 if (cfg & LADBGEN_F)
3537 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3539 for (i = 0; i < CIM_MALA_SIZE; i++) {
3540 for (j = 0; j < 5; j++) {
3542 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3543 PILADBGRDPTR_V(idx));
3544 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3545 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3548 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3551 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3555 for (i = 0; i < 8; i++) {
3556 u32 *p = la_buf + i;
3558 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3559 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3560 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3561 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3562 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3566 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3567 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3571 * t4_link_l1cfg - apply link configuration to MAC/PHY
3572 * @phy: the PHY to setup
3573 * @mac: the MAC to setup
3574 * @lc: the requested link configuration
3576 * Set up a port's MAC and PHY according to a desired link configuration.
3577 * - If the PHY can auto-negotiate first decide what to advertise, then
3578 * enable/disable auto-negotiation as desired, and reset.
3579 * - If the PHY does not auto-negotiate just reset it.
3580 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3581 * otherwise do it later based on the outcome of auto-negotiation.
3583 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3584 struct link_config *lc)
3586 struct fw_port_cmd c;
3587 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3590 if (lc->requested_fc & PAUSE_RX)
3591 fc |= FW_PORT_CAP_FC_RX;
3592 if (lc->requested_fc & PAUSE_TX)
3593 fc |= FW_PORT_CAP_FC_TX;
3595 memset(&c, 0, sizeof(c));
3596 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3597 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3598 FW_PORT_CMD_PORTID_V(port));
3600 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3603 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3604 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3606 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3607 } else if (lc->autoneg == AUTONEG_DISABLE) {
3608 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3609 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3611 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3613 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3617 * t4_restart_aneg - restart autonegotiation
3618 * @adap: the adapter
3619 * @mbox: mbox to use for the FW command
3620 * @port: the port id
3622 * Restarts autonegotiation for the selected port.
3624 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3626 struct fw_port_cmd c;
3628 memset(&c, 0, sizeof(c));
3629 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3630 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3631 FW_PORT_CMD_PORTID_V(port));
3633 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3635 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3636 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3639 typedef void (*int_handler_t)(struct adapter *adap);
3642 unsigned int mask; /* bits to check in interrupt status */
3643 const char *msg; /* message to print or NULL */
3644 short stat_idx; /* stat counter to increment or -1 */
3645 unsigned short fatal; /* whether the condition reported is fatal */
3646 int_handler_t int_handler; /* platform-specific int handler */
3650 * t4_handle_intr_status - table driven interrupt handler
3651 * @adapter: the adapter that generated the interrupt
3652 * @reg: the interrupt status register to process
3653 * @acts: table of interrupt actions
3655 * A table driven interrupt handler that applies a set of masks to an
3656 * interrupt status word and performs the corresponding actions if the
3657 * interrupts described by the mask have occurred. The actions include
3658 * optionally emitting a warning or alert message. The table is terminated
3659 * by an entry specifying mask 0. Returns the number of fatal interrupt
3662 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3663 const struct intr_info *acts)
3666 unsigned int mask = 0;
3667 unsigned int status = t4_read_reg(adapter, reg);
3669 for ( ; acts->mask; ++acts) {
3670 if (!(status & acts->mask))
3674 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3675 status & acts->mask);
3676 } else if (acts->msg && printk_ratelimit())
3677 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3678 status & acts->mask);
3679 if (acts->int_handler)
3680 acts->int_handler(adapter);
3684 if (status) /* clear processed interrupts */
3685 t4_write_reg(adapter, reg, status);
3690 * Interrupt handler for the PCIE module.
3692 static void pcie_intr_handler(struct adapter *adapter)
3694 static const struct intr_info sysbus_intr_info[] = {
3695 { RNPP_F, "RXNP array parity error", -1, 1 },
3696 { RPCP_F, "RXPC array parity error", -1, 1 },
3697 { RCIP_F, "RXCIF array parity error", -1, 1 },
3698 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3699 { RFTP_F, "RXFT array parity error", -1, 1 },
3702 static const struct intr_info pcie_port_intr_info[] = {
3703 { TPCP_F, "TXPC array parity error", -1, 1 },
3704 { TNPP_F, "TXNP array parity error", -1, 1 },
3705 { TFTP_F, "TXFT array parity error", -1, 1 },
3706 { TCAP_F, "TXCA array parity error", -1, 1 },
3707 { TCIP_F, "TXCIF array parity error", -1, 1 },
3708 { RCAP_F, "RXCA array parity error", -1, 1 },
3709 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3710 { RDPE_F, "Rx data parity error", -1, 1 },
3711 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3714 static const struct intr_info pcie_intr_info[] = {
3715 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3716 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3717 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3718 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3719 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3720 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3721 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3722 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3723 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3724 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3725 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3726 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3727 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3728 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3729 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3730 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3731 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3732 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3733 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3734 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3735 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3736 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3737 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3738 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3739 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3740 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3741 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3742 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3743 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3744 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3749 static struct intr_info t5_pcie_intr_info[] = {
3750 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3752 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3753 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3754 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3755 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3756 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3757 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3758 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3760 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3762 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3763 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3764 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3765 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3766 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3768 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3769 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3770 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3771 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3772 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3773 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3774 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3775 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3776 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3777 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3778 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3780 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3782 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3783 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3784 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3785 { READRSPERR_F, "Outbound read error", -1, 0 },
3791 if (is_t4(adapter->params.chip))
3792 fat = t4_handle_intr_status(adapter,
3793 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3795 t4_handle_intr_status(adapter,
3796 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3797 pcie_port_intr_info) +
3798 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3801 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3805 t4_fatal_err(adapter);
3809 * TP interrupt handler.
3811 static void tp_intr_handler(struct adapter *adapter)
3813 static const struct intr_info tp_intr_info[] = {
3814 { 0x3fffffff, "TP parity error", -1, 1 },
3815 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3819 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3820 t4_fatal_err(adapter);
3824 * SGE interrupt handler.
3826 static void sge_intr_handler(struct adapter *adapter)
3831 static const struct intr_info sge_intr_info[] = {
3832 { ERR_CPL_EXCEED_IQE_SIZE_F,
3833 "SGE received CPL exceeding IQE size", -1, 1 },
3834 { ERR_INVALID_CIDX_INC_F,
3835 "SGE GTS CIDX increment too large", -1, 0 },
3836 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3837 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3838 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3839 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3840 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3842 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3844 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3846 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3848 { ERR_ING_CTXT_PRIO_F,
3849 "SGE too many priority ingress contexts", -1, 0 },
3850 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3851 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3855 static struct intr_info t4t5_sge_intr_info[] = {
3856 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3857 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3858 { ERR_EGR_CTXT_PRIO_F,
3859 "SGE too many priority egress contexts", -1, 0 },
3863 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3864 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3866 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3867 (unsigned long long)v);
3868 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3869 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3872 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3873 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3874 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3875 t4t5_sge_intr_info);
3877 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3878 if (err & ERROR_QID_VALID_F) {
3879 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3881 if (err & UNCAPTURED_ERROR_F)
3882 dev_err(adapter->pdev_dev,
3883 "SGE UNCAPTURED_ERROR set (clearing)\n");
3884 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3885 UNCAPTURED_ERROR_F);
3889 t4_fatal_err(adapter);
3892 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3893 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3894 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3895 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3898 * CIM interrupt handler.
3900 static void cim_intr_handler(struct adapter *adapter)
3902 static const struct intr_info cim_intr_info[] = {
3903 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3904 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3905 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3906 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3907 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3908 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3909 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3912 static const struct intr_info cim_upintr_info[] = {
3913 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3914 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3915 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3916 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3917 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3918 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3919 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3920 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3921 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3922 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3923 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3924 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3925 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3926 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3927 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3928 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3929 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3930 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3931 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3932 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3933 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3934 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3935 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3936 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3937 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3938 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3939 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3940 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3946 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3947 t4_report_fw_error(adapter);
3949 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3951 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3954 t4_fatal_err(adapter);
3958 * ULP RX interrupt handler.
3960 static void ulprx_intr_handler(struct adapter *adapter)
3962 static const struct intr_info ulprx_intr_info[] = {
3963 { 0x1800000, "ULPRX context error", -1, 1 },
3964 { 0x7fffff, "ULPRX parity error", -1, 1 },
3968 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3969 t4_fatal_err(adapter);
3973 * ULP TX interrupt handler.
3975 static void ulptx_intr_handler(struct adapter *adapter)
3977 static const struct intr_info ulptx_intr_info[] = {
3978 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3980 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3982 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3984 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3986 { 0xfffffff, "ULPTX parity error", -1, 1 },
3990 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
3991 t4_fatal_err(adapter);
3995 * PM TX interrupt handler.
3997 static void pmtx_intr_handler(struct adapter *adapter)
3999 static const struct intr_info pmtx_intr_info[] = {
4000 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4001 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4002 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4003 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4004 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4005 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4006 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4008 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4009 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4013 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4014 t4_fatal_err(adapter);
4018 * PM RX interrupt handler.
4020 static void pmrx_intr_handler(struct adapter *adapter)
4022 static const struct intr_info pmrx_intr_info[] = {
4023 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4024 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4025 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4026 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4028 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4029 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4033 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4034 t4_fatal_err(adapter);
4038 * CPL switch interrupt handler.
4040 static void cplsw_intr_handler(struct adapter *adapter)
4042 static const struct intr_info cplsw_intr_info[] = {
4043 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4044 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4045 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4046 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4047 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4048 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4052 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4053 t4_fatal_err(adapter);
4057 * LE interrupt handler.
4059 static void le_intr_handler(struct adapter *adap)
4061 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4062 static const struct intr_info le_intr_info[] = {
4063 { LIPMISS_F, "LE LIP miss", -1, 0 },
4064 { LIP0_F, "LE 0 LIP error", -1, 0 },
4065 { PARITYERR_F, "LE parity error", -1, 1 },
4066 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4067 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4071 static struct intr_info t6_le_intr_info[] = {
4072 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4073 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4074 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4075 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4076 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4080 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4081 (chip <= CHELSIO_T5) ?
4082 le_intr_info : t6_le_intr_info))
4087 * MPS interrupt handler.
4089 static void mps_intr_handler(struct adapter *adapter)
4091 static const struct intr_info mps_rx_intr_info[] = {
4092 { 0xffffff, "MPS Rx parity error", -1, 1 },
4095 static const struct intr_info mps_tx_intr_info[] = {
4096 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4097 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4098 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4100 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4102 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4103 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4104 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4107 static const struct intr_info mps_trc_intr_info[] = {
4108 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4109 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4111 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4114 static const struct intr_info mps_stat_sram_intr_info[] = {
4115 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4118 static const struct intr_info mps_stat_tx_intr_info[] = {
4119 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4122 static const struct intr_info mps_stat_rx_intr_info[] = {
4123 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4126 static const struct intr_info mps_cls_intr_info[] = {
4127 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4128 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4129 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4135 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4137 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4139 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4140 mps_trc_intr_info) +
4141 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4142 mps_stat_sram_intr_info) +
4143 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4144 mps_stat_tx_intr_info) +
4145 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4146 mps_stat_rx_intr_info) +
4147 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4150 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4151 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4153 t4_fatal_err(adapter);
4156 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4160 * EDC/MC interrupt handler.
4162 static void mem_intr_handler(struct adapter *adapter, int idx)
4164 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4166 unsigned int addr, cnt_addr, v;
4168 if (idx <= MEM_EDC1) {
4169 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4170 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4171 } else if (idx == MEM_MC) {
4172 if (is_t4(adapter->params.chip)) {
4173 addr = MC_INT_CAUSE_A;
4174 cnt_addr = MC_ECC_STATUS_A;
4176 addr = MC_P_INT_CAUSE_A;
4177 cnt_addr = MC_P_ECC_STATUS_A;
4180 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4181 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4184 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4185 if (v & PERR_INT_CAUSE_F)
4186 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4188 if (v & ECC_CE_INT_CAUSE_F) {
4189 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4191 t4_edc_err_read(adapter, idx);
4193 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4194 if (printk_ratelimit())
4195 dev_warn(adapter->pdev_dev,
4196 "%u %s correctable ECC data error%s\n",
4197 cnt, name[idx], cnt > 1 ? "s" : "");
4199 if (v & ECC_UE_INT_CAUSE_F)
4200 dev_alert(adapter->pdev_dev,
4201 "%s uncorrectable ECC data error\n", name[idx]);
4203 t4_write_reg(adapter, addr, v);
4204 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4205 t4_fatal_err(adapter);
4209 * MA interrupt handler.
4211 static void ma_intr_handler(struct adapter *adap)
4213 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4215 if (status & MEM_PERR_INT_CAUSE_F) {
4216 dev_alert(adap->pdev_dev,
4217 "MA parity error, parity status %#x\n",
4218 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4219 if (is_t5(adap->params.chip))
4220 dev_alert(adap->pdev_dev,
4221 "MA parity error, parity status %#x\n",
4223 MA_PARITY_ERROR_STATUS2_A));
4225 if (status & MEM_WRAP_INT_CAUSE_F) {
4226 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4227 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4228 "client %u to address %#x\n",
4229 MEM_WRAP_CLIENT_NUM_G(v),
4230 MEM_WRAP_ADDRESS_G(v) << 4);
4232 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4237 * SMB interrupt handler.
4239 static void smb_intr_handler(struct adapter *adap)
4241 static const struct intr_info smb_intr_info[] = {
4242 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4243 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4244 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4248 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4253 * NC-SI interrupt handler.
4255 static void ncsi_intr_handler(struct adapter *adap)
4257 static const struct intr_info ncsi_intr_info[] = {
4258 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4259 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4260 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4261 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4265 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4270 * XGMAC interrupt handler.
4272 static void xgmac_intr_handler(struct adapter *adap, int port)
4274 u32 v, int_cause_reg;
4276 if (is_t4(adap->params.chip))
4277 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4279 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4281 v = t4_read_reg(adap, int_cause_reg);
4283 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4287 if (v & TXFIFO_PRTY_ERR_F)
4288 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4290 if (v & RXFIFO_PRTY_ERR_F)
4291 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4293 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4298 * PL interrupt handler.
4300 static void pl_intr_handler(struct adapter *adap)
4302 static const struct intr_info pl_intr_info[] = {
4303 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4304 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4308 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4312 #define PF_INTR_MASK (PFSW_F)
4313 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4314 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4315 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4318 * t4_slow_intr_handler - control path interrupt handler
4319 * @adapter: the adapter
4321 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4322 * The designation 'slow' is because it involves register reads, while
4323 * data interrupts typically don't involve any MMIOs.
4325 int t4_slow_intr_handler(struct adapter *adapter)
4327 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4329 if (!(cause & GLBL_INTR_MASK))
4332 cim_intr_handler(adapter);
4334 mps_intr_handler(adapter);
4336 ncsi_intr_handler(adapter);
4338 pl_intr_handler(adapter);
4340 smb_intr_handler(adapter);
4341 if (cause & XGMAC0_F)
4342 xgmac_intr_handler(adapter, 0);
4343 if (cause & XGMAC1_F)
4344 xgmac_intr_handler(adapter, 1);
4345 if (cause & XGMAC_KR0_F)
4346 xgmac_intr_handler(adapter, 2);
4347 if (cause & XGMAC_KR1_F)
4348 xgmac_intr_handler(adapter, 3);
4350 pcie_intr_handler(adapter);
4352 mem_intr_handler(adapter, MEM_MC);
4353 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4354 mem_intr_handler(adapter, MEM_MC1);
4356 mem_intr_handler(adapter, MEM_EDC0);
4358 mem_intr_handler(adapter, MEM_EDC1);
4360 le_intr_handler(adapter);
4362 tp_intr_handler(adapter);
4364 ma_intr_handler(adapter);
4365 if (cause & PM_TX_F)
4366 pmtx_intr_handler(adapter);
4367 if (cause & PM_RX_F)
4368 pmrx_intr_handler(adapter);
4369 if (cause & ULP_RX_F)
4370 ulprx_intr_handler(adapter);
4371 if (cause & CPL_SWITCH_F)
4372 cplsw_intr_handler(adapter);
4374 sge_intr_handler(adapter);
4375 if (cause & ULP_TX_F)
4376 ulptx_intr_handler(adapter);
4378 /* Clear the interrupts just processed for which we are the master. */
4379 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4380 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4385 * t4_intr_enable - enable interrupts
4386 * @adapter: the adapter whose interrupts should be enabled
4388 * Enable PF-specific interrupts for the calling function and the top-level
4389 * interrupt concentrator for global interrupts. Interrupts are already
4390 * enabled at each module, here we just enable the roots of the interrupt
4393 * Note: this function should be called only when the driver manages
4394 * non PF-specific interrupts from the various HW modules. Only one PCI
4395 * function at a time should be doing this.
4397 void t4_intr_enable(struct adapter *adapter)
4400 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4401 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4402 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4404 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4405 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4406 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4407 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4408 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4409 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4410 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4411 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4412 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4413 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4414 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4418 * t4_intr_disable - disable interrupts
4419 * @adapter: the adapter whose interrupts should be disabled
4421 * Disable interrupts. We only disable the top-level interrupt
4422 * concentrators. The caller must be a PCI function managing global
4425 void t4_intr_disable(struct adapter *adapter)
4427 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4428 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4429 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4431 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4432 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4436 * hash_mac_addr - return the hash value of a MAC address
4437 * @addr: the 48-bit Ethernet MAC address
4439 * Hashes a MAC address according to the hash function used by HW inexact
4440 * (hash) address matching.
4442 static int hash_mac_addr(const u8 *addr)
4444 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4445 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4453 * t4_config_rss_range - configure a portion of the RSS mapping table
4454 * @adapter: the adapter
4455 * @mbox: mbox to use for the FW command
4456 * @viid: virtual interface whose RSS subtable is to be written
4457 * @start: start entry in the table to write
4458 * @n: how many table entries to write
4459 * @rspq: values for the response queue lookup table
4460 * @nrspq: number of values in @rspq
4462 * Programs the selected part of the VI's RSS mapping table with the
4463 * provided values. If @nrspq < @n the supplied values are used repeatedly
4464 * until the full table range is populated.
4466 * The caller must ensure the values in @rspq are in the range allowed for
4469 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4470 int start, int n, const u16 *rspq, unsigned int nrspq)
4473 const u16 *rsp = rspq;
4474 const u16 *rsp_end = rspq + nrspq;
4475 struct fw_rss_ind_tbl_cmd cmd;
4477 memset(&cmd, 0, sizeof(cmd));
4478 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4479 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4480 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4481 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4483 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4485 int nq = min(n, 32);
4486 __be32 *qp = &cmd.iq0_to_iq2;
4488 cmd.niqid = cpu_to_be16(nq);
4489 cmd.startidx = cpu_to_be16(start);
4497 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4498 if (++rsp >= rsp_end)
4500 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4501 if (++rsp >= rsp_end)
4503 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4504 if (++rsp >= rsp_end)
4507 *qp++ = cpu_to_be32(v);
4511 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4519 * t4_config_glbl_rss - configure the global RSS mode
4520 * @adapter: the adapter
4521 * @mbox: mbox to use for the FW command
4522 * @mode: global RSS mode
4523 * @flags: mode-specific flags
4525 * Sets the global RSS mode.
4527 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4530 struct fw_rss_glb_config_cmd c;
4532 memset(&c, 0, sizeof(c));
4533 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4534 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4535 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4536 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4537 c.u.manual.mode_pkd =
4538 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4539 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4540 c.u.basicvirtual.mode_pkd =
4541 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4542 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4545 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4549 * t4_config_vi_rss - configure per VI RSS settings
4550 * @adapter: the adapter
4551 * @mbox: mbox to use for the FW command
4554 * @defq: id of the default RSS queue for the VI.
4556 * Configures VI-specific RSS properties.
4558 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4559 unsigned int flags, unsigned int defq)
4561 struct fw_rss_vi_config_cmd c;
4563 memset(&c, 0, sizeof(c));
4564 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4565 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4566 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4567 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4568 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4569 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4570 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4573 /* Read an RSS table row */
4574 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4576 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4577 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4582 * t4_read_rss - read the contents of the RSS mapping table
4583 * @adapter: the adapter
4584 * @map: holds the contents of the RSS mapping table
4586 * Reads the contents of the RSS hash->queue mapping table.
4588 int t4_read_rss(struct adapter *adapter, u16 *map)
4593 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4594 ret = rd_rss_row(adapter, i, &val);
4597 *map++ = LKPTBLQUEUE0_G(val);
4598 *map++ = LKPTBLQUEUE1_G(val);
4603 static unsigned int t4_use_ldst(struct adapter *adap)
4605 return (adap->flags & FW_OK) || !adap->use_bd;
4609 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4610 * @adap: the adapter
4611 * @vals: where the indirect register values are stored/written
4612 * @nregs: how many indirect registers to read/write
4613 * @start_idx: index of first indirect register to read/write
4614 * @rw: Read (1) or Write (0)
4616 * Access TP PIO registers through LDST
4618 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4619 unsigned int start_index, unsigned int rw)
4622 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4623 struct fw_ldst_cmd c;
4625 for (i = 0 ; i < nregs; i++) {
4626 memset(&c, 0, sizeof(c));
4627 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4629 (rw ? FW_CMD_READ_F :
4631 FW_LDST_CMD_ADDRSPACE_V(cmd));
4632 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4634 c.u.addrval.addr = cpu_to_be32(start_index + i);
4635 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4636 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4638 vals[i] = be32_to_cpu(c.u.addrval.val);
4643 * t4_read_rss_key - read the global RSS key
4644 * @adap: the adapter
4645 * @key: 10-entry array holding the 320-bit RSS key
4647 * Reads the global 320-bit RSS key.
4649 void t4_read_rss_key(struct adapter *adap, u32 *key)
4651 if (t4_use_ldst(adap))
4652 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4654 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4655 TP_RSS_SECRET_KEY0_A);
4659 * t4_write_rss_key - program one of the RSS keys
4660 * @adap: the adapter
4661 * @key: 10-entry array holding the 320-bit RSS key
4662 * @idx: which RSS key to write
4664 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4665 * 0..15 the corresponding entry in the RSS key table is written,
4666 * otherwise the global RSS key is written.
4668 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4670 u8 rss_key_addr_cnt = 16;
4671 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4673 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4674 * allows access to key addresses 16-63 by using KeyWrAddrX
4675 * as index[5:4](upper 2) into key table
4677 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4678 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4679 rss_key_addr_cnt = 32;
4681 if (t4_use_ldst(adap))
4682 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4684 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4685 TP_RSS_SECRET_KEY0_A);
4687 if (idx >= 0 && idx < rss_key_addr_cnt) {
4688 if (rss_key_addr_cnt > 16)
4689 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4690 KEYWRADDRX_V(idx >> 4) |
4691 T6_VFWRADDR_V(idx) | KEYWREN_F);
4693 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4694 KEYWRADDR_V(idx) | KEYWREN_F);
4699 * t4_read_rss_pf_config - read PF RSS Configuration Table
4700 * @adapter: the adapter
4701 * @index: the entry in the PF RSS table to read
4702 * @valp: where to store the returned value
4704 * Reads the PF RSS Configuration Table at the specified index and returns
4705 * the value found there.
4707 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4710 if (t4_use_ldst(adapter))
4711 t4_fw_tp_pio_rw(adapter, valp, 1,
4712 TP_RSS_PF0_CONFIG_A + index, 1);
4714 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4715 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4719 * t4_read_rss_vf_config - read VF RSS Configuration Table
4720 * @adapter: the adapter
4721 * @index: the entry in the VF RSS table to read
4722 * @vfl: where to store the returned VFL
4723 * @vfh: where to store the returned VFH
4725 * Reads the VF RSS Configuration Table at the specified index and returns
4726 * the (VFL, VFH) values found there.
4728 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4731 u32 vrt, mask, data;
4733 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4734 mask = VFWRADDR_V(VFWRADDR_M);
4735 data = VFWRADDR_V(index);
4737 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4738 data = T6_VFWRADDR_V(index);
4741 /* Request that the index'th VF Table values be read into VFL/VFH.
4743 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4744 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4745 vrt |= data | VFRDEN_F;
4746 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4748 /* Grab the VFL/VFH values ...
4750 if (t4_use_ldst(adapter)) {
4751 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4752 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4754 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4755 vfl, 1, TP_RSS_VFL_CONFIG_A);
4756 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4757 vfh, 1, TP_RSS_VFH_CONFIG_A);
4762 * t4_read_rss_pf_map - read PF RSS Map
4763 * @adapter: the adapter
4765 * Reads the PF RSS Map register and returns its value.
4767 u32 t4_read_rss_pf_map(struct adapter *adapter)
4771 if (t4_use_ldst(adapter))
4772 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4774 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4775 &pfmap, 1, TP_RSS_PF_MAP_A);
4780 * t4_read_rss_pf_mask - read PF RSS Mask
4781 * @adapter: the adapter
4783 * Reads the PF RSS Mask register and returns its value.
4785 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4789 if (t4_use_ldst(adapter))
4790 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4792 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4793 &pfmask, 1, TP_RSS_PF_MSK_A);
4798 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4799 * @adap: the adapter
4800 * @v4: holds the TCP/IP counter values
4801 * @v6: holds the TCP/IPv6 counter values
4803 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4804 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4806 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4807 struct tp_tcp_stats *v6)
4809 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4811 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4812 #define STAT(x) val[STAT_IDX(x)]
4813 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4816 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4817 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4818 v4->tcp_out_rsts = STAT(OUT_RST);
4819 v4->tcp_in_segs = STAT64(IN_SEG);
4820 v4->tcp_out_segs = STAT64(OUT_SEG);
4821 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4824 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4825 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4826 v6->tcp_out_rsts = STAT(OUT_RST);
4827 v6->tcp_in_segs = STAT64(IN_SEG);
4828 v6->tcp_out_segs = STAT64(OUT_SEG);
4829 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4837 * t4_tp_get_err_stats - read TP's error MIB counters
4838 * @adap: the adapter
4839 * @st: holds the counter values
4841 * Returns the values of TP's error counters.
4843 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4845 int nchan = adap->params.arch.nchan;
4847 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4848 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4849 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4850 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4851 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4852 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4853 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4854 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4855 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4856 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4857 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4858 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4859 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4860 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4861 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4862 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4864 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4865 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4869 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4870 * @adap: the adapter
4871 * @st: holds the counter values
4873 * Returns the values of TP's CPL counters.
4875 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4877 int nchan = adap->params.arch.nchan;
4879 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4880 nchan, TP_MIB_CPL_IN_REQ_0_A);
4881 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4882 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4887 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4888 * @adap: the adapter
4889 * @st: holds the counter values
4891 * Returns the values of TP's RDMA counters.
4893 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4895 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4896 2, TP_MIB_RQE_DFR_PKT_A);
4900 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4901 * @adap: the adapter
4902 * @idx: the port index
4903 * @st: holds the counter values
4905 * Returns the values of TP's FCoE counters for the selected port.
4907 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4908 struct tp_fcoe_stats *st)
4912 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4913 1, TP_MIB_FCOE_DDP_0_A + idx);
4914 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4915 1, TP_MIB_FCOE_DROP_0_A + idx);
4916 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4917 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4918 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4922 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4923 * @adap: the adapter
4924 * @st: holds the counter values
4926 * Returns the values of TP's counters for non-TCP directly-placed packets.
4928 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4932 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4934 st->frames = val[0];
4936 st->octets = ((u64)val[2] << 32) | val[3];
4940 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4941 * @adap: the adapter
4942 * @mtus: where to store the MTU values
4943 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4945 * Reads the HW path MTU table.
4947 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4952 for (i = 0; i < NMTUS; ++i) {
4953 t4_write_reg(adap, TP_MTU_TABLE_A,
4954 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4955 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4956 mtus[i] = MTUVALUE_G(v);
4958 mtu_log[i] = MTUWIDTH_G(v);
4963 * t4_read_cong_tbl - reads the congestion control table
4964 * @adap: the adapter
4965 * @incr: where to store the alpha values
4967 * Reads the additive increments programmed into the HW congestion
4970 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4972 unsigned int mtu, w;
4974 for (mtu = 0; mtu < NMTUS; ++mtu)
4975 for (w = 0; w < NCCTRL_WIN; ++w) {
4976 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4977 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4978 incr[mtu][w] = (u16)t4_read_reg(adap,
4979 TP_CCTRL_TABLE_A) & 0x1fff;
4984 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4985 * @adap: the adapter
4986 * @addr: the indirect TP register address
4987 * @mask: specifies the field within the register to modify
4988 * @val: new value for the field
4990 * Sets a field of an indirect TP register to the given value.
4992 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4993 unsigned int mask, unsigned int val)
4995 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4996 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4997 t4_write_reg(adap, TP_PIO_DATA_A, val);
5001 * init_cong_ctrl - initialize congestion control parameters
5002 * @a: the alpha values for congestion control
5003 * @b: the beta values for congestion control
5005 * Initialize the congestion control parameters.
5007 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5009 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5034 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5037 b[13] = b[14] = b[15] = b[16] = 3;
5038 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5039 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5044 /* The minimum additive increment value for the congestion control table */
5045 #define CC_MIN_INCR 2U
5048 * t4_load_mtus - write the MTU and congestion control HW tables
5049 * @adap: the adapter
5050 * @mtus: the values for the MTU table
5051 * @alpha: the values for the congestion control alpha parameter
5052 * @beta: the values for the congestion control beta parameter
5054 * Write the HW MTU table with the supplied MTUs and the high-speed
5055 * congestion control table with the supplied alpha, beta, and MTUs.
5056 * We write the two tables together because the additive increments
5057 * depend on the MTUs.
5059 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5060 const unsigned short *alpha, const unsigned short *beta)
5062 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5063 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5064 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5065 28672, 40960, 57344, 81920, 114688, 163840, 229376
5070 for (i = 0; i < NMTUS; ++i) {
5071 unsigned int mtu = mtus[i];
5072 unsigned int log2 = fls(mtu);
5074 if (!(mtu & ((1 << log2) >> 2))) /* round */
5076 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5077 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5079 for (w = 0; w < NCCTRL_WIN; ++w) {
5082 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5085 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5086 (w << 16) | (beta[w] << 13) | inc);
5091 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5092 * clocks. The formula is
5094 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5096 * which is equivalent to
5098 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5100 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5102 u64 v = bytes256 * adap->params.vpd.cclk;
5104 return v * 62 + v / 2;
5108 * t4_get_chan_txrate - get the current per channel Tx rates
5109 * @adap: the adapter
5110 * @nic_rate: rates for NIC traffic
5111 * @ofld_rate: rates for offloaded traffic
5113 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5116 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5120 v = t4_read_reg(adap, TP_TX_TRATE_A);
5121 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5122 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5123 if (adap->params.arch.nchan == NCHAN) {
5124 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5125 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5128 v = t4_read_reg(adap, TP_TX_ORATE_A);
5129 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5130 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5131 if (adap->params.arch.nchan == NCHAN) {
5132 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5133 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5138 * t4_set_trace_filter - configure one of the tracing filters
5139 * @adap: the adapter
5140 * @tp: the desired trace filter parameters
5141 * @idx: which filter to configure
5142 * @enable: whether to enable or disable the filter
5144 * Configures one of the tracing filters available in HW. If @enable is
5145 * %0 @tp is not examined and may be %NULL. The user is responsible to
5146 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5148 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5149 int idx, int enable)
5151 int i, ofst = idx * 4;
5152 u32 data_reg, mask_reg, cfg;
5153 u32 multitrc = TRCMULTIFILTER_F;
5156 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5160 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5161 if (cfg & TRCMULTIFILTER_F) {
5162 /* If multiple tracers are enabled, then maximum
5163 * capture size is 2.5KB (FIFO size of a single channel)
5164 * minus 2 flits for CPL_TRACE_PKT header.
5166 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5169 /* If multiple tracers are disabled, to avoid deadlocks
5170 * maximum packet capture size of 9600 bytes is recommended.
5171 * Also in this mode, only trace0 can be enabled and running.
5174 if (tp->snap_len > 9600 || idx)
5178 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5179 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5180 tp->min_len > TFMINPKTSIZE_M)
5183 /* stop the tracer we'll be changing */
5184 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5186 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5187 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5188 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5190 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5191 t4_write_reg(adap, data_reg, tp->data[i]);
5192 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5194 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5195 TFCAPTUREMAX_V(tp->snap_len) |
5196 TFMINPKTSIZE_V(tp->min_len));
5197 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5198 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5199 (is_t4(adap->params.chip) ?
5200 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5201 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5202 T5_TFINVERTMATCH_V(tp->invert)));
5208 * t4_get_trace_filter - query one of the tracing filters
5209 * @adap: the adapter
5210 * @tp: the current trace filter parameters
5211 * @idx: which trace filter to query
5212 * @enabled: non-zero if the filter is enabled
5214 * Returns the current settings of one of the HW tracing filters.
5216 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5220 int i, ofst = idx * 4;
5221 u32 data_reg, mask_reg;
5223 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5224 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5226 if (is_t4(adap->params.chip)) {
5227 *enabled = !!(ctla & TFEN_F);
5228 tp->port = TFPORT_G(ctla);
5229 tp->invert = !!(ctla & TFINVERTMATCH_F);
5231 *enabled = !!(ctla & T5_TFEN_F);
5232 tp->port = T5_TFPORT_G(ctla);
5233 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5235 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5236 tp->min_len = TFMINPKTSIZE_G(ctlb);
5237 tp->skip_ofst = TFOFFSET_G(ctla);
5238 tp->skip_len = TFLENGTH_G(ctla);
5240 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5241 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5242 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5244 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5245 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5246 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5251 * t4_pmtx_get_stats - returns the HW stats from PMTX
5252 * @adap: the adapter
5253 * @cnt: where to store the count statistics
5254 * @cycles: where to store the cycle statistics
5256 * Returns performance statistics from PMTX.
5258 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5263 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5264 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5265 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5266 if (is_t4(adap->params.chip)) {
5267 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5269 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5270 PM_TX_DBG_DATA_A, data, 2,
5271 PM_TX_DBG_STAT_MSB_A);
5272 cycles[i] = (((u64)data[0] << 32) | data[1]);
5278 * t4_pmrx_get_stats - returns the HW stats from PMRX
5279 * @adap: the adapter
5280 * @cnt: where to store the count statistics
5281 * @cycles: where to store the cycle statistics
5283 * Returns performance statistics from PMRX.
5285 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5290 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5291 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5292 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5293 if (is_t4(adap->params.chip)) {
5294 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5296 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5297 PM_RX_DBG_DATA_A, data, 2,
5298 PM_RX_DBG_STAT_MSB_A);
5299 cycles[i] = (((u64)data[0] << 32) | data[1]);
5305 * t4_get_mps_bg_map - return the buffer groups associated with a port
5306 * @adap: the adapter
5307 * @idx: the port index
5309 * Returns a bitmap indicating which MPS buffer groups are associated
5310 * with the given port. Bit i is set if buffer group i is used by the
5313 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5315 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5318 return idx == 0 ? 0xf : 0;
5319 /* In T6 (which is a 2 port card),
5320 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5321 * For 2 port T4/T5 adapter,
5322 * port 0 is mapped to channel 0 and 1,
5323 * port 1 is mapped to channel 2 and 3.
5326 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5327 return idx < 2 ? (3 << (2 * idx)) : 0;
5332 * t4_get_port_type_description - return Port Type string description
5333 * @port_type: firmware Port Type enumeration
5335 const char *t4_get_port_type_description(enum fw_port_type port_type)
5337 static const char *const port_type_description[] = {
5356 if (port_type < ARRAY_SIZE(port_type_description))
5357 return port_type_description[port_type];
5362 * t4_get_port_stats_offset - collect port stats relative to a previous
5364 * @adap: The adapter
5366 * @stats: Current stats to fill
5367 * @offset: Previous stats snapshot
5369 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5370 struct port_stats *stats,
5371 struct port_stats *offset)
5376 t4_get_port_stats(adap, idx, stats);
5377 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5378 i < (sizeof(struct port_stats) / sizeof(u64));
5384 * t4_get_port_stats - collect port statistics
5385 * @adap: the adapter
5386 * @idx: the port index
5387 * @p: the stats structure to fill
5389 * Collect statistics related to the given port from HW.
5391 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5393 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5395 #define GET_STAT(name) \
5396 t4_read_reg64(adap, \
5397 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5398 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5399 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5401 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5402 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5403 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5404 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5405 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5406 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5407 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5408 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5409 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5410 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5411 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5412 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5413 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5414 p->tx_drop = GET_STAT(TX_PORT_DROP);
5415 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5416 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5417 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5418 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5419 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5420 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5421 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5422 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5423 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5425 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5426 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5427 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5428 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5429 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5430 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5431 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5432 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5433 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5434 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5435 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5436 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5437 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5438 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5439 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5440 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5441 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5442 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5443 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5444 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5445 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5446 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5447 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5448 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5449 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5450 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5451 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5453 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5454 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5455 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5456 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5457 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5458 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5459 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5460 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5467 * t4_get_lb_stats - collect loopback port statistics
5468 * @adap: the adapter
5469 * @idx: the loopback port index
5470 * @p: the stats structure to fill
5472 * Return HW statistics for the given loopback port.
5474 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5476 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5478 #define GET_STAT(name) \
5479 t4_read_reg64(adap, \
5480 (is_t4(adap->params.chip) ? \
5481 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5482 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5483 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5485 p->octets = GET_STAT(BYTES);
5486 p->frames = GET_STAT(FRAMES);
5487 p->bcast_frames = GET_STAT(BCAST);
5488 p->mcast_frames = GET_STAT(MCAST);
5489 p->ucast_frames = GET_STAT(UCAST);
5490 p->error_frames = GET_STAT(ERROR);
5492 p->frames_64 = GET_STAT(64B);
5493 p->frames_65_127 = GET_STAT(65B_127B);
5494 p->frames_128_255 = GET_STAT(128B_255B);
5495 p->frames_256_511 = GET_STAT(256B_511B);
5496 p->frames_512_1023 = GET_STAT(512B_1023B);
5497 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5498 p->frames_1519_max = GET_STAT(1519B_MAX);
5499 p->drop = GET_STAT(DROP_FRAMES);
5501 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5502 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5503 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5504 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5505 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5506 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5507 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5508 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5514 /* t4_mk_filtdelwr - create a delete filter WR
5515 * @ftid: the filter ID
5516 * @wr: the filter work request to populate
5517 * @qid: ingress queue to receive the delete notification
5519 * Creates a filter work request to delete the supplied filter. If @qid is
5520 * negative the delete notification is suppressed.
5522 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5524 memset(wr, 0, sizeof(*wr));
5525 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5526 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5527 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5528 FW_FILTER_WR_NOREPLY_V(qid < 0));
5529 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5531 wr->rx_chan_rx_rpl_iq =
5532 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5535 #define INIT_CMD(var, cmd, rd_wr) do { \
5536 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5537 FW_CMD_REQUEST_F | \
5538 FW_CMD_##rd_wr##_F); \
5539 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5542 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5546 struct fw_ldst_cmd c;
5548 memset(&c, 0, sizeof(c));
5549 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5550 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5554 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5555 c.u.addrval.addr = cpu_to_be32(addr);
5556 c.u.addrval.val = cpu_to_be32(val);
5558 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5562 * t4_mdio_rd - read a PHY register through MDIO
5563 * @adap: the adapter
5564 * @mbox: mailbox to use for the FW command
5565 * @phy_addr: the PHY address
5566 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5567 * @reg: the register to read
5568 * @valp: where to store the value
5570 * Issues a FW command through the given mailbox to read a PHY register.
5572 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5573 unsigned int mmd, unsigned int reg, u16 *valp)
5577 struct fw_ldst_cmd c;
5579 memset(&c, 0, sizeof(c));
5580 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5581 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5582 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5584 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5585 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5586 FW_LDST_CMD_MMD_V(mmd));
5587 c.u.mdio.raddr = cpu_to_be16(reg);
5589 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5591 *valp = be16_to_cpu(c.u.mdio.rval);
5596 * t4_mdio_wr - write a PHY register through MDIO
5597 * @adap: the adapter
5598 * @mbox: mailbox to use for the FW command
5599 * @phy_addr: the PHY address
5600 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5601 * @reg: the register to write
5602 * @valp: value to write
5604 * Issues a FW command through the given mailbox to write a PHY register.
5606 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5607 unsigned int mmd, unsigned int reg, u16 val)
5610 struct fw_ldst_cmd c;
5612 memset(&c, 0, sizeof(c));
5613 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5614 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5615 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5617 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5618 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5619 FW_LDST_CMD_MMD_V(mmd));
5620 c.u.mdio.raddr = cpu_to_be16(reg);
5621 c.u.mdio.rval = cpu_to_be16(val);
5623 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5627 * t4_sge_decode_idma_state - decode the idma state
5628 * @adap: the adapter
5629 * @state: the state idma is stuck in
5631 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5633 static const char * const t4_decode[] = {
5635 "IDMA_PUSH_MORE_CPL_FIFO",
5636 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5638 "IDMA_PHYSADDR_SEND_PCIEHDR",
5639 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5640 "IDMA_PHYSADDR_SEND_PAYLOAD",
5641 "IDMA_SEND_FIFO_TO_IMSG",
5642 "IDMA_FL_REQ_DATA_FL_PREP",
5643 "IDMA_FL_REQ_DATA_FL",
5645 "IDMA_FL_H_REQ_HEADER_FL",
5646 "IDMA_FL_H_SEND_PCIEHDR",
5647 "IDMA_FL_H_PUSH_CPL_FIFO",
5648 "IDMA_FL_H_SEND_CPL",
5649 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5650 "IDMA_FL_H_SEND_IP_HDR",
5651 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5652 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5653 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5654 "IDMA_FL_D_SEND_PCIEHDR",
5655 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5656 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5657 "IDMA_FL_SEND_PCIEHDR",
5658 "IDMA_FL_PUSH_CPL_FIFO",
5660 "IDMA_FL_SEND_PAYLOAD_FIRST",
5661 "IDMA_FL_SEND_PAYLOAD",
5662 "IDMA_FL_REQ_NEXT_DATA_FL",
5663 "IDMA_FL_SEND_NEXT_PCIEHDR",
5664 "IDMA_FL_SEND_PADDING",
5665 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5666 "IDMA_FL_SEND_FIFO_TO_IMSG",
5667 "IDMA_FL_REQ_DATAFL_DONE",
5668 "IDMA_FL_REQ_HEADERFL_DONE",
5670 static const char * const t5_decode[] = {
5673 "IDMA_PUSH_MORE_CPL_FIFO",
5674 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5675 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5676 "IDMA_PHYSADDR_SEND_PCIEHDR",
5677 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5678 "IDMA_PHYSADDR_SEND_PAYLOAD",
5679 "IDMA_SEND_FIFO_TO_IMSG",
5680 "IDMA_FL_REQ_DATA_FL",
5682 "IDMA_FL_DROP_SEND_INC",
5683 "IDMA_FL_H_REQ_HEADER_FL",
5684 "IDMA_FL_H_SEND_PCIEHDR",
5685 "IDMA_FL_H_PUSH_CPL_FIFO",
5686 "IDMA_FL_H_SEND_CPL",
5687 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5688 "IDMA_FL_H_SEND_IP_HDR",
5689 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5690 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5691 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5692 "IDMA_FL_D_SEND_PCIEHDR",
5693 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5694 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5695 "IDMA_FL_SEND_PCIEHDR",
5696 "IDMA_FL_PUSH_CPL_FIFO",
5698 "IDMA_FL_SEND_PAYLOAD_FIRST",
5699 "IDMA_FL_SEND_PAYLOAD",
5700 "IDMA_FL_REQ_NEXT_DATA_FL",
5701 "IDMA_FL_SEND_NEXT_PCIEHDR",
5702 "IDMA_FL_SEND_PADDING",
5703 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5705 static const u32 sge_regs[] = {
5706 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5707 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5708 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5710 const char **sge_idma_decode;
5711 int sge_idma_decode_nstates;
5714 if (is_t4(adapter->params.chip)) {
5715 sge_idma_decode = (const char **)t4_decode;
5716 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5718 sge_idma_decode = (const char **)t5_decode;
5719 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5722 if (state < sge_idma_decode_nstates)
5723 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5725 CH_WARN(adapter, "idma state %d unknown\n", state);
5727 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5728 CH_WARN(adapter, "SGE register %#x value %#x\n",
5729 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5733 * t4_sge_ctxt_flush - flush the SGE context cache
5734 * @adap: the adapter
5735 * @mbox: mailbox to use for the FW command
5737 * Issues a FW command through the given mailbox to flush the
5738 * SGE context cache.
5740 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5744 struct fw_ldst_cmd c;
5746 memset(&c, 0, sizeof(c));
5747 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5748 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5749 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5751 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5752 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5754 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5759 * t4_fw_hello - establish communication with FW
5760 * @adap: the adapter
5761 * @mbox: mailbox to use for the FW command
5762 * @evt_mbox: mailbox to receive async FW events
5763 * @master: specifies the caller's willingness to be the device master
5764 * @state: returns the current device state (if non-NULL)
5766 * Issues a command to establish communication with FW. Returns either
5767 * an error (negative integer) or the mailbox of the Master PF.
5769 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5770 enum dev_master master, enum dev_state *state)
5773 struct fw_hello_cmd c;
5775 unsigned int master_mbox;
5776 int retries = FW_CMD_HELLO_RETRIES;
5779 memset(&c, 0, sizeof(c));
5780 INIT_CMD(c, HELLO, WRITE);
5781 c.err_to_clearinit = cpu_to_be32(
5782 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5783 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5784 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5785 mbox : FW_HELLO_CMD_MBMASTER_M) |
5786 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5787 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5788 FW_HELLO_CMD_CLEARINIT_F);
5791 * Issue the HELLO command to the firmware. If it's not successful
5792 * but indicates that we got a "busy" or "timeout" condition, retry
5793 * the HELLO until we exhaust our retry limit. If we do exceed our
5794 * retry limit, check to see if the firmware left us any error
5795 * information and report that if so.
5797 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5799 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5801 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5802 t4_report_fw_error(adap);
5806 v = be32_to_cpu(c.err_to_clearinit);
5807 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5809 if (v & FW_HELLO_CMD_ERR_F)
5810 *state = DEV_STATE_ERR;
5811 else if (v & FW_HELLO_CMD_INIT_F)
5812 *state = DEV_STATE_INIT;
5814 *state = DEV_STATE_UNINIT;
5818 * If we're not the Master PF then we need to wait around for the
5819 * Master PF Driver to finish setting up the adapter.
5821 * Note that we also do this wait if we're a non-Master-capable PF and
5822 * there is no current Master PF; a Master PF may show up momentarily
5823 * and we wouldn't want to fail pointlessly. (This can happen when an
5824 * OS loads lots of different drivers rapidly at the same time). In
5825 * this case, the Master PF returned by the firmware will be
5826 * PCIE_FW_MASTER_M so the test below will work ...
5828 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5829 master_mbox != mbox) {
5830 int waiting = FW_CMD_HELLO_TIMEOUT;
5833 * Wait for the firmware to either indicate an error or
5834 * initialized state. If we see either of these we bail out
5835 * and report the issue to the caller. If we exhaust the
5836 * "hello timeout" and we haven't exhausted our retries, try
5837 * again. Otherwise bail with a timeout error.
5846 * If neither Error nor Initialialized are indicated
5847 * by the firmware keep waiting till we exaust our
5848 * timeout ... and then retry if we haven't exhausted
5851 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5852 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5863 * We either have an Error or Initialized condition
5864 * report errors preferentially.
5867 if (pcie_fw & PCIE_FW_ERR_F)
5868 *state = DEV_STATE_ERR;
5869 else if (pcie_fw & PCIE_FW_INIT_F)
5870 *state = DEV_STATE_INIT;
5874 * If we arrived before a Master PF was selected and
5875 * there's not a valid Master PF, grab its identity
5878 if (master_mbox == PCIE_FW_MASTER_M &&
5879 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5880 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5889 * t4_fw_bye - end communication with FW
5890 * @adap: the adapter
5891 * @mbox: mailbox to use for the FW command
5893 * Issues a command to terminate communication with FW.
5895 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5897 struct fw_bye_cmd c;
5899 memset(&c, 0, sizeof(c));
5900 INIT_CMD(c, BYE, WRITE);
5901 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5905 * t4_init_cmd - ask FW to initialize the device
5906 * @adap: the adapter
5907 * @mbox: mailbox to use for the FW command
5909 * Issues a command to FW to partially initialize the device. This
5910 * performs initialization that generally doesn't depend on user input.
5912 int t4_early_init(struct adapter *adap, unsigned int mbox)
5914 struct fw_initialize_cmd c;
5916 memset(&c, 0, sizeof(c));
5917 INIT_CMD(c, INITIALIZE, WRITE);
5918 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5922 * t4_fw_reset - issue a reset to FW
5923 * @adap: the adapter
5924 * @mbox: mailbox to use for the FW command
5925 * @reset: specifies the type of reset to perform
5927 * Issues a reset command of the specified type to FW.
5929 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5931 struct fw_reset_cmd c;
5933 memset(&c, 0, sizeof(c));
5934 INIT_CMD(c, RESET, WRITE);
5935 c.val = cpu_to_be32(reset);
5936 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5940 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
5941 * @adap: the adapter
5942 * @mbox: mailbox to use for the FW RESET command (if desired)
5943 * @force: force uP into RESET even if FW RESET command fails
5945 * Issues a RESET command to firmware (if desired) with a HALT indication
5946 * and then puts the microprocessor into RESET state. The RESET command
5947 * will only be issued if a legitimate mailbox is provided (mbox <=
5948 * PCIE_FW_MASTER_M).
5950 * This is generally used in order for the host to safely manipulate the
5951 * adapter without fear of conflicting with whatever the firmware might
5952 * be doing. The only way out of this state is to RESTART the firmware
5955 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
5960 * If a legitimate mailbox is provided, issue a RESET command
5961 * with a HALT indication.
5963 if (mbox <= PCIE_FW_MASTER_M) {
5964 struct fw_reset_cmd c;
5966 memset(&c, 0, sizeof(c));
5967 INIT_CMD(c, RESET, WRITE);
5968 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
5969 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
5970 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5974 * Normally we won't complete the operation if the firmware RESET
5975 * command fails but if our caller insists we'll go ahead and put the
5976 * uP into RESET. This can be useful if the firmware is hung or even
5977 * missing ... We'll have to take the risk of putting the uP into
5978 * RESET without the cooperation of firmware in that case.
5980 * We also force the firmware's HALT flag to be on in case we bypassed
5981 * the firmware RESET command above or we're dealing with old firmware
5982 * which doesn't have the HALT capability. This will serve as a flag
5983 * for the incoming firmware to know that it's coming out of a HALT
5984 * rather than a RESET ... if it's new enough to understand that ...
5986 if (ret == 0 || force) {
5987 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
5988 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
5993 * And we always return the result of the firmware RESET command
5994 * even when we force the uP into RESET ...
6000 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6001 * @adap: the adapter
6002 * @reset: if we want to do a RESET to restart things
6004 * Restart firmware previously halted by t4_fw_halt(). On successful
6005 * return the previous PF Master remains as the new PF Master and there
6006 * is no need to issue a new HELLO command, etc.
6008 * We do this in two ways:
6010 * 1. If we're dealing with newer firmware we'll simply want to take
6011 * the chip's microprocessor out of RESET. This will cause the
6012 * firmware to start up from its start vector. And then we'll loop
6013 * until the firmware indicates it's started again (PCIE_FW.HALT
6014 * reset to 0) or we timeout.
6016 * 2. If we're dealing with older firmware then we'll need to RESET
6017 * the chip since older firmware won't recognize the PCIE_FW.HALT
6018 * flag and automatically RESET itself on startup.
6020 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6024 * Since we're directing the RESET instead of the firmware
6025 * doing it automatically, we need to clear the PCIE_FW.HALT
6028 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6031 * If we've been given a valid mailbox, first try to get the
6032 * firmware to do the RESET. If that works, great and we can
6033 * return success. Otherwise, if we haven't been given a
6034 * valid mailbox or the RESET command failed, fall back to
6035 * hitting the chip with a hammer.
6037 if (mbox <= PCIE_FW_MASTER_M) {
6038 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6040 if (t4_fw_reset(adap, mbox,
6041 PIORST_F | PIORSTMODE_F) == 0)
6045 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6050 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6051 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6052 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6063 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6064 * @adap: the adapter
6065 * @mbox: mailbox to use for the FW RESET command (if desired)
6066 * @fw_data: the firmware image to write
6068 * @force: force upgrade even if firmware doesn't cooperate
6070 * Perform all of the steps necessary for upgrading an adapter's
6071 * firmware image. Normally this requires the cooperation of the
6072 * existing firmware in order to halt all existing activities
6073 * but if an invalid mailbox token is passed in we skip that step
6074 * (though we'll still put the adapter microprocessor into RESET in
6077 * On successful return the new firmware will have been loaded and
6078 * the adapter will have been fully RESET losing all previous setup
6079 * state. On unsuccessful return the adapter may be completely hosed ...
6080 * positive errno indicates that the adapter is ~probably~ intact, a
6081 * negative errno indicates that things are looking bad ...
6083 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6084 const u8 *fw_data, unsigned int size, int force)
6086 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6089 if (!t4_fw_matches_chip(adap, fw_hdr))
6092 ret = t4_fw_halt(adap, mbox, force);
6093 if (ret < 0 && !force)
6096 ret = t4_load_fw(adap, fw_data, size);
6101 * Older versions of the firmware don't understand the new
6102 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6103 * restart. So for newly loaded older firmware we'll have to do the
6104 * RESET for it so it starts up on a clean slate. We can tell if
6105 * the newly loaded firmware will handle this right by checking
6106 * its header flags to see if it advertises the capability.
6108 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6109 return t4_fw_restart(adap, mbox, reset);
6113 * t4_fl_pkt_align - return the fl packet alignment
6114 * @adap: the adapter
6116 * T4 has a single field to specify the packing and padding boundary.
6117 * T5 onwards has separate fields for this and hence the alignment for
6118 * next packet offset is maximum of these two.
6121 int t4_fl_pkt_align(struct adapter *adap)
6123 u32 sge_control, sge_control2;
6124 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6126 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6128 /* T4 uses a single control field to specify both the PCIe Padding and
6129 * Packing Boundary. T5 introduced the ability to specify these
6130 * separately. The actual Ingress Packet Data alignment boundary
6131 * within Packed Buffer Mode is the maximum of these two
6132 * specifications. (Note that it makes no real practical sense to
6133 * have the Pading Boudary be larger than the Packing Boundary but you
6134 * could set the chip up that way and, in fact, legacy T4 code would
6135 * end doing this because it would initialize the Padding Boundary and
6136 * leave the Packing Boundary initialized to 0 (16 bytes).)
6137 * Padding Boundary values in T6 starts from 8B,
6138 * where as it is 32B for T4 and T5.
6140 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6141 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6143 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6145 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6147 fl_align = ingpadboundary;
6148 if (!is_t4(adap->params.chip)) {
6149 /* T5 has a weird interpretation of one of the PCIe Packing
6150 * Boundary values. No idea why ...
6152 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6153 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6154 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6155 ingpackboundary = 16;
6157 ingpackboundary = 1 << (ingpackboundary +
6158 INGPACKBOUNDARY_SHIFT_X);
6160 fl_align = max(ingpadboundary, ingpackboundary);
6166 * t4_fixup_host_params - fix up host-dependent parameters
6167 * @adap: the adapter
6168 * @page_size: the host's Base Page Size
6169 * @cache_line_size: the host's Cache Line Size
6171 * Various registers in T4 contain values which are dependent on the
6172 * host's Base Page and Cache Line Sizes. This function will fix all of
6173 * those registers with the appropriate values as passed in ...
6175 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6176 unsigned int cache_line_size)
6178 unsigned int page_shift = fls(page_size) - 1;
6179 unsigned int sge_hps = page_shift - 10;
6180 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6181 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6182 unsigned int fl_align_log = fls(fl_align) - 1;
6183 unsigned int ingpad;
6185 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6186 HOSTPAGESIZEPF0_V(sge_hps) |
6187 HOSTPAGESIZEPF1_V(sge_hps) |
6188 HOSTPAGESIZEPF2_V(sge_hps) |
6189 HOSTPAGESIZEPF3_V(sge_hps) |
6190 HOSTPAGESIZEPF4_V(sge_hps) |
6191 HOSTPAGESIZEPF5_V(sge_hps) |
6192 HOSTPAGESIZEPF6_V(sge_hps) |
6193 HOSTPAGESIZEPF7_V(sge_hps));
6195 if (is_t4(adap->params.chip)) {
6196 t4_set_reg_field(adap, SGE_CONTROL_A,
6197 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6198 EGRSTATUSPAGESIZE_F,
6199 INGPADBOUNDARY_V(fl_align_log -
6200 INGPADBOUNDARY_SHIFT_X) |
6201 EGRSTATUSPAGESIZE_V(stat_len != 64));
6203 /* T5 introduced the separation of the Free List Padding and
6204 * Packing Boundaries. Thus, we can select a smaller Padding
6205 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6206 * Bandwidth, and use a Packing Boundary which is large enough
6207 * to avoid false sharing between CPUs, etc.
6209 * For the PCI Link, the smaller the Padding Boundary the
6210 * better. For the Memory Controller, a smaller Padding
6211 * Boundary is better until we cross under the Memory Line
6212 * Size (the minimum unit of transfer to/from Memory). If we
6213 * have a Padding Boundary which is smaller than the Memory
6214 * Line Size, that'll involve a Read-Modify-Write cycle on the
6215 * Memory Controller which is never good. For T5 the smallest
6216 * Padding Boundary which we can select is 32 bytes which is
6217 * larger than any known Memory Controller Line Size so we'll
6220 * T5 has a different interpretation of the "0" value for the
6221 * Packing Boundary. This corresponds to 16 bytes instead of
6222 * the expected 32 bytes. We never have a Packing Boundary
6223 * less than 32 bytes so we can't use that special value but
6224 * on the other hand, if we wanted 32 bytes, the best we can
6225 * really do is 64 bytes.
6227 if (fl_align <= 32) {
6232 if (is_t5(adap->params.chip))
6233 ingpad = INGPCIEBOUNDARY_32B_X;
6235 ingpad = T6_INGPADBOUNDARY_32B_X;
6237 t4_set_reg_field(adap, SGE_CONTROL_A,
6238 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6239 EGRSTATUSPAGESIZE_F,
6240 INGPADBOUNDARY_V(ingpad) |
6241 EGRSTATUSPAGESIZE_V(stat_len != 64));
6242 t4_set_reg_field(adap, SGE_CONTROL2_A,
6243 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6244 INGPACKBOUNDARY_V(fl_align_log -
6245 INGPACKBOUNDARY_SHIFT_X));
6248 * Adjust various SGE Free List Host Buffer Sizes.
6250 * This is something of a crock since we're using fixed indices into
6251 * the array which are also known by the sge.c code and the T4
6252 * Firmware Configuration File. We need to come up with a much better
6253 * approach to managing this array. For now, the first four entries
6258 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6259 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6261 * For the single-MTU buffers in unpacked mode we need to include
6262 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6263 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6264 * Padding boundary. All of these are accommodated in the Factory
6265 * Default Firmware Configuration File but we need to adjust it for
6266 * this host's cache line size.
6268 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6269 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6270 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6272 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6273 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6276 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6282 * t4_fw_initialize - ask FW to initialize the device
6283 * @adap: the adapter
6284 * @mbox: mailbox to use for the FW command
6286 * Issues a command to FW to partially initialize the device. This
6287 * performs initialization that generally doesn't depend on user input.
6289 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6291 struct fw_initialize_cmd c;
6293 memset(&c, 0, sizeof(c));
6294 INIT_CMD(c, INITIALIZE, WRITE);
6295 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6299 * t4_query_params_rw - query FW or device parameters
6300 * @adap: the adapter
6301 * @mbox: mailbox to use for the FW command
6304 * @nparams: the number of parameters
6305 * @params: the parameter names
6306 * @val: the parameter values
6307 * @rw: Write and read flag
6309 * Reads the value of FW or device parameters. Up to 7 parameters can be
6312 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6313 unsigned int vf, unsigned int nparams, const u32 *params,
6317 struct fw_params_cmd c;
6318 __be32 *p = &c.param[0].mnem;
6323 memset(&c, 0, sizeof(c));
6324 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6325 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6326 FW_PARAMS_CMD_PFN_V(pf) |
6327 FW_PARAMS_CMD_VFN_V(vf));
6328 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6330 for (i = 0; i < nparams; i++) {
6331 *p++ = cpu_to_be32(*params++);
6333 *p = cpu_to_be32(*(val + i));
6337 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6339 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6340 *val++ = be32_to_cpu(*p);
6344 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6345 unsigned int vf, unsigned int nparams, const u32 *params,
6348 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6352 * t4_set_params_timeout - sets FW or device parameters
6353 * @adap: the adapter
6354 * @mbox: mailbox to use for the FW command
6357 * @nparams: the number of parameters
6358 * @params: the parameter names
6359 * @val: the parameter values
6360 * @timeout: the timeout time
6362 * Sets the value of FW or device parameters. Up to 7 parameters can be
6363 * specified at once.
6365 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6366 unsigned int pf, unsigned int vf,
6367 unsigned int nparams, const u32 *params,
6368 const u32 *val, int timeout)
6370 struct fw_params_cmd c;
6371 __be32 *p = &c.param[0].mnem;
6376 memset(&c, 0, sizeof(c));
6377 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6378 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6379 FW_PARAMS_CMD_PFN_V(pf) |
6380 FW_PARAMS_CMD_VFN_V(vf));
6381 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6384 *p++ = cpu_to_be32(*params++);
6385 *p++ = cpu_to_be32(*val++);
6388 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6392 * t4_set_params - sets FW or device parameters
6393 * @adap: the adapter
6394 * @mbox: mailbox to use for the FW command
6397 * @nparams: the number of parameters
6398 * @params: the parameter names
6399 * @val: the parameter values
6401 * Sets the value of FW or device parameters. Up to 7 parameters can be
6402 * specified at once.
6404 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6405 unsigned int vf, unsigned int nparams, const u32 *params,
6408 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6409 FW_CMD_MAX_TIMEOUT);
6413 * t4_cfg_pfvf - configure PF/VF resource limits
6414 * @adap: the adapter
6415 * @mbox: mailbox to use for the FW command
6416 * @pf: the PF being configured
6417 * @vf: the VF being configured
6418 * @txq: the max number of egress queues
6419 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6420 * @rxqi: the max number of interrupt-capable ingress queues
6421 * @rxq: the max number of interruptless ingress queues
6422 * @tc: the PCI traffic class
6423 * @vi: the max number of virtual interfaces
6424 * @cmask: the channel access rights mask for the PF/VF
6425 * @pmask: the port access rights mask for the PF/VF
6426 * @nexact: the maximum number of exact MPS filters
6427 * @rcaps: read capabilities
6428 * @wxcaps: write/execute capabilities
6430 * Configures resource limits and capabilities for a physical or virtual
6433 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6434 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6435 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6436 unsigned int vi, unsigned int cmask, unsigned int pmask,
6437 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6439 struct fw_pfvf_cmd c;
6441 memset(&c, 0, sizeof(c));
6442 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6443 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6444 FW_PFVF_CMD_VFN_V(vf));
6445 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6446 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6447 FW_PFVF_CMD_NIQ_V(rxq));
6448 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6449 FW_PFVF_CMD_PMASK_V(pmask) |
6450 FW_PFVF_CMD_NEQ_V(txq));
6451 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6452 FW_PFVF_CMD_NVI_V(vi) |
6453 FW_PFVF_CMD_NEXACTF_V(nexact));
6454 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6455 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6456 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6457 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6461 * t4_alloc_vi - allocate a virtual interface
6462 * @adap: the adapter
6463 * @mbox: mailbox to use for the FW command
6464 * @port: physical port associated with the VI
6465 * @pf: the PF owning the VI
6466 * @vf: the VF owning the VI
6467 * @nmac: number of MAC addresses needed (1 to 5)
6468 * @mac: the MAC addresses of the VI
6469 * @rss_size: size of RSS table slice associated with this VI
6471 * Allocates a virtual interface for the given physical port. If @mac is
6472 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6473 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6474 * stored consecutively so the space needed is @nmac * 6 bytes.
6475 * Returns a negative error number or the non-negative VI id.
6477 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6478 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6479 unsigned int *rss_size)
6484 memset(&c, 0, sizeof(c));
6485 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6486 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6487 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6488 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6489 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6492 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6497 memcpy(mac, c.mac, sizeof(c.mac));
6500 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6502 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6504 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6506 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6510 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6511 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6515 * t4_free_vi - free a virtual interface
6516 * @adap: the adapter
6517 * @mbox: mailbox to use for the FW command
6518 * @pf: the PF owning the VI
6519 * @vf: the VF owning the VI
6520 * @viid: virtual interface identifiler
6522 * Free a previously allocated virtual interface.
6524 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6525 unsigned int vf, unsigned int viid)
6529 memset(&c, 0, sizeof(c));
6530 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6533 FW_VI_CMD_PFN_V(pf) |
6534 FW_VI_CMD_VFN_V(vf));
6535 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6536 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6538 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6542 * t4_set_rxmode - set Rx properties of a virtual interface
6543 * @adap: the adapter
6544 * @mbox: mailbox to use for the FW command
6546 * @mtu: the new MTU or -1
6547 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6548 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6549 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6550 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6551 * @sleep_ok: if true we may sleep while awaiting command completion
6553 * Sets Rx properties of a virtual interface.
6555 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6556 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6559 struct fw_vi_rxmode_cmd c;
6561 /* convert to FW values */
6563 mtu = FW_RXMODE_MTU_NO_CHG;
6565 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6567 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6569 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6571 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6573 memset(&c, 0, sizeof(c));
6574 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6575 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6576 FW_VI_RXMODE_CMD_VIID_V(viid));
6577 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6579 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6580 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6581 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6582 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6583 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6584 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6588 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6589 * @adap: the adapter
6590 * @mbox: mailbox to use for the FW command
6592 * @free: if true any existing filters for this VI id are first removed
6593 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6594 * @addr: the MAC address(es)
6595 * @idx: where to store the index of each allocated filter
6596 * @hash: pointer to hash address filter bitmap
6597 * @sleep_ok: call is allowed to sleep
6599 * Allocates an exact-match filter for each of the supplied addresses and
6600 * sets it to the corresponding address. If @idx is not %NULL it should
6601 * have at least @naddr entries, each of which will be set to the index of
6602 * the filter allocated for the corresponding MAC address. If a filter
6603 * could not be allocated for an address its index is set to 0xffff.
6604 * If @hash is not %NULL addresses that fail to allocate an exact filter
6605 * are hashed and update the hash filter bitmap pointed at by @hash.
6607 * Returns a negative error number or the number of filters allocated.
6609 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6610 unsigned int viid, bool free, unsigned int naddr,
6611 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6613 int offset, ret = 0;
6614 struct fw_vi_mac_cmd c;
6615 unsigned int nfilters = 0;
6616 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6617 unsigned int rem = naddr;
6619 if (naddr > max_naddr)
6622 for (offset = 0; offset < naddr ; /**/) {
6623 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6624 rem : ARRAY_SIZE(c.u.exact));
6625 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6626 u.exact[fw_naddr]), 16);
6627 struct fw_vi_mac_exact *p;
6630 memset(&c, 0, sizeof(c));
6631 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6634 FW_CMD_EXEC_V(free) |
6635 FW_VI_MAC_CMD_VIID_V(viid));
6636 c.freemacs_to_len16 =
6637 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6638 FW_CMD_LEN16_V(len16));
6640 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6642 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6643 FW_VI_MAC_CMD_IDX_V(
6644 FW_VI_MAC_ADD_MAC));
6645 memcpy(p->macaddr, addr[offset + i],
6646 sizeof(p->macaddr));
6649 /* It's okay if we run out of space in our MAC address arena.
6650 * Some of the addresses we submit may get stored so we need
6651 * to run through the reply to see what the results were ...
6653 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6654 if (ret && ret != -FW_ENOMEM)
6657 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6658 u16 index = FW_VI_MAC_CMD_IDX_G(
6659 be16_to_cpu(p->valid_to_idx));
6662 idx[offset + i] = (index >= max_naddr ?
6664 if (index < max_naddr)
6668 hash_mac_addr(addr[offset + i]));
6676 if (ret == 0 || ret == -FW_ENOMEM)
6682 * t4_change_mac - modifies the exact-match filter for a MAC address
6683 * @adap: the adapter
6684 * @mbox: mailbox to use for the FW command
6686 * @idx: index of existing filter for old value of MAC address, or -1
6687 * @addr: the new MAC address value
6688 * @persist: whether a new MAC allocation should be persistent
6689 * @add_smt: if true also add the address to the HW SMT
6691 * Modifies an exact-match filter and sets it to the new MAC address.
6692 * Note that in general it is not possible to modify the value of a given
6693 * filter so the generic way to modify an address filter is to free the one
6694 * being used by the old address value and allocate a new filter for the
6695 * new address value. @idx can be -1 if the address is a new addition.
6697 * Returns a negative error number or the index of the filter with the new
6700 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6701 int idx, const u8 *addr, bool persist, bool add_smt)
6704 struct fw_vi_mac_cmd c;
6705 struct fw_vi_mac_exact *p = c.u.exact;
6706 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6708 if (idx < 0) /* new allocation */
6709 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6710 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6712 memset(&c, 0, sizeof(c));
6713 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6714 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6715 FW_VI_MAC_CMD_VIID_V(viid));
6716 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6717 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6718 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6719 FW_VI_MAC_CMD_IDX_V(idx));
6720 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6722 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6724 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6725 if (ret >= max_mac_addr)
6732 * t4_set_addr_hash - program the MAC inexact-match hash filter
6733 * @adap: the adapter
6734 * @mbox: mailbox to use for the FW command
6736 * @ucast: whether the hash filter should also match unicast addresses
6737 * @vec: the value to be written to the hash filter
6738 * @sleep_ok: call is allowed to sleep
6740 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6742 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6743 bool ucast, u64 vec, bool sleep_ok)
6745 struct fw_vi_mac_cmd c;
6747 memset(&c, 0, sizeof(c));
6748 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6749 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6750 FW_VI_ENABLE_CMD_VIID_V(viid));
6751 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6752 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6754 c.u.hash.hashvec = cpu_to_be64(vec);
6755 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6759 * t4_enable_vi_params - enable/disable a virtual interface
6760 * @adap: the adapter
6761 * @mbox: mailbox to use for the FW command
6763 * @rx_en: 1=enable Rx, 0=disable Rx
6764 * @tx_en: 1=enable Tx, 0=disable Tx
6765 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6767 * Enables/disables a virtual interface. Note that setting DCB Enable
6768 * only makes sense when enabling a Virtual Interface ...
6770 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6771 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6773 struct fw_vi_enable_cmd c;
6775 memset(&c, 0, sizeof(c));
6776 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6777 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6778 FW_VI_ENABLE_CMD_VIID_V(viid));
6779 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6780 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6781 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6783 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6787 * t4_enable_vi - enable/disable a virtual interface
6788 * @adap: the adapter
6789 * @mbox: mailbox to use for the FW command
6791 * @rx_en: 1=enable Rx, 0=disable Rx
6792 * @tx_en: 1=enable Tx, 0=disable Tx
6794 * Enables/disables a virtual interface.
6796 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6797 bool rx_en, bool tx_en)
6799 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6803 * t4_identify_port - identify a VI's port by blinking its LED
6804 * @adap: the adapter
6805 * @mbox: mailbox to use for the FW command
6807 * @nblinks: how many times to blink LED at 2.5 Hz
6809 * Identifies a VI's port by blinking its LED.
6811 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6812 unsigned int nblinks)
6814 struct fw_vi_enable_cmd c;
6816 memset(&c, 0, sizeof(c));
6817 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6818 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6819 FW_VI_ENABLE_CMD_VIID_V(viid));
6820 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6821 c.blinkdur = cpu_to_be16(nblinks);
6822 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6826 * t4_iq_free - free an ingress queue and its FLs
6827 * @adap: the adapter
6828 * @mbox: mailbox to use for the FW command
6829 * @pf: the PF owning the queues
6830 * @vf: the VF owning the queues
6831 * @iqtype: the ingress queue type
6832 * @iqid: ingress queue id
6833 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6834 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6836 * Frees an ingress queue and its associated FLs, if any.
6838 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6839 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6840 unsigned int fl0id, unsigned int fl1id)
6844 memset(&c, 0, sizeof(c));
6845 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6846 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6847 FW_IQ_CMD_VFN_V(vf));
6848 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
6849 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6850 c.iqid = cpu_to_be16(iqid);
6851 c.fl0id = cpu_to_be16(fl0id);
6852 c.fl1id = cpu_to_be16(fl1id);
6853 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6857 * t4_eth_eq_free - free an Ethernet egress queue
6858 * @adap: the adapter
6859 * @mbox: mailbox to use for the FW command
6860 * @pf: the PF owning the queue
6861 * @vf: the VF owning the queue
6862 * @eqid: egress queue id
6864 * Frees an Ethernet egress queue.
6866 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6867 unsigned int vf, unsigned int eqid)
6869 struct fw_eq_eth_cmd c;
6871 memset(&c, 0, sizeof(c));
6872 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
6873 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6874 FW_EQ_ETH_CMD_PFN_V(pf) |
6875 FW_EQ_ETH_CMD_VFN_V(vf));
6876 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
6877 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
6878 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6882 * t4_ctrl_eq_free - free a control egress queue
6883 * @adap: the adapter
6884 * @mbox: mailbox to use for the FW command
6885 * @pf: the PF owning the queue
6886 * @vf: the VF owning the queue
6887 * @eqid: egress queue id
6889 * Frees a control egress queue.
6891 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6892 unsigned int vf, unsigned int eqid)
6894 struct fw_eq_ctrl_cmd c;
6896 memset(&c, 0, sizeof(c));
6897 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
6898 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6899 FW_EQ_CTRL_CMD_PFN_V(pf) |
6900 FW_EQ_CTRL_CMD_VFN_V(vf));
6901 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
6902 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
6903 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6907 * t4_ofld_eq_free - free an offload egress queue
6908 * @adap: the adapter
6909 * @mbox: mailbox to use for the FW command
6910 * @pf: the PF owning the queue
6911 * @vf: the VF owning the queue
6912 * @eqid: egress queue id
6914 * Frees a control egress queue.
6916 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6917 unsigned int vf, unsigned int eqid)
6919 struct fw_eq_ofld_cmd c;
6921 memset(&c, 0, sizeof(c));
6922 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
6923 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6924 FW_EQ_OFLD_CMD_PFN_V(pf) |
6925 FW_EQ_OFLD_CMD_VFN_V(vf));
6926 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
6927 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
6928 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6932 * t4_handle_fw_rpl - process a FW reply message
6933 * @adap: the adapter
6934 * @rpl: start of the FW message
6936 * Processes a FW message, such as link state change messages.
6938 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
6940 u8 opcode = *(const u8 *)rpl;
6942 if (opcode == FW_PORT_CMD) { /* link/module state change message */
6943 int speed = 0, fc = 0;
6944 const struct fw_port_cmd *p = (void *)rpl;
6945 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
6946 int port = adap->chan_map[chan];
6947 struct port_info *pi = adap2pinfo(adap, port);
6948 struct link_config *lc = &pi->link_cfg;
6949 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
6950 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
6951 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
6953 if (stat & FW_PORT_CMD_RXPAUSE_F)
6955 if (stat & FW_PORT_CMD_TXPAUSE_F)
6957 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
6959 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
6961 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
6963 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
6966 if (link_ok != lc->link_ok || speed != lc->speed ||
6967 fc != lc->fc) { /* something changed */
6968 lc->link_ok = link_ok;
6971 lc->supported = be16_to_cpu(p->u.info.pcap);
6972 t4_os_link_changed(adap, port, link_ok);
6974 if (mod != pi->mod_type) {
6976 t4_os_portmod_changed(adap, port);
6982 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
6986 if (pci_is_pcie(adapter->pdev)) {
6987 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
6988 p->speed = val & PCI_EXP_LNKSTA_CLS;
6989 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
6994 * init_link_config - initialize a link's SW state
6995 * @lc: structure holding the link state
6996 * @caps: link capabilities
6998 * Initializes the SW state maintained for each link, including the link's
6999 * capabilities and default speed/flow-control/autonegotiation settings.
7001 static void init_link_config(struct link_config *lc, unsigned int caps)
7003 lc->supported = caps;
7004 lc->requested_speed = 0;
7006 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7007 if (lc->supported & FW_PORT_CAP_ANEG) {
7008 lc->advertising = lc->supported & ADVERT_MASK;
7009 lc->autoneg = AUTONEG_ENABLE;
7010 lc->requested_fc |= PAUSE_AUTONEG;
7012 lc->advertising = 0;
7013 lc->autoneg = AUTONEG_DISABLE;
7017 #define CIM_PF_NOACCESS 0xeeeeeeee
7019 int t4_wait_dev_ready(void __iomem *regs)
7023 whoami = readl(regs + PL_WHOAMI_A);
7024 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7028 whoami = readl(regs + PL_WHOAMI_A);
7029 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7033 u32 vendor_and_model_id;
7037 static int get_flash_params(struct adapter *adap)
7039 /* Table for non-Numonix supported flash parts. Numonix parts are left
7040 * to the preexisting code. All flash parts have 64KB sectors.
7042 static struct flash_desc supported_flash[] = {
7043 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7049 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7051 ret = sf1_read(adap, 3, 0, 1, &info);
7052 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7056 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7057 if (supported_flash[ret].vendor_and_model_id == info) {
7058 adap->params.sf_size = supported_flash[ret].size_mb;
7059 adap->params.sf_nsec =
7060 adap->params.sf_size / SF_SEC_SIZE;
7064 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7066 info >>= 16; /* log2 of size */
7067 if (info >= 0x14 && info < 0x18)
7068 adap->params.sf_nsec = 1 << (info - 16);
7069 else if (info == 0x18)
7070 adap->params.sf_nsec = 64;
7073 adap->params.sf_size = 1 << info;
7074 adap->params.sf_fw_start =
7075 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7077 if (adap->params.sf_size < FLASH_MIN_SIZE)
7078 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7079 adap->params.sf_size, FLASH_MIN_SIZE);
7083 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7088 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7090 pci_read_config_word(adapter->pdev,
7091 pcie_cap + PCI_EXP_DEVCTL2, &val);
7092 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7094 pci_write_config_word(adapter->pdev,
7095 pcie_cap + PCI_EXP_DEVCTL2, val);
7100 * t4_prep_adapter - prepare SW and HW for operation
7101 * @adapter: the adapter
7102 * @reset: if true perform a HW reset
7104 * Initialize adapter SW state for the various HW modules, set initial
7105 * values for some adapter tunables, take PHYs out of reset, and
7106 * initialize the MDIO interface.
7108 int t4_prep_adapter(struct adapter *adapter)
7114 get_pci_mode(adapter, &adapter->params.pci);
7115 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7117 ret = get_flash_params(adapter);
7119 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7123 /* Retrieve adapter's device ID
7125 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7126 ver = device_id >> 12;
7127 adapter->params.chip = 0;
7130 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7131 adapter->params.arch.sge_fl_db = DBPRIO_F;
7132 adapter->params.arch.mps_tcam_size =
7133 NUM_MPS_CLS_SRAM_L_INSTANCES;
7134 adapter->params.arch.mps_rplc_size = 128;
7135 adapter->params.arch.nchan = NCHAN;
7136 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7137 adapter->params.arch.vfcount = 128;
7140 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7141 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7142 adapter->params.arch.mps_tcam_size =
7143 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7144 adapter->params.arch.mps_rplc_size = 128;
7145 adapter->params.arch.nchan = NCHAN;
7146 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7147 adapter->params.arch.vfcount = 128;
7150 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7151 adapter->params.arch.sge_fl_db = 0;
7152 adapter->params.arch.mps_tcam_size =
7153 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7154 adapter->params.arch.mps_rplc_size = 256;
7155 adapter->params.arch.nchan = 2;
7156 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7157 adapter->params.arch.vfcount = 256;
7160 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7165 adapter->params.cim_la_size = CIMLA_SIZE;
7166 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7169 * Default port for debugging in case we can't reach FW.
7171 adapter->params.nports = 1;
7172 adapter->params.portvec = 1;
7173 adapter->params.vpd.cclk = 50000;
7175 /* Set pci completion timeout value to 4 seconds. */
7176 set_pcie_completion_timeout(adapter, 0xd);
7181 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7182 * @adapter: the adapter
7183 * @qid: the Queue ID
7184 * @qtype: the Ingress or Egress type for @qid
7185 * @user: true if this request is for a user mode queue
7186 * @pbar2_qoffset: BAR2 Queue Offset
7187 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7189 * Returns the BAR2 SGE Queue Registers information associated with the
7190 * indicated Absolute Queue ID. These are passed back in return value
7191 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7192 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7194 * This may return an error which indicates that BAR2 SGE Queue
7195 * registers aren't available. If an error is not returned, then the
7196 * following values are returned:
7198 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7199 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7201 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7202 * require the "Inferred Queue ID" ability may be used. E.g. the
7203 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7204 * then these "Inferred Queue ID" register may not be used.
7206 int t4_bar2_sge_qregs(struct adapter *adapter,
7208 enum t4_bar2_qtype qtype,
7211 unsigned int *pbar2_qid)
7213 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7214 u64 bar2_page_offset, bar2_qoffset;
7215 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7217 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7218 if (!user && is_t4(adapter->params.chip))
7221 /* Get our SGE Page Size parameters.
7223 page_shift = adapter->params.sge.hps + 10;
7224 page_size = 1 << page_shift;
7226 /* Get the right Queues per Page parameters for our Queue.
7228 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7229 ? adapter->params.sge.eq_qpp
7230 : adapter->params.sge.iq_qpp);
7231 qpp_mask = (1 << qpp_shift) - 1;
7233 /* Calculate the basics of the BAR2 SGE Queue register area:
7234 * o The BAR2 page the Queue registers will be in.
7235 * o The BAR2 Queue ID.
7236 * o The BAR2 Queue ID Offset into the BAR2 page.
7238 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7239 bar2_qid = qid & qpp_mask;
7240 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7242 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7243 * hardware will infer the Absolute Queue ID simply from the writes to
7244 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7245 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7246 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7247 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7248 * from the BAR2 Page and BAR2 Queue ID.
7250 * One important censequence of this is that some BAR2 SGE registers
7251 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7252 * there. But other registers synthesize the SGE Queue ID purely
7253 * from the writes to the registers -- the Write Combined Doorbell
7254 * Buffer is a good example. These BAR2 SGE Registers are only
7255 * available for those BAR2 SGE Register areas where the SGE Absolute
7256 * Queue ID can be inferred from simple writes.
7258 bar2_qoffset = bar2_page_offset;
7259 bar2_qinferred = (bar2_qid_offset < page_size);
7260 if (bar2_qinferred) {
7261 bar2_qoffset += bar2_qid_offset;
7265 *pbar2_qoffset = bar2_qoffset;
7266 *pbar2_qid = bar2_qid;
7271 * t4_init_devlog_params - initialize adapter->params.devlog
7272 * @adap: the adapter
7274 * Initialize various fields of the adapter's Firmware Device Log
7275 * Parameters structure.
7277 int t4_init_devlog_params(struct adapter *adap)
7279 struct devlog_params *dparams = &adap->params.devlog;
7281 unsigned int devlog_meminfo;
7282 struct fw_devlog_cmd devlog_cmd;
7285 /* If we're dealing with newer firmware, the Device Log Paramerters
7286 * are stored in a designated register which allows us to access the
7287 * Device Log even if we can't talk to the firmware.
7290 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7292 unsigned int nentries, nentries128;
7294 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7295 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7297 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7298 nentries = (nentries128 + 1) * 128;
7299 dparams->size = nentries * sizeof(struct fw_devlog_e);
7304 /* Otherwise, ask the firmware for it's Device Log Parameters.
7306 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7307 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7308 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7309 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7310 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7316 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7317 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7318 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7319 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7325 * t4_init_sge_params - initialize adap->params.sge
7326 * @adapter: the adapter
7328 * Initialize various fields of the adapter's SGE Parameters structure.
7330 int t4_init_sge_params(struct adapter *adapter)
7332 struct sge_params *sge_params = &adapter->params.sge;
7334 unsigned int s_hps, s_qpp;
7336 /* Extract the SGE Page Size for our PF.
7338 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7339 s_hps = (HOSTPAGESIZEPF0_S +
7340 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7341 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7343 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7345 s_qpp = (QUEUESPERPAGEPF0_S +
7346 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7347 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7348 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7349 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7350 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7356 * t4_init_tp_params - initialize adap->params.tp
7357 * @adap: the adapter
7359 * Initialize various fields of the adapter's TP Parameters structure.
7361 int t4_init_tp_params(struct adapter *adap)
7366 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7367 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7368 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7370 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7371 for (chan = 0; chan < NCHAN; chan++)
7372 adap->params.tp.tx_modq[chan] = chan;
7374 /* Cache the adapter's Compressed Filter Mode and global Incress
7377 if (t4_use_ldst(adap)) {
7378 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7379 TP_VLAN_PRI_MAP_A, 1);
7380 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7381 TP_INGRESS_CONFIG_A, 1);
7383 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7384 &adap->params.tp.vlan_pri_map, 1,
7386 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7387 &adap->params.tp.ingress_config, 1,
7388 TP_INGRESS_CONFIG_A);
7391 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7392 * shift positions of several elements of the Compressed Filter Tuple
7393 * for this adapter which we need frequently ...
7395 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7396 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7397 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7398 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7401 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7402 * represents the presence of an Outer VLAN instead of a VNIC ID.
7404 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7405 adap->params.tp.vnic_shift = -1;
7411 * t4_filter_field_shift - calculate filter field shift
7412 * @adap: the adapter
7413 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7415 * Return the shift position of a filter field within the Compressed
7416 * Filter Tuple. The filter field is specified via its selection bit
7417 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7419 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7421 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7425 if ((filter_mode & filter_sel) == 0)
7428 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7429 switch (filter_mode & sel) {
7431 field_shift += FT_FCOE_W;
7434 field_shift += FT_PORT_W;
7437 field_shift += FT_VNIC_ID_W;
7440 field_shift += FT_VLAN_W;
7443 field_shift += FT_TOS_W;
7446 field_shift += FT_PROTOCOL_W;
7449 field_shift += FT_ETHERTYPE_W;
7452 field_shift += FT_MACMATCH_W;
7455 field_shift += FT_MPSHITTYPE_W;
7457 case FRAGMENTATION_F:
7458 field_shift += FT_FRAGMENTATION_W;
7465 int t4_init_rss_mode(struct adapter *adap, int mbox)
7468 struct fw_rss_vi_config_cmd rvc;
7470 memset(&rvc, 0, sizeof(rvc));
7472 for_each_port(adap, i) {
7473 struct port_info *p = adap2pinfo(adap, i);
7476 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7477 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7478 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7479 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7480 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7483 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7488 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7492 struct fw_port_cmd c;
7493 struct fw_rss_vi_config_cmd rvc;
7495 memset(&c, 0, sizeof(c));
7496 memset(&rvc, 0, sizeof(rvc));
7498 for_each_port(adap, i) {
7499 unsigned int rss_size;
7500 struct port_info *p = adap2pinfo(adap, i);
7502 while ((adap->params.portvec & (1 << j)) == 0)
7505 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7506 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7507 FW_PORT_CMD_PORTID_V(j));
7508 c.action_to_len16 = cpu_to_be32(
7509 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7511 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7515 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7522 p->rss_size = rss_size;
7523 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7524 adap->port[i]->dev_port = j;
7526 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7527 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7528 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7529 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
7530 p->mod_type = FW_PORT_MOD_TYPE_NA;
7533 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7534 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7535 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
7536 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7537 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7540 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7542 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7549 * t4_read_cimq_cfg - read CIM queue configuration
7550 * @adap: the adapter
7551 * @base: holds the queue base addresses in bytes
7552 * @size: holds the queue sizes in bytes
7553 * @thres: holds the queue full thresholds in bytes
7555 * Returns the current configuration of the CIM queues, starting with
7556 * the IBQs, then the OBQs.
7558 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7561 int cim_num_obq = is_t4(adap->params.chip) ?
7562 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7564 for (i = 0; i < CIM_NUM_IBQ; i++) {
7565 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7567 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7568 /* value is in 256-byte units */
7569 *base++ = CIMQBASE_G(v) * 256;
7570 *size++ = CIMQSIZE_G(v) * 256;
7571 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7573 for (i = 0; i < cim_num_obq; i++) {
7574 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7576 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7577 /* value is in 256-byte units */
7578 *base++ = CIMQBASE_G(v) * 256;
7579 *size++ = CIMQSIZE_G(v) * 256;
7584 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7585 * @adap: the adapter
7586 * @qid: the queue index
7587 * @data: where to store the queue contents
7588 * @n: capacity of @data in 32-bit words
7590 * Reads the contents of the selected CIM queue starting at address 0 up
7591 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7592 * error and the number of 32-bit words actually read on success.
7594 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7596 int i, err, attempts;
7598 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7600 if (qid > 5 || (n & 3))
7603 addr = qid * nwords;
7607 /* It might take 3-10ms before the IBQ debug read access is allowed.
7608 * Wait for 1 Sec with a delay of 1 usec.
7612 for (i = 0; i < n; i++, addr++) {
7613 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7615 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7619 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7621 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7626 * t4_read_cim_obq - read the contents of a CIM outbound queue
7627 * @adap: the adapter
7628 * @qid: the queue index
7629 * @data: where to store the queue contents
7630 * @n: capacity of @data in 32-bit words
7632 * Reads the contents of the selected CIM queue starting at address 0 up
7633 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7634 * error and the number of 32-bit words actually read on success.
7636 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7639 unsigned int addr, v, nwords;
7640 int cim_num_obq = is_t4(adap->params.chip) ?
7641 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7643 if ((qid > (cim_num_obq - 1)) || (n & 3))
7646 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7647 QUENUMSELECT_V(qid));
7648 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7650 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7651 nwords = CIMQSIZE_G(v) * 64; /* same */
7655 for (i = 0; i < n; i++, addr++) {
7656 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7658 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7662 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7664 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7669 * t4_cim_read - read a block from CIM internal address space
7670 * @adap: the adapter
7671 * @addr: the start address within the CIM address space
7672 * @n: number of words to read
7673 * @valp: where to store the result
7675 * Reads a block of 4-byte words from the CIM intenal address space.
7677 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7682 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7685 for ( ; !ret && n--; addr += 4) {
7686 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7687 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7690 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7696 * t4_cim_write - write a block into CIM internal address space
7697 * @adap: the adapter
7698 * @addr: the start address within the CIM address space
7699 * @n: number of words to write
7700 * @valp: set of values to write
7702 * Writes a block of 4-byte words into the CIM intenal address space.
7704 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7705 const unsigned int *valp)
7709 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7712 for ( ; !ret && n--; addr += 4) {
7713 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7714 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7715 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7721 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7724 return t4_cim_write(adap, addr, 1, &val);
7728 * t4_cim_read_la - read CIM LA capture buffer
7729 * @adap: the adapter
7730 * @la_buf: where to store the LA data
7731 * @wrptr: the HW write pointer within the capture buffer
7733 * Reads the contents of the CIM LA buffer with the most recent entry at
7734 * the end of the returned data and with the entry at @wrptr first.
7735 * We try to leave the LA in the running state we find it in.
7737 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7740 unsigned int cfg, val, idx;
7742 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7746 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7747 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7752 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7756 idx = UPDBGLAWRPTR_G(val);
7760 for (i = 0; i < adap->params.cim_la_size; i++) {
7761 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7762 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7765 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7768 if (val & UPDBGLARDEN_F) {
7772 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7775 idx = (idx + 1) & UPDBGLARDPTR_M;
7778 if (cfg & UPDBGLAEN_F) {
7779 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7780 cfg & ~UPDBGLARDEN_F);
7788 * t4_tp_read_la - read TP LA capture buffer
7789 * @adap: the adapter
7790 * @la_buf: where to store the LA data
7791 * @wrptr: the HW write pointer within the capture buffer
7793 * Reads the contents of the TP LA buffer with the most recent entry at
7794 * the end of the returned data and with the entry at @wrptr first.
7795 * We leave the LA in the running state we find it in.
7797 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7799 bool last_incomplete;
7800 unsigned int i, cfg, val, idx;
7802 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7803 if (cfg & DBGLAENABLE_F) /* freeze LA */
7804 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7805 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
7807 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
7808 idx = DBGLAWPTR_G(val);
7809 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
7810 if (last_incomplete)
7811 idx = (idx + 1) & DBGLARPTR_M;
7816 val &= ~DBGLARPTR_V(DBGLARPTR_M);
7817 val |= adap->params.tp.la_mask;
7819 for (i = 0; i < TPLA_SIZE; i++) {
7820 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
7821 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
7822 idx = (idx + 1) & DBGLARPTR_M;
7825 /* Wipe out last entry if it isn't valid */
7826 if (last_incomplete)
7827 la_buf[TPLA_SIZE - 1] = ~0ULL;
7829 if (cfg & DBGLAENABLE_F) /* restore running state */
7830 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7831 cfg | adap->params.tp.la_mask);
7834 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
7835 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
7836 * state for more than the Warning Threshold then we'll issue a warning about
7837 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
7838 * appears to be hung every Warning Repeat second till the situation clears.
7839 * If the situation clears, we'll note that as well.
7841 #define SGE_IDMA_WARN_THRESH 1
7842 #define SGE_IDMA_WARN_REPEAT 300
7845 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
7846 * @adapter: the adapter
7847 * @idma: the adapter IDMA Monitor state
7849 * Initialize the state of an SGE Ingress DMA Monitor.
7851 void t4_idma_monitor_init(struct adapter *adapter,
7852 struct sge_idma_monitor_state *idma)
7854 /* Initialize the state variables for detecting an SGE Ingress DMA
7855 * hang. The SGE has internal counters which count up on each clock
7856 * tick whenever the SGE finds its Ingress DMA State Engines in the
7857 * same state they were on the previous clock tick. The clock used is
7858 * the Core Clock so we have a limit on the maximum "time" they can
7859 * record; typically a very small number of seconds. For instance,
7860 * with a 600MHz Core Clock, we can only count up to a bit more than
7861 * 7s. So we'll synthesize a larger counter in order to not run the
7862 * risk of having the "timers" overflow and give us the flexibility to
7863 * maintain a Hung SGE State Machine of our own which operates across
7864 * a longer time frame.
7866 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
7867 idma->idma_stalled[0] = 0;
7868 idma->idma_stalled[1] = 0;
7872 * t4_idma_monitor - monitor SGE Ingress DMA state
7873 * @adapter: the adapter
7874 * @idma: the adapter IDMA Monitor state
7875 * @hz: number of ticks/second
7876 * @ticks: number of ticks since the last IDMA Monitor call
7878 void t4_idma_monitor(struct adapter *adapter,
7879 struct sge_idma_monitor_state *idma,
7882 int i, idma_same_state_cnt[2];
7884 /* Read the SGE Debug Ingress DMA Same State Count registers. These
7885 * are counters inside the SGE which count up on each clock when the
7886 * SGE finds its Ingress DMA State Engines in the same states they
7887 * were in the previous clock. The counters will peg out at
7888 * 0xffffffff without wrapping around so once they pass the 1s
7889 * threshold they'll stay above that till the IDMA state changes.
7891 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
7892 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
7893 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7895 for (i = 0; i < 2; i++) {
7896 u32 debug0, debug11;
7898 /* If the Ingress DMA Same State Counter ("timer") is less
7899 * than 1s, then we can reset our synthesized Stall Timer and
7900 * continue. If we have previously emitted warnings about a
7901 * potential stalled Ingress Queue, issue a note indicating
7902 * that the Ingress Queue has resumed forward progress.
7904 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
7905 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
7906 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
7907 "resumed after %d seconds\n",
7908 i, idma->idma_qid[i],
7909 idma->idma_stalled[i] / hz);
7910 idma->idma_stalled[i] = 0;
7914 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
7915 * domain. The first time we get here it'll be because we
7916 * passed the 1s Threshold; each additional time it'll be
7917 * because the RX Timer Callback is being fired on its regular
7920 * If the stall is below our Potential Hung Ingress Queue
7921 * Warning Threshold, continue.
7923 if (idma->idma_stalled[i] == 0) {
7924 idma->idma_stalled[i] = hz;
7925 idma->idma_warn[i] = 0;
7927 idma->idma_stalled[i] += ticks;
7928 idma->idma_warn[i] -= ticks;
7931 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
7934 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
7936 if (idma->idma_warn[i] > 0)
7938 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
7940 /* Read and save the SGE IDMA State and Queue ID information.
7941 * We do this every time in case it changes across time ...
7942 * can't be too careful ...
7944 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
7945 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7946 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
7948 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
7949 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7950 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
7952 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
7953 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
7954 i, idma->idma_qid[i], idma->idma_state[i],
7955 idma->idma_stalled[i] / hz,
7957 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);