drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
 228 {
 229         dev_err(adap->pdev_dev,
 230                 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 231                 (unsigned long long)t4_read_reg64(adap, data_reg),
 232                 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 233                 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 234                 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 235                 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 236                 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 237                 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 238                 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 239 }
 240
 241 /**
 242  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 243  *      @adap: the adapter
 244  *      @mbox: index of the mailbox to use
 245  *      @cmd: the command to write
 246  *      @size: command length in bytes
 247  *      @rpl: where to optionally store the reply
 248  *      @sleep_ok: if true we may sleep while awaiting command completion
 249  *      @timeout: time to wait for command to finish before timing out
 250  *
 251  *      Sends the given command to FW through the selected mailbox and waits
 252  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 253  *      store the FW's reply to the command.  The command and its optional
 254  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 255  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 256  *      the response.  If sleeping is allowed we use progressive backoff
 257  *      otherwise we spin.
 258  *
 259  *      The return value is 0 on success or a negative errno on failure.  A
 260  *      failure can happen either because we are not able to execute the
 261  *      command or FW executes it but signals an error.  In the latter case
 262  *      the return value is the error code indicated by FW (negated).
 263  */
 264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 265                             int size, void *rpl, bool sleep_ok, int timeout)
 266 {
 267         static const int delay[] = {
 268                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 269         };
 270
 271         u32 v;
 272         u64 res;
 273         int i, ms, delay_idx;
 274         const __be64 *p = cmd;
 275         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 276         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 277
 278         if ((size & 15) || size > MBOX_LEN)
 279                 return -EINVAL;
 280
 281         /*
 282          * If the device is off-line, as in EEH, commands will time out.
 283          * Fail them early so we don't waste time waiting.
 284          */
 285         if (adap->pdev->error_state != pci_channel_io_normal)
 286                 return -EIO;
 287
 288         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 289         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 290                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 291
 292         if (v != MBOX_OWNER_DRV)
 293                 return v ? -EBUSY : -ETIMEDOUT;
 294
 295         for (i = 0; i < size; i += 8)
 296                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 297
 298         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 299         t4_read_reg(adap, ctl_reg);          /* flush write */
 300
 301         delay_idx = 0;
 302         ms = delay[0];
 303
 304         for (i = 0; i < timeout; i += ms) {
 305                 if (sleep_ok) {
 306                         ms = delay[delay_idx];  /* last element may repeat */
 307                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 308                                 delay_idx++;
 309                         msleep(ms);
 310                 } else
 311                         mdelay(ms);
 312
 313                 v = t4_read_reg(adap, ctl_reg);
 314                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 315                         if (!(v & MBMSGVALID_F)) {
 316                                 t4_write_reg(adap, ctl_reg, 0);
 317                                 continue;
 318                         }
 319
 320                         res = t4_read_reg64(adap, data_reg);
 321                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 322                                 fw_asrt(adap, data_reg);
 323                                 res = FW_CMD_RETVAL_V(EIO);
 324                         } else if (rpl) {
 325                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 326                         }
 327
 328                         if (FW_CMD_RETVAL_G((int)res))
 329                                 dump_mbox(adap, mbox, data_reg);
 330                         t4_write_reg(adap, ctl_reg, 0);
 331                         return -FW_CMD_RETVAL_G((int)res);
 332                 }
 333         }
 334
 335         dump_mbox(adap, mbox, data_reg);
 336         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 337                 *(const u8 *)cmd, mbox);
 338         t4_report_fw_error(adap);
 339         return -ETIMEDOUT;
 340 }
 341
 342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 343                     void *rpl, bool sleep_ok)
 344 {
 345         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 346                                        FW_CMD_MAX_TIMEOUT);
 347 }
 348
 349 static int t4_edc_err_read(struct adapter *adap, int idx)
 350 {
 351         u32 edc_ecc_err_addr_reg;
 352         u32 rdata_reg;
 353
 354         if (is_t4(adap->params.chip)) {
 355                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 356                 return 0;
 357         }
 358         if (idx != 0 && idx != 1) {
 359                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 360                 return 0;
 361         }
 362
 363         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 364         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 365
 366         CH_WARN(adap,
 367                 "edc%d err addr 0x%x: 0x%x.\n",
 368                 idx, edc_ecc_err_addr_reg,
 369                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 370         CH_WARN(adap,
 371                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 372                 rdata_reg,
 373                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 374                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 375                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 376                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 377                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 378                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 379                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 380                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 381                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 382
 383         return 0;
 384 }
 385
 386 /**
 387  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 388  *      @adap: the adapter
 389  *      @win: PCI-E Memory Window to use
 390  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 391  *      @addr: address within indicated memory type
 392  *      @len: amount of memory to transfer
 393  *      @hbuf: host memory buffer
 394  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 395  *
 396  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 397  *      firmware memory address and host buffer must be aligned on 32-bit
 398  *      boudaries; the length may be arbitrary.  The memory is transferred as
 399  *      a raw byte sequence from/to the firmware's memory.  If this memory
 400  *      contains data structures which contain multi-byte integers, it's the
 401  *      caller's responsibility to perform appropriate byte order conversions.
 402  */
 403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 404                  u32 len, void *hbuf, int dir)
 405 {
 406         u32 pos, offset, resid, memoffset;
 407         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 408         u32 *buf;
 409
 410         /* Argument sanity checks ...
 411          */
 412         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 413                 return -EINVAL;
 414         buf = (u32 *)hbuf;
 415
 416         /* It's convenient to be able to handle lengths which aren't a
 417          * multiple of 32-bits because we often end up transferring files to
 418          * the firmware.  So we'll handle that by normalizing the length here
 419          * and then handling any residual transfer at the end.
 420          */
 421         resid = len & 0x3;
 422         len -= resid;
 423
 424         /* Offset into the region of memory which is being accessed
 425          * MEM_EDC0 = 0
 426          * MEM_EDC1 = 1
 427          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 428          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 429          */
 430         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 431         if (mtype != MEM_MC1)
 432                 memoffset = (mtype * (edc_size * 1024 * 1024));
 433         else {
 434                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 435                                                       MA_EXT_MEMORY0_BAR_A));
 436                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 437         }
 438
 439         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 440         addr = addr + memoffset;
 441
 442         /* Each PCI-E Memory Window is programmed with a window size -- or
 443          * "aperture" -- which controls the granularity of its mapping onto
 444          * adapter memory.  We need to grab that aperture in order to know
 445          * how to use the specified window.  The window is also programmed
 446          * with the base address of the Memory Window in BAR0's address
 447          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 448          * the address is relative to BAR0.
 449          */
 450         mem_reg = t4_read_reg(adap,
 451                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 452                                                   win));
 453         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 454         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 455         if (is_t4(adap->params.chip))
 456                 mem_base -= adap->t4_bar0;
 457         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 458
 459         /* Calculate our initial PCI-E Memory Window Position and Offset into
 460          * that Window.
 461          */
 462         pos = addr & ~(mem_aperture-1);
 463         offset = addr - pos;
 464
 465         /* Set up initial PCI-E Memory Window to cover the start of our
 466          * transfer.  (Read it back to ensure that changes propagate before we
 467          * attempt to use the new value.)
 468          */
 469         t4_write_reg(adap,
 470                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 471                      pos | win_pf);
 472         t4_read_reg(adap,
 473                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 474
 475         /* Transfer data to/from the adapter as long as there's an integral
 476          * number of 32-bit transfers to complete.
 477          *
 478          * A note on Endianness issues:
 479          *
 480          * The "register" reads and writes below from/to the PCI-E Memory
 481          * Window invoke the standard adapter Big-Endian to PCI-E Link
 482          * Little-Endian "swizzel."  As a result, if we have the following
 483          * data in adapter memory:
 484          *
 485          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 486          *     Address:      i+0  i+1  i+2  i+3
 487          *
 488          * Then a read of the adapter memory via the PCI-E Memory Window
 489          * will yield:
 490          *
 491          *     x = readl(i)
 492          *         31                  0
 493          *         [ b3 | b2 | b1 | b0 ]
 494          *
 495          * If this value is stored into local memory on a Little-Endian system
 496          * it will show up correctly in local memory as:
 497          *
 498          *     ( ..., b0, b1, b2, b3, ... )
 499          *
 500          * But on a Big-Endian system, the store will show up in memory
 501          * incorrectly swizzled as:
 502          *
 503          *     ( ..., b3, b2, b1, b0, ... )
 504          *
 505          * So we need to account for this in the reads and writes to the
 506          * PCI-E Memory Window below by undoing the register read/write
 507          * swizzels.
 508          */
 509         while (len > 0) {
 510                 if (dir == T4_MEMORY_READ)
 511                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 512                                                 mem_base + offset));
 513                 else
 514                         t4_write_reg(adap, mem_base + offset,
 515                                      (__force u32)cpu_to_le32(*buf++));
 516                 offset += sizeof(__be32);
 517                 len -= sizeof(__be32);
 518
 519                 /* If we've reached the end of our current window aperture,
 520                  * move the PCI-E Memory Window on to the next.  Note that
 521                  * doing this here after "len" may be 0 allows us to set up
 522                  * the PCI-E Memory Window for a possible final residual
 523                  * transfer below ...
 524                  */
 525                 if (offset == mem_aperture) {
 526                         pos += mem_aperture;
 527                         offset = 0;
 528                         t4_write_reg(adap,
 529                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 530                                                     win), pos | win_pf);
 531                         t4_read_reg(adap,
 532                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 533                                                     win));
 534                 }
 535         }
 536
 537         /* If the original transfer had a length which wasn't a multiple of
 538          * 32-bits, now's where we need to finish off the transfer of the
 539          * residual amount.  The PCI-E Memory Window has already been moved
 540          * above (if necessary) to cover this final transfer.
 541          */
 542         if (resid) {
 543                 union {
 544                         u32 word;
 545                         char byte[4];
 546                 } last;
 547                 unsigned char *bp;
 548                 int i;
 549
 550                 if (dir == T4_MEMORY_READ) {
 551                         last.word = le32_to_cpu(
 552                                         (__force __le32)t4_read_reg(adap,
 553                                                 mem_base + offset));
 554                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 555                                 bp[i] = last.byte[i];
 556                 } else {
 557                         last.word = *buf;
 558                         for (i = resid; i < 4; i++)
 559                                 last.byte[i] = 0;
 560                         t4_write_reg(adap, mem_base + offset,
 561                                      (__force u32)cpu_to_le32(last.word));
 562                 }
 563         }
 564
 565         return 0;
 566 }
 567
 568 /* Return the specified PCI-E Configuration Space register from our Physical
 569  * Function.  We try first via a Firmware LDST Command since we prefer to let
 570  * the firmware own all of these registers, but if that fails we go for it
 571  * directly ourselves.
 572  */
 573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 574 {
 575         u32 val, ldst_addrspace;
 576
 577         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 578          * retrieve the specified PCI-E Configuration Space register.
 579          */
 580         struct fw_ldst_cmd ldst_cmd;
 581         int ret;
 582
 583         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 584         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 585         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 586                                                FW_CMD_REQUEST_F |
 587                                                FW_CMD_READ_F |
 588                                                ldst_addrspace);
 589         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 590         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 591         ldst_cmd.u.pcie.ctrl_to_fn =
 592                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 593         ldst_cmd.u.pcie.r = reg;
 594
 595         /* If the LDST Command succeeds, return the result, otherwise
 596          * fall through to reading it directly ourselves ...
 597          */
 598         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 599                          &ldst_cmd);
 600         if (ret == 0)
 601                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 602         else
 603                 /* Read the desired Configuration Space register via the PCI-E
 604                  * Backdoor mechanism.
 605                  */
 606                 t4_hw_pci_read_cfg4(adap, reg, &val);
 607         return val;
 608 }
 609
 610 /* Get the window based on base passed to it.
 611  * Window aperture is currently unhandled, but there is no use case for it
 612  * right now
 613  */
 614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 615                          u32 memwin_base)
 616 {
 617         u32 ret;
 618
 619         if (is_t4(adap->params.chip)) {
 620                 u32 bar0;
 621
 622                 /* Truncation intentional: we only read the bottom 32-bits of
 623                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 624                  * mechanism to read BAR0 instead of using
 625                  * pci_resource_start() because we could be operating from
 626                  * within a Virtual Machine which is trapping our accesses to
 627                  * our Configuration Space and we need to set up the PCI-E
 628                  * Memory Window decoders with the actual addresses which will
 629                  * be coming across the PCI-E link.
 630                  */
 631                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 632                 bar0 &= pci_mask;
 633                 adap->t4_bar0 = bar0;
 634
 635                 ret = bar0 + memwin_base;
 636         } else {
 637                 /* For T5, only relative offset inside the PCIe BAR is passed */
 638                 ret = memwin_base;
 639         }
 640         return ret;
 641 }
 642
 643 /* Get the default utility window (win0) used by everyone */
 644 u32 t4_get_util_window(struct adapter *adap)
 645 {
 646         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 647                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 648 }
 649
 650 /* Set up memory window for accessing adapter memory ranges.  (Read
 651  * back MA register to ensure that changes propagate before we attempt
 652  * to use the new values.)
 653  */
 654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 655 {
 656         t4_write_reg(adap,
 657                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 658                      memwin_base | BIR_V(0) |
 659                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 660         t4_read_reg(adap,
 661                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 662 }
 663
 664 /**
 665  *      t4_get_regs_len - return the size of the chips register set
 666  *      @adapter: the adapter
 667  *
 668  *      Returns the size of the chip's BAR0 register space.
 669  */
 670 unsigned int t4_get_regs_len(struct adapter *adapter)
 671 {
 672         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 673
 674         switch (chip_version) {
 675         case CHELSIO_T4:
 676                 return T4_REGMAP_SIZE;
 677
 678         case CHELSIO_T5:
 679         case CHELSIO_T6:
 680                 return T5_REGMAP_SIZE;
 681         }
 682
 683         dev_err(adapter->pdev_dev,
 684                 "Unsupported chip version %d\n", chip_version);
 685         return 0;
 686 }
 687
 688 /**
 689  *      t4_get_regs - read chip registers into provided buffer
 690  *      @adap: the adapter
 691  *      @buf: register buffer
 692  *      @buf_size: size (in bytes) of register buffer
 693  *
 694  *      If the provided register buffer isn't large enough for the chip's
 695  *      full register range, the register dump will be truncated to the
 696  *      register buffer's size.
 697  */
 698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 699 {
 700         static const unsigned int t4_reg_ranges[] = {
 701                 0x1008, 0x1108,
 702                 0x1180, 0x1184,
 703                 0x1190, 0x1194,
 704                 0x11a0, 0x11a4,
 705                 0x11b0, 0x11b4,
 706                 0x11fc, 0x123c,
 707                 0x1300, 0x173c,
 708                 0x1800, 0x18fc,
 709                 0x3000, 0x30d8,
 710                 0x30e0, 0x30e4,
 711                 0x30ec, 0x5910,
 712                 0x5920, 0x5924,
 713                 0x5960, 0x5960,
 714                 0x5968, 0x5968,
 715                 0x5970, 0x5970,
 716                 0x5978, 0x5978,
 717                 0x5980, 0x5980,
 718                 0x5988, 0x5988,
 719                 0x5990, 0x5990,
 720                 0x5998, 0x5998,
 721                 0x59a0, 0x59d4,
 722                 0x5a00, 0x5ae0,
 723                 0x5ae8, 0x5ae8,
 724                 0x5af0, 0x5af0,
 725                 0x5af8, 0x5af8,
 726                 0x6000, 0x6098,
 727                 0x6100, 0x6150,
 728                 0x6200, 0x6208,
 729                 0x6240, 0x6248,
 730                 0x6280, 0x62b0,
 731                 0x62c0, 0x6338,
 732                 0x6370, 0x638c,
 733                 0x6400, 0x643c,
 734                 0x6500, 0x6524,
 735                 0x6a00, 0x6a04,
 736                 0x6a14, 0x6a38,
 737                 0x6a60, 0x6a70,
 738                 0x6a78, 0x6a78,
 739                 0x6b00, 0x6b0c,
 740                 0x6b1c, 0x6b84,
 741                 0x6bf0, 0x6bf8,
 742                 0x6c00, 0x6c0c,
 743                 0x6c1c, 0x6c84,
 744                 0x6cf0, 0x6cf8,
 745                 0x6d00, 0x6d0c,
 746                 0x6d1c, 0x6d84,
 747                 0x6df0, 0x6df8,
 748                 0x6e00, 0x6e0c,
 749                 0x6e1c, 0x6e84,
 750                 0x6ef0, 0x6ef8,
 751                 0x6f00, 0x6f0c,
 752                 0x6f1c, 0x6f84,
 753                 0x6ff0, 0x6ff8,
 754                 0x7000, 0x700c,
 755                 0x701c, 0x7084,
 756                 0x70f0, 0x70f8,
 757                 0x7100, 0x710c,
 758                 0x711c, 0x7184,
 759                 0x71f0, 0x71f8,
 760                 0x7200, 0x720c,
 761                 0x721c, 0x7284,
 762                 0x72f0, 0x72f8,
 763                 0x7300, 0x730c,
 764                 0x731c, 0x7384,
 765                 0x73f0, 0x73f8,
 766                 0x7400, 0x7450,
 767                 0x7500, 0x7530,
 768                 0x7600, 0x760c,
 769                 0x7614, 0x761c,
 770                 0x7680, 0x76cc,
 771                 0x7700, 0x7798,
 772                 0x77c0, 0x77fc,
 773                 0x7900, 0x79fc,
 774                 0x7b00, 0x7b58,
 775                 0x7b60, 0x7b84,
 776                 0x7b8c, 0x7c38,
 777                 0x7d00, 0x7d38,
 778                 0x7d40, 0x7d80,
 779                 0x7d8c, 0x7ddc,
 780                 0x7de4, 0x7e04,
 781                 0x7e10, 0x7e1c,
 782                 0x7e24, 0x7e38,
 783                 0x7e40, 0x7e44,
 784                 0x7e4c, 0x7e78,
 785                 0x7e80, 0x7ea4,
 786                 0x7eac, 0x7edc,
 787                 0x7ee8, 0x7efc,
 788                 0x8dc0, 0x8e04,
 789                 0x8e10, 0x8e1c,
 790                 0x8e30, 0x8e78,
 791                 0x8ea0, 0x8eb8,
 792                 0x8ec0, 0x8f6c,
 793                 0x8fc0, 0x9008,
 794                 0x9010, 0x9058,
 795                 0x9060, 0x9060,
 796                 0x9068, 0x9074,
 797                 0x90fc, 0x90fc,
 798                 0x9400, 0x9408,
 799                 0x9410, 0x9458,
 800                 0x9600, 0x9600,
 801                 0x9608, 0x9638,
 802                 0x9640, 0x96bc,
 803                 0x9800, 0x9808,
 804                 0x9820, 0x983c,
 805                 0x9850, 0x9864,
 806                 0x9c00, 0x9c6c,
 807                 0x9c80, 0x9cec,
 808                 0x9d00, 0x9d6c,
 809                 0x9d80, 0x9dec,
 810                 0x9e00, 0x9e6c,
 811                 0x9e80, 0x9eec,
 812                 0x9f00, 0x9f6c,
 813                 0x9f80, 0x9fec,
 814                 0xd004, 0xd004,
 815                 0xd010, 0xd03c,
 816                 0xdfc0, 0xdfe0,
 817                 0xe000, 0xea7c,
 818                 0xf000, 0x11190,
 819                 0x19040, 0x1906c,
 820                 0x19078, 0x19080,
 821                 0x1908c, 0x190e4,
 822                 0x190f0, 0x190f8,
 823                 0x19100, 0x19110,
 824                 0x19120, 0x19124,
 825                 0x19150, 0x19194,
 826                 0x1919c, 0x191b0,
 827                 0x191d0, 0x191e8,
 828                 0x19238, 0x1924c,
 829                 0x193f8, 0x1943c,
 830                 0x1944c, 0x19474,
 831                 0x19490, 0x194e0,
 832                 0x194f0, 0x194f8,
 833                 0x19800, 0x19c08,
 834                 0x19c10, 0x19c90,
 835                 0x19ca0, 0x19ce4,
 836                 0x19cf0, 0x19d40,
 837                 0x19d50, 0x19d94,
 838                 0x19da0, 0x19de8,
 839                 0x19df0, 0x19e40,
 840                 0x19e50, 0x19e90,
 841                 0x19ea0, 0x19f4c,
 842                 0x1a000, 0x1a004,
 843                 0x1a010, 0x1a06c,
 844                 0x1a0b0, 0x1a0e4,
 845                 0x1a0ec, 0x1a0f4,
 846                 0x1a100, 0x1a108,
 847                 0x1a114, 0x1a120,
 848                 0x1a128, 0x1a130,
 849                 0x1a138, 0x1a138,
 850                 0x1a190, 0x1a1c4,
 851                 0x1a1fc, 0x1a1fc,
 852                 0x1e040, 0x1e04c,
 853                 0x1e284, 0x1e28c,
 854                 0x1e2c0, 0x1e2c0,
 855                 0x1e2e0, 0x1e2e0,
 856                 0x1e300, 0x1e384,
 857                 0x1e3c0, 0x1e3c8,
 858                 0x1e440, 0x1e44c,
 859                 0x1e684, 0x1e68c,
 860                 0x1e6c0, 0x1e6c0,
 861                 0x1e6e0, 0x1e6e0,
 862                 0x1e700, 0x1e784,
 863                 0x1e7c0, 0x1e7c8,
 864                 0x1e840, 0x1e84c,
 865                 0x1ea84, 0x1ea8c,
 866                 0x1eac0, 0x1eac0,
 867                 0x1eae0, 0x1eae0,
 868                 0x1eb00, 0x1eb84,
 869                 0x1ebc0, 0x1ebc8,
 870                 0x1ec40, 0x1ec4c,
 871                 0x1ee84, 0x1ee8c,
 872                 0x1eec0, 0x1eec0,
 873                 0x1eee0, 0x1eee0,
 874                 0x1ef00, 0x1ef84,
 875                 0x1efc0, 0x1efc8,
 876                 0x1f040, 0x1f04c,
 877                 0x1f284, 0x1f28c,
 878                 0x1f2c0, 0x1f2c0,
 879                 0x1f2e0, 0x1f2e0,
 880                 0x1f300, 0x1f384,
 881                 0x1f3c0, 0x1f3c8,
 882                 0x1f440, 0x1f44c,
 883                 0x1f684, 0x1f68c,
 884                 0x1f6c0, 0x1f6c0,
 885                 0x1f6e0, 0x1f6e0,
 886                 0x1f700, 0x1f784,
 887                 0x1f7c0, 0x1f7c8,
 888                 0x1f840, 0x1f84c,
 889                 0x1fa84, 0x1fa8c,
 890                 0x1fac0, 0x1fac0,
 891                 0x1fae0, 0x1fae0,
 892                 0x1fb00, 0x1fb84,
 893                 0x1fbc0, 0x1fbc8,
 894                 0x1fc40, 0x1fc4c,
 895                 0x1fe84, 0x1fe8c,
 896                 0x1fec0, 0x1fec0,
 897                 0x1fee0, 0x1fee0,
 898                 0x1ff00, 0x1ff84,
 899                 0x1ffc0, 0x1ffc8,
 900                 0x20000, 0x2002c,
 901                 0x20100, 0x2013c,
 902                 0x20190, 0x201a0,
 903                 0x201a8, 0x201b8,
 904                 0x201c4, 0x201c8,
 905                 0x20200, 0x20318,
 906                 0x20400, 0x204b4,
 907                 0x204c0, 0x20528,
 908                 0x20540, 0x20614,
 909                 0x21000, 0x21040,
 910                 0x2104c, 0x21060,
 911                 0x210c0, 0x210ec,
 912                 0x21200, 0x21268,
 913                 0x21270, 0x21284,
 914                 0x212fc, 0x21388,
 915                 0x21400, 0x21404,
 916                 0x21500, 0x21500,
 917                 0x21510, 0x21518,
 918                 0x2152c, 0x21530,
 919                 0x2153c, 0x2153c,
 920                 0x21550, 0x21554,
 921                 0x21600, 0x21600,
 922                 0x21608, 0x2161c,
 923                 0x21624, 0x21628,
 924                 0x21630, 0x21634,
 925                 0x2163c, 0x2163c,
 926                 0x21700, 0x2171c,
 927                 0x21780, 0x2178c,
 928                 0x21800, 0x21818,
 929                 0x21820, 0x21828,
 930                 0x21830, 0x21848,
 931                 0x21850, 0x21854,
 932                 0x21860, 0x21868,
 933                 0x21870, 0x21870,
 934                 0x21878, 0x21898,
 935                 0x218a0, 0x218a8,
 936                 0x218b0, 0x218c8,
 937                 0x218d0, 0x218d4,
 938                 0x218e0, 0x218e8,
 939                 0x218f0, 0x218f0,
 940                 0x218f8, 0x21a18,
 941                 0x21a20, 0x21a28,
 942                 0x21a30, 0x21a48,
 943                 0x21a50, 0x21a54,
 944                 0x21a60, 0x21a68,
 945                 0x21a70, 0x21a70,
 946                 0x21a78, 0x21a98,
 947                 0x21aa0, 0x21aa8,
 948                 0x21ab0, 0x21ac8,
 949                 0x21ad0, 0x21ad4,
 950                 0x21ae0, 0x21ae8,
 951                 0x21af0, 0x21af0,
 952                 0x21af8, 0x21c18,
 953                 0x21c20, 0x21c20,
 954                 0x21c28, 0x21c30,
 955                 0x21c38, 0x21c38,
 956                 0x21c80, 0x21c98,
 957                 0x21ca0, 0x21ca8,
 958                 0x21cb0, 0x21cc8,
 959                 0x21cd0, 0x21cd4,
 960                 0x21ce0, 0x21ce8,
 961                 0x21cf0, 0x21cf0,
 962                 0x21cf8, 0x21d7c,
 963                 0x21e00, 0x21e04,
 964                 0x22000, 0x2202c,
 965                 0x22100, 0x2213c,
 966                 0x22190, 0x221a0,
 967                 0x221a8, 0x221b8,
 968                 0x221c4, 0x221c8,
 969                 0x22200, 0x22318,
 970                 0x22400, 0x224b4,
 971                 0x224c0, 0x22528,
 972                 0x22540, 0x22614,
 973                 0x23000, 0x23040,
 974                 0x2304c, 0x23060,
 975                 0x230c0, 0x230ec,
 976                 0x23200, 0x23268,
 977                 0x23270, 0x23284,
 978                 0x232fc, 0x23388,
 979                 0x23400, 0x23404,
 980                 0x23500, 0x23500,
 981                 0x23510, 0x23518,
 982                 0x2352c, 0x23530,
 983                 0x2353c, 0x2353c,
 984                 0x23550, 0x23554,
 985                 0x23600, 0x23600,
 986                 0x23608, 0x2361c,
 987                 0x23624, 0x23628,
 988                 0x23630, 0x23634,
 989                 0x2363c, 0x2363c,
 990                 0x23700, 0x2371c,
 991                 0x23780, 0x2378c,
 992                 0x23800, 0x23818,
 993                 0x23820, 0x23828,
 994                 0x23830, 0x23848,
 995                 0x23850, 0x23854,
 996                 0x23860, 0x23868,
 997                 0x23870, 0x23870,
 998                 0x23878, 0x23898,
 999                 0x238a0, 0x238a8,
1000                 0x238b0, 0x238c8,
1001                 0x238d0, 0x238d4,
1002                 0x238e0, 0x238e8,
1003                 0x238f0, 0x238f0,
1004                 0x238f8, 0x23a18,
1005                 0x23a20, 0x23a28,
1006                 0x23a30, 0x23a48,
1007                 0x23a50, 0x23a54,
1008                 0x23a60, 0x23a68,
1009                 0x23a70, 0x23a70,
1010                 0x23a78, 0x23a98,
1011                 0x23aa0, 0x23aa8,
1012                 0x23ab0, 0x23ac8,
1013                 0x23ad0, 0x23ad4,
1014                 0x23ae0, 0x23ae8,
1015                 0x23af0, 0x23af0,
1016                 0x23af8, 0x23c18,
1017                 0x23c20, 0x23c20,
1018                 0x23c28, 0x23c30,
1019                 0x23c38, 0x23c38,
1020                 0x23c80, 0x23c98,
1021                 0x23ca0, 0x23ca8,
1022                 0x23cb0, 0x23cc8,
1023                 0x23cd0, 0x23cd4,
1024                 0x23ce0, 0x23ce8,
1025                 0x23cf0, 0x23cf0,
1026                 0x23cf8, 0x23d7c,
1027                 0x23e00, 0x23e04,
1028                 0x24000, 0x2402c,
1029                 0x24100, 0x2413c,
1030                 0x24190, 0x241a0,
1031                 0x241a8, 0x241b8,
1032                 0x241c4, 0x241c8,
1033                 0x24200, 0x24318,
1034                 0x24400, 0x244b4,
1035                 0x244c0, 0x24528,
1036                 0x24540, 0x24614,
1037                 0x25000, 0x25040,
1038                 0x2504c, 0x25060,
1039                 0x250c0, 0x250ec,
1040                 0x25200, 0x25268,
1041                 0x25270, 0x25284,
1042                 0x252fc, 0x25388,
1043                 0x25400, 0x25404,
1044                 0x25500, 0x25500,
1045                 0x25510, 0x25518,
1046                 0x2552c, 0x25530,
1047                 0x2553c, 0x2553c,
1048                 0x25550, 0x25554,
1049                 0x25600, 0x25600,
1050                 0x25608, 0x2561c,
1051                 0x25624, 0x25628,
1052                 0x25630, 0x25634,
1053                 0x2563c, 0x2563c,
1054                 0x25700, 0x2571c,
1055                 0x25780, 0x2578c,
1056                 0x25800, 0x25818,
1057                 0x25820, 0x25828,
1058                 0x25830, 0x25848,
1059                 0x25850, 0x25854,
1060                 0x25860, 0x25868,
1061                 0x25870, 0x25870,
1062                 0x25878, 0x25898,
1063                 0x258a0, 0x258a8,
1064                 0x258b0, 0x258c8,
1065                 0x258d0, 0x258d4,
1066                 0x258e0, 0x258e8,
1067                 0x258f0, 0x258f0,
1068                 0x258f8, 0x25a18,
1069                 0x25a20, 0x25a28,
1070                 0x25a30, 0x25a48,
1071                 0x25a50, 0x25a54,
1072                 0x25a60, 0x25a68,
1073                 0x25a70, 0x25a70,
1074                 0x25a78, 0x25a98,
1075                 0x25aa0, 0x25aa8,
1076                 0x25ab0, 0x25ac8,
1077                 0x25ad0, 0x25ad4,
1078                 0x25ae0, 0x25ae8,
1079                 0x25af0, 0x25af0,
1080                 0x25af8, 0x25c18,
1081                 0x25c20, 0x25c20,
1082                 0x25c28, 0x25c30,
1083                 0x25c38, 0x25c38,
1084                 0x25c80, 0x25c98,
1085                 0x25ca0, 0x25ca8,
1086                 0x25cb0, 0x25cc8,
1087                 0x25cd0, 0x25cd4,
1088                 0x25ce0, 0x25ce8,
1089                 0x25cf0, 0x25cf0,
1090                 0x25cf8, 0x25d7c,
1091                 0x25e00, 0x25e04,
1092                 0x26000, 0x2602c,
1093                 0x26100, 0x2613c,
1094                 0x26190, 0x261a0,
1095                 0x261a8, 0x261b8,
1096                 0x261c4, 0x261c8,
1097                 0x26200, 0x26318,
1098                 0x26400, 0x264b4,
1099                 0x264c0, 0x26528,
1100                 0x26540, 0x26614,
1101                 0x27000, 0x27040,
1102                 0x2704c, 0x27060,
1103                 0x270c0, 0x270ec,
1104                 0x27200, 0x27268,
1105                 0x27270, 0x27284,
1106                 0x272fc, 0x27388,
1107                 0x27400, 0x27404,
1108                 0x27500, 0x27500,
1109                 0x27510, 0x27518,
1110                 0x2752c, 0x27530,
1111                 0x2753c, 0x2753c,
1112                 0x27550, 0x27554,
1113                 0x27600, 0x27600,
1114                 0x27608, 0x2761c,
1115                 0x27624, 0x27628,
1116                 0x27630, 0x27634,
1117                 0x2763c, 0x2763c,
1118                 0x27700, 0x2771c,
1119                 0x27780, 0x2778c,
1120                 0x27800, 0x27818,
1121                 0x27820, 0x27828,
1122                 0x27830, 0x27848,
1123                 0x27850, 0x27854,
1124                 0x27860, 0x27868,
1125                 0x27870, 0x27870,
1126                 0x27878, 0x27898,
1127                 0x278a0, 0x278a8,
1128                 0x278b0, 0x278c8,
1129                 0x278d0, 0x278d4,
1130                 0x278e0, 0x278e8,
1131                 0x278f0, 0x278f0,
1132                 0x278f8, 0x27a18,
1133                 0x27a20, 0x27a28,
1134                 0x27a30, 0x27a48,
1135                 0x27a50, 0x27a54,
1136                 0x27a60, 0x27a68,
1137                 0x27a70, 0x27a70,
1138                 0x27a78, 0x27a98,
1139                 0x27aa0, 0x27aa8,
1140                 0x27ab0, 0x27ac8,
1141                 0x27ad0, 0x27ad4,
1142                 0x27ae0, 0x27ae8,
1143                 0x27af0, 0x27af0,
1144                 0x27af8, 0x27c18,
1145                 0x27c20, 0x27c20,
1146                 0x27c28, 0x27c30,
1147                 0x27c38, 0x27c38,
1148                 0x27c80, 0x27c98,
1149                 0x27ca0, 0x27ca8,
1150                 0x27cb0, 0x27cc8,
1151                 0x27cd0, 0x27cd4,
1152                 0x27ce0, 0x27ce8,
1153                 0x27cf0, 0x27cf0,
1154                 0x27cf8, 0x27d7c,
1155                 0x27e00, 0x27e04,
1156         };
1157
1158         static const unsigned int t5_reg_ranges[] = {
1159                 0x1008, 0x10c0,
1160                 0x10cc, 0x10f8,
1161                 0x1100, 0x1100,
1162                 0x110c, 0x1148,
1163                 0x1180, 0x1184,
1164                 0x1190, 0x1194,
1165                 0x11a0, 0x11a4,
1166                 0x11b0, 0x11b4,
1167                 0x11fc, 0x123c,
1168                 0x1280, 0x173c,
1169                 0x1800, 0x18fc,
1170                 0x3000, 0x3028,
1171                 0x3060, 0x30b0,
1172                 0x30b8, 0x30d8,
1173                 0x30e0, 0x30fc,
1174                 0x3140, 0x357c,
1175                 0x35a8, 0x35cc,
1176                 0x35ec, 0x35ec,
1177                 0x3600, 0x5624,
1178                 0x56cc, 0x56ec,
1179                 0x56f4, 0x5720,
1180                 0x5728, 0x575c,
1181                 0x580c, 0x5814,
1182                 0x5890, 0x589c,
1183                 0x58a4, 0x58ac,
1184                 0x58b8, 0x58bc,
1185                 0x5940, 0x59c8,
1186                 0x59d0, 0x59dc,
1187                 0x59fc, 0x5a18,
1188                 0x5a60, 0x5a70,
1189                 0x5a80, 0x5a9c,
1190                 0x5b94, 0x5bfc,
1191                 0x6000, 0x6020,
1192                 0x6028, 0x6040,
1193                 0x6058, 0x609c,
1194                 0x60a8, 0x614c,
1195                 0x7700, 0x7798,
1196                 0x77c0, 0x78fc,
1197                 0x7b00, 0x7b58,
1198                 0x7b60, 0x7b84,
1199                 0x7b8c, 0x7c54,
1200                 0x7d00, 0x7d38,
1201                 0x7d40, 0x7d80,
1202                 0x7d8c, 0x7ddc,
1203                 0x7de4, 0x7e04,
1204                 0x7e10, 0x7e1c,
1205                 0x7e24, 0x7e38,
1206                 0x7e40, 0x7e44,
1207                 0x7e4c, 0x7e78,
1208                 0x7e80, 0x7edc,
1209                 0x7ee8, 0x7efc,
1210                 0x8dc0, 0x8de0,
1211                 0x8df8, 0x8e04,
1212                 0x8e10, 0x8e84,
1213                 0x8ea0, 0x8f84,
1214                 0x8fc0, 0x9058,
1215                 0x9060, 0x9060,
1216                 0x9068, 0x90f8,
1217                 0x9400, 0x9408,
1218                 0x9410, 0x9470,
1219                 0x9600, 0x9600,
1220                 0x9608, 0x9638,
1221                 0x9640, 0x96f4,
1222                 0x9800, 0x9808,
1223                 0x9820, 0x983c,
1224                 0x9850, 0x9864,
1225                 0x9c00, 0x9c6c,
1226                 0x9c80, 0x9cec,
1227                 0x9d00, 0x9d6c,
1228                 0x9d80, 0x9dec,
1229                 0x9e00, 0x9e6c,
1230                 0x9e80, 0x9eec,
1231                 0x9f00, 0x9f6c,
1232                 0x9f80, 0xa020,
1233                 0xd004, 0xd004,
1234                 0xd010, 0xd03c,
1235                 0xdfc0, 0xdfe0,
1236                 0xe000, 0x1106c,
1237                 0x11074, 0x11088,
1238                 0x1109c, 0x1117c,
1239                 0x11190, 0x11204,
1240                 0x19040, 0x1906c,
1241                 0x19078, 0x19080,
1242                 0x1908c, 0x190e8,
1243                 0x190f0, 0x190f8,
1244                 0x19100, 0x19110,
1245                 0x19120, 0x19124,
1246                 0x19150, 0x19194,
1247                 0x1919c, 0x191b0,
1248                 0x191d0, 0x191e8,
1249                 0x19238, 0x19290,
1250                 0x193f8, 0x19428,
1251                 0x19430, 0x19444,
1252                 0x1944c, 0x1946c,
1253                 0x19474, 0x19474,
1254                 0x19490, 0x194cc,
1255                 0x194f0, 0x194f8,
1256                 0x19c00, 0x19c08,
1257                 0x19c10, 0x19c60,
1258                 0x19c94, 0x19ce4,
1259                 0x19cf0, 0x19d40,
1260                 0x19d50, 0x19d94,
1261                 0x19da0, 0x19de8,
1262                 0x19df0, 0x19e10,
1263                 0x19e50, 0x19e90,
1264                 0x19ea0, 0x19f24,
1265                 0x19f34, 0x19f34,
1266                 0x19f40, 0x19f50,
1267                 0x19f90, 0x19fb4,
1268                 0x19fc4, 0x19fe4,
1269                 0x1a000, 0x1a004,
1270                 0x1a010, 0x1a06c,
1271                 0x1a0b0, 0x1a0e4,
1272                 0x1a0ec, 0x1a0f8,
1273                 0x1a100, 0x1a108,
1274                 0x1a114, 0x1a120,
1275                 0x1a128, 0x1a130,
1276                 0x1a138, 0x1a138,
1277                 0x1a190, 0x1a1c4,
1278                 0x1a1fc, 0x1a1fc,
1279                 0x1e008, 0x1e00c,
1280                 0x1e040, 0x1e044,
1281                 0x1e04c, 0x1e04c,
1282                 0x1e284, 0x1e290,
1283                 0x1e2c0, 0x1e2c0,
1284                 0x1e2e0, 0x1e2e0,
1285                 0x1e300, 0x1e384,
1286                 0x1e3c0, 0x1e3c8,
1287                 0x1e408, 0x1e40c,
1288                 0x1e440, 0x1e444,
1289                 0x1e44c, 0x1e44c,
1290                 0x1e684, 0x1e690,
1291                 0x1e6c0, 0x1e6c0,
1292                 0x1e6e0, 0x1e6e0,
1293                 0x1e700, 0x1e784,
1294                 0x1e7c0, 0x1e7c8,
1295                 0x1e808, 0x1e80c,
1296                 0x1e840, 0x1e844,
1297                 0x1e84c, 0x1e84c,
1298                 0x1ea84, 0x1ea90,
1299                 0x1eac0, 0x1eac0,
1300                 0x1eae0, 0x1eae0,
1301                 0x1eb00, 0x1eb84,
1302                 0x1ebc0, 0x1ebc8,
1303                 0x1ec08, 0x1ec0c,
1304                 0x1ec40, 0x1ec44,
1305                 0x1ec4c, 0x1ec4c,
1306                 0x1ee84, 0x1ee90,
1307                 0x1eec0, 0x1eec0,
1308                 0x1eee0, 0x1eee0,
1309                 0x1ef00, 0x1ef84,
1310                 0x1efc0, 0x1efc8,
1311                 0x1f008, 0x1f00c,
1312                 0x1f040, 0x1f044,
1313                 0x1f04c, 0x1f04c,
1314                 0x1f284, 0x1f290,
1315                 0x1f2c0, 0x1f2c0,
1316                 0x1f2e0, 0x1f2e0,
1317                 0x1f300, 0x1f384,
1318                 0x1f3c0, 0x1f3c8,
1319                 0x1f408, 0x1f40c,
1320                 0x1f440, 0x1f444,
1321                 0x1f44c, 0x1f44c,
1322                 0x1f684, 0x1f690,
1323                 0x1f6c0, 0x1f6c0,
1324                 0x1f6e0, 0x1f6e0,
1325                 0x1f700, 0x1f784,
1326                 0x1f7c0, 0x1f7c8,
1327                 0x1f808, 0x1f80c,
1328                 0x1f840, 0x1f844,
1329                 0x1f84c, 0x1f84c,
1330                 0x1fa84, 0x1fa90,
1331                 0x1fac0, 0x1fac0,
1332                 0x1fae0, 0x1fae0,
1333                 0x1fb00, 0x1fb84,
1334                 0x1fbc0, 0x1fbc8,
1335                 0x1fc08, 0x1fc0c,
1336                 0x1fc40, 0x1fc44,
1337                 0x1fc4c, 0x1fc4c,
1338                 0x1fe84, 0x1fe90,
1339                 0x1fec0, 0x1fec0,
1340                 0x1fee0, 0x1fee0,
1341                 0x1ff00, 0x1ff84,
1342                 0x1ffc0, 0x1ffc8,
1343                 0x30000, 0x30030,
1344                 0x30038, 0x30038,
1345                 0x30040, 0x30040,
1346                 0x30100, 0x30144,
1347                 0x30190, 0x301a0,
1348                 0x301a8, 0x301b8,
1349                 0x301c4, 0x301c8,
1350                 0x301d0, 0x301d0,
1351                 0x30200, 0x30318,
1352                 0x30400, 0x304b4,
1353                 0x304c0, 0x3052c,
1354                 0x30540, 0x3061c,
1355                 0x30800, 0x30828,
1356                 0x30834, 0x30834,
1357                 0x308c0, 0x30908,
1358                 0x30910, 0x309ac,
1359                 0x30a00, 0x30a14,
1360                 0x30a1c, 0x30a2c,
1361                 0x30a44, 0x30a50,
1362                 0x30a74, 0x30a74,
1363                 0x30a7c, 0x30afc,
1364                 0x30b08, 0x30c24,
1365                 0x30d00, 0x30d00,
1366                 0x30d08, 0x30d14,
1367                 0x30d1c, 0x30d20,
1368                 0x30d3c, 0x30d3c,
1369                 0x30d48, 0x30d50,
1370                 0x31200, 0x3120c,
1371                 0x31220, 0x31220,
1372                 0x31240, 0x31240,
1373                 0x31600, 0x3160c,
1374                 0x31a00, 0x31a1c,
1375                 0x31e00, 0x31e20,
1376                 0x31e38, 0x31e3c,
1377                 0x31e80, 0x31e80,
1378                 0x31e88, 0x31ea8,
1379                 0x31eb0, 0x31eb4,
1380                 0x31ec8, 0x31ed4,
1381                 0x31fb8, 0x32004,
1382                 0x32200, 0x32200,
1383                 0x32208, 0x32240,
1384                 0x32248, 0x32280,
1385                 0x32288, 0x322c0,
1386                 0x322c8, 0x322fc,
1387                 0x32600, 0x32630,
1388                 0x32a00, 0x32abc,
1389                 0x32b00, 0x32b10,
1390                 0x32b20, 0x32b30,
1391                 0x32b40, 0x32b50,
1392                 0x32b60, 0x32b70,
1393                 0x33000, 0x33028,
1394                 0x33030, 0x33048,
1395                 0x33060, 0x33068,
1396                 0x33070, 0x3309c,
1397                 0x330f0, 0x33128,
1398                 0x33130, 0x33148,
1399                 0x33160, 0x33168,
1400                 0x33170, 0x3319c,
1401                 0x331f0, 0x33238,
1402                 0x33240, 0x33240,
1403                 0x33248, 0x33250,
1404                 0x3325c, 0x33264,
1405                 0x33270, 0x332b8,
1406                 0x332c0, 0x332e4,
1407                 0x332f8, 0x33338,
1408                 0x33340, 0x33340,
1409                 0x33348, 0x33350,
1410                 0x3335c, 0x33364,
1411                 0x33370, 0x333b8,
1412                 0x333c0, 0x333e4,
1413                 0x333f8, 0x33428,
1414                 0x33430, 0x33448,
1415                 0x33460, 0x33468,
1416                 0x33470, 0x3349c,
1417                 0x334f0, 0x33528,
1418                 0x33530, 0x33548,
1419                 0x33560, 0x33568,
1420                 0x33570, 0x3359c,
1421                 0x335f0, 0x33638,
1422                 0x33640, 0x33640,
1423                 0x33648, 0x33650,
1424                 0x3365c, 0x33664,
1425                 0x33670, 0x336b8,
1426                 0x336c0, 0x336e4,
1427                 0x336f8, 0x33738,
1428                 0x33740, 0x33740,
1429                 0x33748, 0x33750,
1430                 0x3375c, 0x33764,
1431                 0x33770, 0x337b8,
1432                 0x337c0, 0x337e4,
1433                 0x337f8, 0x337fc,
1434                 0x33814, 0x33814,
1435                 0x3382c, 0x3382c,
1436                 0x33880, 0x3388c,
1437                 0x338e8, 0x338ec,
1438                 0x33900, 0x33928,
1439                 0x33930, 0x33948,
1440                 0x33960, 0x33968,
1441                 0x33970, 0x3399c,
1442                 0x339f0, 0x33a38,
1443                 0x33a40, 0x33a40,
1444                 0x33a48, 0x33a50,
1445                 0x33a5c, 0x33a64,
1446                 0x33a70, 0x33ab8,
1447                 0x33ac0, 0x33ae4,
1448                 0x33af8, 0x33b10,
1449                 0x33b28, 0x33b28,
1450                 0x33b3c, 0x33b50,
1451                 0x33bf0, 0x33c10,
1452                 0x33c28, 0x33c28,
1453                 0x33c3c, 0x33c50,
1454                 0x33cf0, 0x33cfc,
1455                 0x34000, 0x34030,
1456                 0x34038, 0x34038,
1457                 0x34040, 0x34040,
1458                 0x34100, 0x34144,
1459                 0x34190, 0x341a0,
1460                 0x341a8, 0x341b8,
1461                 0x341c4, 0x341c8,
1462                 0x341d0, 0x341d0,
1463                 0x34200, 0x34318,
1464                 0x34400, 0x344b4,
1465                 0x344c0, 0x3452c,
1466                 0x34540, 0x3461c,
1467                 0x34800, 0x34828,
1468                 0x34834, 0x34834,
1469                 0x348c0, 0x34908,
1470                 0x34910, 0x349ac,
1471                 0x34a00, 0x34a14,
1472                 0x34a1c, 0x34a2c,
1473                 0x34a44, 0x34a50,
1474                 0x34a74, 0x34a74,
1475                 0x34a7c, 0x34afc,
1476                 0x34b08, 0x34c24,
1477                 0x34d00, 0x34d00,
1478                 0x34d08, 0x34d14,
1479                 0x34d1c, 0x34d20,
1480                 0x34d3c, 0x34d3c,
1481                 0x34d48, 0x34d50,
1482                 0x35200, 0x3520c,
1483                 0x35220, 0x35220,
1484                 0x35240, 0x35240,
1485                 0x35600, 0x3560c,
1486                 0x35a00, 0x35a1c,
1487                 0x35e00, 0x35e20,
1488                 0x35e38, 0x35e3c,
1489                 0x35e80, 0x35e80,
1490                 0x35e88, 0x35ea8,
1491                 0x35eb0, 0x35eb4,
1492                 0x35ec8, 0x35ed4,
1493                 0x35fb8, 0x36004,
1494                 0x36200, 0x36200,
1495                 0x36208, 0x36240,
1496                 0x36248, 0x36280,
1497                 0x36288, 0x362c0,
1498                 0x362c8, 0x362fc,
1499                 0x36600, 0x36630,
1500                 0x36a00, 0x36abc,
1501                 0x36b00, 0x36b10,
1502                 0x36b20, 0x36b30,
1503                 0x36b40, 0x36b50,
1504                 0x36b60, 0x36b70,
1505                 0x37000, 0x37028,
1506                 0x37030, 0x37048,
1507                 0x37060, 0x37068,
1508                 0x37070, 0x3709c,
1509                 0x370f0, 0x37128,
1510                 0x37130, 0x37148,
1511                 0x37160, 0x37168,
1512                 0x37170, 0x3719c,
1513                 0x371f0, 0x37238,
1514                 0x37240, 0x37240,
1515                 0x37248, 0x37250,
1516                 0x3725c, 0x37264,
1517                 0x37270, 0x372b8,
1518                 0x372c0, 0x372e4,
1519                 0x372f8, 0x37338,
1520                 0x37340, 0x37340,
1521                 0x37348, 0x37350,
1522                 0x3735c, 0x37364,
1523                 0x37370, 0x373b8,
1524                 0x373c0, 0x373e4,
1525                 0x373f8, 0x37428,
1526                 0x37430, 0x37448,
1527                 0x37460, 0x37468,
1528                 0x37470, 0x3749c,
1529                 0x374f0, 0x37528,
1530                 0x37530, 0x37548,
1531                 0x37560, 0x37568,
1532                 0x37570, 0x3759c,
1533                 0x375f0, 0x37638,
1534                 0x37640, 0x37640,
1535                 0x37648, 0x37650,
1536                 0x3765c, 0x37664,
1537                 0x37670, 0x376b8,
1538                 0x376c0, 0x376e4,
1539                 0x376f8, 0x37738,
1540                 0x37740, 0x37740,
1541                 0x37748, 0x37750,
1542                 0x3775c, 0x37764,
1543                 0x37770, 0x377b8,
1544                 0x377c0, 0x377e4,
1545                 0x377f8, 0x377fc,
1546                 0x37814, 0x37814,
1547                 0x3782c, 0x3782c,
1548                 0x37880, 0x3788c,
1549                 0x378e8, 0x378ec,
1550                 0x37900, 0x37928,
1551                 0x37930, 0x37948,
1552                 0x37960, 0x37968,
1553                 0x37970, 0x3799c,
1554                 0x379f0, 0x37a38,
1555                 0x37a40, 0x37a40,
1556                 0x37a48, 0x37a50,
1557                 0x37a5c, 0x37a64,
1558                 0x37a70, 0x37ab8,
1559                 0x37ac0, 0x37ae4,
1560                 0x37af8, 0x37b10,
1561                 0x37b28, 0x37b28,
1562                 0x37b3c, 0x37b50,
1563                 0x37bf0, 0x37c10,
1564                 0x37c28, 0x37c28,
1565                 0x37c3c, 0x37c50,
1566                 0x37cf0, 0x37cfc,
1567                 0x38000, 0x38030,
1568                 0x38038, 0x38038,
1569                 0x38040, 0x38040,
1570                 0x38100, 0x38144,
1571                 0x38190, 0x381a0,
1572                 0x381a8, 0x381b8,
1573                 0x381c4, 0x381c8,
1574                 0x381d0, 0x381d0,
1575                 0x38200, 0x38318,
1576                 0x38400, 0x384b4,
1577                 0x384c0, 0x3852c,
1578                 0x38540, 0x3861c,
1579                 0x38800, 0x38828,
1580                 0x38834, 0x38834,
1581                 0x388c0, 0x38908,
1582                 0x38910, 0x389ac,
1583                 0x38a00, 0x38a14,
1584                 0x38a1c, 0x38a2c,
1585                 0x38a44, 0x38a50,
1586                 0x38a74, 0x38a74,
1587                 0x38a7c, 0x38afc,
1588                 0x38b08, 0x38c24,
1589                 0x38d00, 0x38d00,
1590                 0x38d08, 0x38d14,
1591                 0x38d1c, 0x38d20,
1592                 0x38d3c, 0x38d3c,
1593                 0x38d48, 0x38d50,
1594                 0x39200, 0x3920c,
1595                 0x39220, 0x39220,
1596                 0x39240, 0x39240,
1597                 0x39600, 0x3960c,
1598                 0x39a00, 0x39a1c,
1599                 0x39e00, 0x39e20,
1600                 0x39e38, 0x39e3c,
1601                 0x39e80, 0x39e80,
1602                 0x39e88, 0x39ea8,
1603                 0x39eb0, 0x39eb4,
1604                 0x39ec8, 0x39ed4,
1605                 0x39fb8, 0x3a004,
1606                 0x3a200, 0x3a200,
1607                 0x3a208, 0x3a240,
1608                 0x3a248, 0x3a280,
1609                 0x3a288, 0x3a2c0,
1610                 0x3a2c8, 0x3a2fc,
1611                 0x3a600, 0x3a630,
1612                 0x3aa00, 0x3aabc,
1613                 0x3ab00, 0x3ab10,
1614                 0x3ab20, 0x3ab30,
1615                 0x3ab40, 0x3ab50,
1616                 0x3ab60, 0x3ab70,
1617                 0x3b000, 0x3b028,
1618                 0x3b030, 0x3b048,
1619                 0x3b060, 0x3b068,
1620                 0x3b070, 0x3b09c,
1621                 0x3b0f0, 0x3b128,
1622                 0x3b130, 0x3b148,
1623                 0x3b160, 0x3b168,
1624                 0x3b170, 0x3b19c,
1625                 0x3b1f0, 0x3b238,
1626                 0x3b240, 0x3b240,
1627                 0x3b248, 0x3b250,
1628                 0x3b25c, 0x3b264,
1629                 0x3b270, 0x3b2b8,
1630                 0x3b2c0, 0x3b2e4,
1631                 0x3b2f8, 0x3b338,
1632                 0x3b340, 0x3b340,
1633                 0x3b348, 0x3b350,
1634                 0x3b35c, 0x3b364,
1635                 0x3b370, 0x3b3b8,
1636                 0x3b3c0, 0x3b3e4,
1637                 0x3b3f8, 0x3b428,
1638                 0x3b430, 0x3b448,
1639                 0x3b460, 0x3b468,
1640                 0x3b470, 0x3b49c,
1641                 0x3b4f0, 0x3b528,
1642                 0x3b530, 0x3b548,
1643                 0x3b560, 0x3b568,
1644                 0x3b570, 0x3b59c,
1645                 0x3b5f0, 0x3b638,
1646                 0x3b640, 0x3b640,
1647                 0x3b648, 0x3b650,
1648                 0x3b65c, 0x3b664,
1649                 0x3b670, 0x3b6b8,
1650                 0x3b6c0, 0x3b6e4,
1651                 0x3b6f8, 0x3b738,
1652                 0x3b740, 0x3b740,
1653                 0x3b748, 0x3b750,
1654                 0x3b75c, 0x3b764,
1655                 0x3b770, 0x3b7b8,
1656                 0x3b7c0, 0x3b7e4,
1657                 0x3b7f8, 0x3b7fc,
1658                 0x3b814, 0x3b814,
1659                 0x3b82c, 0x3b82c,
1660                 0x3b880, 0x3b88c,
1661                 0x3b8e8, 0x3b8ec,
1662                 0x3b900, 0x3b928,
1663                 0x3b930, 0x3b948,
1664                 0x3b960, 0x3b968,
1665                 0x3b970, 0x3b99c,
1666                 0x3b9f0, 0x3ba38,
1667                 0x3ba40, 0x3ba40,
1668                 0x3ba48, 0x3ba50,
1669                 0x3ba5c, 0x3ba64,
1670                 0x3ba70, 0x3bab8,
1671                 0x3bac0, 0x3bae4,
1672                 0x3baf8, 0x3bb10,
1673                 0x3bb28, 0x3bb28,
1674                 0x3bb3c, 0x3bb50,
1675                 0x3bbf0, 0x3bc10,
1676                 0x3bc28, 0x3bc28,
1677                 0x3bc3c, 0x3bc50,
1678                 0x3bcf0, 0x3bcfc,
1679                 0x3c000, 0x3c030,
1680                 0x3c038, 0x3c038,
1681                 0x3c040, 0x3c040,
1682                 0x3c100, 0x3c144,
1683                 0x3c190, 0x3c1a0,
1684                 0x3c1a8, 0x3c1b8,
1685                 0x3c1c4, 0x3c1c8,
1686                 0x3c1d0, 0x3c1d0,
1687                 0x3c200, 0x3c318,
1688                 0x3c400, 0x3c4b4,
1689                 0x3c4c0, 0x3c52c,
1690                 0x3c540, 0x3c61c,
1691                 0x3c800, 0x3c828,
1692                 0x3c834, 0x3c834,
1693                 0x3c8c0, 0x3c908,
1694                 0x3c910, 0x3c9ac,
1695                 0x3ca00, 0x3ca14,
1696                 0x3ca1c, 0x3ca2c,
1697                 0x3ca44, 0x3ca50,
1698                 0x3ca74, 0x3ca74,
1699                 0x3ca7c, 0x3cafc,
1700                 0x3cb08, 0x3cc24,
1701                 0x3cd00, 0x3cd00,
1702                 0x3cd08, 0x3cd14,
1703                 0x3cd1c, 0x3cd20,
1704                 0x3cd3c, 0x3cd3c,
1705                 0x3cd48, 0x3cd50,
1706                 0x3d200, 0x3d20c,
1707                 0x3d220, 0x3d220,
1708                 0x3d240, 0x3d240,
1709                 0x3d600, 0x3d60c,
1710                 0x3da00, 0x3da1c,
1711                 0x3de00, 0x3de20,
1712                 0x3de38, 0x3de3c,
1713                 0x3de80, 0x3de80,
1714                 0x3de88, 0x3dea8,
1715                 0x3deb0, 0x3deb4,
1716                 0x3dec8, 0x3ded4,
1717                 0x3dfb8, 0x3e004,
1718                 0x3e200, 0x3e200,
1719                 0x3e208, 0x3e240,
1720                 0x3e248, 0x3e280,
1721                 0x3e288, 0x3e2c0,
1722                 0x3e2c8, 0x3e2fc,
1723                 0x3e600, 0x3e630,
1724                 0x3ea00, 0x3eabc,
1725                 0x3eb00, 0x3eb10,
1726                 0x3eb20, 0x3eb30,
1727                 0x3eb40, 0x3eb50,
1728                 0x3eb60, 0x3eb70,
1729                 0x3f000, 0x3f028,
1730                 0x3f030, 0x3f048,
1731                 0x3f060, 0x3f068,
1732                 0x3f070, 0x3f09c,
1733                 0x3f0f0, 0x3f128,
1734                 0x3f130, 0x3f148,
1735                 0x3f160, 0x3f168,
1736                 0x3f170, 0x3f19c,
1737                 0x3f1f0, 0x3f238,
1738                 0x3f240, 0x3f240,
1739                 0x3f248, 0x3f250,
1740                 0x3f25c, 0x3f264,
1741                 0x3f270, 0x3f2b8,
1742                 0x3f2c0, 0x3f2e4,
1743                 0x3f2f8, 0x3f338,
1744                 0x3f340, 0x3f340,
1745                 0x3f348, 0x3f350,
1746                 0x3f35c, 0x3f364,
1747                 0x3f370, 0x3f3b8,
1748                 0x3f3c0, 0x3f3e4,
1749                 0x3f3f8, 0x3f428,
1750                 0x3f430, 0x3f448,
1751                 0x3f460, 0x3f468,
1752                 0x3f470, 0x3f49c,
1753                 0x3f4f0, 0x3f528,
1754                 0x3f530, 0x3f548,
1755                 0x3f560, 0x3f568,
1756                 0x3f570, 0x3f59c,
1757                 0x3f5f0, 0x3f638,
1758                 0x3f640, 0x3f640,
1759                 0x3f648, 0x3f650,
1760                 0x3f65c, 0x3f664,
1761                 0x3f670, 0x3f6b8,
1762                 0x3f6c0, 0x3f6e4,
1763                 0x3f6f8, 0x3f738,
1764                 0x3f740, 0x3f740,
1765                 0x3f748, 0x3f750,
1766                 0x3f75c, 0x3f764,
1767                 0x3f770, 0x3f7b8,
1768                 0x3f7c0, 0x3f7e4,
1769                 0x3f7f8, 0x3f7fc,
1770                 0x3f814, 0x3f814,
1771                 0x3f82c, 0x3f82c,
1772                 0x3f880, 0x3f88c,
1773                 0x3f8e8, 0x3f8ec,
1774                 0x3f900, 0x3f928,
1775                 0x3f930, 0x3f948,
1776                 0x3f960, 0x3f968,
1777                 0x3f970, 0x3f99c,
1778                 0x3f9f0, 0x3fa38,
1779                 0x3fa40, 0x3fa40,
1780                 0x3fa48, 0x3fa50,
1781                 0x3fa5c, 0x3fa64,
1782                 0x3fa70, 0x3fab8,
1783                 0x3fac0, 0x3fae4,
1784                 0x3faf8, 0x3fb10,
1785                 0x3fb28, 0x3fb28,
1786                 0x3fb3c, 0x3fb50,
1787                 0x3fbf0, 0x3fc10,
1788                 0x3fc28, 0x3fc28,
1789                 0x3fc3c, 0x3fc50,
1790                 0x3fcf0, 0x3fcfc,
1791                 0x40000, 0x4000c,
1792                 0x40040, 0x40050,
1793                 0x40060, 0x40068,
1794                 0x4007c, 0x4008c,
1795                 0x40094, 0x400b0,
1796                 0x400c0, 0x40144,
1797                 0x40180, 0x4018c,
1798                 0x40200, 0x40254,
1799                 0x40260, 0x40264,
1800                 0x40270, 0x40288,
1801                 0x40290, 0x40298,
1802                 0x402ac, 0x402c8,
1803                 0x402d0, 0x402e0,
1804                 0x402f0, 0x402f0,
1805                 0x40300, 0x4033c,
1806                 0x403f8, 0x403fc,
1807                 0x41304, 0x413c4,
1808                 0x41400, 0x4140c,
1809                 0x41414, 0x4141c,
1810                 0x41480, 0x414d0,
1811                 0x44000, 0x44054,
1812                 0x4405c, 0x44078,
1813                 0x440c0, 0x44174,
1814                 0x44180, 0x441ac,
1815                 0x441b4, 0x441b8,
1816                 0x441c0, 0x44254,
1817                 0x4425c, 0x44278,
1818                 0x442c0, 0x44374,
1819                 0x44380, 0x443ac,
1820                 0x443b4, 0x443b8,
1821                 0x443c0, 0x44454,
1822                 0x4445c, 0x44478,
1823                 0x444c0, 0x44574,
1824                 0x44580, 0x445ac,
1825                 0x445b4, 0x445b8,
1826                 0x445c0, 0x44654,
1827                 0x4465c, 0x44678,
1828                 0x446c0, 0x44774,
1829                 0x44780, 0x447ac,
1830                 0x447b4, 0x447b8,
1831                 0x447c0, 0x44854,
1832                 0x4485c, 0x44878,
1833                 0x448c0, 0x44974,
1834                 0x44980, 0x449ac,
1835                 0x449b4, 0x449b8,
1836                 0x449c0, 0x449fc,
1837                 0x45000, 0x45004,
1838                 0x45010, 0x45030,
1839                 0x45040, 0x45060,
1840                 0x45068, 0x45068,
1841                 0x45080, 0x45084,
1842                 0x450a0, 0x450b0,
1843                 0x45200, 0x45204,
1844                 0x45210, 0x45230,
1845                 0x45240, 0x45260,
1846                 0x45268, 0x45268,
1847                 0x45280, 0x45284,
1848                 0x452a0, 0x452b0,
1849                 0x460c0, 0x460e4,
1850                 0x47000, 0x4703c,
1851                 0x47044, 0x4708c,
1852                 0x47200, 0x47250,
1853                 0x47400, 0x47408,
1854                 0x47414, 0x47420,
1855                 0x47600, 0x47618,
1856                 0x47800, 0x47814,
1857                 0x48000, 0x4800c,
1858                 0x48040, 0x48050,
1859                 0x48060, 0x48068,
1860                 0x4807c, 0x4808c,
1861                 0x48094, 0x480b0,
1862                 0x480c0, 0x48144,
1863                 0x48180, 0x4818c,
1864                 0x48200, 0x48254,
1865                 0x48260, 0x48264,
1866                 0x48270, 0x48288,
1867                 0x48290, 0x48298,
1868                 0x482ac, 0x482c8,
1869                 0x482d0, 0x482e0,
1870                 0x482f0, 0x482f0,
1871                 0x48300, 0x4833c,
1872                 0x483f8, 0x483fc,
1873                 0x49304, 0x493c4,
1874                 0x49400, 0x4940c,
1875                 0x49414, 0x4941c,
1876                 0x49480, 0x494d0,
1877                 0x4c000, 0x4c054,
1878                 0x4c05c, 0x4c078,
1879                 0x4c0c0, 0x4c174,
1880                 0x4c180, 0x4c1ac,
1881                 0x4c1b4, 0x4c1b8,
1882                 0x4c1c0, 0x4c254,
1883                 0x4c25c, 0x4c278,
1884                 0x4c2c0, 0x4c374,
1885                 0x4c380, 0x4c3ac,
1886                 0x4c3b4, 0x4c3b8,
1887                 0x4c3c0, 0x4c454,
1888                 0x4c45c, 0x4c478,
1889                 0x4c4c0, 0x4c574,
1890                 0x4c580, 0x4c5ac,
1891                 0x4c5b4, 0x4c5b8,
1892                 0x4c5c0, 0x4c654,
1893                 0x4c65c, 0x4c678,
1894                 0x4c6c0, 0x4c774,
1895                 0x4c780, 0x4c7ac,
1896                 0x4c7b4, 0x4c7b8,
1897                 0x4c7c0, 0x4c854,
1898                 0x4c85c, 0x4c878,
1899                 0x4c8c0, 0x4c974,
1900                 0x4c980, 0x4c9ac,
1901                 0x4c9b4, 0x4c9b8,
1902                 0x4c9c0, 0x4c9fc,
1903                 0x4d000, 0x4d004,
1904                 0x4d010, 0x4d030,
1905                 0x4d040, 0x4d060,
1906                 0x4d068, 0x4d068,
1907                 0x4d080, 0x4d084,
1908                 0x4d0a0, 0x4d0b0,
1909                 0x4d200, 0x4d204,
1910                 0x4d210, 0x4d230,
1911                 0x4d240, 0x4d260,
1912                 0x4d268, 0x4d268,
1913                 0x4d280, 0x4d284,
1914                 0x4d2a0, 0x4d2b0,
1915                 0x4e0c0, 0x4e0e4,
1916                 0x4f000, 0x4f03c,
1917                 0x4f044, 0x4f08c,
1918                 0x4f200, 0x4f250,
1919                 0x4f400, 0x4f408,
1920                 0x4f414, 0x4f420,
1921                 0x4f600, 0x4f618,
1922                 0x4f800, 0x4f814,
1923                 0x50000, 0x50084,
1924                 0x50090, 0x500cc,
1925                 0x50400, 0x50400,
1926                 0x50800, 0x50884,
1927                 0x50890, 0x508cc,
1928                 0x50c00, 0x50c00,
1929                 0x51000, 0x5101c,
1930                 0x51300, 0x51308,
1931         };
1932
1933         static const unsigned int t6_reg_ranges[] = {
1934                 0x1008, 0x101c,
1935                 0x1024, 0x10a8,
1936                 0x10b4, 0x10f8,
1937                 0x1100, 0x1114,
1938                 0x111c, 0x112c,
1939                 0x1138, 0x113c,
1940                 0x1144, 0x114c,
1941                 0x1180, 0x1184,
1942                 0x1190, 0x1194,
1943                 0x11a0, 0x11a4,
1944                 0x11b0, 0x11b4,
1945                 0x11fc, 0x1258,
1946                 0x1280, 0x12d4,
1947                 0x12d9, 0x12d9,
1948                 0x12de, 0x12de,
1949                 0x12e3, 0x12e3,
1950                 0x12e8, 0x133c,
1951                 0x1800, 0x18fc,
1952                 0x3000, 0x302c,
1953                 0x3060, 0x30b0,
1954                 0x30b8, 0x30d8,
1955                 0x30e0, 0x30fc,
1956                 0x3140, 0x357c,
1957                 0x35a8, 0x35cc,
1958                 0x35ec, 0x35ec,
1959                 0x3600, 0x5624,
1960                 0x56cc, 0x56ec,
1961                 0x56f4, 0x5720,
1962                 0x5728, 0x575c,
1963                 0x580c, 0x5814,
1964                 0x5890, 0x589c,
1965                 0x58a4, 0x58ac,
1966                 0x58b8, 0x58bc,
1967                 0x5940, 0x595c,
1968                 0x5980, 0x598c,
1969                 0x59b0, 0x59c8,
1970                 0x59d0, 0x59dc,
1971                 0x59fc, 0x5a18,
1972                 0x5a60, 0x5a6c,
1973                 0x5a80, 0x5a8c,
1974                 0x5a94, 0x5a9c,
1975                 0x5b94, 0x5bfc,
1976                 0x5c10, 0x5e48,
1977                 0x5e50, 0x5e94,
1978                 0x5ea0, 0x5eb0,
1979                 0x5ec0, 0x5ec0,
1980                 0x5ec8, 0x5ed0,
1981                 0x6000, 0x6020,
1982                 0x6028, 0x6040,
1983                 0x6058, 0x609c,
1984                 0x60a8, 0x619c,
1985                 0x7700, 0x7798,
1986                 0x77c0, 0x7880,
1987                 0x78cc, 0x78fc,
1988                 0x7b00, 0x7b58,
1989                 0x7b60, 0x7b84,
1990                 0x7b8c, 0x7c54,
1991                 0x7d00, 0x7d38,
1992                 0x7d40, 0x7d84,
1993                 0x7d8c, 0x7ddc,
1994                 0x7de4, 0x7e04,
1995                 0x7e10, 0x7e1c,
1996                 0x7e24, 0x7e38,
1997                 0x7e40, 0x7e44,
1998                 0x7e4c, 0x7e78,
1999                 0x7e80, 0x7edc,
2000                 0x7ee8, 0x7efc,
2001                 0x8dc0, 0x8de4,
2002                 0x8df8, 0x8e04,
2003                 0x8e10, 0x8e84,
2004                 0x8ea0, 0x8f88,
2005                 0x8fb8, 0x9058,
2006                 0x9060, 0x9060,
2007                 0x9068, 0x90f8,
2008                 0x9100, 0x9124,
2009                 0x9400, 0x9470,
2010                 0x9600, 0x9600,
2011                 0x9608, 0x9638,
2012                 0x9640, 0x9704,
2013                 0x9710, 0x971c,
2014                 0x9800, 0x9808,
2015                 0x9820, 0x983c,
2016                 0x9850, 0x9864,
2017                 0x9c00, 0x9c6c,
2018                 0x9c80, 0x9cec,
2019                 0x9d00, 0x9d6c,
2020                 0x9d80, 0x9dec,
2021                 0x9e00, 0x9e6c,
2022                 0x9e80, 0x9eec,
2023                 0x9f00, 0x9f6c,
2024                 0x9f80, 0xa020,
2025                 0xd004, 0xd03c,
2026                 0xd100, 0xd118,
2027                 0xd200, 0xd214,
2028                 0xd220, 0xd234,
2029                 0xd240, 0xd254,
2030                 0xd260, 0xd274,
2031                 0xd280, 0xd294,
2032                 0xd2a0, 0xd2b4,
2033                 0xd2c0, 0xd2d4,
2034                 0xd2e0, 0xd2f4,
2035                 0xd300, 0xd31c,
2036                 0xdfc0, 0xdfe0,
2037                 0xe000, 0xf008,
2038                 0x11000, 0x11014,
2039                 0x11048, 0x1106c,
2040                 0x11074, 0x11088,
2041                 0x11098, 0x11120,
2042                 0x1112c, 0x1117c,
2043                 0x11190, 0x112e0,
2044                 0x11300, 0x1130c,
2045                 0x12000, 0x1206c,
2046                 0x19040, 0x1906c,
2047                 0x19078, 0x19080,
2048                 0x1908c, 0x190e8,
2049                 0x190f0, 0x190f8,
2050                 0x19100, 0x19110,
2051                 0x19120, 0x19124,
2052                 0x19150, 0x19194,
2053                 0x1919c, 0x191b0,
2054                 0x191d0, 0x191e8,
2055                 0x19238, 0x19290,
2056                 0x192a4, 0x192b0,
2057                 0x192bc, 0x192bc,
2058                 0x19348, 0x1934c,
2059                 0x193f8, 0x19418,
2060                 0x19420, 0x19428,
2061                 0x19430, 0x19444,
2062                 0x1944c, 0x1946c,
2063                 0x19474, 0x19474,
2064                 0x19490, 0x194cc,
2065                 0x194f0, 0x194f8,
2066                 0x19c00, 0x19c48,
2067                 0x19c50, 0x19c80,
2068                 0x19c94, 0x19c98,
2069                 0x19ca0, 0x19cbc,
2070                 0x19ce4, 0x19ce4,
2071                 0x19cf0, 0x19cf8,
2072                 0x19d00, 0x19d28,
2073                 0x19d50, 0x19d78,
2074                 0x19d94, 0x19d98,
2075                 0x19da0, 0x19dc8,
2076                 0x19df0, 0x19e10,
2077                 0x19e50, 0x19e6c,
2078                 0x19ea0, 0x19ebc,
2079                 0x19ec4, 0x19ef4,
2080                 0x19f04, 0x19f2c,
2081                 0x19f34, 0x19f34,
2082                 0x19f40, 0x19f50,
2083                 0x19f90, 0x19fac,
2084                 0x19fc4, 0x19fc8,
2085                 0x19fd0, 0x19fe4,
2086                 0x1a000, 0x1a004,
2087                 0x1a010, 0x1a06c,
2088                 0x1a0b0, 0x1a0e4,
2089                 0x1a0ec, 0x1a0f8,
2090                 0x1a100, 0x1a108,
2091                 0x1a114, 0x1a120,
2092                 0x1a128, 0x1a130,
2093                 0x1a138, 0x1a138,
2094                 0x1a190, 0x1a1c4,
2095                 0x1a1fc, 0x1a1fc,
2096                 0x1e008, 0x1e00c,
2097                 0x1e040, 0x1e044,
2098                 0x1e04c, 0x1e04c,
2099                 0x1e284, 0x1e290,
2100                 0x1e2c0, 0x1e2c0,
2101                 0x1e2e0, 0x1e2e0,
2102                 0x1e300, 0x1e384,
2103                 0x1e3c0, 0x1e3c8,
2104                 0x1e408, 0x1e40c,
2105                 0x1e440, 0x1e444,
2106                 0x1e44c, 0x1e44c,
2107                 0x1e684, 0x1e690,
2108                 0x1e6c0, 0x1e6c0,
2109                 0x1e6e0, 0x1e6e0,
2110                 0x1e700, 0x1e784,
2111                 0x1e7c0, 0x1e7c8,
2112                 0x1e808, 0x1e80c,
2113                 0x1e840, 0x1e844,
2114                 0x1e84c, 0x1e84c,
2115                 0x1ea84, 0x1ea90,
2116                 0x1eac0, 0x1eac0,
2117                 0x1eae0, 0x1eae0,
2118                 0x1eb00, 0x1eb84,
2119                 0x1ebc0, 0x1ebc8,
2120                 0x1ec08, 0x1ec0c,
2121                 0x1ec40, 0x1ec44,
2122                 0x1ec4c, 0x1ec4c,
2123                 0x1ee84, 0x1ee90,
2124                 0x1eec0, 0x1eec0,
2125                 0x1eee0, 0x1eee0,
2126                 0x1ef00, 0x1ef84,
2127                 0x1efc0, 0x1efc8,
2128                 0x1f008, 0x1f00c,
2129                 0x1f040, 0x1f044,
2130                 0x1f04c, 0x1f04c,
2131                 0x1f284, 0x1f290,
2132                 0x1f2c0, 0x1f2c0,
2133                 0x1f2e0, 0x1f2e0,
2134                 0x1f300, 0x1f384,
2135                 0x1f3c0, 0x1f3c8,
2136                 0x1f408, 0x1f40c,
2137                 0x1f440, 0x1f444,
2138                 0x1f44c, 0x1f44c,
2139                 0x1f684, 0x1f690,
2140                 0x1f6c0, 0x1f6c0,
2141                 0x1f6e0, 0x1f6e0,
2142                 0x1f700, 0x1f784,
2143                 0x1f7c0, 0x1f7c8,
2144                 0x1f808, 0x1f80c,
2145                 0x1f840, 0x1f844,
2146                 0x1f84c, 0x1f84c,
2147                 0x1fa84, 0x1fa90,
2148                 0x1fac0, 0x1fac0,
2149                 0x1fae0, 0x1fae0,
2150                 0x1fb00, 0x1fb84,
2151                 0x1fbc0, 0x1fbc8,
2152                 0x1fc08, 0x1fc0c,
2153                 0x1fc40, 0x1fc44,
2154                 0x1fc4c, 0x1fc4c,
2155                 0x1fe84, 0x1fe90,
2156                 0x1fec0, 0x1fec0,
2157                 0x1fee0, 0x1fee0,
2158                 0x1ff00, 0x1ff84,
2159                 0x1ffc0, 0x1ffc8,
2160                 0x30000, 0x30030,
2161                 0x30038, 0x30038,
2162                 0x30040, 0x30040,
2163                 0x30048, 0x30048,
2164                 0x30050, 0x30050,
2165                 0x3005c, 0x30060,
2166                 0x30068, 0x30068,
2167                 0x30070, 0x30070,
2168                 0x30100, 0x30168,
2169                 0x30190, 0x301a0,
2170                 0x301a8, 0x301b8,
2171                 0x301c4, 0x301c8,
2172                 0x301d0, 0x301d0,
2173                 0x30200, 0x30320,
2174                 0x30400, 0x304b4,
2175                 0x304c0, 0x3052c,
2176                 0x30540, 0x3061c,
2177                 0x30800, 0x308a0,
2178                 0x308c0, 0x30908,
2179                 0x30910, 0x309b8,
2180                 0x30a00, 0x30a04,
2181                 0x30a0c, 0x30a14,
2182                 0x30a1c, 0x30a2c,
2183                 0x30a44, 0x30a50,
2184                 0x30a74, 0x30a74,
2185                 0x30a7c, 0x30afc,
2186                 0x30b08, 0x30c24,
2187                 0x30d00, 0x30d14,
2188                 0x30d1c, 0x30d3c,
2189                 0x30d44, 0x30d4c,
2190                 0x30d54, 0x30d74,
2191                 0x30d7c, 0x30d7c,
2192                 0x30de0, 0x30de0,
2193                 0x30e00, 0x30ed4,
2194                 0x30f00, 0x30fa4,
2195                 0x30fc0, 0x30fc4,
2196                 0x31000, 0x31004,
2197                 0x31080, 0x310fc,
2198                 0x31208, 0x31220,
2199                 0x3123c, 0x31254,
2200                 0x31300, 0x31300,
2201                 0x31308, 0x3131c,
2202                 0x31338, 0x3133c,
2203                 0x31380, 0x31380,
2204                 0x31388, 0x313a8,
2205                 0x313b4, 0x313b4,
2206                 0x31400, 0x31420,
2207                 0x31438, 0x3143c,
2208                 0x31480, 0x31480,
2209                 0x314a8, 0x314a8,
2210                 0x314b0, 0x314b4,
2211                 0x314c8, 0x314d4,
2212                 0x31a40, 0x31a4c,
2213                 0x31af0, 0x31b20,
2214                 0x31b38, 0x31b3c,
2215                 0x31b80, 0x31b80,
2216                 0x31ba8, 0x31ba8,
2217                 0x31bb0, 0x31bb4,
2218                 0x31bc8, 0x31bd4,
2219                 0x32140, 0x3218c,
2220                 0x321f0, 0x321f4,
2221                 0x32200, 0x32200,
2222                 0x32218, 0x32218,
2223                 0x32400, 0x32400,
2224                 0x32408, 0x3241c,
2225                 0x32618, 0x32620,
2226                 0x32664, 0x32664,
2227                 0x326a8, 0x326a8,
2228                 0x326ec, 0x326ec,
2229                 0x32a00, 0x32abc,
2230                 0x32b00, 0x32b38,
2231                 0x32b40, 0x32b58,
2232                 0x32b60, 0x32b78,
2233                 0x32c00, 0x32c00,
2234                 0x32c08, 0x32c3c,
2235                 0x32e00, 0x32e2c,
2236                 0x32f00, 0x32f2c,
2237                 0x33000, 0x3302c,
2238                 0x33034, 0x33050,
2239                 0x33058, 0x33058,
2240                 0x33060, 0x3308c,
2241                 0x3309c, 0x330ac,
2242                 0x330c0, 0x330c0,
2243                 0x330c8, 0x330d0,
2244                 0x330d8, 0x330e0,
2245                 0x330ec, 0x3312c,
2246                 0x33134, 0x33150,
2247                 0x33158, 0x33158,
2248                 0x33160, 0x3318c,
2249                 0x3319c, 0x331ac,
2250                 0x331c0, 0x331c0,
2251                 0x331c8, 0x331d0,
2252                 0x331d8, 0x331e0,
2253                 0x331ec, 0x33290,
2254                 0x33298, 0x332c4,
2255                 0x332e4, 0x33390,
2256                 0x33398, 0x333c4,
2257                 0x333e4, 0x3342c,
2258                 0x33434, 0x33450,
2259                 0x33458, 0x33458,
2260                 0x33460, 0x3348c,
2261                 0x3349c, 0x334ac,
2262                 0x334c0, 0x334c0,
2263                 0x334c8, 0x334d0,
2264                 0x334d8, 0x334e0,
2265                 0x334ec, 0x3352c,
2266                 0x33534, 0x33550,
2267                 0x33558, 0x33558,
2268                 0x33560, 0x3358c,
2269                 0x3359c, 0x335ac,
2270                 0x335c0, 0x335c0,
2271                 0x335c8, 0x335d0,
2272                 0x335d8, 0x335e0,
2273                 0x335ec, 0x33690,
2274                 0x33698, 0x336c4,
2275                 0x336e4, 0x33790,
2276                 0x33798, 0x337c4,
2277                 0x337e4, 0x337fc,
2278                 0x33814, 0x33814,
2279                 0x33854, 0x33868,
2280                 0x33880, 0x3388c,
2281                 0x338c0, 0x338d0,
2282                 0x338e8, 0x338ec,
2283                 0x33900, 0x3392c,
2284                 0x33934, 0x33950,
2285                 0x33958, 0x33958,
2286                 0x33960, 0x3398c,
2287                 0x3399c, 0x339ac,
2288                 0x339c0, 0x339c0,
2289                 0x339c8, 0x339d0,
2290                 0x339d8, 0x339e0,
2291                 0x339ec, 0x33a90,
2292                 0x33a98, 0x33ac4,
2293                 0x33ae4, 0x33b10,
2294                 0x33b24, 0x33b28,
2295                 0x33b38, 0x33b50,
2296                 0x33bf0, 0x33c10,
2297                 0x33c24, 0x33c28,
2298                 0x33c38, 0x33c50,
2299                 0x33cf0, 0x33cfc,
2300                 0x34000, 0x34030,
2301                 0x34038, 0x34038,
2302                 0x34040, 0x34040,
2303                 0x34048, 0x34048,
2304                 0x34050, 0x34050,
2305                 0x3405c, 0x34060,
2306                 0x34068, 0x34068,
2307                 0x34070, 0x34070,
2308                 0x34100, 0x34168,
2309                 0x34190, 0x341a0,
2310                 0x341a8, 0x341b8,
2311                 0x341c4, 0x341c8,
2312                 0x341d0, 0x341d0,
2313                 0x34200, 0x34320,
2314                 0x34400, 0x344b4,
2315                 0x344c0, 0x3452c,
2316                 0x34540, 0x3461c,
2317                 0x34800, 0x348a0,
2318                 0x348c0, 0x34908,
2319                 0x34910, 0x349b8,
2320                 0x34a00, 0x34a04,
2321                 0x34a0c, 0x34a14,
2322                 0x34a1c, 0x34a2c,
2323                 0x34a44, 0x34a50,
2324                 0x34a74, 0x34a74,
2325                 0x34a7c, 0x34afc,
2326                 0x34b08, 0x34c24,
2327                 0x34d00, 0x34d14,
2328                 0x34d1c, 0x34d3c,
2329                 0x34d44, 0x34d4c,
2330                 0x34d54, 0x34d74,
2331                 0x34d7c, 0x34d7c,
2332                 0x34de0, 0x34de0,
2333                 0x34e00, 0x34ed4,
2334                 0x34f00, 0x34fa4,
2335                 0x34fc0, 0x34fc4,
2336                 0x35000, 0x35004,
2337                 0x35080, 0x350fc,
2338                 0x35208, 0x35220,
2339                 0x3523c, 0x35254,
2340                 0x35300, 0x35300,
2341                 0x35308, 0x3531c,
2342                 0x35338, 0x3533c,
2343                 0x35380, 0x35380,
2344                 0x35388, 0x353a8,
2345                 0x353b4, 0x353b4,
2346                 0x35400, 0x35420,
2347                 0x35438, 0x3543c,
2348                 0x35480, 0x35480,
2349                 0x354a8, 0x354a8,
2350                 0x354b0, 0x354b4,
2351                 0x354c8, 0x354d4,
2352                 0x35a40, 0x35a4c,
2353                 0x35af0, 0x35b20,
2354                 0x35b38, 0x35b3c,
2355                 0x35b80, 0x35b80,
2356                 0x35ba8, 0x35ba8,
2357                 0x35bb0, 0x35bb4,
2358                 0x35bc8, 0x35bd4,
2359                 0x36140, 0x3618c,
2360                 0x361f0, 0x361f4,
2361                 0x36200, 0x36200,
2362                 0x36218, 0x36218,
2363                 0x36400, 0x36400,
2364                 0x36408, 0x3641c,
2365                 0x36618, 0x36620,
2366                 0x36664, 0x36664,
2367                 0x366a8, 0x366a8,
2368                 0x366ec, 0x366ec,
2369                 0x36a00, 0x36abc,
2370                 0x36b00, 0x36b38,
2371                 0x36b40, 0x36b58,
2372                 0x36b60, 0x36b78,
2373                 0x36c00, 0x36c00,
2374                 0x36c08, 0x36c3c,
2375                 0x36e00, 0x36e2c,
2376                 0x36f00, 0x36f2c,
2377                 0x37000, 0x3702c,
2378                 0x37034, 0x37050,
2379                 0x37058, 0x37058,
2380                 0x37060, 0x3708c,
2381                 0x3709c, 0x370ac,
2382                 0x370c0, 0x370c0,
2383                 0x370c8, 0x370d0,
2384                 0x370d8, 0x370e0,
2385                 0x370ec, 0x3712c,
2386                 0x37134, 0x37150,
2387                 0x37158, 0x37158,
2388                 0x37160, 0x3718c,
2389                 0x3719c, 0x371ac,
2390                 0x371c0, 0x371c0,
2391                 0x371c8, 0x371d0,
2392                 0x371d8, 0x371e0,
2393                 0x371ec, 0x37290,
2394                 0x37298, 0x372c4,
2395                 0x372e4, 0x37390,
2396                 0x37398, 0x373c4,
2397                 0x373e4, 0x3742c,
2398                 0x37434, 0x37450,
2399                 0x37458, 0x37458,
2400                 0x37460, 0x3748c,
2401                 0x3749c, 0x374ac,
2402                 0x374c0, 0x374c0,
2403                 0x374c8, 0x374d0,
2404                 0x374d8, 0x374e0,
2405                 0x374ec, 0x3752c,
2406                 0x37534, 0x37550,
2407                 0x37558, 0x37558,
2408                 0x37560, 0x3758c,
2409                 0x3759c, 0x375ac,
2410                 0x375c0, 0x375c0,
2411                 0x375c8, 0x375d0,
2412                 0x375d8, 0x375e0,
2413                 0x375ec, 0x37690,
2414                 0x37698, 0x376c4,
2415                 0x376e4, 0x37790,
2416                 0x37798, 0x377c4,
2417                 0x377e4, 0x377fc,
2418                 0x37814, 0x37814,
2419                 0x37854, 0x37868,
2420                 0x37880, 0x3788c,
2421                 0x378c0, 0x378d0,
2422                 0x378e8, 0x378ec,
2423                 0x37900, 0x3792c,
2424                 0x37934, 0x37950,
2425                 0x37958, 0x37958,
2426                 0x37960, 0x3798c,
2427                 0x3799c, 0x379ac,
2428                 0x379c0, 0x379c0,
2429                 0x379c8, 0x379d0,
2430                 0x379d8, 0x379e0,
2431                 0x379ec, 0x37a90,
2432                 0x37a98, 0x37ac4,
2433                 0x37ae4, 0x37b10,
2434                 0x37b24, 0x37b28,
2435                 0x37b38, 0x37b50,
2436                 0x37bf0, 0x37c10,
2437                 0x37c24, 0x37c28,
2438                 0x37c38, 0x37c50,
2439                 0x37cf0, 0x37cfc,
2440                 0x40040, 0x40040,
2441                 0x40080, 0x40084,
2442                 0x40100, 0x40100,
2443                 0x40140, 0x401bc,
2444                 0x40200, 0x40214,
2445                 0x40228, 0x40228,
2446                 0x40240, 0x40258,
2447                 0x40280, 0x40280,
2448                 0x40304, 0x40304,
2449                 0x40330, 0x4033c,
2450                 0x41304, 0x413b8,
2451                 0x413c0, 0x413c8,
2452                 0x413d0, 0x413dc,
2453                 0x413f0, 0x413f0,
2454                 0x41400, 0x4140c,
2455                 0x41414, 0x4141c,
2456                 0x41480, 0x414d0,
2457                 0x44000, 0x4407c,
2458                 0x440c0, 0x441ac,
2459                 0x441b4, 0x4427c,
2460                 0x442c0, 0x443ac,
2461                 0x443b4, 0x4447c,
2462                 0x444c0, 0x445ac,
2463                 0x445b4, 0x4467c,
2464                 0x446c0, 0x447ac,
2465                 0x447b4, 0x4487c,
2466                 0x448c0, 0x449ac,
2467                 0x449b4, 0x44a7c,
2468                 0x44ac0, 0x44bac,
2469                 0x44bb4, 0x44c7c,
2470                 0x44cc0, 0x44dac,
2471                 0x44db4, 0x44e7c,
2472                 0x44ec0, 0x44fac,
2473                 0x44fb4, 0x4507c,
2474                 0x450c0, 0x451ac,
2475                 0x451b4, 0x451fc,
2476                 0x45800, 0x45804,
2477                 0x45810, 0x45830,
2478                 0x45840, 0x45860,
2479                 0x45868, 0x45868,
2480                 0x45880, 0x45884,
2481                 0x458a0, 0x458b0,
2482                 0x45a00, 0x45a04,
2483                 0x45a10, 0x45a30,
2484                 0x45a40, 0x45a60,
2485                 0x45a68, 0x45a68,
2486                 0x45a80, 0x45a84,
2487                 0x45aa0, 0x45ab0,
2488                 0x460c0, 0x460e4,
2489                 0x47000, 0x4703c,
2490                 0x47044, 0x4708c,
2491                 0x47200, 0x47250,
2492                 0x47400, 0x47408,
2493                 0x47414, 0x47420,
2494                 0x47600, 0x47618,
2495                 0x47800, 0x47814,
2496                 0x47820, 0x4782c,
2497                 0x50000, 0x50084,
2498                 0x50090, 0x500cc,
2499                 0x50300, 0x50384,
2500                 0x50400, 0x50400,
2501                 0x50800, 0x50884,
2502                 0x50890, 0x508cc,
2503                 0x50b00, 0x50b84,
2504                 0x50c00, 0x50c00,
2505                 0x51000, 0x51020,
2506                 0x51028, 0x510b0,
2507                 0x51300, 0x51324,
2508         };
2509
2510         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511         const unsigned int *reg_ranges;
2512         int reg_ranges_size, range;
2513         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2514
2515         /* Select the right set of register ranges to dump depending on the
2516          * adapter chip type.
2517          */
2518         switch (chip_version) {
2519         case CHELSIO_T4:
2520                 reg_ranges = t4_reg_ranges;
2521                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2522                 break;
2523
2524         case CHELSIO_T5:
2525                 reg_ranges = t5_reg_ranges;
2526                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2527                 break;
2528
2529         case CHELSIO_T6:
2530                 reg_ranges = t6_reg_ranges;
2531                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2532                 break;
2533
2534         default:
2535                 dev_err(adap->pdev_dev,
2536                         "Unsupported chip version %d\n", chip_version);
2537                 return;
2538         }
2539
2540         /* Clear the register buffer and insert the appropriate register
2541          * values selected by the above register ranges.
2542          */
2543         memset(buf, 0, buf_size);
2544         for (range = 0; range < reg_ranges_size; range += 2) {
2545                 unsigned int reg = reg_ranges[range];
2546                 unsigned int last_reg = reg_ranges[range + 1];
2547                 u32 *bufp = (u32 *)((char *)buf + reg);
2548
2549                 /* Iterate across the register range filling in the register
2550                  * buffer but don't write past the end of the register buffer.
2551                  */
2552                 while (reg <= last_reg && bufp < buf_end) {
2553                         *bufp++ = t4_read_reg(adap, reg);
2554                         reg += sizeof(u32);
2555                 }
2556         }
2557 }
2558
2559 #define EEPROM_STAT_ADDR   0x7bfc
2560 #define VPD_SIZE           0x800
2561 #define VPD_BASE           0x400
2562 #define VPD_BASE_OLD       0
2563 #define VPD_LEN            1024
2564 #define CHELSIO_VPD_UNIQUE_ID 0x82
2565
2566 /**
2567  *      t4_seeprom_wp - enable/disable EEPROM write protection
2568  *      @adapter: the adapter
2569  *      @enable: whether to enable or disable write protection
2570  *
2571  *      Enables or disables write protection on the serial EEPROM.
2572  */
2573 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2574 {
2575         unsigned int v = enable ? 0xc : 0;
2576         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2577         return ret < 0 ? ret : 0;
2578 }
2579
2580 /**
2581  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2582  *      @adapter: adapter to read
2583  *      @p: where to store the parameters
2584  *
2585  *      Reads card parameters stored in VPD EEPROM.
2586  */
2587 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2588 {
2589         int i, ret = 0, addr;
2590         int ec, sn, pn, na;
2591         u8 *vpd, csum;
2592         unsigned int vpdr_len, kw_offset, id_len;
2593
2594         vpd = vmalloc(VPD_LEN);
2595         if (!vpd)
2596                 return -ENOMEM;
2597
2598         /* We have two VPD data structures stored in the adapter VPD area.
2599          * By default, Linux calculates the size of the VPD area by traversing
2600          * the first VPD area at offset 0x0, so we need to tell the OS what
2601          * our real VPD size is.
2602          */
2603         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2604         if (ret < 0)
2605                 goto out;
2606
2607         /* Card information normally starts at VPD_BASE but early cards had
2608          * it at 0.
2609          */
2610         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2611         if (ret < 0)
2612                 goto out;
2613
2614         /* The VPD shall have a unique identifier specified by the PCI SIG.
2615          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2616          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2617          * is expected to automatically put this entry at the
2618          * beginning of the VPD.
2619          */
2620         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2621
2622         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2623         if (ret < 0)
2624                 goto out;
2625
2626         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2627                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2628                 ret = -EINVAL;
2629                 goto out;
2630         }
2631
2632         id_len = pci_vpd_lrdt_size(vpd);
2633         if (id_len > ID_LEN)
2634                 id_len = ID_LEN;
2635
2636         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2637         if (i < 0) {
2638                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2639                 ret = -EINVAL;
2640                 goto out;
2641         }
2642
2643         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2644         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2645         if (vpdr_len + kw_offset > VPD_LEN) {
2646                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2647                 ret = -EINVAL;
2648                 goto out;
2649         }
2650
2651 #define FIND_VPD_KW(var, name) do { \
2652         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2653         if (var < 0) { \
2654                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2655                 ret = -EINVAL; \
2656                 goto out; \
2657         } \
2658         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2659 } while (0)
2660
2661         FIND_VPD_KW(i, "RV");
2662         for (csum = 0; i >= 0; i--)
2663                 csum += vpd[i];
2664
2665         if (csum) {
2666                 dev_err(adapter->pdev_dev,
2667                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2668                 ret = -EINVAL;
2669                 goto out;
2670         }
2671
2672         FIND_VPD_KW(ec, "EC");
2673         FIND_VPD_KW(sn, "SN");
2674         FIND_VPD_KW(pn, "PN");
2675         FIND_VPD_KW(na, "NA");
2676 #undef FIND_VPD_KW
2677
2678         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2679         strim(p->id);
2680         memcpy(p->ec, vpd + ec, EC_LEN);
2681         strim(p->ec);
2682         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2683         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2684         strim(p->sn);
2685         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2686         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2687         strim(p->pn);
2688         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2689         strim((char *)p->na);
2690
2691 out:
2692         vfree(vpd);
2693         return ret;
2694 }
2695
2696 /**
2697  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2698  *      @adapter: adapter to read
2699  *      @p: where to store the parameters
2700  *
2701  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2702  *      Clock.  This can only be called after a connection to the firmware
2703  *      is established.
2704  */
2705 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2706 {
2707         u32 cclk_param, cclk_val;
2708         int ret;
2709
2710         /* Grab the raw VPD parameters.
2711          */
2712         ret = t4_get_raw_vpd_params(adapter, p);
2713         if (ret)
2714                 return ret;
2715
2716         /* Ask firmware for the Core Clock since it knows how to translate the
2717          * Reference Clock ('V2') VPD field into a Core Clock value ...
2718          */
2719         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2720                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2721         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2722                               1, &cclk_param, &cclk_val);
2723
2724         if (ret)
2725                 return ret;
2726         p->cclk = cclk_val;
2727
2728         return 0;
2729 }
2730
2731 /* serial flash and firmware constants */
2732 enum {
2733         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2734
2735         /* flash command opcodes */
2736         SF_PROG_PAGE    = 2,          /* program page */
2737         SF_WR_DISABLE   = 4,          /* disable writes */
2738         SF_RD_STATUS    = 5,          /* read status register */
2739         SF_WR_ENABLE    = 6,          /* enable writes */
2740         SF_RD_DATA_FAST = 0xb,        /* read flash */
2741         SF_RD_ID        = 0x9f,       /* read ID */
2742         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2743
2744         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2745 };
2746
2747 /**
2748  *      sf1_read - read data from the serial flash
2749  *      @adapter: the adapter
2750  *      @byte_cnt: number of bytes to read
2751  *      @cont: whether another operation will be chained
2752  *      @lock: whether to lock SF for PL access only
2753  *      @valp: where to store the read data
2754  *
2755  *      Reads up to 4 bytes of data from the serial flash.  The location of
2756  *      the read needs to be specified prior to calling this by issuing the
2757  *      appropriate commands to the serial flash.
2758  */
2759 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2760                     int lock, u32 *valp)
2761 {
2762         int ret;
2763
2764         if (!byte_cnt || byte_cnt > 4)
2765                 return -EINVAL;
2766         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2767                 return -EBUSY;
2768         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2769                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2770         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2771         if (!ret)
2772                 *valp = t4_read_reg(adapter, SF_DATA_A);
2773         return ret;
2774 }
2775
2776 /**
2777  *      sf1_write - write data to the serial flash
2778  *      @adapter: the adapter
2779  *      @byte_cnt: number of bytes to write
2780  *      @cont: whether another operation will be chained
2781  *      @lock: whether to lock SF for PL access only
2782  *      @val: value to write
2783  *
2784  *      Writes up to 4 bytes of data to the serial flash.  The location of
2785  *      the write needs to be specified prior to calling this by issuing the
2786  *      appropriate commands to the serial flash.
2787  */
2788 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2789                      int lock, u32 val)
2790 {
2791         if (!byte_cnt || byte_cnt > 4)
2792                 return -EINVAL;
2793         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2794                 return -EBUSY;
2795         t4_write_reg(adapter, SF_DATA_A, val);
2796         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2797                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2798         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2799 }
2800
2801 /**
2802  *      flash_wait_op - wait for a flash operation to complete
2803  *      @adapter: the adapter
2804  *      @attempts: max number of polls of the status register
2805  *      @delay: delay between polls in ms
2806  *
2807  *      Wait for a flash operation to complete by polling the status register.
2808  */
2809 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2810 {
2811         int ret;
2812         u32 status;
2813
2814         while (1) {
2815                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2816                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2817                         return ret;
2818                 if (!(status & 1))
2819                         return 0;
2820                 if (--attempts == 0)
2821                         return -EAGAIN;
2822                 if (delay)
2823                         msleep(delay);
2824         }
2825 }
2826
2827 /**
2828  *      t4_read_flash - read words from serial flash
2829  *      @adapter: the adapter
2830  *      @addr: the start address for the read
2831  *      @nwords: how many 32-bit words to read
2832  *      @data: where to store the read data
2833  *      @byte_oriented: whether to store data as bytes or as words
2834  *
2835  *      Read the specified number of 32-bit words from the serial flash.
2836  *      If @byte_oriented is set the read data is stored as a byte array
2837  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2838  *      natural endianness.
2839  */
2840 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2841                   unsigned int nwords, u32 *data, int byte_oriented)
2842 {
2843         int ret;
2844
2845         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2846                 return -EINVAL;
2847
2848         addr = swab32(addr) | SF_RD_DATA_FAST;
2849
2850         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2851             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2852                 return ret;
2853
2854         for ( ; nwords; nwords--, data++) {
2855                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2856                 if (nwords == 1)
2857                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2858                 if (ret)
2859                         return ret;
2860                 if (byte_oriented)
2861                         *data = (__force __u32)(cpu_to_be32(*data));
2862         }
2863         return 0;
2864 }
2865
2866 /**
2867  *      t4_write_flash - write up to a page of data to the serial flash
2868  *      @adapter: the adapter
2869  *      @addr: the start address to write
2870  *      @n: length of data to write in bytes
2871  *      @data: the data to write
2872  *
2873  *      Writes up to a page of data (256 bytes) to the serial flash starting
2874  *      at the given address.  All the data must be written to the same page.
2875  */
2876 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2877                           unsigned int n, const u8 *data)
2878 {
2879         int ret;
2880         u32 buf[64];
2881         unsigned int i, c, left, val, offset = addr & 0xff;
2882
2883         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2884                 return -EINVAL;
2885
2886         val = swab32(addr) | SF_PROG_PAGE;
2887
2888         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2889             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2890                 goto unlock;
2891
2892         for (left = n; left; left -= c) {
2893                 c = min(left, 4U);
2894                 for (val = 0, i = 0; i < c; ++i)
2895                         val = (val << 8) + *data++;
2896
2897                 ret = sf1_write(adapter, c, c != left, 1, val);
2898                 if (ret)
2899                         goto unlock;
2900         }
2901         ret = flash_wait_op(adapter, 8, 1);
2902         if (ret)
2903                 goto unlock;
2904
2905         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2906
2907         /* Read the page to verify the write succeeded */
2908         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2909         if (ret)
2910                 return ret;
2911
2912         if (memcmp(data - n, (u8 *)buf + offset, n)) {
2913                 dev_err(adapter->pdev_dev,
2914                         "failed to correctly write the flash page at %#x\n",
2915                         addr);
2916                 return -EIO;
2917         }
2918         return 0;
2919
2920 unlock:
2921         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2922         return ret;
2923 }
2924
2925 /**
2926  *      t4_get_fw_version - read the firmware version
2927  *      @adapter: the adapter
2928  *      @vers: where to place the version
2929  *
2930  *      Reads the FW version from flash.
2931  */
2932 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2933 {
2934         return t4_read_flash(adapter, FLASH_FW_START +
2935                              offsetof(struct fw_hdr, fw_ver), 1,
2936                              vers, 0);
2937 }
2938
2939 /**
2940  *      t4_get_bs_version - read the firmware bootstrap version
2941  *      @adapter: the adapter
2942  *      @vers: where to place the version
2943  *
2944  *      Reads the FW Bootstrap version from flash.
2945  */
2946 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2947 {
2948         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2949                              offsetof(struct fw_hdr, fw_ver), 1,
2950                              vers, 0);
2951 }
2952
2953 /**
2954  *      t4_get_tp_version - read the TP microcode version
2955  *      @adapter: the adapter
2956  *      @vers: where to place the version
2957  *
2958  *      Reads the TP microcode version from flash.
2959  */
2960 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2961 {
2962         return t4_read_flash(adapter, FLASH_FW_START +
2963                              offsetof(struct fw_hdr, tp_microcode_ver),
2964                              1, vers, 0);
2965 }
2966
2967 /**
2968  *      t4_get_exprom_version - return the Expansion ROM version (if any)
2969  *      @adapter: the adapter
2970  *      @vers: where to place the version
2971  *
2972  *      Reads the Expansion ROM header from FLASH and returns the version
2973  *      number (if present) through the @vers return value pointer.  We return
2974  *      this in the Firmware Version Format since it's convenient.  Return
2975  *      0 on success, -ENOENT if no Expansion ROM is present.
2976  */
2977 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2978 {
2979         struct exprom_header {
2980                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2981                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2982         } *hdr;
2983         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2984                                            sizeof(u32))];
2985         int ret;
2986
2987         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2988                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2989                             0);
2990         if (ret)
2991                 return ret;
2992
2993         hdr = (struct exprom_header *)exprom_header_buf;
2994         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2995                 return -ENOENT;
2996
2997         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2998                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2999                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3000                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3001         return 0;
3002 }
3003
3004 /**
3005  *      t4_check_fw_version - check if the FW is supported with this driver
3006  *      @adap: the adapter
3007  *
3008  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3009  *      if there's exact match, a negative error if the version could not be
3010  *      read or there's a major version mismatch
3011  */
3012 int t4_check_fw_version(struct adapter *adap)
3013 {
3014         int i, ret, major, minor, micro;
3015         int exp_major, exp_minor, exp_micro;
3016         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3017
3018         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3019         /* Try multiple times before returning error */
3020         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3021                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3022
3023         if (ret)
3024                 return ret;
3025
3026         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3027         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3028         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3029
3030         switch (chip_version) {
3031         case CHELSIO_T4:
3032                 exp_major = T4FW_MIN_VERSION_MAJOR;
3033                 exp_minor = T4FW_MIN_VERSION_MINOR;
3034                 exp_micro = T4FW_MIN_VERSION_MICRO;
3035                 break;
3036         case CHELSIO_T5:
3037                 exp_major = T5FW_MIN_VERSION_MAJOR;
3038                 exp_minor = T5FW_MIN_VERSION_MINOR;
3039                 exp_micro = T5FW_MIN_VERSION_MICRO;
3040                 break;
3041         case CHELSIO_T6:
3042                 exp_major = T6FW_MIN_VERSION_MAJOR;
3043                 exp_minor = T6FW_MIN_VERSION_MINOR;
3044                 exp_micro = T6FW_MIN_VERSION_MICRO;
3045                 break;
3046         default:
3047                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3048                         adap->chip);
3049                 return -EINVAL;
3050         }
3051
3052         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3053             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3054                 dev_err(adap->pdev_dev,
3055                         "Card has firmware version %u.%u.%u, minimum "
3056                         "supported firmware is %u.%u.%u.\n", major, minor,
3057                         micro, exp_major, exp_minor, exp_micro);
3058                 return -EFAULT;
3059         }
3060         return 0;
3061 }
3062
3063 /* Is the given firmware API compatible with the one the driver was compiled
3064  * with?
3065  */
3066 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3067 {
3068
3069         /* short circuit if it's the exact same firmware version */
3070         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3071                 return 1;
3072
3073 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3074         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3075             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3076                 return 1;
3077 #undef SAME_INTF
3078
3079         return 0;
3080 }
3081
3082 /* The firmware in the filesystem is usable, but should it be installed?
3083  * This routine explains itself in detail if it indicates the filesystem
3084  * firmware should be installed.
3085  */
3086 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3087                                 int k, int c)
3088 {
3089         const char *reason;
3090
3091         if (!card_fw_usable) {
3092                 reason = "incompatible or unusable";
3093                 goto install;
3094         }
3095
3096         if (k > c) {
3097                 reason = "older than the version supported with this driver";
3098                 goto install;
3099         }
3100
3101         return 0;
3102
3103 install:
3104         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3105                 "installing firmware %u.%u.%u.%u on card.\n",
3106                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3107                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3108                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3109                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3110
3111         return 1;
3112 }
3113
3114 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3115                const u8 *fw_data, unsigned int fw_size,
3116                struct fw_hdr *card_fw, enum dev_state state,
3117                int *reset)
3118 {
3119         int ret, card_fw_usable, fs_fw_usable;
3120         const struct fw_hdr *fs_fw;
3121         const struct fw_hdr *drv_fw;
3122
3123         drv_fw = &fw_info->fw_hdr;
3124
3125         /* Read the header of the firmware on the card */
3126         ret = -t4_read_flash(adap, FLASH_FW_START,
3127                             sizeof(*card_fw) / sizeof(uint32_t),
3128                             (uint32_t *)card_fw, 1);
3129         if (ret == 0) {
3130                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3131         } else {
3132                 dev_err(adap->pdev_dev,
3133                         "Unable to read card's firmware header: %d\n", ret);
3134                 card_fw_usable = 0;
3135         }
3136
3137         if (fw_data != NULL) {
3138                 fs_fw = (const void *)fw_data;
3139                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3140         } else {
3141                 fs_fw = NULL;
3142                 fs_fw_usable = 0;
3143         }
3144
3145         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3146             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3147                 /* Common case: the firmware on the card is an exact match and
3148                  * the filesystem one is an exact match too, or the filesystem
3149                  * one is absent/incompatible.
3150                  */
3151         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3152                    should_install_fs_fw(adap, card_fw_usable,
3153                                         be32_to_cpu(fs_fw->fw_ver),
3154                                         be32_to_cpu(card_fw->fw_ver))) {
3155                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3156                                      fw_size, 0);
3157                 if (ret != 0) {
3158                         dev_err(adap->pdev_dev,
3159                                 "failed to install firmware: %d\n", ret);
3160                         goto bye;
3161                 }
3162
3163                 /* Installed successfully, update the cached header too. */
3164                 *card_fw = *fs_fw;
3165                 card_fw_usable = 1;
3166                 *reset = 0;     /* already reset as part of load_fw */
3167         }
3168
3169         if (!card_fw_usable) {
3170                 uint32_t d, c, k;
3171
3172                 d = be32_to_cpu(drv_fw->fw_ver);
3173                 c = be32_to_cpu(card_fw->fw_ver);
3174                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3175
3176                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3177                         "chip state %d, "
3178                         "driver compiled with %d.%d.%d.%d, "
3179                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3180                         state,
3181                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3182                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3183                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3184                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3185                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3186                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3187                 ret = EINVAL;
3188                 goto bye;
3189         }
3190
3191         /* We're using whatever's on the card and it's known to be good. */
3192         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3193         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3194
3195 bye:
3196         return ret;
3197 }
3198
3199 /**
3200  *      t4_flash_erase_sectors - erase a range of flash sectors
3201  *      @adapter: the adapter
3202  *      @start: the first sector to erase
3203  *      @end: the last sector to erase
3204  *
3205  *      Erases the sectors in the given inclusive range.
3206  */
3207 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3208 {
3209         int ret = 0;
3210
3211         if (end >= adapter->params.sf_nsec)
3212                 return -EINVAL;
3213
3214         while (start <= end) {
3215                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3216                     (ret = sf1_write(adapter, 4, 0, 1,
3217                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3218                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3219                         dev_err(adapter->pdev_dev,
3220                                 "erase of flash sector %d failed, error %d\n",
3221                                 start, ret);
3222                         break;
3223                 }
3224                 start++;
3225         }
3226         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3227         return ret;
3228 }
3229
3230 /**
3231  *      t4_flash_cfg_addr - return the address of the flash configuration file
3232  *      @adapter: the adapter
3233  *
3234  *      Return the address within the flash where the Firmware Configuration
3235  *      File is stored.
3236  */
3237 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3238 {
3239         if (adapter->params.sf_size == 0x100000)
3240                 return FLASH_FPGA_CFG_START;
3241         else
3242                 return FLASH_CFG_START;
3243 }
3244
3245 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3246  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3247  * and emit an error message for mismatched firmware to save our caller the
3248  * effort ...
3249  */
3250 static bool t4_fw_matches_chip(const struct adapter *adap,
3251                                const struct fw_hdr *hdr)
3252 {
3253         /* The expression below will return FALSE for any unsupported adapter
3254          * which will keep us "honest" in the future ...
3255          */
3256         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3257             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3258             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3259                 return true;
3260
3261         dev_err(adap->pdev_dev,
3262                 "FW image (%d) is not suitable for this adapter (%d)\n",
3263                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3264         return false;
3265 }
3266
3267 /**
3268  *      t4_load_fw - download firmware
3269  *      @adap: the adapter
3270  *      @fw_data: the firmware image to write
3271  *      @size: image size
3272  *
3273  *      Write the supplied firmware image to the card's serial flash.
3274  */
3275 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3276 {
3277         u32 csum;
3278         int ret, addr;
3279         unsigned int i;
3280         u8 first_page[SF_PAGE_SIZE];
3281         const __be32 *p = (const __be32 *)fw_data;
3282         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3283         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3284         unsigned int fw_img_start = adap->params.sf_fw_start;
3285         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3286
3287         if (!size) {
3288                 dev_err(adap->pdev_dev, "FW image has no data\n");
3289                 return -EINVAL;
3290         }
3291         if (size & 511) {
3292                 dev_err(adap->pdev_dev,
3293                         "FW image size not multiple of 512 bytes\n");
3294                 return -EINVAL;
3295         }
3296         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3297                 dev_err(adap->pdev_dev,
3298                         "FW image size differs from size in FW header\n");
3299                 return -EINVAL;
3300         }
3301         if (size > FW_MAX_SIZE) {
3302                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3303                         FW_MAX_SIZE);
3304                 return -EFBIG;
3305         }
3306         if (!t4_fw_matches_chip(adap, hdr))
3307                 return -EINVAL;
3308
3309         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3310                 csum += be32_to_cpu(p[i]);
3311
3312         if (csum != 0xffffffff) {
3313                 dev_err(adap->pdev_dev,
3314                         "corrupted firmware image, checksum %#x\n", csum);
3315                 return -EINVAL;
3316         }
3317
3318         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3319         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3320         if (ret)
3321                 goto out;
3322
3323         /*
3324          * We write the correct version at the end so the driver can see a bad
3325          * version if the FW write fails.  Start by writing a copy of the
3326          * first page with a bad version.
3327          */
3328         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3329         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3330         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3331         if (ret)
3332                 goto out;
3333
3334         addr = fw_img_start;
3335         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3336                 addr += SF_PAGE_SIZE;
3337                 fw_data += SF_PAGE_SIZE;
3338                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3339                 if (ret)
3340                         goto out;
3341         }
3342
3343         ret = t4_write_flash(adap,
3344                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3345                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3346 out:
3347         if (ret)
3348                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3349                         ret);
3350         else
3351                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3352         return ret;
3353 }
3354
3355 /**
3356  *      t4_phy_fw_ver - return current PHY firmware version
3357  *      @adap: the adapter
3358  *      @phy_fw_ver: return value buffer for PHY firmware version
3359  *
3360  *      Returns the current version of external PHY firmware on the
3361  *      adapter.
3362  */
3363 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3364 {
3365         u32 param, val;
3366         int ret;
3367
3368         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3369                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3370                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3371                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3372         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3373                               &param, &val);
3374         if (ret < 0)
3375                 return ret;
3376         *phy_fw_ver = val;
3377         return 0;
3378 }
3379
3380 /**
3381  *      t4_load_phy_fw - download port PHY firmware
3382  *      @adap: the adapter
3383  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3384  *      @win_lock: the lock to use to guard the memory copy
3385  *      @phy_fw_version: function to check PHY firmware versions
3386  *      @phy_fw_data: the PHY firmware image to write
3387  *      @phy_fw_size: image size
3388  *
3389  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3390  *      @phy_fw_version is supplied, then it will be used to determine if
3391  *      it's necessary to perform the transfer by comparing the version
3392  *      of any existing adapter PHY firmware with that of the passed in
3393  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3394  *      around the call to t4_memory_rw() which transfers the PHY firmware
3395  *      to the adapter.
3396  *
3397  *      A negative error number will be returned if an error occurs.  If
3398  *      version number support is available and there's no need to upgrade
3399  *      the firmware, 0 will be returned.  If firmware is successfully
3400  *      transferred to the adapter, 1 will be retured.
3401  *
3402  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3403  *      a result, a RESET of the adapter would cause that RAM to lose its
3404  *      contents.  Thus, loading PHY firmware on such adapters must happen
3405  *      after any FW_RESET_CMDs ...
3406  */
3407 int t4_load_phy_fw(struct adapter *adap,
3408                    int win, spinlock_t *win_lock,
3409                    int (*phy_fw_version)(const u8 *, size_t),
3410                    const u8 *phy_fw_data, size_t phy_fw_size)
3411 {
3412         unsigned long mtype = 0, maddr = 0;
3413         u32 param, val;
3414         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3415         int ret;
3416
3417         /* If we have version number support, then check to see if the adapter
3418          * already has up-to-date PHY firmware loaded.
3419          */
3420          if (phy_fw_version) {
3421                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3422                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3423                 if (ret < 0)
3424                         return ret;
3425
3426                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3427                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3428                                 "version %#x\n", cur_phy_fw_ver);
3429                         return 0;
3430                 }
3431         }
3432
3433         /* Ask the firmware where it wants us to copy the PHY firmware image.
3434          * The size of the file requires a special version of the READ coommand
3435          * which will pass the file size via the values field in PARAMS_CMD and
3436          * retrieve the return value from firmware and place it in the same
3437          * buffer values
3438          */
3439         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3440                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3441                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3442                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3443         val = phy_fw_size;
3444         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3445                                  &param, &val, 1);
3446         if (ret < 0)
3447                 return ret;
3448         mtype = val >> 8;
3449         maddr = (val & 0xff) << 16;
3450
3451         /* Copy the supplied PHY Firmware image to the adapter memory location
3452          * allocated by the adapter firmware.
3453          */
3454         if (win_lock)
3455                 spin_lock_bh(win_lock);
3456         ret = t4_memory_rw(adap, win, mtype, maddr,
3457                            phy_fw_size, (__be32 *)phy_fw_data,
3458                            T4_MEMORY_WRITE);
3459         if (win_lock)
3460                 spin_unlock_bh(win_lock);
3461         if (ret)
3462                 return ret;
3463
3464         /* Tell the firmware that the PHY firmware image has been written to
3465          * RAM and it can now start copying it over to the PHYs.  The chip
3466          * firmware will RESET the affected PHYs as part of this operation
3467          * leaving them running the new PHY firmware image.
3468          */
3469         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3470                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3471                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3472                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3473         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3474                                     &param, &val, 30000);
3475
3476         /* If we have version number support, then check to see that the new
3477          * firmware got loaded properly.
3478          */
3479         if (phy_fw_version) {
3480                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3481                 if (ret < 0)
3482                         return ret;
3483
3484                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3485                         CH_WARN(adap, "PHY Firmware did not update: "
3486                                 "version on adapter %#x, "
3487                                 "version flashed %#x\n",
3488                                 cur_phy_fw_ver, new_phy_fw_vers);
3489                         return -ENXIO;
3490                 }
3491         }
3492
3493         return 1;
3494 }
3495
3496 /**
3497  *      t4_fwcache - firmware cache operation
3498  *      @adap: the adapter
3499  *      @op  : the operation (flush or flush and invalidate)
3500  */
3501 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3502 {
3503         struct fw_params_cmd c;
3504
3505         memset(&c, 0, sizeof(c));
3506         c.op_to_vfn =
3507                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3508                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3509                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3510                             FW_PARAMS_CMD_VFN_V(0));
3511         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3512         c.param[0].mnem =
3513                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3514                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3515         c.param[0].val = (__force __be32)op;
3516
3517         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3518 }
3519
3520 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3521                         unsigned int *pif_req_wrptr,
3522                         unsigned int *pif_rsp_wrptr)
3523 {
3524         int i, j;
3525         u32 cfg, val, req, rsp;
3526
3527         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3528         if (cfg & LADBGEN_F)
3529                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3530
3531         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3532         req = POLADBGWRPTR_G(val);
3533         rsp = PILADBGWRPTR_G(val);
3534         if (pif_req_wrptr)
3535                 *pif_req_wrptr = req;
3536         if (pif_rsp_wrptr)
3537                 *pif_rsp_wrptr = rsp;
3538
3539         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3540                 for (j = 0; j < 6; j++) {
3541                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3542                                      PILADBGRDPTR_V(rsp));
3543                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3544                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3545                         req++;
3546                         rsp++;
3547                 }
3548                 req = (req + 2) & POLADBGRDPTR_M;
3549                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3550         }
3551         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3552 }
3553
3554 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3555 {
3556         u32 cfg;
3557         int i, j, idx;
3558
3559         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3560         if (cfg & LADBGEN_F)
3561                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3562
3563         for (i = 0; i < CIM_MALA_SIZE; i++) {
3564                 for (j = 0; j < 5; j++) {
3565                         idx = 8 * i + j;
3566                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3567                                      PILADBGRDPTR_V(idx));
3568                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3569                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3570                 }
3571         }
3572         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3573 }
3574
3575 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3576 {
3577         unsigned int i, j;
3578
3579         for (i = 0; i < 8; i++) {
3580                 u32 *p = la_buf + i;
3581
3582                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3583                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3584                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3585                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3586                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3587         }
3588 }
3589
3590 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3591                      FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3592                      FW_PORT_CAP_ANEG)
3593
3594 /**
3595  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3596  *      @phy: the PHY to setup
3597  *      @mac: the MAC to setup
3598  *      @lc: the requested link configuration
3599  *
3600  *      Set up a port's MAC and PHY according to a desired link configuration.
3601  *      - If the PHY can auto-negotiate first decide what to advertise, then
3602  *        enable/disable auto-negotiation as desired, and reset.
3603  *      - If the PHY does not auto-negotiate just reset it.
3604  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3605  *        otherwise do it later based on the outcome of auto-negotiation.
3606  */
3607 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3608                   struct link_config *lc)
3609 {
3610         struct fw_port_cmd c;
3611         unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3612
3613         lc->link_ok = 0;
3614         if (lc->requested_fc & PAUSE_RX)
3615                 fc |= FW_PORT_CAP_FC_RX;
3616         if (lc->requested_fc & PAUSE_TX)
3617                 fc |= FW_PORT_CAP_FC_TX;
3618
3619         memset(&c, 0, sizeof(c));
3620         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3621                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3622                                      FW_PORT_CMD_PORTID_V(port));
3623         c.action_to_len16 =
3624                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3625                             FW_LEN16(c));
3626
3627         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3628                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3629                                              fc);
3630                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3631         } else if (lc->autoneg == AUTONEG_DISABLE) {
3632                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3633                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3634         } else
3635                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3636
3637         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3638 }
3639
3640 /**
3641  *      t4_restart_aneg - restart autonegotiation
3642  *      @adap: the adapter
3643  *      @mbox: mbox to use for the FW command
3644  *      @port: the port id
3645  *
3646  *      Restarts autonegotiation for the selected port.
3647  */
3648 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3649 {
3650         struct fw_port_cmd c;
3651
3652         memset(&c, 0, sizeof(c));
3653         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3654                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3655                                      FW_PORT_CMD_PORTID_V(port));
3656         c.action_to_len16 =
3657                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3658                             FW_LEN16(c));
3659         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3660         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3661 }
3662
3663 typedef void (*int_handler_t)(struct adapter *adap);
3664
3665 struct intr_info {
3666         unsigned int mask;       /* bits to check in interrupt status */
3667         const char *msg;         /* message to print or NULL */
3668         short stat_idx;          /* stat counter to increment or -1 */
3669         unsigned short fatal;    /* whether the condition reported is fatal */
3670         int_handler_t int_handler; /* platform-specific int handler */
3671 };
3672
3673 /**
3674  *      t4_handle_intr_status - table driven interrupt handler
3675  *      @adapter: the adapter that generated the interrupt
3676  *      @reg: the interrupt status register to process
3677  *      @acts: table of interrupt actions
3678  *
3679  *      A table driven interrupt handler that applies a set of masks to an
3680  *      interrupt status word and performs the corresponding actions if the
3681  *      interrupts described by the mask have occurred.  The actions include
3682  *      optionally emitting a warning or alert message.  The table is terminated
3683  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3684  *      conditions.
3685  */
3686 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3687                                  const struct intr_info *acts)
3688 {
3689         int fatal = 0;
3690         unsigned int mask = 0;
3691         unsigned int status = t4_read_reg(adapter, reg);
3692
3693         for ( ; acts->mask; ++acts) {
3694                 if (!(status & acts->mask))
3695                         continue;
3696                 if (acts->fatal) {
3697                         fatal++;
3698                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3699                                   status & acts->mask);
3700                 } else if (acts->msg && printk_ratelimit())
3701                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3702                                  status & acts->mask);
3703                 if (acts->int_handler)
3704                         acts->int_handler(adapter);
3705                 mask |= acts->mask;
3706         }
3707         status &= mask;
3708         if (status)                           /* clear processed interrupts */
3709                 t4_write_reg(adapter, reg, status);
3710         return fatal;
3711 }
3712
3713 /*
3714  * Interrupt handler for the PCIE module.
3715  */
3716 static void pcie_intr_handler(struct adapter *adapter)
3717 {
3718         static const struct intr_info sysbus_intr_info[] = {
3719                 { RNPP_F, "RXNP array parity error", -1, 1 },
3720                 { RPCP_F, "RXPC array parity error", -1, 1 },
3721                 { RCIP_F, "RXCIF array parity error", -1, 1 },
3722                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3723                 { RFTP_F, "RXFT array parity error", -1, 1 },
3724                 { 0 }
3725         };
3726         static const struct intr_info pcie_port_intr_info[] = {
3727                 { TPCP_F, "TXPC array parity error", -1, 1 },
3728                 { TNPP_F, "TXNP array parity error", -1, 1 },
3729                 { TFTP_F, "TXFT array parity error", -1, 1 },
3730                 { TCAP_F, "TXCA array parity error", -1, 1 },
3731                 { TCIP_F, "TXCIF array parity error", -1, 1 },
3732                 { RCAP_F, "RXCA array parity error", -1, 1 },
3733                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3734                 { RDPE_F, "Rx data parity error", -1, 1 },
3735                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3736                 { 0 }
3737         };
3738         static const struct intr_info pcie_intr_info[] = {
3739                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3740                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3741                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3742                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3743                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3744                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3745                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3746                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3747                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3748                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3749                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3750                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3751                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3752                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3753                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3754                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3755                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3756                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3757                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3758                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3759                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3760                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3761                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3762                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3763                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3764                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3765                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3766                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3767                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3768                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3769                   -1, 0 },
3770                 { 0 }
3771         };
3772
3773         static struct intr_info t5_pcie_intr_info[] = {
3774                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3775                   -1, 1 },
3776                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3777                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3778                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3779                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3780                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3781                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3782                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3783                   -1, 1 },
3784                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3785                   -1, 1 },
3786                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3787                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3788                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3789                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3790                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3791                   -1, 1 },
3792                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3793                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3794                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3795                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3796                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3797                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3798                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3799                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3800                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3801                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3802                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3803                   -1, 1 },
3804                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3805                   -1, 1 },
3806                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3807                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3808                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3809                 { READRSPERR_F, "Outbound read error", -1, 0 },
3810                 { 0 }
3811         };
3812
3813         int fat;
3814
3815         if (is_t4(adapter->params.chip))
3816                 fat = t4_handle_intr_status(adapter,
3817                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3818                                 sysbus_intr_info) +
3819                         t4_handle_intr_status(adapter,
3820                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3821                                         pcie_port_intr_info) +
3822                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3823                                               pcie_intr_info);
3824         else
3825                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3826                                             t5_pcie_intr_info);
3827
3828         if (fat)
3829                 t4_fatal_err(adapter);
3830 }
3831
3832 /*
3833  * TP interrupt handler.
3834  */
3835 static void tp_intr_handler(struct adapter *adapter)
3836 {
3837         static const struct intr_info tp_intr_info[] = {
3838                 { 0x3fffffff, "TP parity error", -1, 1 },
3839                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3840                 { 0 }
3841         };
3842
3843         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3844                 t4_fatal_err(adapter);
3845 }
3846
3847 /*
3848  * SGE interrupt handler.
3849  */
3850 static void sge_intr_handler(struct adapter *adapter)
3851 {
3852         u64 v;
3853         u32 err;
3854
3855         static const struct intr_info sge_intr_info[] = {
3856                 { ERR_CPL_EXCEED_IQE_SIZE_F,
3857                   "SGE received CPL exceeding IQE size", -1, 1 },
3858                 { ERR_INVALID_CIDX_INC_F,
3859                   "SGE GTS CIDX increment too large", -1, 0 },
3860                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3861                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3862                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3863                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
3864                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3865                   0 },
3866                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3867                   0 },
3868                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3869                   0 },
3870                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3871                   0 },
3872                 { ERR_ING_CTXT_PRIO_F,
3873                   "SGE too many priority ingress contexts", -1, 0 },
3874                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3875                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3876                 { 0 }
3877         };
3878
3879         static struct intr_info t4t5_sge_intr_info[] = {
3880                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3881                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3882                 { ERR_EGR_CTXT_PRIO_F,
3883                   "SGE too many priority egress contexts", -1, 0 },
3884                 { 0 }
3885         };
3886
3887         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3888                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3889         if (v) {
3890                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3891                                 (unsigned long long)v);
3892                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3893                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3894         }
3895
3896         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3897         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3898                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3899                                            t4t5_sge_intr_info);
3900
3901         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3902         if (err & ERROR_QID_VALID_F) {
3903                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3904                         ERROR_QID_G(err));
3905                 if (err & UNCAPTURED_ERROR_F)
3906                         dev_err(adapter->pdev_dev,
3907                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
3908                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3909                              UNCAPTURED_ERROR_F);
3910         }
3911
3912         if (v != 0)
3913                 t4_fatal_err(adapter);
3914 }
3915
3916 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3917                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3918 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3919                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3920
3921 /*
3922  * CIM interrupt handler.
3923  */
3924 static void cim_intr_handler(struct adapter *adapter)
3925 {
3926         static const struct intr_info cim_intr_info[] = {
3927                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3928                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3929                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3930                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3931                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3932                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3933                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3934                 { 0 }
3935         };
3936         static const struct intr_info cim_upintr_info[] = {
3937                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3938                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3939                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3940                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3941                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3942                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3943                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3944                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3945                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3946                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3947                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3948                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3949                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3950                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3951                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3952                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3953                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3954                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3955                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3956                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3957                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3958                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3959                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3960                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3961                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3962                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3963                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3964                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3965                 { 0 }
3966         };
3967
3968         int fat;
3969
3970         if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3971                 t4_report_fw_error(adapter);
3972
3973         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3974                                     cim_intr_info) +
3975               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3976                                     cim_upintr_info);
3977         if (fat)
3978                 t4_fatal_err(adapter);
3979 }
3980
3981 /*
3982  * ULP RX interrupt handler.
3983  */
3984 static void ulprx_intr_handler(struct adapter *adapter)
3985 {
3986         static const struct intr_info ulprx_intr_info[] = {
3987                 { 0x1800000, "ULPRX context error", -1, 1 },
3988                 { 0x7fffff, "ULPRX parity error", -1, 1 },
3989                 { 0 }
3990         };
3991
3992         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3993                 t4_fatal_err(adapter);
3994 }
3995
3996 /*
3997  * ULP TX interrupt handler.
3998  */
3999 static void ulptx_intr_handler(struct adapter *adapter)
4000 {
4001         static const struct intr_info ulptx_intr_info[] = {
4002                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4003                   0 },
4004                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4005                   0 },
4006                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4007                   0 },
4008                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4009                   0 },
4010                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4011                 { 0 }
4012         };
4013
4014         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4015                 t4_fatal_err(adapter);
4016 }
4017
4018 /*
4019  * PM TX interrupt handler.
4020  */
4021 static void pmtx_intr_handler(struct adapter *adapter)
4022 {
4023         static const struct intr_info pmtx_intr_info[] = {
4024                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4025                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4026                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4027                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4028                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4029                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4030                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4031                   -1, 1 },
4032                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4033                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4034                 { 0 }
4035         };
4036
4037         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4038                 t4_fatal_err(adapter);
4039 }
4040
4041 /*
4042  * PM RX interrupt handler.
4043  */
4044 static void pmrx_intr_handler(struct adapter *adapter)
4045 {
4046         static const struct intr_info pmrx_intr_info[] = {
4047                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4048                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4049                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4050                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4051                   -1, 1 },
4052                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4053                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4054                 { 0 }
4055         };
4056
4057         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4058                 t4_fatal_err(adapter);
4059 }
4060
4061 /*
4062  * CPL switch interrupt handler.
4063  */
4064 static void cplsw_intr_handler(struct adapter *adapter)
4065 {
4066         static const struct intr_info cplsw_intr_info[] = {
4067                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4068                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4069                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4070                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4071                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4072                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4073                 { 0 }
4074         };
4075
4076         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4077                 t4_fatal_err(adapter);
4078 }
4079
4080 /*
4081  * LE interrupt handler.
4082  */
4083 static void le_intr_handler(struct adapter *adap)
4084 {
4085         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4086         static const struct intr_info le_intr_info[] = {
4087                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4088                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4089                 { PARITYERR_F, "LE parity error", -1, 1 },
4090                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4091                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4092                 { 0 }
4093         };
4094
4095         static struct intr_info t6_le_intr_info[] = {
4096                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4097                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4098                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4099                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4100                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4101                 { 0 }
4102         };
4103
4104         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4105                                   (chip <= CHELSIO_T5) ?
4106                                   le_intr_info : t6_le_intr_info))
4107                 t4_fatal_err(adap);
4108 }
4109
4110 /*
4111  * MPS interrupt handler.
4112  */
4113 static void mps_intr_handler(struct adapter *adapter)
4114 {
4115         static const struct intr_info mps_rx_intr_info[] = {
4116                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4117                 { 0 }
4118         };
4119         static const struct intr_info mps_tx_intr_info[] = {
4120                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4121                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4122                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4123                   -1, 1 },
4124                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4125                   -1, 1 },
4126                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4127                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4128                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4129                 { 0 }
4130         };
4131         static const struct intr_info mps_trc_intr_info[] = {
4132                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4133                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4134                   -1, 1 },
4135                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4136                 { 0 }
4137         };
4138         static const struct intr_info mps_stat_sram_intr_info[] = {
4139                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4140                 { 0 }
4141         };
4142         static const struct intr_info mps_stat_tx_intr_info[] = {
4143                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4144                 { 0 }
4145         };
4146         static const struct intr_info mps_stat_rx_intr_info[] = {
4147                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4148                 { 0 }
4149         };
4150         static const struct intr_info mps_cls_intr_info[] = {
4151                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4152                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4153                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4154                 { 0 }
4155         };
4156
4157         int fat;
4158
4159         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4160                                     mps_rx_intr_info) +
4161               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4162                                     mps_tx_intr_info) +
4163               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4164                                     mps_trc_intr_info) +
4165               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4166                                     mps_stat_sram_intr_info) +
4167               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4168                                     mps_stat_tx_intr_info) +
4169               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4170                                     mps_stat_rx_intr_info) +
4171               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4172                                     mps_cls_intr_info);
4173
4174         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4175         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4176         if (fat)
4177                 t4_fatal_err(adapter);
4178 }
4179
4180 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4181                       ECC_UE_INT_CAUSE_F)
4182
4183 /*
4184  * EDC/MC interrupt handler.
4185  */
4186 static void mem_intr_handler(struct adapter *adapter, int idx)
4187 {
4188         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4189
4190         unsigned int addr, cnt_addr, v;
4191
4192         if (idx <= MEM_EDC1) {
4193                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4194                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4195         } else if (idx == MEM_MC) {
4196                 if (is_t4(adapter->params.chip)) {
4197                         addr = MC_INT_CAUSE_A;
4198                         cnt_addr = MC_ECC_STATUS_A;
4199                 } else {
4200                         addr = MC_P_INT_CAUSE_A;
4201                         cnt_addr = MC_P_ECC_STATUS_A;
4202                 }
4203         } else {
4204                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4205                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4206         }
4207
4208         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4209         if (v & PERR_INT_CAUSE_F)
4210                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4211                           name[idx]);
4212         if (v & ECC_CE_INT_CAUSE_F) {
4213                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4214
4215                 t4_edc_err_read(adapter, idx);
4216
4217                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4218                 if (printk_ratelimit())
4219                         dev_warn(adapter->pdev_dev,
4220                                  "%u %s correctable ECC data error%s\n",
4221                                  cnt, name[idx], cnt > 1 ? "s" : "");
4222         }
4223         if (v & ECC_UE_INT_CAUSE_F)
4224                 dev_alert(adapter->pdev_dev,
4225                           "%s uncorrectable ECC data error\n", name[idx]);
4226
4227         t4_write_reg(adapter, addr, v);
4228         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4229                 t4_fatal_err(adapter);
4230 }
4231
4232 /*
4233  * MA interrupt handler.
4234  */
4235 static void ma_intr_handler(struct adapter *adap)
4236 {
4237         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4238
4239         if (status & MEM_PERR_INT_CAUSE_F) {
4240                 dev_alert(adap->pdev_dev,
4241                           "MA parity error, parity status %#x\n",
4242                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4243                 if (is_t5(adap->params.chip))
4244                         dev_alert(adap->pdev_dev,
4245                                   "MA parity error, parity status %#x\n",
4246                                   t4_read_reg(adap,
4247                                               MA_PARITY_ERROR_STATUS2_A));
4248         }
4249         if (status & MEM_WRAP_INT_CAUSE_F) {
4250                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4251                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4252                           "client %u to address %#x\n",
4253                           MEM_WRAP_CLIENT_NUM_G(v),
4254                           MEM_WRAP_ADDRESS_G(v) << 4);
4255         }
4256         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4257         t4_fatal_err(adap);
4258 }
4259
4260 /*
4261  * SMB interrupt handler.
4262  */
4263 static void smb_intr_handler(struct adapter *adap)
4264 {
4265         static const struct intr_info smb_intr_info[] = {
4266                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4267                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4268                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4269                 { 0 }
4270         };
4271
4272         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4273                 t4_fatal_err(adap);
4274 }
4275
4276 /*
4277  * NC-SI interrupt handler.
4278  */
4279 static void ncsi_intr_handler(struct adapter *adap)
4280 {
4281         static const struct intr_info ncsi_intr_info[] = {
4282                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4283                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4284                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4285                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4286                 { 0 }
4287         };
4288
4289         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4290                 t4_fatal_err(adap);
4291 }
4292
4293 /*
4294  * XGMAC interrupt handler.
4295  */
4296 static void xgmac_intr_handler(struct adapter *adap, int port)
4297 {
4298         u32 v, int_cause_reg;
4299
4300         if (is_t4(adap->params.chip))
4301                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4302         else
4303                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4304
4305         v = t4_read_reg(adap, int_cause_reg);
4306
4307         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4308         if (!v)
4309                 return;
4310
4311         if (v & TXFIFO_PRTY_ERR_F)
4312                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4313                           port);
4314         if (v & RXFIFO_PRTY_ERR_F)
4315                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4316                           port);
4317         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4318         t4_fatal_err(adap);
4319 }
4320
4321 /*
4322  * PL interrupt handler.
4323  */
4324 static void pl_intr_handler(struct adapter *adap)
4325 {
4326         static const struct intr_info pl_intr_info[] = {
4327                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4328                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4329                 { 0 }
4330         };
4331
4332         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4333                 t4_fatal_err(adap);
4334 }
4335
4336 #define PF_INTR_MASK (PFSW_F)
4337 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4338                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4339                 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4340
4341 /**
4342  *      t4_slow_intr_handler - control path interrupt handler
4343  *      @adapter: the adapter
4344  *
4345  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4346  *      The designation 'slow' is because it involves register reads, while
4347  *      data interrupts typically don't involve any MMIOs.
4348  */
4349 int t4_slow_intr_handler(struct adapter *adapter)
4350 {
4351         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4352
4353         if (!(cause & GLBL_INTR_MASK))
4354                 return 0;
4355         if (cause & CIM_F)
4356                 cim_intr_handler(adapter);
4357         if (cause & MPS_F)
4358                 mps_intr_handler(adapter);
4359         if (cause & NCSI_F)
4360                 ncsi_intr_handler(adapter);
4361         if (cause & PL_F)
4362                 pl_intr_handler(adapter);
4363         if (cause & SMB_F)
4364                 smb_intr_handler(adapter);
4365         if (cause & XGMAC0_F)
4366                 xgmac_intr_handler(adapter, 0);
4367         if (cause & XGMAC1_F)
4368                 xgmac_intr_handler(adapter, 1);
4369         if (cause & XGMAC_KR0_F)
4370                 xgmac_intr_handler(adapter, 2);
4371         if (cause & XGMAC_KR1_F)
4372                 xgmac_intr_handler(adapter, 3);
4373         if (cause & PCIE_F)
4374                 pcie_intr_handler(adapter);
4375         if (cause & MC_F)
4376                 mem_intr_handler(adapter, MEM_MC);
4377         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4378                 mem_intr_handler(adapter, MEM_MC1);
4379         if (cause & EDC0_F)
4380                 mem_intr_handler(adapter, MEM_EDC0);
4381         if (cause & EDC1_F)
4382                 mem_intr_handler(adapter, MEM_EDC1);
4383         if (cause & LE_F)
4384                 le_intr_handler(adapter);
4385         if (cause & TP_F)
4386                 tp_intr_handler(adapter);
4387         if (cause & MA_F)
4388                 ma_intr_handler(adapter);
4389         if (cause & PM_TX_F)
4390                 pmtx_intr_handler(adapter);
4391         if (cause & PM_RX_F)
4392                 pmrx_intr_handler(adapter);
4393         if (cause & ULP_RX_F)
4394                 ulprx_intr_handler(adapter);
4395         if (cause & CPL_SWITCH_F)
4396                 cplsw_intr_handler(adapter);
4397         if (cause & SGE_F)
4398                 sge_intr_handler(adapter);
4399         if (cause & ULP_TX_F)
4400                 ulptx_intr_handler(adapter);
4401
4402         /* Clear the interrupts just processed for which we are the master. */
4403         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4404         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4405         return 1;
4406 }
4407
4408 /**
4409  *      t4_intr_enable - enable interrupts
4410  *      @adapter: the adapter whose interrupts should be enabled
4411  *
4412  *      Enable PF-specific interrupts for the calling function and the top-level
4413  *      interrupt concentrator for global interrupts.  Interrupts are already
4414  *      enabled at each module, here we just enable the roots of the interrupt
4415  *      hierarchies.
4416  *
4417  *      Note: this function should be called only when the driver manages
4418  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4419  *      function at a time should be doing this.
4420  */
4421 void t4_intr_enable(struct adapter *adapter)
4422 {
4423         u32 val = 0;
4424         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4425         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4426                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4427
4428         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4429                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4430         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4431                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4432                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4433                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4434                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4435                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4436                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4437         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4438         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4439 }
4440
4441 /**
4442  *      t4_intr_disable - disable interrupts
4443  *      @adapter: the adapter whose interrupts should be disabled
4444  *
4445  *      Disable interrupts.  We only disable the top-level interrupt
4446  *      concentrators.  The caller must be a PCI function managing global
4447  *      interrupts.
4448  */
4449 void t4_intr_disable(struct adapter *adapter)
4450 {
4451         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4452         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4453                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4454
4455         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4456         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4457 }
4458
4459 /**
4460  *      t4_config_rss_range - configure a portion of the RSS mapping table
4461  *      @adapter: the adapter
4462  *      @mbox: mbox to use for the FW command
4463  *      @viid: virtual interface whose RSS subtable is to be written
4464  *      @start: start entry in the table to write
4465  *      @n: how many table entries to write
4466  *      @rspq: values for the response queue lookup table
4467  *      @nrspq: number of values in @rspq
4468  *
4469  *      Programs the selected part of the VI's RSS mapping table with the
4470  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4471  *      until the full table range is populated.
4472  *
4473  *      The caller must ensure the values in @rspq are in the range allowed for
4474  *      @viid.
4475  */
4476 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4477                         int start, int n, const u16 *rspq, unsigned int nrspq)
4478 {
4479         int ret;
4480         const u16 *rsp = rspq;
4481         const u16 *rsp_end = rspq + nrspq;
4482         struct fw_rss_ind_tbl_cmd cmd;
4483
4484         memset(&cmd, 0, sizeof(cmd));
4485         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4486                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4487                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4488         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4489
4490         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4491         while (n > 0) {
4492                 int nq = min(n, 32);
4493                 __be32 *qp = &cmd.iq0_to_iq2;
4494
4495                 cmd.niqid = cpu_to_be16(nq);
4496                 cmd.startidx = cpu_to_be16(start);
4497
4498                 start += nq;
4499                 n -= nq;
4500
4501                 while (nq > 0) {
4502                         unsigned int v;
4503
4504                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4505                         if (++rsp >= rsp_end)
4506                                 rsp = rspq;
4507                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4508                         if (++rsp >= rsp_end)
4509                                 rsp = rspq;
4510                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4511                         if (++rsp >= rsp_end)
4512                                 rsp = rspq;
4513
4514                         *qp++ = cpu_to_be32(v);
4515                         nq -= 3;
4516                 }
4517
4518                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4519                 if (ret)
4520                         return ret;
4521         }
4522         return 0;
4523 }
4524
4525 /**
4526  *      t4_config_glbl_rss - configure the global RSS mode
4527  *      @adapter: the adapter
4528  *      @mbox: mbox to use for the FW command
4529  *      @mode: global RSS mode
4530  *      @flags: mode-specific flags
4531  *
4532  *      Sets the global RSS mode.
4533  */
4534 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4535                        unsigned int flags)
4536 {
4537         struct fw_rss_glb_config_cmd c;
4538
4539         memset(&c, 0, sizeof(c));
4540         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4541                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4542         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4543         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4544                 c.u.manual.mode_pkd =
4545                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4546         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4547                 c.u.basicvirtual.mode_pkd =
4548                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4549                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4550         } else
4551                 return -EINVAL;
4552         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4553 }
4554
4555 /**
4556  *      t4_config_vi_rss - configure per VI RSS settings
4557  *      @adapter: the adapter
4558  *      @mbox: mbox to use for the FW command
4559  *      @viid: the VI id
4560  *      @flags: RSS flags
4561  *      @defq: id of the default RSS queue for the VI.
4562  *
4563  *      Configures VI-specific RSS properties.
4564  */
4565 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4566                      unsigned int flags, unsigned int defq)
4567 {
4568         struct fw_rss_vi_config_cmd c;
4569
4570         memset(&c, 0, sizeof(c));
4571         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4572                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4573                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4574         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4575         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4576                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4577         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4578 }
4579
4580 /* Read an RSS table row */
4581 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4582 {
4583         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4584         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4585                                    5, 0, val);
4586 }
4587
4588 /**
4589  *      t4_read_rss - read the contents of the RSS mapping table
4590  *      @adapter: the adapter
4591  *      @map: holds the contents of the RSS mapping table
4592  *
4593  *      Reads the contents of the RSS hash->queue mapping table.
4594  */
4595 int t4_read_rss(struct adapter *adapter, u16 *map)
4596 {
4597         u32 val;
4598         int i, ret;
4599
4600         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4601                 ret = rd_rss_row(adapter, i, &val);
4602                 if (ret)
4603                         return ret;
4604                 *map++ = LKPTBLQUEUE0_G(val);
4605                 *map++ = LKPTBLQUEUE1_G(val);
4606         }
4607         return 0;
4608 }
4609
4610 static unsigned int t4_use_ldst(struct adapter *adap)
4611 {
4612         return (adap->flags & FW_OK) || !adap->use_bd;
4613 }
4614
4615 /**
4616  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
4617  *      @adap: the adapter
4618  *      @vals: where the indirect register values are stored/written
4619  *      @nregs: how many indirect registers to read/write
4620  *      @start_idx: index of first indirect register to read/write
4621  *      @rw: Read (1) or Write (0)
4622  *
4623  *      Access TP PIO registers through LDST
4624  */
4625 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4626                             unsigned int start_index, unsigned int rw)
4627 {
4628         int ret, i;
4629         int cmd = FW_LDST_ADDRSPC_TP_PIO;
4630         struct fw_ldst_cmd c;
4631
4632         for (i = 0 ; i < nregs; i++) {
4633                 memset(&c, 0, sizeof(c));
4634                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4635                                                 FW_CMD_REQUEST_F |
4636                                                 (rw ? FW_CMD_READ_F :
4637                                                       FW_CMD_WRITE_F) |
4638                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
4639                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4640
4641                 c.u.addrval.addr = cpu_to_be32(start_index + i);
4642                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4643                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4644                 if (!ret && rw)
4645                         vals[i] = be32_to_cpu(c.u.addrval.val);
4646         }
4647 }
4648
4649 /**
4650  *      t4_read_rss_key - read the global RSS key
4651  *      @adap: the adapter
4652  *      @key: 10-entry array holding the 320-bit RSS key
4653  *
4654  *      Reads the global 320-bit RSS key.
4655  */
4656 void t4_read_rss_key(struct adapter *adap, u32 *key)
4657 {
4658         if (t4_use_ldst(adap))
4659                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4660         else
4661                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4662                                  TP_RSS_SECRET_KEY0_A);
4663 }
4664
4665 /**
4666  *      t4_write_rss_key - program one of the RSS keys
4667  *      @adap: the adapter
4668  *      @key: 10-entry array holding the 320-bit RSS key
4669  *      @idx: which RSS key to write
4670  *
4671  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
4672  *      0..15 the corresponding entry in the RSS key table is written,
4673  *      otherwise the global RSS key is written.
4674  */
4675 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4676 {
4677         u8 rss_key_addr_cnt = 16;
4678         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4679
4680         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4681          * allows access to key addresses 16-63 by using KeyWrAddrX
4682          * as index[5:4](upper 2) into key table
4683          */
4684         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4685             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4686                 rss_key_addr_cnt = 32;
4687
4688         if (t4_use_ldst(adap))
4689                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4690         else
4691                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4692                                   TP_RSS_SECRET_KEY0_A);
4693
4694         if (idx >= 0 && idx < rss_key_addr_cnt) {
4695                 if (rss_key_addr_cnt > 16)
4696                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4697                                      KEYWRADDRX_V(idx >> 4) |
4698                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
4699                 else
4700                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4701                                      KEYWRADDR_V(idx) | KEYWREN_F);
4702         }
4703 }
4704
4705 /**
4706  *      t4_read_rss_pf_config - read PF RSS Configuration Table
4707  *      @adapter: the adapter
4708  *      @index: the entry in the PF RSS table to read
4709  *      @valp: where to store the returned value
4710  *
4711  *      Reads the PF RSS Configuration Table at the specified index and returns
4712  *      the value found there.
4713  */
4714 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4715                            u32 *valp)
4716 {
4717         if (t4_use_ldst(adapter))
4718                 t4_fw_tp_pio_rw(adapter, valp, 1,
4719                                 TP_RSS_PF0_CONFIG_A + index, 1);
4720         else
4721                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4722                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
4723 }
4724
4725 /**
4726  *      t4_read_rss_vf_config - read VF RSS Configuration Table
4727  *      @adapter: the adapter
4728  *      @index: the entry in the VF RSS table to read
4729  *      @vfl: where to store the returned VFL
4730  *      @vfh: where to store the returned VFH
4731  *
4732  *      Reads the VF RSS Configuration Table at the specified index and returns
4733  *      the (VFL, VFH) values found there.
4734  */
4735 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4736                            u32 *vfl, u32 *vfh)
4737 {
4738         u32 vrt, mask, data;
4739
4740         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4741                 mask = VFWRADDR_V(VFWRADDR_M);
4742                 data = VFWRADDR_V(index);
4743         } else {
4744                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
4745                  data = T6_VFWRADDR_V(index);
4746         }
4747
4748         /* Request that the index'th VF Table values be read into VFL/VFH.
4749          */
4750         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4751         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4752         vrt |= data | VFRDEN_F;
4753         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4754
4755         /* Grab the VFL/VFH values ...
4756          */
4757         if (t4_use_ldst(adapter)) {
4758                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4759                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4760         } else {
4761                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4762                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
4763                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4764                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
4765         }
4766 }
4767
4768 /**
4769  *      t4_read_rss_pf_map - read PF RSS Map
4770  *      @adapter: the adapter
4771  *
4772  *      Reads the PF RSS Map register and returns its value.
4773  */
4774 u32 t4_read_rss_pf_map(struct adapter *adapter)
4775 {
4776         u32 pfmap;
4777
4778         if (t4_use_ldst(adapter))
4779                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4780         else
4781                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4782                                  &pfmap, 1, TP_RSS_PF_MAP_A);
4783         return pfmap;
4784 }
4785
4786 /**
4787  *      t4_read_rss_pf_mask - read PF RSS Mask
4788  *      @adapter: the adapter
4789  *
4790  *      Reads the PF RSS Mask register and returns its value.
4791  */
4792 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4793 {
4794         u32 pfmask;
4795
4796         if (t4_use_ldst(adapter))
4797                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4798         else
4799                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4800                                  &pfmask, 1, TP_RSS_PF_MSK_A);
4801         return pfmask;
4802 }
4803
4804 /**
4805  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
4806  *      @adap: the adapter
4807  *      @v4: holds the TCP/IP counter values
4808  *      @v6: holds the TCP/IPv6 counter values
4809  *
4810  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4811  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4812  */
4813 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4814                          struct tp_tcp_stats *v6)
4815 {
4816         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4817
4818 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4819 #define STAT(x)     val[STAT_IDX(x)]
4820 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4821
4822         if (v4) {
4823                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4824                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4825                 v4->tcp_out_rsts = STAT(OUT_RST);
4826                 v4->tcp_in_segs  = STAT64(IN_SEG);
4827                 v4->tcp_out_segs = STAT64(OUT_SEG);
4828                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4829         }
4830         if (v6) {
4831                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4832                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4833                 v6->tcp_out_rsts = STAT(OUT_RST);
4834                 v6->tcp_in_segs  = STAT64(IN_SEG);
4835                 v6->tcp_out_segs = STAT64(OUT_SEG);
4836                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4837         }
4838 #undef STAT64
4839 #undef STAT
4840 #undef STAT_IDX
4841 }
4842
4843 /**
4844  *      t4_tp_get_err_stats - read TP's error MIB counters
4845  *      @adap: the adapter
4846  *      @st: holds the counter values
4847  *
4848  *      Returns the values of TP's error counters.
4849  */
4850 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4851 {
4852         int nchan = adap->params.arch.nchan;
4853
4854         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4855                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4856         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4857                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4858         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4859                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4860         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4861                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4862         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4863                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4864         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4865                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4866         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4867                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4868         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4869                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4870
4871         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4872                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4873 }
4874
4875 /**
4876  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
4877  *      @adap: the adapter
4878  *      @st: holds the counter values
4879  *
4880  *      Returns the values of TP's CPL counters.
4881  */
4882 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4883 {
4884         int nchan = adap->params.arch.nchan;
4885
4886         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4887                          nchan, TP_MIB_CPL_IN_REQ_0_A);
4888         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4889                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
4890
4891 }
4892
4893 /**
4894  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4895  *      @adap: the adapter
4896  *      @st: holds the counter values
4897  *
4898  *      Returns the values of TP's RDMA counters.
4899  */
4900 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4901 {
4902         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4903                          2, TP_MIB_RQE_DFR_PKT_A);
4904 }
4905
4906 /**
4907  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4908  *      @adap: the adapter
4909  *      @idx: the port index
4910  *      @st: holds the counter values
4911  *
4912  *      Returns the values of TP's FCoE counters for the selected port.
4913  */
4914 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4915                        struct tp_fcoe_stats *st)
4916 {
4917         u32 val[2];
4918
4919         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4920                          1, TP_MIB_FCOE_DDP_0_A + idx);
4921         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4922                          1, TP_MIB_FCOE_DROP_0_A + idx);
4923         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4924                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4925         st->octets_ddp = ((u64)val[0] << 32) | val[1];
4926 }
4927
4928 /**
4929  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4930  *      @adap: the adapter
4931  *      @st: holds the counter values
4932  *
4933  *      Returns the values of TP's counters for non-TCP directly-placed packets.
4934  */
4935 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4936 {
4937         u32 val[4];
4938
4939         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4940                          TP_MIB_USM_PKTS_A);
4941         st->frames = val[0];
4942         st->drops = val[1];
4943         st->octets = ((u64)val[2] << 32) | val[3];
4944 }
4945
4946 /**
4947  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
4948  *      @adap: the adapter
4949  *      @mtus: where to store the MTU values
4950  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
4951  *
4952  *      Reads the HW path MTU table.
4953  */
4954 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4955 {
4956         u32 v;
4957         int i;
4958
4959         for (i = 0; i < NMTUS; ++i) {
4960                 t4_write_reg(adap, TP_MTU_TABLE_A,
4961                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
4962                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4963                 mtus[i] = MTUVALUE_G(v);
4964                 if (mtu_log)
4965                         mtu_log[i] = MTUWIDTH_G(v);
4966         }
4967 }
4968
4969 /**
4970  *      t4_read_cong_tbl - reads the congestion control table
4971  *      @adap: the adapter
4972  *      @incr: where to store the alpha values
4973  *
4974  *      Reads the additive increments programmed into the HW congestion
4975  *      control table.
4976  */
4977 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4978 {
4979         unsigned int mtu, w;
4980
4981         for (mtu = 0; mtu < NMTUS; ++mtu)
4982                 for (w = 0; w < NCCTRL_WIN; ++w) {
4983                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
4984                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
4985                         incr[mtu][w] = (u16)t4_read_reg(adap,
4986                                                 TP_CCTRL_TABLE_A) & 0x1fff;
4987                 }
4988 }
4989
4990 /**
4991  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4992  *      @adap: the adapter
4993  *      @addr: the indirect TP register address
4994  *      @mask: specifies the field within the register to modify
4995  *      @val: new value for the field
4996  *
4997  *      Sets a field of an indirect TP register to the given value.
4998  */
4999 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5000                             unsigned int mask, unsigned int val)
5001 {
5002         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5003         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5004         t4_write_reg(adap, TP_PIO_DATA_A, val);
5005 }
5006
5007 /**
5008  *      init_cong_ctrl - initialize congestion control parameters
5009  *      @a: the alpha values for congestion control
5010  *      @b: the beta values for congestion control
5011  *
5012  *      Initialize the congestion control parameters.
5013  */
5014 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5015 {
5016         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5017         a[9] = 2;
5018         a[10] = 3;
5019         a[11] = 4;
5020         a[12] = 5;
5021         a[13] = 6;
5022         a[14] = 7;
5023         a[15] = 8;
5024         a[16] = 9;
5025         a[17] = 10;
5026         a[18] = 14;
5027         a[19] = 17;
5028         a[20] = 21;
5029         a[21] = 25;
5030         a[22] = 30;
5031         a[23] = 35;
5032         a[24] = 45;
5033         a[25] = 60;
5034         a[26] = 80;
5035         a[27] = 100;
5036         a[28] = 200;
5037         a[29] = 300;
5038         a[30] = 400;
5039         a[31] = 500;
5040
5041         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5042         b[9] = b[10] = 1;
5043         b[11] = b[12] = 2;
5044         b[13] = b[14] = b[15] = b[16] = 3;
5045         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5046         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5047         b[28] = b[29] = 6;
5048         b[30] = b[31] = 7;
5049 }
5050
5051 /* The minimum additive increment value for the congestion control table */
5052 #define CC_MIN_INCR 2U
5053
5054 /**
5055  *      t4_load_mtus - write the MTU and congestion control HW tables
5056  *      @adap: the adapter
5057  *      @mtus: the values for the MTU table
5058  *      @alpha: the values for the congestion control alpha parameter
5059  *      @beta: the values for the congestion control beta parameter
5060  *
5061  *      Write the HW MTU table with the supplied MTUs and the high-speed
5062  *      congestion control table with the supplied alpha, beta, and MTUs.
5063  *      We write the two tables together because the additive increments
5064  *      depend on the MTUs.
5065  */
5066 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5067                   const unsigned short *alpha, const unsigned short *beta)
5068 {
5069         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5070                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5071                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5072                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5073         };
5074
5075         unsigned int i, w;
5076
5077         for (i = 0; i < NMTUS; ++i) {
5078                 unsigned int mtu = mtus[i];
5079                 unsigned int log2 = fls(mtu);
5080
5081                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5082                         log2--;
5083                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5084                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5085
5086                 for (w = 0; w < NCCTRL_WIN; ++w) {
5087                         unsigned int inc;
5088
5089                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5090                                   CC_MIN_INCR);
5091
5092                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5093                                      (w << 16) | (beta[w] << 13) | inc);
5094                 }
5095         }
5096 }
5097
5098 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5099  * clocks.  The formula is
5100  *
5101  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5102  *
5103  * which is equivalent to
5104  *
5105  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5106  */
5107 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5108 {
5109         u64 v = bytes256 * adap->params.vpd.cclk;
5110
5111         return v * 62 + v / 2;
5112 }
5113
5114 /**
5115  *      t4_get_chan_txrate - get the current per channel Tx rates
5116  *      @adap: the adapter
5117  *      @nic_rate: rates for NIC traffic
5118  *      @ofld_rate: rates for offloaded traffic
5119  *
5120  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5121  *      for each channel.
5122  */
5123 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5124 {
5125         u32 v;
5126
5127         v = t4_read_reg(adap, TP_TX_TRATE_A);
5128         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5129         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5130         if (adap->params.arch.nchan == NCHAN) {
5131                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5132                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5133         }
5134
5135         v = t4_read_reg(adap, TP_TX_ORATE_A);
5136         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5137         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5138         if (adap->params.arch.nchan == NCHAN) {
5139                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5140                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5141         }
5142 }
5143
5144 /**
5145  *      t4_set_trace_filter - configure one of the tracing filters
5146  *      @adap: the adapter
5147  *      @tp: the desired trace filter parameters
5148  *      @idx: which filter to configure
5149  *      @enable: whether to enable or disable the filter
5150  *
5151  *      Configures one of the tracing filters available in HW.  If @enable is
5152  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5153  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5154  */
5155 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5156                         int idx, int enable)
5157 {
5158         int i, ofst = idx * 4;
5159         u32 data_reg, mask_reg, cfg;
5160         u32 multitrc = TRCMULTIFILTER_F;
5161
5162         if (!enable) {
5163                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5164                 return 0;
5165         }
5166
5167         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5168         if (cfg & TRCMULTIFILTER_F) {
5169                 /* If multiple tracers are enabled, then maximum
5170                  * capture size is 2.5KB (FIFO size of a single channel)
5171                  * minus 2 flits for CPL_TRACE_PKT header.
5172                  */
5173                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5174                         return -EINVAL;
5175         } else {
5176                 /* If multiple tracers are disabled, to avoid deadlocks
5177                  * maximum packet capture size of 9600 bytes is recommended.
5178                  * Also in this mode, only trace0 can be enabled and running.
5179                  */
5180                 multitrc = 0;
5181                 if (tp->snap_len > 9600 || idx)
5182                         return -EINVAL;
5183         }
5184
5185         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5186             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5187             tp->min_len > TFMINPKTSIZE_M)
5188                 return -EINVAL;
5189
5190         /* stop the tracer we'll be changing */
5191         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5192
5193         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5194         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5195         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5196
5197         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5198                 t4_write_reg(adap, data_reg, tp->data[i]);
5199                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5200         }
5201         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5202                      TFCAPTUREMAX_V(tp->snap_len) |
5203                      TFMINPKTSIZE_V(tp->min_len));
5204         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5205                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5206                      (is_t4(adap->params.chip) ?
5207                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5208                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5209                      T5_TFINVERTMATCH_V(tp->invert)));
5210
5211         return 0;
5212 }
5213
5214 /**
5215  *      t4_get_trace_filter - query one of the tracing filters
5216  *      @adap: the adapter
5217  *      @tp: the current trace filter parameters
5218  *      @idx: which trace filter to query
5219  *      @enabled: non-zero if the filter is enabled
5220  *
5221  *      Returns the current settings of one of the HW tracing filters.
5222  */
5223 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5224                          int *enabled)
5225 {
5226         u32 ctla, ctlb;
5227         int i, ofst = idx * 4;
5228         u32 data_reg, mask_reg;
5229
5230         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5231         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5232
5233         if (is_t4(adap->params.chip)) {
5234                 *enabled = !!(ctla & TFEN_F);
5235                 tp->port =  TFPORT_G(ctla);
5236                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5237         } else {
5238                 *enabled = !!(ctla & T5_TFEN_F);
5239                 tp->port = T5_TFPORT_G(ctla);
5240                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5241         }
5242         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5243         tp->min_len = TFMINPKTSIZE_G(ctlb);
5244         tp->skip_ofst = TFOFFSET_G(ctla);
5245         tp->skip_len = TFLENGTH_G(ctla);
5246
5247         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5248         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5249         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5250
5251         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5252                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5253                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5254         }
5255 }
5256
5257 /**
5258  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5259  *      @adap: the adapter
5260  *      @cnt: where to store the count statistics
5261  *      @cycles: where to store the cycle statistics
5262  *
5263  *      Returns performance statistics from PMTX.
5264  */
5265 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5266 {
5267         int i;
5268         u32 data[2];
5269
5270         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5271                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5272                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5273                 if (is_t4(adap->params.chip)) {
5274                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5275                 } else {
5276                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5277                                          PM_TX_DBG_DATA_A, data, 2,
5278                                          PM_TX_DBG_STAT_MSB_A);
5279                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5280                 }
5281         }
5282 }
5283
5284 /**
5285  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5286  *      @adap: the adapter
5287  *      @cnt: where to store the count statistics
5288  *      @cycles: where to store the cycle statistics
5289  *
5290  *      Returns performance statistics from PMRX.
5291  */
5292 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5293 {
5294         int i;
5295         u32 data[2];
5296
5297         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5298                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5299                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5300                 if (is_t4(adap->params.chip)) {
5301                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5302                 } else {
5303                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5304                                          PM_RX_DBG_DATA_A, data, 2,
5305                                          PM_RX_DBG_STAT_MSB_A);
5306                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5307                 }
5308         }
5309 }
5310
5311 /**
5312  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5313  *      @adap: the adapter
5314  *      @idx: the port index
5315  *
5316  *      Returns a bitmap indicating which MPS buffer groups are associated
5317  *      with the given port.  Bit i is set if buffer group i is used by the
5318  *      port.
5319  */
5320 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5321 {
5322         u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5323
5324         if (n == 0)
5325                 return idx == 0 ? 0xf : 0;
5326         /* In T6 (which is a 2 port card),
5327          * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5328          * For 2 port T4/T5 adapter,
5329          * port 0 is mapped to channel 0 and 1,
5330          * port 1 is mapped to channel 2 and 3.
5331          */
5332         if ((n == 1) &&
5333             (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5334                 return idx < 2 ? (3 << (2 * idx)) : 0;
5335         return 1 << idx;
5336 }
5337
5338 /**
5339  *      t4_get_port_type_description - return Port Type string description
5340  *      @port_type: firmware Port Type enumeration
5341  */
5342 const char *t4_get_port_type_description(enum fw_port_type port_type)
5343 {
5344         static const char *const port_type_description[] = {
5345                 "R XFI",
5346                 "R XAUI",
5347                 "T SGMII",
5348                 "T XFI",
5349                 "T XAUI",
5350                 "KX4",
5351                 "CX4",
5352                 "KX",
5353                 "KR",
5354                 "R SFP+",
5355                 "KR/KX",
5356                 "KR/KX/KX4",
5357                 "R QSFP_10G",
5358                 "R QSA",
5359                 "R QSFP",
5360                 "R BP40_BA",
5361         };
5362
5363         if (port_type < ARRAY_SIZE(port_type_description))
5364                 return port_type_description[port_type];
5365         return "UNKNOWN";
5366 }
5367
5368 /**
5369  *      t4_get_port_stats_offset - collect port stats relative to a previous
5370  *                                 snapshot
5371  *      @adap: The adapter
5372  *      @idx: The port
5373  *      @stats: Current stats to fill
5374  *      @offset: Previous stats snapshot
5375  */
5376 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5377                               struct port_stats *stats,
5378                               struct port_stats *offset)
5379 {
5380         u64 *s, *o;
5381         int i;
5382
5383         t4_get_port_stats(adap, idx, stats);
5384         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5385                         i < (sizeof(struct port_stats) / sizeof(u64));
5386                         i++, s++, o++)
5387                 *s -= *o;
5388 }
5389
5390 /**
5391  *      t4_get_port_stats - collect port statistics
5392  *      @adap: the adapter
5393  *      @idx: the port index
5394  *      @p: the stats structure to fill
5395  *
5396  *      Collect statistics related to the given port from HW.
5397  */
5398 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5399 {
5400         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5401
5402 #define GET_STAT(name) \
5403         t4_read_reg64(adap, \
5404         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5405         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5406 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5407
5408         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5409         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5410         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5411         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5412         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5413         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5414         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5415         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5416         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5417         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5418         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5419         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5420         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5421         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5422         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5423         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5424         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5425         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5426         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5427         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5428         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
5429         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
5430         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
5431
5432         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
5433         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
5434         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
5435         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
5436         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
5437         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
5438         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5439         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
5440         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
5441         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
5442         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
5443         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
5444         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
5445         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
5446         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
5447         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
5448         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5449         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
5450         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
5451         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
5452         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
5453         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
5454         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
5455         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
5456         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
5457         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
5458         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
5459
5460         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5461         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5462         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5463         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5464         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5465         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5466         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5467         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5468
5469 #undef GET_STAT
5470 #undef GET_STAT_COM
5471 }
5472
5473 /**
5474  *      t4_get_lb_stats - collect loopback port statistics
5475  *      @adap: the adapter
5476  *      @idx: the loopback port index
5477  *      @p: the stats structure to fill
5478  *
5479  *      Return HW statistics for the given loopback port.
5480  */
5481 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5482 {
5483         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5484
5485 #define GET_STAT(name) \
5486         t4_read_reg64(adap, \
5487         (is_t4(adap->params.chip) ? \
5488         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5489         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5490 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5491
5492         p->octets           = GET_STAT(BYTES);
5493         p->frames           = GET_STAT(FRAMES);
5494         p->bcast_frames     = GET_STAT(BCAST);
5495         p->mcast_frames     = GET_STAT(MCAST);
5496         p->ucast_frames     = GET_STAT(UCAST);
5497         p->error_frames     = GET_STAT(ERROR);
5498
5499         p->frames_64        = GET_STAT(64B);
5500         p->frames_65_127    = GET_STAT(65B_127B);
5501         p->frames_128_255   = GET_STAT(128B_255B);
5502         p->frames_256_511   = GET_STAT(256B_511B);
5503         p->frames_512_1023  = GET_STAT(512B_1023B);
5504         p->frames_1024_1518 = GET_STAT(1024B_1518B);
5505         p->frames_1519_max  = GET_STAT(1519B_MAX);
5506         p->drop             = GET_STAT(DROP_FRAMES);
5507
5508         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5509         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5510         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5511         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5512         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5513         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5514         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5515         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5516
5517 #undef GET_STAT
5518 #undef GET_STAT_COM
5519 }
5520
5521 /*     t4_mk_filtdelwr - create a delete filter WR
5522  *     @ftid: the filter ID
5523  *     @wr: the filter work request to populate
5524  *     @qid: ingress queue to receive the delete notification
5525  *
5526  *     Creates a filter work request to delete the supplied filter.  If @qid is
5527  *     negative the delete notification is suppressed.
5528  */
5529 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5530 {
5531         memset(wr, 0, sizeof(*wr));
5532         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5533         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5534         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5535                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
5536         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5537         if (qid >= 0)
5538                 wr->rx_chan_rx_rpl_iq =
5539                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5540 }
5541
5542 #define INIT_CMD(var, cmd, rd_wr) do { \
5543         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5544                                         FW_CMD_REQUEST_F | \
5545                                         FW_CMD_##rd_wr##_F); \
5546         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5547 } while (0)
5548
5549 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5550                           u32 addr, u32 val)
5551 {
5552         u32 ldst_addrspace;
5553         struct fw_ldst_cmd c;
5554
5555         memset(&c, 0, sizeof(c));
5556         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5557         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5558                                         FW_CMD_REQUEST_F |
5559                                         FW_CMD_WRITE_F |
5560                                         ldst_addrspace);
5561         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5562         c.u.addrval.addr = cpu_to_be32(addr);
5563         c.u.addrval.val = cpu_to_be32(val);
5564
5565         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5566 }
5567
5568 /**
5569  *      t4_mdio_rd - read a PHY register through MDIO
5570  *      @adap: the adapter
5571  *      @mbox: mailbox to use for the FW command
5572  *      @phy_addr: the PHY address
5573  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5574  *      @reg: the register to read
5575  *      @valp: where to store the value
5576  *
5577  *      Issues a FW command through the given mailbox to read a PHY register.
5578  */
5579 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5580                unsigned int mmd, unsigned int reg, u16 *valp)
5581 {
5582         int ret;
5583         u32 ldst_addrspace;
5584         struct fw_ldst_cmd c;
5585
5586         memset(&c, 0, sizeof(c));
5587         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5588         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5589                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5590                                         ldst_addrspace);
5591         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5592         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5593                                          FW_LDST_CMD_MMD_V(mmd));
5594         c.u.mdio.raddr = cpu_to_be16(reg);
5595
5596         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5597         if (ret == 0)
5598                 *valp = be16_to_cpu(c.u.mdio.rval);
5599         return ret;
5600 }
5601
5602 /**
5603  *      t4_mdio_wr - write a PHY register through MDIO
5604  *      @adap: the adapter
5605  *      @mbox: mailbox to use for the FW command
5606  *      @phy_addr: the PHY address
5607  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5608  *      @reg: the register to write
5609  *      @valp: value to write
5610  *
5611  *      Issues a FW command through the given mailbox to write a PHY register.
5612  */
5613 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5614                unsigned int mmd, unsigned int reg, u16 val)
5615 {
5616         u32 ldst_addrspace;
5617         struct fw_ldst_cmd c;
5618
5619         memset(&c, 0, sizeof(c));
5620         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5621         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5622                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5623                                         ldst_addrspace);
5624         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5625         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5626                                          FW_LDST_CMD_MMD_V(mmd));
5627         c.u.mdio.raddr = cpu_to_be16(reg);
5628         c.u.mdio.rval = cpu_to_be16(val);
5629
5630         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5631 }
5632
5633 /**
5634  *      t4_sge_decode_idma_state - decode the idma state
5635  *      @adap: the adapter
5636  *      @state: the state idma is stuck in
5637  */
5638 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5639 {
5640         static const char * const t4_decode[] = {
5641                 "IDMA_IDLE",
5642                 "IDMA_PUSH_MORE_CPL_FIFO",
5643                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5644                 "Not used",
5645                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5646                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5647                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5648                 "IDMA_SEND_FIFO_TO_IMSG",
5649                 "IDMA_FL_REQ_DATA_FL_PREP",
5650                 "IDMA_FL_REQ_DATA_FL",
5651                 "IDMA_FL_DROP",
5652                 "IDMA_FL_H_REQ_HEADER_FL",
5653                 "IDMA_FL_H_SEND_PCIEHDR",
5654                 "IDMA_FL_H_PUSH_CPL_FIFO",
5655                 "IDMA_FL_H_SEND_CPL",
5656                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5657                 "IDMA_FL_H_SEND_IP_HDR",
5658                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5659                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5660                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5661                 "IDMA_FL_D_SEND_PCIEHDR",
5662                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5663                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5664                 "IDMA_FL_SEND_PCIEHDR",
5665                 "IDMA_FL_PUSH_CPL_FIFO",
5666                 "IDMA_FL_SEND_CPL",
5667                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5668                 "IDMA_FL_SEND_PAYLOAD",
5669                 "IDMA_FL_REQ_NEXT_DATA_FL",
5670                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5671                 "IDMA_FL_SEND_PADDING",
5672                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5673                 "IDMA_FL_SEND_FIFO_TO_IMSG",
5674                 "IDMA_FL_REQ_DATAFL_DONE",
5675                 "IDMA_FL_REQ_HEADERFL_DONE",
5676         };
5677         static const char * const t5_decode[] = {
5678                 "IDMA_IDLE",
5679                 "IDMA_ALMOST_IDLE",
5680                 "IDMA_PUSH_MORE_CPL_FIFO",
5681                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5682                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5683                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5684                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5685                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5686                 "IDMA_SEND_FIFO_TO_IMSG",
5687                 "IDMA_FL_REQ_DATA_FL",
5688                 "IDMA_FL_DROP",
5689                 "IDMA_FL_DROP_SEND_INC",
5690                 "IDMA_FL_H_REQ_HEADER_FL",
5691                 "IDMA_FL_H_SEND_PCIEHDR",
5692                 "IDMA_FL_H_PUSH_CPL_FIFO",
5693                 "IDMA_FL_H_SEND_CPL",
5694                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5695                 "IDMA_FL_H_SEND_IP_HDR",
5696                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5697                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5698                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5699                 "IDMA_FL_D_SEND_PCIEHDR",
5700                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5701                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5702                 "IDMA_FL_SEND_PCIEHDR",
5703                 "IDMA_FL_PUSH_CPL_FIFO",
5704                 "IDMA_FL_SEND_CPL",
5705                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5706                 "IDMA_FL_SEND_PAYLOAD",
5707                 "IDMA_FL_REQ_NEXT_DATA_FL",
5708                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5709                 "IDMA_FL_SEND_PADDING",
5710                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5711         };
5712         static const char * const t6_decode[] = {
5713                 "IDMA_IDLE",
5714                 "IDMA_PUSH_MORE_CPL_FIFO",
5715                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5716                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5717                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5718                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5719                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5720                 "IDMA_FL_REQ_DATA_FL",
5721                 "IDMA_FL_DROP",
5722                 "IDMA_FL_DROP_SEND_INC",
5723                 "IDMA_FL_H_REQ_HEADER_FL",
5724                 "IDMA_FL_H_SEND_PCIEHDR",
5725                 "IDMA_FL_H_PUSH_CPL_FIFO",
5726                 "IDMA_FL_H_SEND_CPL",
5727                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5728                 "IDMA_FL_H_SEND_IP_HDR",
5729                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5730                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5731                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5732                 "IDMA_FL_D_SEND_PCIEHDR",
5733                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5734                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5735                 "IDMA_FL_SEND_PCIEHDR",
5736                 "IDMA_FL_PUSH_CPL_FIFO",
5737                 "IDMA_FL_SEND_CPL",
5738                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5739                 "IDMA_FL_SEND_PAYLOAD",
5740                 "IDMA_FL_REQ_NEXT_DATA_FL",
5741                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5742                 "IDMA_FL_SEND_PADDING",
5743                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5744         };
5745         static const u32 sge_regs[] = {
5746                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5747                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5748                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5749         };
5750         const char **sge_idma_decode;
5751         int sge_idma_decode_nstates;
5752         int i;
5753         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5754
5755         /* Select the right set of decode strings to dump depending on the
5756          * adapter chip type.
5757          */
5758         switch (chip_version) {
5759         case CHELSIO_T4:
5760                 sge_idma_decode = (const char **)t4_decode;
5761                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5762                 break;
5763
5764         case CHELSIO_T5:
5765                 sge_idma_decode = (const char **)t5_decode;
5766                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5767                 break;
5768
5769         case CHELSIO_T6:
5770                 sge_idma_decode = (const char **)t6_decode;
5771                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5772                 break;
5773
5774         default:
5775                 dev_err(adapter->pdev_dev,
5776                         "Unsupported chip version %d\n", chip_version);
5777                 return;
5778         }
5779
5780         if (is_t4(adapter->params.chip)) {
5781                 sge_idma_decode = (const char **)t4_decode;
5782                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5783         } else {
5784                 sge_idma_decode = (const char **)t5_decode;
5785                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5786         }
5787
5788         if (state < sge_idma_decode_nstates)
5789                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5790         else
5791                 CH_WARN(adapter, "idma state %d unknown\n", state);
5792
5793         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5794                 CH_WARN(adapter, "SGE register %#x value %#x\n",
5795                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5796 }
5797
5798 /**
5799  *      t4_sge_ctxt_flush - flush the SGE context cache
5800  *      @adap: the adapter
5801  *      @mbox: mailbox to use for the FW command
5802  *
5803  *      Issues a FW command through the given mailbox to flush the
5804  *      SGE context cache.
5805  */
5806 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5807 {
5808         int ret;
5809         u32 ldst_addrspace;
5810         struct fw_ldst_cmd c;
5811
5812         memset(&c, 0, sizeof(c));
5813         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5814         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5815                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5816                                         ldst_addrspace);
5817         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5818         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5819
5820         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5821         return ret;
5822 }
5823
5824 /**
5825  *      t4_fw_hello - establish communication with FW
5826  *      @adap: the adapter
5827  *      @mbox: mailbox to use for the FW command
5828  *      @evt_mbox: mailbox to receive async FW events
5829  *      @master: specifies the caller's willingness to be the device master
5830  *      @state: returns the current device state (if non-NULL)
5831  *
5832  *      Issues a command to establish communication with FW.  Returns either
5833  *      an error (negative integer) or the mailbox of the Master PF.
5834  */
5835 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5836                 enum dev_master master, enum dev_state *state)
5837 {
5838         int ret;
5839         struct fw_hello_cmd c;
5840         u32 v;
5841         unsigned int master_mbox;
5842         int retries = FW_CMD_HELLO_RETRIES;
5843
5844 retry:
5845         memset(&c, 0, sizeof(c));
5846         INIT_CMD(c, HELLO, WRITE);
5847         c.err_to_clearinit = cpu_to_be32(
5848                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5849                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5850                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5851                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
5852                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5853                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5854                 FW_HELLO_CMD_CLEARINIT_F);
5855
5856         /*
5857          * Issue the HELLO command to the firmware.  If it's not successful
5858          * but indicates that we got a "busy" or "timeout" condition, retry
5859          * the HELLO until we exhaust our retry limit.  If we do exceed our
5860          * retry limit, check to see if the firmware left us any error
5861          * information and report that if so.
5862          */
5863         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5864         if (ret < 0) {
5865                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5866                         goto retry;
5867                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5868                         t4_report_fw_error(adap);
5869                 return ret;
5870         }
5871
5872         v = be32_to_cpu(c.err_to_clearinit);
5873         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5874         if (state) {
5875                 if (v & FW_HELLO_CMD_ERR_F)
5876                         *state = DEV_STATE_ERR;
5877                 else if (v & FW_HELLO_CMD_INIT_F)
5878                         *state = DEV_STATE_INIT;
5879                 else
5880                         *state = DEV_STATE_UNINIT;
5881         }
5882
5883         /*
5884          * If we're not the Master PF then we need to wait around for the
5885          * Master PF Driver to finish setting up the adapter.
5886          *
5887          * Note that we also do this wait if we're a non-Master-capable PF and
5888          * there is no current Master PF; a Master PF may show up momentarily
5889          * and we wouldn't want to fail pointlessly.  (This can happen when an
5890          * OS loads lots of different drivers rapidly at the same time).  In
5891          * this case, the Master PF returned by the firmware will be
5892          * PCIE_FW_MASTER_M so the test below will work ...
5893          */
5894         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5895             master_mbox != mbox) {
5896                 int waiting = FW_CMD_HELLO_TIMEOUT;
5897
5898                 /*
5899                  * Wait for the firmware to either indicate an error or
5900                  * initialized state.  If we see either of these we bail out
5901                  * and report the issue to the caller.  If we exhaust the
5902                  * "hello timeout" and we haven't exhausted our retries, try
5903                  * again.  Otherwise bail with a timeout error.
5904                  */
5905                 for (;;) {
5906                         u32 pcie_fw;
5907
5908                         msleep(50);
5909                         waiting -= 50;
5910
5911                         /*
5912                          * If neither Error nor Initialialized are indicated
5913                          * by the firmware keep waiting till we exaust our
5914                          * timeout ... and then retry if we haven't exhausted
5915                          * our retries ...
5916                          */
5917                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5918                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5919                                 if (waiting <= 0) {
5920                                         if (retries-- > 0)
5921                                                 goto retry;
5922
5923                                         return -ETIMEDOUT;
5924                                 }
5925                                 continue;
5926                         }
5927
5928                         /*
5929                          * We either have an Error or Initialized condition
5930                          * report errors preferentially.
5931                          */
5932                         if (state) {
5933                                 if (pcie_fw & PCIE_FW_ERR_F)
5934                                         *state = DEV_STATE_ERR;
5935                                 else if (pcie_fw & PCIE_FW_INIT_F)
5936                                         *state = DEV_STATE_INIT;
5937                         }
5938
5939                         /*
5940                          * If we arrived before a Master PF was selected and
5941                          * there's not a valid Master PF, grab its identity
5942                          * for our caller.
5943                          */
5944                         if (master_mbox == PCIE_FW_MASTER_M &&
5945                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
5946                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5947                         break;
5948                 }
5949         }
5950
5951         return master_mbox;
5952 }
5953
5954 /**
5955  *      t4_fw_bye - end communication with FW
5956  *      @adap: the adapter
5957  *      @mbox: mailbox to use for the FW command
5958  *
5959  *      Issues a command to terminate communication with FW.
5960  */
5961 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5962 {
5963         struct fw_bye_cmd c;
5964
5965         memset(&c, 0, sizeof(c));
5966         INIT_CMD(c, BYE, WRITE);
5967         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5968 }
5969
5970 /**
5971  *      t4_init_cmd - ask FW to initialize the device
5972  *      @adap: the adapter
5973  *      @mbox: mailbox to use for the FW command
5974  *
5975  *      Issues a command to FW to partially initialize the device.  This
5976  *      performs initialization that generally doesn't depend on user input.
5977  */
5978 int t4_early_init(struct adapter *adap, unsigned int mbox)
5979 {
5980         struct fw_initialize_cmd c;
5981
5982         memset(&c, 0, sizeof(c));
5983         INIT_CMD(c, INITIALIZE, WRITE);
5984         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5985 }
5986
5987 /**
5988  *      t4_fw_reset - issue a reset to FW
5989  *      @adap: the adapter
5990  *      @mbox: mailbox to use for the FW command
5991  *      @reset: specifies the type of reset to perform
5992  *
5993  *      Issues a reset command of the specified type to FW.
5994  */
5995 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5996 {
5997         struct fw_reset_cmd c;
5998
5999         memset(&c, 0, sizeof(c));
6000         INIT_CMD(c, RESET, WRITE);
6001         c.val = cpu_to_be32(reset);
6002         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6003 }
6004
6005 /**
6006  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6007  *      @adap: the adapter
6008  *      @mbox: mailbox to use for the FW RESET command (if desired)
6009  *      @force: force uP into RESET even if FW RESET command fails
6010  *
6011  *      Issues a RESET command to firmware (if desired) with a HALT indication
6012  *      and then puts the microprocessor into RESET state.  The RESET command
6013  *      will only be issued if a legitimate mailbox is provided (mbox <=
6014  *      PCIE_FW_MASTER_M).
6015  *
6016  *      This is generally used in order for the host to safely manipulate the
6017  *      adapter without fear of conflicting with whatever the firmware might
6018  *      be doing.  The only way out of this state is to RESTART the firmware
6019  *      ...
6020  */
6021 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6022 {
6023         int ret = 0;
6024
6025         /*
6026          * If a legitimate mailbox is provided, issue a RESET command
6027          * with a HALT indication.
6028          */
6029         if (mbox <= PCIE_FW_MASTER_M) {
6030                 struct fw_reset_cmd c;
6031
6032                 memset(&c, 0, sizeof(c));
6033                 INIT_CMD(c, RESET, WRITE);
6034                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6035                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6036                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6037         }
6038
6039         /*
6040          * Normally we won't complete the operation if the firmware RESET
6041          * command fails but if our caller insists we'll go ahead and put the
6042          * uP into RESET.  This can be useful if the firmware is hung or even
6043          * missing ...  We'll have to take the risk of putting the uP into
6044          * RESET without the cooperation of firmware in that case.
6045          *
6046          * We also force the firmware's HALT flag to be on in case we bypassed
6047          * the firmware RESET command above or we're dealing with old firmware
6048          * which doesn't have the HALT capability.  This will serve as a flag
6049          * for the incoming firmware to know that it's coming out of a HALT
6050          * rather than a RESET ... if it's new enough to understand that ...
6051          */
6052         if (ret == 0 || force) {
6053                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6054                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6055                                  PCIE_FW_HALT_F);
6056         }
6057
6058         /*
6059          * And we always return the result of the firmware RESET command
6060          * even when we force the uP into RESET ...
6061          */
6062         return ret;
6063 }
6064
6065 /**
6066  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6067  *      @adap: the adapter
6068  *      @reset: if we want to do a RESET to restart things
6069  *
6070  *      Restart firmware previously halted by t4_fw_halt().  On successful
6071  *      return the previous PF Master remains as the new PF Master and there
6072  *      is no need to issue a new HELLO command, etc.
6073  *
6074  *      We do this in two ways:
6075  *
6076  *       1. If we're dealing with newer firmware we'll simply want to take
6077  *          the chip's microprocessor out of RESET.  This will cause the
6078  *          firmware to start up from its start vector.  And then we'll loop
6079  *          until the firmware indicates it's started again (PCIE_FW.HALT
6080  *          reset to 0) or we timeout.
6081  *
6082  *       2. If we're dealing with older firmware then we'll need to RESET
6083  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6084  *          flag and automatically RESET itself on startup.
6085  */
6086 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6087 {
6088         if (reset) {
6089                 /*
6090                  * Since we're directing the RESET instead of the firmware
6091                  * doing it automatically, we need to clear the PCIE_FW.HALT
6092                  * bit.
6093                  */
6094                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6095
6096                 /*
6097                  * If we've been given a valid mailbox, first try to get the
6098                  * firmware to do the RESET.  If that works, great and we can
6099                  * return success.  Otherwise, if we haven't been given a
6100                  * valid mailbox or the RESET command failed, fall back to
6101                  * hitting the chip with a hammer.
6102                  */
6103                 if (mbox <= PCIE_FW_MASTER_M) {
6104                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6105                         msleep(100);
6106                         if (t4_fw_reset(adap, mbox,
6107                                         PIORST_F | PIORSTMODE_F) == 0)
6108                                 return 0;
6109                 }
6110
6111                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6112                 msleep(2000);
6113         } else {
6114                 int ms;
6115
6116                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6117                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6118                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6119                                 return 0;
6120                         msleep(100);
6121                         ms += 100;
6122                 }
6123                 return -ETIMEDOUT;
6124         }
6125         return 0;
6126 }
6127
6128 /**
6129  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6130  *      @adap: the adapter
6131  *      @mbox: mailbox to use for the FW RESET command (if desired)
6132  *      @fw_data: the firmware image to write
6133  *      @size: image size
6134  *      @force: force upgrade even if firmware doesn't cooperate
6135  *
6136  *      Perform all of the steps necessary for upgrading an adapter's
6137  *      firmware image.  Normally this requires the cooperation of the
6138  *      existing firmware in order to halt all existing activities
6139  *      but if an invalid mailbox token is passed in we skip that step
6140  *      (though we'll still put the adapter microprocessor into RESET in
6141  *      that case).
6142  *
6143  *      On successful return the new firmware will have been loaded and
6144  *      the adapter will have been fully RESET losing all previous setup
6145  *      state.  On unsuccessful return the adapter may be completely hosed ...
6146  *      positive errno indicates that the adapter is ~probably~ intact, a
6147  *      negative errno indicates that things are looking bad ...
6148  */
6149 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6150                   const u8 *fw_data, unsigned int size, int force)
6151 {
6152         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6153         int reset, ret;
6154
6155         if (!t4_fw_matches_chip(adap, fw_hdr))
6156                 return -EINVAL;
6157
6158         ret = t4_fw_halt(adap, mbox, force);
6159         if (ret < 0 && !force)
6160                 return ret;
6161
6162         ret = t4_load_fw(adap, fw_data, size);
6163         if (ret < 0)
6164                 return ret;
6165
6166         /*
6167          * Older versions of the firmware don't understand the new
6168          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6169          * restart.  So for newly loaded older firmware we'll have to do the
6170          * RESET for it so it starts up on a clean slate.  We can tell if
6171          * the newly loaded firmware will handle this right by checking
6172          * its header flags to see if it advertises the capability.
6173          */
6174         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6175         return t4_fw_restart(adap, mbox, reset);
6176 }
6177
6178 /**
6179  *      t4_fl_pkt_align - return the fl packet alignment
6180  *      @adap: the adapter
6181  *
6182  *      T4 has a single field to specify the packing and padding boundary.
6183  *      T5 onwards has separate fields for this and hence the alignment for
6184  *      next packet offset is maximum of these two.
6185  *
6186  */
6187 int t4_fl_pkt_align(struct adapter *adap)
6188 {
6189         u32 sge_control, sge_control2;
6190         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6191
6192         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6193
6194         /* T4 uses a single control field to specify both the PCIe Padding and
6195          * Packing Boundary.  T5 introduced the ability to specify these
6196          * separately.  The actual Ingress Packet Data alignment boundary
6197          * within Packed Buffer Mode is the maximum of these two
6198          * specifications.  (Note that it makes no real practical sense to
6199          * have the Pading Boudary be larger than the Packing Boundary but you
6200          * could set the chip up that way and, in fact, legacy T4 code would
6201          * end doing this because it would initialize the Padding Boundary and
6202          * leave the Packing Boundary initialized to 0 (16 bytes).)
6203          * Padding Boundary values in T6 starts from 8B,
6204          * where as it is 32B for T4 and T5.
6205          */
6206         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6207                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6208         else
6209                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6210
6211         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6212
6213         fl_align = ingpadboundary;
6214         if (!is_t4(adap->params.chip)) {
6215                 /* T5 has a weird interpretation of one of the PCIe Packing
6216                  * Boundary values.  No idea why ...
6217                  */
6218                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6219                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6220                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6221                         ingpackboundary = 16;
6222                 else
6223                         ingpackboundary = 1 << (ingpackboundary +
6224                                                 INGPACKBOUNDARY_SHIFT_X);
6225
6226                 fl_align = max(ingpadboundary, ingpackboundary);
6227         }
6228         return fl_align;
6229 }
6230
6231 /**
6232  *      t4_fixup_host_params - fix up host-dependent parameters
6233  *      @adap: the adapter
6234  *      @page_size: the host's Base Page Size
6235  *      @cache_line_size: the host's Cache Line Size
6236  *
6237  *      Various registers in T4 contain values which are dependent on the
6238  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6239  *      those registers with the appropriate values as passed in ...
6240  */
6241 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6242                          unsigned int cache_line_size)
6243 {
6244         unsigned int page_shift = fls(page_size) - 1;
6245         unsigned int sge_hps = page_shift - 10;
6246         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6247         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6248         unsigned int fl_align_log = fls(fl_align) - 1;
6249         unsigned int ingpad;
6250
6251         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6252                      HOSTPAGESIZEPF0_V(sge_hps) |
6253                      HOSTPAGESIZEPF1_V(sge_hps) |
6254                      HOSTPAGESIZEPF2_V(sge_hps) |
6255                      HOSTPAGESIZEPF3_V(sge_hps) |
6256                      HOSTPAGESIZEPF4_V(sge_hps) |
6257                      HOSTPAGESIZEPF5_V(sge_hps) |
6258                      HOSTPAGESIZEPF6_V(sge_hps) |
6259                      HOSTPAGESIZEPF7_V(sge_hps));
6260
6261         if (is_t4(adap->params.chip)) {
6262                 t4_set_reg_field(adap, SGE_CONTROL_A,
6263                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6264                                  EGRSTATUSPAGESIZE_F,
6265                                  INGPADBOUNDARY_V(fl_align_log -
6266                                                   INGPADBOUNDARY_SHIFT_X) |
6267                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6268         } else {
6269                 /* T5 introduced the separation of the Free List Padding and
6270                  * Packing Boundaries.  Thus, we can select a smaller Padding
6271                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6272                  * Bandwidth, and use a Packing Boundary which is large enough
6273                  * to avoid false sharing between CPUs, etc.
6274                  *
6275                  * For the PCI Link, the smaller the Padding Boundary the
6276                  * better.  For the Memory Controller, a smaller Padding
6277                  * Boundary is better until we cross under the Memory Line
6278                  * Size (the minimum unit of transfer to/from Memory).  If we
6279                  * have a Padding Boundary which is smaller than the Memory
6280                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6281                  * Memory Controller which is never good.  For T5 the smallest
6282                  * Padding Boundary which we can select is 32 bytes which is
6283                  * larger than any known Memory Controller Line Size so we'll
6284                  * use that.
6285                  *
6286                  * T5 has a different interpretation of the "0" value for the
6287                  * Packing Boundary.  This corresponds to 16 bytes instead of
6288                  * the expected 32 bytes.  We never have a Packing Boundary
6289                  * less than 32 bytes so we can't use that special value but
6290                  * on the other hand, if we wanted 32 bytes, the best we can
6291                  * really do is 64 bytes.
6292                 */
6293                 if (fl_align <= 32) {
6294                         fl_align = 64;
6295                         fl_align_log = 6;
6296                 }
6297
6298                 if (is_t5(adap->params.chip))
6299                         ingpad = INGPCIEBOUNDARY_32B_X;
6300                 else
6301                         ingpad = T6_INGPADBOUNDARY_32B_X;
6302
6303                 t4_set_reg_field(adap, SGE_CONTROL_A,
6304                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6305                                  EGRSTATUSPAGESIZE_F,
6306                                  INGPADBOUNDARY_V(ingpad) |
6307                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6308                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6309                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6310                                  INGPACKBOUNDARY_V(fl_align_log -
6311                                                    INGPACKBOUNDARY_SHIFT_X));
6312         }
6313         /*
6314          * Adjust various SGE Free List Host Buffer Sizes.
6315          *
6316          * This is something of a crock since we're using fixed indices into
6317          * the array which are also known by the sge.c code and the T4
6318          * Firmware Configuration File.  We need to come up with a much better
6319          * approach to managing this array.  For now, the first four entries
6320          * are:
6321          *
6322          *   0: Host Page Size
6323          *   1: 64KB
6324          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6325          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6326          *
6327          * For the single-MTU buffers in unpacked mode we need to include
6328          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6329          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6330          * Padding boundary.  All of these are accommodated in the Factory
6331          * Default Firmware Configuration File but we need to adjust it for
6332          * this host's cache line size.
6333          */
6334         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6335         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6336                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6337                      & ~(fl_align-1));
6338         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6339                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6340                      & ~(fl_align-1));
6341
6342         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6343
6344         return 0;
6345 }
6346
6347 /**
6348  *      t4_fw_initialize - ask FW to initialize the device
6349  *      @adap: the adapter
6350  *      @mbox: mailbox to use for the FW command
6351  *
6352  *      Issues a command to FW to partially initialize the device.  This
6353  *      performs initialization that generally doesn't depend on user input.
6354  */
6355 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6356 {
6357         struct fw_initialize_cmd c;
6358
6359         memset(&c, 0, sizeof(c));
6360         INIT_CMD(c, INITIALIZE, WRITE);
6361         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6362 }
6363
6364 /**
6365  *      t4_query_params_rw - query FW or device parameters
6366  *      @adap: the adapter
6367  *      @mbox: mailbox to use for the FW command
6368  *      @pf: the PF
6369  *      @vf: the VF
6370  *      @nparams: the number of parameters
6371  *      @params: the parameter names
6372  *      @val: the parameter values
6373  *      @rw: Write and read flag
6374  *
6375  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
6376  *      queried at once.
6377  */
6378 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6379                        unsigned int vf, unsigned int nparams, const u32 *params,
6380                        u32 *val, int rw)
6381 {
6382         int i, ret;
6383         struct fw_params_cmd c;
6384         __be32 *p = &c.param[0].mnem;
6385
6386         if (nparams > 7)
6387                 return -EINVAL;
6388
6389         memset(&c, 0, sizeof(c));
6390         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6391                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
6392                                   FW_PARAMS_CMD_PFN_V(pf) |
6393                                   FW_PARAMS_CMD_VFN_V(vf));
6394         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6395
6396         for (i = 0; i < nparams; i++) {
6397                 *p++ = cpu_to_be32(*params++);
6398                 if (rw)
6399                         *p = cpu_to_be32(*(val + i));
6400                 p++;
6401         }
6402
6403         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6404         if (ret == 0)
6405                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6406                         *val++ = be32_to_cpu(*p);
6407         return ret;
6408 }
6409
6410 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6411                     unsigned int vf, unsigned int nparams, const u32 *params,
6412                     u32 *val)
6413 {
6414         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6415 }
6416
6417 /**
6418  *      t4_set_params_timeout - sets FW or device parameters
6419  *      @adap: the adapter
6420  *      @mbox: mailbox to use for the FW command
6421  *      @pf: the PF
6422  *      @vf: the VF
6423  *      @nparams: the number of parameters
6424  *      @params: the parameter names
6425  *      @val: the parameter values
6426  *      @timeout: the timeout time
6427  *
6428  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6429  *      specified at once.
6430  */
6431 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6432                           unsigned int pf, unsigned int vf,
6433                           unsigned int nparams, const u32 *params,
6434                           const u32 *val, int timeout)
6435 {
6436         struct fw_params_cmd c;
6437         __be32 *p = &c.param[0].mnem;
6438
6439         if (nparams > 7)
6440                 return -EINVAL;
6441
6442         memset(&c, 0, sizeof(c));
6443         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6444                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6445                                   FW_PARAMS_CMD_PFN_V(pf) |
6446                                   FW_PARAMS_CMD_VFN_V(vf));
6447         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6448
6449         while (nparams--) {
6450                 *p++ = cpu_to_be32(*params++);
6451                 *p++ = cpu_to_be32(*val++);
6452         }
6453
6454         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6455 }
6456
6457 /**
6458  *      t4_set_params - sets FW or device parameters
6459  *      @adap: the adapter
6460  *      @mbox: mailbox to use for the FW command
6461  *      @pf: the PF
6462  *      @vf: the VF
6463  *      @nparams: the number of parameters
6464  *      @params: the parameter names
6465  *      @val: the parameter values
6466  *
6467  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6468  *      specified at once.
6469  */
6470 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6471                   unsigned int vf, unsigned int nparams, const u32 *params,
6472                   const u32 *val)
6473 {
6474         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6475                                      FW_CMD_MAX_TIMEOUT);
6476 }
6477
6478 /**
6479  *      t4_cfg_pfvf - configure PF/VF resource limits
6480  *      @adap: the adapter
6481  *      @mbox: mailbox to use for the FW command
6482  *      @pf: the PF being configured
6483  *      @vf: the VF being configured
6484  *      @txq: the max number of egress queues
6485  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
6486  *      @rxqi: the max number of interrupt-capable ingress queues
6487  *      @rxq: the max number of interruptless ingress queues
6488  *      @tc: the PCI traffic class
6489  *      @vi: the max number of virtual interfaces
6490  *      @cmask: the channel access rights mask for the PF/VF
6491  *      @pmask: the port access rights mask for the PF/VF
6492  *      @nexact: the maximum number of exact MPS filters
6493  *      @rcaps: read capabilities
6494  *      @wxcaps: write/execute capabilities
6495  *
6496  *      Configures resource limits and capabilities for a physical or virtual
6497  *      function.
6498  */
6499 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6500                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6501                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6502                 unsigned int vi, unsigned int cmask, unsigned int pmask,
6503                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6504 {
6505         struct fw_pfvf_cmd c;
6506
6507         memset(&c, 0, sizeof(c));
6508         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6509                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6510                                   FW_PFVF_CMD_VFN_V(vf));
6511         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6512         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6513                                      FW_PFVF_CMD_NIQ_V(rxq));
6514         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6515                                     FW_PFVF_CMD_PMASK_V(pmask) |
6516                                     FW_PFVF_CMD_NEQ_V(txq));
6517         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6518                                       FW_PFVF_CMD_NVI_V(vi) |
6519                                       FW_PFVF_CMD_NEXACTF_V(nexact));
6520         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6521                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6522                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6523         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6524 }
6525
6526 /**
6527  *      t4_alloc_vi - allocate a virtual interface
6528  *      @adap: the adapter
6529  *      @mbox: mailbox to use for the FW command
6530  *      @port: physical port associated with the VI
6531  *      @pf: the PF owning the VI
6532  *      @vf: the VF owning the VI
6533  *      @nmac: number of MAC addresses needed (1 to 5)
6534  *      @mac: the MAC addresses of the VI
6535  *      @rss_size: size of RSS table slice associated with this VI
6536  *
6537  *      Allocates a virtual interface for the given physical port.  If @mac is
6538  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
6539  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
6540  *      stored consecutively so the space needed is @nmac * 6 bytes.
6541  *      Returns a negative error number or the non-negative VI id.
6542  */
6543 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6544                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6545                 unsigned int *rss_size)
6546 {
6547         int ret;
6548         struct fw_vi_cmd c;
6549
6550         memset(&c, 0, sizeof(c));
6551         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6552                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6553                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6554         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6555         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6556         c.nmac = nmac - 1;
6557
6558         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6559         if (ret)
6560                 return ret;
6561
6562         if (mac) {
6563                 memcpy(mac, c.mac, sizeof(c.mac));
6564                 switch (nmac) {
6565                 case 5:
6566                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6567                 case 4:
6568                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6569                 case 3:
6570                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6571                 case 2:
6572                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6573                 }
6574         }
6575         if (rss_size)
6576                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6577         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6578 }
6579
6580 /**
6581  *      t4_free_vi - free a virtual interface
6582  *      @adap: the adapter
6583  *      @mbox: mailbox to use for the FW command
6584  *      @pf: the PF owning the VI
6585  *      @vf: the VF owning the VI
6586  *      @viid: virtual interface identifiler
6587  *
6588  *      Free a previously allocated virtual interface.
6589  */
6590 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6591                unsigned int vf, unsigned int viid)
6592 {
6593         struct fw_vi_cmd c;
6594
6595         memset(&c, 0, sizeof(c));
6596         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6597                                   FW_CMD_REQUEST_F |
6598                                   FW_CMD_EXEC_F |
6599                                   FW_VI_CMD_PFN_V(pf) |
6600                                   FW_VI_CMD_VFN_V(vf));
6601         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6602         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6603
6604         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6605 }
6606
6607 /**
6608  *      t4_set_rxmode - set Rx properties of a virtual interface
6609  *      @adap: the adapter
6610  *      @mbox: mailbox to use for the FW command
6611  *      @viid: the VI id
6612  *      @mtu: the new MTU or -1
6613  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6614  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6615  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6616  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6617  *      @sleep_ok: if true we may sleep while awaiting command completion
6618  *
6619  *      Sets Rx properties of a virtual interface.
6620  */
6621 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6622                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
6623                   bool sleep_ok)
6624 {
6625         struct fw_vi_rxmode_cmd c;
6626
6627         /* convert to FW values */
6628         if (mtu < 0)
6629                 mtu = FW_RXMODE_MTU_NO_CHG;
6630         if (promisc < 0)
6631                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6632         if (all_multi < 0)
6633                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6634         if (bcast < 0)
6635                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6636         if (vlanex < 0)
6637                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6638
6639         memset(&c, 0, sizeof(c));
6640         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6641                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6642                                    FW_VI_RXMODE_CMD_VIID_V(viid));
6643         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6644         c.mtu_to_vlanexen =
6645                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6646                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6647                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6648                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6649                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6650         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6651 }
6652
6653 /**
6654  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6655  *      @adap: the adapter
6656  *      @mbox: mailbox to use for the FW command
6657  *      @viid: the VI id
6658  *      @free: if true any existing filters for this VI id are first removed
6659  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6660  *      @addr: the MAC address(es)
6661  *      @idx: where to store the index of each allocated filter
6662  *      @hash: pointer to hash address filter bitmap
6663  *      @sleep_ok: call is allowed to sleep
6664  *
6665  *      Allocates an exact-match filter for each of the supplied addresses and
6666  *      sets it to the corresponding address.  If @idx is not %NULL it should
6667  *      have at least @naddr entries, each of which will be set to the index of
6668  *      the filter allocated for the corresponding MAC address.  If a filter
6669  *      could not be allocated for an address its index is set to 0xffff.
6670  *      If @hash is not %NULL addresses that fail to allocate an exact filter
6671  *      are hashed and update the hash filter bitmap pointed at by @hash.
6672  *
6673  *      Returns a negative error number or the number of filters allocated.
6674  */
6675 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6676                       unsigned int viid, bool free, unsigned int naddr,
6677                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6678 {
6679         int offset, ret = 0;
6680         struct fw_vi_mac_cmd c;
6681         unsigned int nfilters = 0;
6682         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6683         unsigned int rem = naddr;
6684
6685         if (naddr > max_naddr)
6686                 return -EINVAL;
6687
6688         for (offset = 0; offset < naddr ; /**/) {
6689                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6690                                          rem : ARRAY_SIZE(c.u.exact));
6691                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6692                                                      u.exact[fw_naddr]), 16);
6693                 struct fw_vi_mac_exact *p;
6694                 int i;
6695
6696                 memset(&c, 0, sizeof(c));
6697                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6698                                            FW_CMD_REQUEST_F |
6699                                            FW_CMD_WRITE_F |
6700                                            FW_CMD_EXEC_V(free) |
6701                                            FW_VI_MAC_CMD_VIID_V(viid));
6702                 c.freemacs_to_len16 =
6703                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6704                                     FW_CMD_LEN16_V(len16));
6705
6706                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6707                         p->valid_to_idx =
6708                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6709                                             FW_VI_MAC_CMD_IDX_V(
6710                                                     FW_VI_MAC_ADD_MAC));
6711                         memcpy(p->macaddr, addr[offset + i],
6712                                sizeof(p->macaddr));
6713                 }
6714
6715                 /* It's okay if we run out of space in our MAC address arena.
6716                  * Some of the addresses we submit may get stored so we need
6717                  * to run through the reply to see what the results were ...
6718                  */
6719                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6720                 if (ret && ret != -FW_ENOMEM)
6721                         break;
6722
6723                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6724                         u16 index = FW_VI_MAC_CMD_IDX_G(
6725                                         be16_to_cpu(p->valid_to_idx));
6726
6727                         if (idx)
6728                                 idx[offset + i] = (index >= max_naddr ?
6729                                                    0xffff : index);
6730                         if (index < max_naddr)
6731                                 nfilters++;
6732                         else if (hash)
6733                                 *hash |= (1ULL <<
6734                                           hash_mac_addr(addr[offset + i]));
6735                 }
6736
6737                 free = false;
6738                 offset += fw_naddr;
6739                 rem -= fw_naddr;
6740         }
6741
6742         if (ret == 0 || ret == -FW_ENOMEM)
6743                 ret = nfilters;
6744         return ret;
6745 }
6746
6747 /**
6748  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
6749  *      @adap: the adapter
6750  *      @mbox: mailbox to use for the FW command
6751  *      @viid: the VI id
6752  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6753  *      @addr: the MAC address(es)
6754  *      @sleep_ok: call is allowed to sleep
6755  *
6756  *      Frees the exact-match filter for each of the supplied addresses
6757  *
6758  *      Returns a negative error number or the number of filters freed.
6759  */
6760 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6761                      unsigned int viid, unsigned int naddr,
6762                      const u8 **addr, bool sleep_ok)
6763 {
6764         int offset, ret = 0;
6765         struct fw_vi_mac_cmd c;
6766         unsigned int nfilters = 0;
6767         unsigned int max_naddr = is_t4(adap->params.chip) ?
6768                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
6769                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6770         unsigned int rem = naddr;
6771
6772         if (naddr > max_naddr)
6773                 return -EINVAL;
6774
6775         for (offset = 0; offset < (int)naddr ; /**/) {
6776                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6777                                          ? rem
6778                                          : ARRAY_SIZE(c.u.exact));
6779                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6780                                                      u.exact[fw_naddr]), 16);
6781                 struct fw_vi_mac_exact *p;
6782                 int i;
6783
6784                 memset(&c, 0, sizeof(c));
6785                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6786                                      FW_CMD_REQUEST_F |
6787                                      FW_CMD_WRITE_F |
6788                                      FW_CMD_EXEC_V(0) |
6789                                      FW_VI_MAC_CMD_VIID_V(viid));
6790                 c.freemacs_to_len16 =
6791                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6792                                             FW_CMD_LEN16_V(len16));
6793
6794                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6795                         p->valid_to_idx = cpu_to_be16(
6796                                 FW_VI_MAC_CMD_VALID_F |
6797                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6798                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6799                 }
6800
6801                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6802                 if (ret)
6803                         break;
6804
6805                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6806                         u16 index = FW_VI_MAC_CMD_IDX_G(
6807                                                 be16_to_cpu(p->valid_to_idx));
6808
6809                         if (index < max_naddr)
6810                                 nfilters++;
6811                 }
6812
6813                 offset += fw_naddr;
6814                 rem -= fw_naddr;
6815         }
6816
6817         if (ret == 0)
6818                 ret = nfilters;
6819         return ret;
6820 }
6821
6822 /**
6823  *      t4_change_mac - modifies the exact-match filter for a MAC address
6824  *      @adap: the adapter
6825  *      @mbox: mailbox to use for the FW command
6826  *      @viid: the VI id
6827  *      @idx: index of existing filter for old value of MAC address, or -1
6828  *      @addr: the new MAC address value
6829  *      @persist: whether a new MAC allocation should be persistent
6830  *      @add_smt: if true also add the address to the HW SMT
6831  *
6832  *      Modifies an exact-match filter and sets it to the new MAC address.
6833  *      Note that in general it is not possible to modify the value of a given
6834  *      filter so the generic way to modify an address filter is to free the one
6835  *      being used by the old address value and allocate a new filter for the
6836  *      new address value.  @idx can be -1 if the address is a new addition.
6837  *
6838  *      Returns a negative error number or the index of the filter with the new
6839  *      MAC value.
6840  */
6841 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6842                   int idx, const u8 *addr, bool persist, bool add_smt)
6843 {
6844         int ret, mode;
6845         struct fw_vi_mac_cmd c;
6846         struct fw_vi_mac_exact *p = c.u.exact;
6847         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6848
6849         if (idx < 0)                             /* new allocation */
6850                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6851         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6852
6853         memset(&c, 0, sizeof(c));
6854         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6855                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6856                                    FW_VI_MAC_CMD_VIID_V(viid));
6857         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6858         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6859                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6860                                       FW_VI_MAC_CMD_IDX_V(idx));
6861         memcpy(p->macaddr, addr, sizeof(p->macaddr));
6862
6863         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6864         if (ret == 0) {
6865                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6866                 if (ret >= max_mac_addr)
6867                         ret = -ENOMEM;
6868         }
6869         return ret;
6870 }
6871
6872 /**
6873  *      t4_set_addr_hash - program the MAC inexact-match hash filter
6874  *      @adap: the adapter
6875  *      @mbox: mailbox to use for the FW command
6876  *      @viid: the VI id
6877  *      @ucast: whether the hash filter should also match unicast addresses
6878  *      @vec: the value to be written to the hash filter
6879  *      @sleep_ok: call is allowed to sleep
6880  *
6881  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
6882  */
6883 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6884                      bool ucast, u64 vec, bool sleep_ok)
6885 {
6886         struct fw_vi_mac_cmd c;
6887
6888         memset(&c, 0, sizeof(c));
6889         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6890                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6891                                    FW_VI_ENABLE_CMD_VIID_V(viid));
6892         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6893                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6894                                           FW_CMD_LEN16_V(1));
6895         c.u.hash.hashvec = cpu_to_be64(vec);
6896         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6897 }
6898
6899 /**
6900  *      t4_enable_vi_params - enable/disable a virtual interface
6901  *      @adap: the adapter
6902  *      @mbox: mailbox to use for the FW command
6903  *      @viid: the VI id
6904  *      @rx_en: 1=enable Rx, 0=disable Rx
6905  *      @tx_en: 1=enable Tx, 0=disable Tx
6906  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
6907  *
6908  *      Enables/disables a virtual interface.  Note that setting DCB Enable
6909  *      only makes sense when enabling a Virtual Interface ...
6910  */
6911 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6912                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6913 {
6914         struct fw_vi_enable_cmd c;
6915
6916         memset(&c, 0, sizeof(c));
6917         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6918                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6919                                    FW_VI_ENABLE_CMD_VIID_V(viid));
6920         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6921                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6922                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6923                                      FW_LEN16(c));
6924         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6925 }
6926
6927 /**
6928  *      t4_enable_vi - enable/disable a virtual interface
6929  *      @adap: the adapter
6930  *      @mbox: mailbox to use for the FW command
6931  *      @viid: the VI id
6932  *      @rx_en: 1=enable Rx, 0=disable Rx
6933  *      @tx_en: 1=enable Tx, 0=disable Tx
6934  *
6935  *      Enables/disables a virtual interface.
6936  */
6937 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6938                  bool rx_en, bool tx_en)
6939 {
6940         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6941 }
6942
6943 /**
6944  *      t4_identify_port - identify a VI's port by blinking its LED
6945  *      @adap: the adapter
6946  *      @mbox: mailbox to use for the FW command
6947  *      @viid: the VI id
6948  *      @nblinks: how many times to blink LED at 2.5 Hz
6949  *
6950  *      Identifies a VI's port by blinking its LED.
6951  */
6952 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6953                      unsigned int nblinks)
6954 {
6955         struct fw_vi_enable_cmd c;
6956
6957         memset(&c, 0, sizeof(c));
6958         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6959                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6960                                    FW_VI_ENABLE_CMD_VIID_V(viid));
6961         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6962         c.blinkdur = cpu_to_be16(nblinks);
6963         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6964 }
6965
6966 /**
6967  *      t4_iq_stop - stop an ingress queue and its FLs
6968  *      @adap: the adapter
6969  *      @mbox: mailbox to use for the FW command
6970  *      @pf: the PF owning the queues
6971  *      @vf: the VF owning the queues
6972  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
6973  *      @iqid: ingress queue id
6974  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
6975  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
6976  *
6977  *      Stops an ingress queue and its associated FLs, if any.  This causes
6978  *      any current or future data/messages destined for these queues to be
6979  *      tossed.
6980  */
6981 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
6982                unsigned int vf, unsigned int iqtype, unsigned int iqid,
6983                unsigned int fl0id, unsigned int fl1id)
6984 {
6985         struct fw_iq_cmd c;
6986
6987         memset(&c, 0, sizeof(c));
6988         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6989                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6990                                   FW_IQ_CMD_VFN_V(vf));
6991         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
6992         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6993         c.iqid = cpu_to_be16(iqid);
6994         c.fl0id = cpu_to_be16(fl0id);
6995         c.fl1id = cpu_to_be16(fl1id);
6996         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6997 }
6998
6999 /**
7000  *      t4_iq_free - free an ingress queue and its FLs
7001  *      @adap: the adapter
7002  *      @mbox: mailbox to use for the FW command
7003  *      @pf: the PF owning the queues
7004  *      @vf: the VF owning the queues
7005  *      @iqtype: the ingress queue type
7006  *      @iqid: ingress queue id
7007  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7008  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7009  *
7010  *      Frees an ingress queue and its associated FLs, if any.
7011  */
7012 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7013                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7014                unsigned int fl0id, unsigned int fl1id)
7015 {
7016         struct fw_iq_cmd c;
7017
7018         memset(&c, 0, sizeof(c));
7019         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7020                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7021                                   FW_IQ_CMD_VFN_V(vf));
7022         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7023         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7024         c.iqid = cpu_to_be16(iqid);
7025         c.fl0id = cpu_to_be16(fl0id);
7026         c.fl1id = cpu_to_be16(fl1id);
7027         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7028 }
7029
7030 /**
7031  *      t4_eth_eq_free - free an Ethernet egress queue
7032  *      @adap: the adapter
7033  *      @mbox: mailbox to use for the FW command
7034  *      @pf: the PF owning the queue
7035  *      @vf: the VF owning the queue
7036  *      @eqid: egress queue id
7037  *
7038  *      Frees an Ethernet egress queue.
7039  */
7040 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7041                    unsigned int vf, unsigned int eqid)
7042 {
7043         struct fw_eq_eth_cmd c;
7044
7045         memset(&c, 0, sizeof(c));
7046         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7047                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7048                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7049                                   FW_EQ_ETH_CMD_VFN_V(vf));
7050         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7051         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7052         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7053 }
7054
7055 /**
7056  *      t4_ctrl_eq_free - free a control egress queue
7057  *      @adap: the adapter
7058  *      @mbox: mailbox to use for the FW command
7059  *      @pf: the PF owning the queue
7060  *      @vf: the VF owning the queue
7061  *      @eqid: egress queue id
7062  *
7063  *      Frees a control egress queue.
7064  */
7065 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7066                     unsigned int vf, unsigned int eqid)
7067 {
7068         struct fw_eq_ctrl_cmd c;
7069
7070         memset(&c, 0, sizeof(c));
7071         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7072                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7073                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7074                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7075         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7076         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7077         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7078 }
7079
7080 /**
7081  *      t4_ofld_eq_free - free an offload egress queue
7082  *      @adap: the adapter
7083  *      @mbox: mailbox to use for the FW command
7084  *      @pf: the PF owning the queue
7085  *      @vf: the VF owning the queue
7086  *      @eqid: egress queue id
7087  *
7088  *      Frees a control egress queue.
7089  */
7090 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7091                     unsigned int vf, unsigned int eqid)
7092 {
7093         struct fw_eq_ofld_cmd c;
7094
7095         memset(&c, 0, sizeof(c));
7096         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7097                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7098                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7099                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7100         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7101         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7102         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7103 }
7104
7105 /**
7106  *      t4_handle_get_port_info - process a FW reply message
7107  *      @pi: the port info
7108  *      @rpl: start of the FW message
7109  *
7110  *      Processes a GET_PORT_INFO FW reply message.
7111  */
7112 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7113 {
7114         const struct fw_port_cmd *p = (const void *)rpl;
7115         struct adapter *adap = pi->adapter;
7116
7117         /* link/module state change message */
7118         int speed = 0, fc = 0;
7119         struct link_config *lc;
7120         u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7121         int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7122         u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7123
7124         if (stat & FW_PORT_CMD_RXPAUSE_F)
7125                 fc |= PAUSE_RX;
7126         if (stat & FW_PORT_CMD_TXPAUSE_F)
7127                 fc |= PAUSE_TX;
7128         if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7129                 speed = 100;
7130         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7131                 speed = 1000;
7132         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7133                 speed = 10000;
7134         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7135                 speed = 40000;
7136
7137         lc = &pi->link_cfg;
7138
7139         if (mod != pi->mod_type) {
7140                 pi->mod_type = mod;
7141                 t4_os_portmod_changed(adap, pi->port_id);
7142         }
7143         if (link_ok != lc->link_ok || speed != lc->speed ||
7144             fc != lc->fc) {     /* something changed */
7145                 lc->link_ok = link_ok;
7146                 lc->speed = speed;
7147                 lc->fc = fc;
7148                 lc->supported = be16_to_cpu(p->u.info.pcap);
7149                 t4_os_link_changed(adap, pi->port_id, link_ok);
7150         }
7151 }
7152
7153 /**
7154  *      t4_handle_fw_rpl - process a FW reply message
7155  *      @adap: the adapter
7156  *      @rpl: start of the FW message
7157  *
7158  *      Processes a FW message, such as link state change messages.
7159  */
7160 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7161 {
7162         u8 opcode = *(const u8 *)rpl;
7163
7164         /* This might be a port command ... this simplifies the following
7165          * conditionals ...  We can get away with pre-dereferencing
7166          * action_to_len16 because it's in the first 16 bytes and all messages
7167          * will be at least that long.
7168          */
7169         const struct fw_port_cmd *p = (const void *)rpl;
7170         unsigned int action =
7171                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7172
7173         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7174                 int i;
7175                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7176                 struct port_info *pi = NULL;
7177
7178                 for_each_port(adap, i) {
7179                         pi = adap2pinfo(adap, i);
7180                         if (pi->tx_chan == chan)
7181                                 break;
7182                 }
7183
7184                 t4_handle_get_port_info(pi, rpl);
7185         } else {
7186                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7187                 return -EINVAL;
7188         }
7189         return 0;
7190 }
7191
7192 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7193 {
7194         u16 val;
7195
7196         if (pci_is_pcie(adapter->pdev)) {
7197                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7198                 p->speed = val & PCI_EXP_LNKSTA_CLS;
7199                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7200         }
7201 }
7202
7203 /**
7204  *      init_link_config - initialize a link's SW state
7205  *      @lc: structure holding the link state
7206  *      @caps: link capabilities
7207  *
7208  *      Initializes the SW state maintained for each link, including the link's
7209  *      capabilities and default speed/flow-control/autonegotiation settings.
7210  */
7211 static void init_link_config(struct link_config *lc, unsigned int caps)
7212 {
7213         lc->supported = caps;
7214         lc->requested_speed = 0;
7215         lc->speed = 0;
7216         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7217         if (lc->supported & FW_PORT_CAP_ANEG) {
7218                 lc->advertising = lc->supported & ADVERT_MASK;
7219                 lc->autoneg = AUTONEG_ENABLE;
7220                 lc->requested_fc |= PAUSE_AUTONEG;
7221         } else {
7222                 lc->advertising = 0;
7223                 lc->autoneg = AUTONEG_DISABLE;
7224         }
7225 }
7226
7227 #define CIM_PF_NOACCESS 0xeeeeeeee
7228
7229 int t4_wait_dev_ready(void __iomem *regs)
7230 {
7231         u32 whoami;
7232
7233         whoami = readl(regs + PL_WHOAMI_A);
7234         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7235                 return 0;
7236
7237         msleep(500);
7238         whoami = readl(regs + PL_WHOAMI_A);
7239         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7240 }
7241
7242 struct flash_desc {
7243         u32 vendor_and_model_id;
7244         u32 size_mb;
7245 };
7246
7247 static int get_flash_params(struct adapter *adap)
7248 {
7249         /* Table for non-Numonix supported flash parts.  Numonix parts are left
7250          * to the preexisting code.  All flash parts have 64KB sectors.
7251          */
7252         static struct flash_desc supported_flash[] = {
7253                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7254         };
7255
7256         int ret;
7257         u32 info;
7258
7259         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7260         if (!ret)
7261                 ret = sf1_read(adap, 3, 0, 1, &info);
7262         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
7263         if (ret)
7264                 return ret;
7265
7266         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7267                 if (supported_flash[ret].vendor_and_model_id == info) {
7268                         adap->params.sf_size = supported_flash[ret].size_mb;
7269                         adap->params.sf_nsec =
7270                                 adap->params.sf_size / SF_SEC_SIZE;
7271                         return 0;
7272                 }
7273
7274         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
7275                 return -EINVAL;
7276         info >>= 16;                           /* log2 of size */
7277         if (info >= 0x14 && info < 0x18)
7278                 adap->params.sf_nsec = 1 << (info - 16);
7279         else if (info == 0x18)
7280                 adap->params.sf_nsec = 64;
7281         else
7282                 return -EINVAL;
7283         adap->params.sf_size = 1 << info;
7284         adap->params.sf_fw_start =
7285                 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7286
7287         if (adap->params.sf_size < FLASH_MIN_SIZE)
7288                 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7289                          adap->params.sf_size, FLASH_MIN_SIZE);
7290         return 0;
7291 }
7292
7293 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7294 {
7295         u16 val;
7296         u32 pcie_cap;
7297
7298         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7299         if (pcie_cap) {
7300                 pci_read_config_word(adapter->pdev,
7301                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
7302                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7303                 val |= range;
7304                 pci_write_config_word(adapter->pdev,
7305                                       pcie_cap + PCI_EXP_DEVCTL2, val);
7306         }
7307 }
7308
7309 /**
7310  *      t4_prep_adapter - prepare SW and HW for operation
7311  *      @adapter: the adapter
7312  *      @reset: if true perform a HW reset
7313  *
7314  *      Initialize adapter SW state for the various HW modules, set initial
7315  *      values for some adapter tunables, take PHYs out of reset, and
7316  *      initialize the MDIO interface.
7317  */
7318 int t4_prep_adapter(struct adapter *adapter)
7319 {
7320         int ret, ver;
7321         uint16_t device_id;
7322         u32 pl_rev;
7323
7324         get_pci_mode(adapter, &adapter->params.pci);
7325         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7326
7327         ret = get_flash_params(adapter);
7328         if (ret < 0) {
7329                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7330                 return ret;
7331         }
7332
7333         /* Retrieve adapter's device ID
7334          */
7335         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7336         ver = device_id >> 12;
7337         adapter->params.chip = 0;
7338         switch (ver) {
7339         case CHELSIO_T4:
7340                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7341                 adapter->params.arch.sge_fl_db = DBPRIO_F;
7342                 adapter->params.arch.mps_tcam_size =
7343                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
7344                 adapter->params.arch.mps_rplc_size = 128;
7345                 adapter->params.arch.nchan = NCHAN;
7346                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7347                 adapter->params.arch.vfcount = 128;
7348                 /* Congestion map is for 4 channels so that
7349                  * MPS can have 4 priority per port.
7350                  */
7351                 adapter->params.arch.cng_ch_bits_log = 2;
7352                 break;
7353         case CHELSIO_T5:
7354                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7355                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7356                 adapter->params.arch.mps_tcam_size =
7357                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7358                 adapter->params.arch.mps_rplc_size = 128;
7359                 adapter->params.arch.nchan = NCHAN;
7360                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7361                 adapter->params.arch.vfcount = 128;
7362                 adapter->params.arch.cng_ch_bits_log = 2;
7363                 break;
7364         case CHELSIO_T6:
7365                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7366                 adapter->params.arch.sge_fl_db = 0;
7367                 adapter->params.arch.mps_tcam_size =
7368                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7369                 adapter->params.arch.mps_rplc_size = 256;
7370                 adapter->params.arch.nchan = 2;
7371                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7372                 adapter->params.arch.vfcount = 256;
7373                 /* Congestion map will be for 2 channels so that
7374                  * MPS can have 8 priority per port.
7375                  */
7376                 adapter->params.arch.cng_ch_bits_log = 3;
7377                 break;
7378         default:
7379                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7380                         device_id);
7381                 return -EINVAL;
7382         }
7383
7384         adapter->params.cim_la_size = CIMLA_SIZE;
7385         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7386
7387         /*
7388          * Default port for debugging in case we can't reach FW.
7389          */
7390         adapter->params.nports = 1;
7391         adapter->params.portvec = 1;
7392         adapter->params.vpd.cclk = 50000;
7393
7394         /* Set pci completion timeout value to 4 seconds. */
7395         set_pcie_completion_timeout(adapter, 0xd);
7396         return 0;
7397 }
7398
7399 /**
7400  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7401  *      @adapter: the adapter
7402  *      @qid: the Queue ID
7403  *      @qtype: the Ingress or Egress type for @qid
7404  *      @user: true if this request is for a user mode queue
7405  *      @pbar2_qoffset: BAR2 Queue Offset
7406  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7407  *
7408  *      Returns the BAR2 SGE Queue Registers information associated with the
7409  *      indicated Absolute Queue ID.  These are passed back in return value
7410  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7411  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7412  *
7413  *      This may return an error which indicates that BAR2 SGE Queue
7414  *      registers aren't available.  If an error is not returned, then the
7415  *      following values are returned:
7416  *
7417  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7418  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7419  *
7420  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7421  *      require the "Inferred Queue ID" ability may be used.  E.g. the
7422  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7423  *      then these "Inferred Queue ID" register may not be used.
7424  */
7425 int t4_bar2_sge_qregs(struct adapter *adapter,
7426                       unsigned int qid,
7427                       enum t4_bar2_qtype qtype,
7428                       int user,
7429                       u64 *pbar2_qoffset,
7430                       unsigned int *pbar2_qid)
7431 {
7432         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7433         u64 bar2_page_offset, bar2_qoffset;
7434         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7435
7436         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7437         if (!user && is_t4(adapter->params.chip))
7438                 return -EINVAL;
7439
7440         /* Get our SGE Page Size parameters.
7441          */
7442         page_shift = adapter->params.sge.hps + 10;
7443         page_size = 1 << page_shift;
7444
7445         /* Get the right Queues per Page parameters for our Queue.
7446          */
7447         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7448                      ? adapter->params.sge.eq_qpp
7449                      : adapter->params.sge.iq_qpp);
7450         qpp_mask = (1 << qpp_shift) - 1;
7451
7452         /*  Calculate the basics of the BAR2 SGE Queue register area:
7453          *  o The BAR2 page the Queue registers will be in.
7454          *  o The BAR2 Queue ID.
7455          *  o The BAR2 Queue ID Offset into the BAR2 page.
7456          */
7457         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7458         bar2_qid = qid & qpp_mask;
7459         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7460
7461         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7462          * hardware will infer the Absolute Queue ID simply from the writes to
7463          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7464          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
7465          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7466          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7467          * from the BAR2 Page and BAR2 Queue ID.
7468          *
7469          * One important censequence of this is that some BAR2 SGE registers
7470          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7471          * there.  But other registers synthesize the SGE Queue ID purely
7472          * from the writes to the registers -- the Write Combined Doorbell
7473          * Buffer is a good example.  These BAR2 SGE Registers are only
7474          * available for those BAR2 SGE Register areas where the SGE Absolute
7475          * Queue ID can be inferred from simple writes.
7476          */
7477         bar2_qoffset = bar2_page_offset;
7478         bar2_qinferred = (bar2_qid_offset < page_size);
7479         if (bar2_qinferred) {
7480                 bar2_qoffset += bar2_qid_offset;
7481                 bar2_qid = 0;
7482         }
7483
7484         *pbar2_qoffset = bar2_qoffset;
7485         *pbar2_qid = bar2_qid;
7486         return 0;
7487 }
7488
7489 /**
7490  *      t4_init_devlog_params - initialize adapter->params.devlog
7491  *      @adap: the adapter
7492  *
7493  *      Initialize various fields of the adapter's Firmware Device Log
7494  *      Parameters structure.
7495  */
7496 int t4_init_devlog_params(struct adapter *adap)
7497 {
7498         struct devlog_params *dparams = &adap->params.devlog;
7499         u32 pf_dparams;
7500         unsigned int devlog_meminfo;
7501         struct fw_devlog_cmd devlog_cmd;
7502         int ret;
7503
7504         /* If we're dealing with newer firmware, the Device Log Paramerters
7505          * are stored in a designated register which allows us to access the
7506          * Device Log even if we can't talk to the firmware.
7507          */
7508         pf_dparams =
7509                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7510         if (pf_dparams) {
7511                 unsigned int nentries, nentries128;
7512
7513                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7514                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7515
7516                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7517                 nentries = (nentries128 + 1) * 128;
7518                 dparams->size = nentries * sizeof(struct fw_devlog_e);
7519
7520                 return 0;
7521         }
7522
7523         /* Otherwise, ask the firmware for it's Device Log Parameters.
7524          */
7525         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7526         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7527                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
7528         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7529         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7530                          &devlog_cmd);
7531         if (ret)
7532                 return ret;
7533
7534         devlog_meminfo =
7535                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7536         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7537         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7538         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7539
7540         return 0;
7541 }
7542
7543 /**
7544  *      t4_init_sge_params - initialize adap->params.sge
7545  *      @adapter: the adapter
7546  *
7547  *      Initialize various fields of the adapter's SGE Parameters structure.
7548  */
7549 int t4_init_sge_params(struct adapter *adapter)
7550 {
7551         struct sge_params *sge_params = &adapter->params.sge;
7552         u32 hps, qpp;
7553         unsigned int s_hps, s_qpp;
7554
7555         /* Extract the SGE Page Size for our PF.
7556          */
7557         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7558         s_hps = (HOSTPAGESIZEPF0_S +
7559                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7560         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7561
7562         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7563          */
7564         s_qpp = (QUEUESPERPAGEPF0_S +
7565                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7566         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7567         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7568         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7569         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7570
7571         return 0;
7572 }
7573
7574 /**
7575  *      t4_init_tp_params - initialize adap->params.tp
7576  *      @adap: the adapter
7577  *
7578  *      Initialize various fields of the adapter's TP Parameters structure.
7579  */
7580 int t4_init_tp_params(struct adapter *adap)
7581 {
7582         int chan;
7583         u32 v;
7584
7585         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7586         adap->params.tp.tre = TIMERRESOLUTION_G(v);
7587         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7588
7589         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7590         for (chan = 0; chan < NCHAN; chan++)
7591                 adap->params.tp.tx_modq[chan] = chan;
7592
7593         /* Cache the adapter's Compressed Filter Mode and global Incress
7594          * Configuration.
7595          */
7596         if (t4_use_ldst(adap)) {
7597                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7598                                 TP_VLAN_PRI_MAP_A, 1);
7599                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7600                                 TP_INGRESS_CONFIG_A, 1);
7601         } else {
7602                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7603                                  &adap->params.tp.vlan_pri_map, 1,
7604                                  TP_VLAN_PRI_MAP_A);
7605                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7606                                  &adap->params.tp.ingress_config, 1,
7607                                  TP_INGRESS_CONFIG_A);
7608         }
7609
7610         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7611          * shift positions of several elements of the Compressed Filter Tuple
7612          * for this adapter which we need frequently ...
7613          */
7614         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7615         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7616         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7617         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7618                                                                PROTOCOL_F);
7619
7620         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7621          * represents the presence of an Outer VLAN instead of a VNIC ID.
7622          */
7623         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7624                 adap->params.tp.vnic_shift = -1;
7625
7626         return 0;
7627 }
7628
7629 /**
7630  *      t4_filter_field_shift - calculate filter field shift
7631  *      @adap: the adapter
7632  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7633  *
7634  *      Return the shift position of a filter field within the Compressed
7635  *      Filter Tuple.  The filter field is specified via its selection bit
7636  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
7637  */
7638 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7639 {
7640         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7641         unsigned int sel;
7642         int field_shift;
7643
7644         if ((filter_mode & filter_sel) == 0)
7645                 return -1;
7646
7647         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7648                 switch (filter_mode & sel) {
7649                 case FCOE_F:
7650                         field_shift += FT_FCOE_W;
7651                         break;
7652                 case PORT_F:
7653                         field_shift += FT_PORT_W;
7654                         break;
7655                 case VNIC_ID_F:
7656                         field_shift += FT_VNIC_ID_W;
7657                         break;
7658                 case VLAN_F:
7659                         field_shift += FT_VLAN_W;
7660                         break;
7661                 case TOS_F:
7662                         field_shift += FT_TOS_W;
7663                         break;
7664                 case PROTOCOL_F:
7665                         field_shift += FT_PROTOCOL_W;
7666                         break;
7667                 case ETHERTYPE_F:
7668                         field_shift += FT_ETHERTYPE_W;
7669                         break;
7670                 case MACMATCH_F:
7671                         field_shift += FT_MACMATCH_W;
7672                         break;
7673                 case MPSHITTYPE_F:
7674                         field_shift += FT_MPSHITTYPE_W;
7675                         break;
7676                 case FRAGMENTATION_F:
7677                         field_shift += FT_FRAGMENTATION_W;
7678                         break;
7679                 }
7680         }
7681         return field_shift;
7682 }
7683
7684 int t4_init_rss_mode(struct adapter *adap, int mbox)
7685 {
7686         int i, ret;
7687         struct fw_rss_vi_config_cmd rvc;
7688
7689         memset(&rvc, 0, sizeof(rvc));
7690
7691         for_each_port(adap, i) {
7692                 struct port_info *p = adap2pinfo(adap, i);
7693
7694                 rvc.op_to_viid =
7695                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7696                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
7697                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7698                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7699                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7700                 if (ret)
7701                         return ret;
7702                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7703         }
7704         return 0;
7705 }
7706
7707 /**
7708  *      t4_init_portinfo - allocate a virtual interface amd initialize port_info
7709  *      @pi: the port_info
7710  *      @mbox: mailbox to use for the FW command
7711  *      @port: physical port associated with the VI
7712  *      @pf: the PF owning the VI
7713  *      @vf: the VF owning the VI
7714  *      @mac: the MAC address of the VI
7715  *
7716  *      Allocates a virtual interface for the given physical port.  If @mac is
7717  *      not %NULL it contains the MAC address of the VI as assigned by FW.
7718  *      @mac should be large enough to hold an Ethernet address.
7719  *      Returns < 0 on error.
7720  */
7721 int t4_init_portinfo(struct port_info *pi, int mbox,
7722                      int port, int pf, int vf, u8 mac[])
7723 {
7724         int ret;
7725         struct fw_port_cmd c;
7726         unsigned int rss_size;
7727
7728         memset(&c, 0, sizeof(c));
7729         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7730                                      FW_CMD_REQUEST_F | FW_CMD_READ_F |
7731                                      FW_PORT_CMD_PORTID_V(port));
7732         c.action_to_len16 = cpu_to_be32(
7733                 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7734                 FW_LEN16(c));
7735         ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7736         if (ret)
7737                 return ret;
7738
7739         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7740         if (ret < 0)
7741                 return ret;
7742
7743         pi->viid = ret;
7744         pi->tx_chan = port;
7745         pi->lport = port;
7746         pi->rss_size = rss_size;
7747
7748         ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7749         pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7750                 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7751         pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7752         pi->mod_type = FW_PORT_MOD_TYPE_NA;
7753
7754         init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7755         return 0;
7756 }
7757
7758 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7759 {
7760         u8 addr[6];
7761         int ret, i, j = 0;
7762
7763         for_each_port(adap, i) {
7764                 struct port_info *pi = adap2pinfo(adap, i);
7765
7766                 while ((adap->params.portvec & (1 << j)) == 0)
7767                         j++;
7768
7769                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7770                 if (ret)
7771                         return ret;
7772
7773                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7774                 adap->port[i]->dev_port = j;
7775                 j++;
7776         }
7777         return 0;
7778 }
7779
7780 /**
7781  *      t4_read_cimq_cfg - read CIM queue configuration
7782  *      @adap: the adapter
7783  *      @base: holds the queue base addresses in bytes
7784  *      @size: holds the queue sizes in bytes
7785  *      @thres: holds the queue full thresholds in bytes
7786  *
7787  *      Returns the current configuration of the CIM queues, starting with
7788  *      the IBQs, then the OBQs.
7789  */
7790 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7791 {
7792         unsigned int i, v;
7793         int cim_num_obq = is_t4(adap->params.chip) ?
7794                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7795
7796         for (i = 0; i < CIM_NUM_IBQ; i++) {
7797                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7798                              QUENUMSELECT_V(i));
7799                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7800                 /* value is in 256-byte units */
7801                 *base++ = CIMQBASE_G(v) * 256;
7802                 *size++ = CIMQSIZE_G(v) * 256;
7803                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7804         }
7805         for (i = 0; i < cim_num_obq; i++) {
7806                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7807                              QUENUMSELECT_V(i));
7808                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7809                 /* value is in 256-byte units */
7810                 *base++ = CIMQBASE_G(v) * 256;
7811                 *size++ = CIMQSIZE_G(v) * 256;
7812         }
7813 }
7814
7815 /**
7816  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
7817  *      @adap: the adapter
7818  *      @qid: the queue index
7819  *      @data: where to store the queue contents
7820  *      @n: capacity of @data in 32-bit words
7821  *
7822  *      Reads the contents of the selected CIM queue starting at address 0 up
7823  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7824  *      error and the number of 32-bit words actually read on success.
7825  */
7826 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7827 {
7828         int i, err, attempts;
7829         unsigned int addr;
7830         const unsigned int nwords = CIM_IBQ_SIZE * 4;
7831
7832         if (qid > 5 || (n & 3))
7833                 return -EINVAL;
7834
7835         addr = qid * nwords;
7836         if (n > nwords)
7837                 n = nwords;
7838
7839         /* It might take 3-10ms before the IBQ debug read access is allowed.
7840          * Wait for 1 Sec with a delay of 1 usec.
7841          */
7842         attempts = 1000000;
7843
7844         for (i = 0; i < n; i++, addr++) {
7845                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7846                              IBQDBGEN_F);
7847                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7848                                       attempts, 1);
7849                 if (err)
7850                         return err;
7851                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7852         }
7853         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7854         return i;
7855 }
7856
7857 /**
7858  *      t4_read_cim_obq - read the contents of a CIM outbound queue
7859  *      @adap: the adapter
7860  *      @qid: the queue index
7861  *      @data: where to store the queue contents
7862  *      @n: capacity of @data in 32-bit words
7863  *
7864  *      Reads the contents of the selected CIM queue starting at address 0 up
7865  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7866  *      error and the number of 32-bit words actually read on success.
7867  */
7868 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7869 {
7870         int i, err;
7871         unsigned int addr, v, nwords;
7872         int cim_num_obq = is_t4(adap->params.chip) ?
7873                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7874
7875         if ((qid > (cim_num_obq - 1)) || (n & 3))
7876                 return -EINVAL;
7877
7878         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7879                      QUENUMSELECT_V(qid));
7880         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7881
7882         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
7883         nwords = CIMQSIZE_G(v) * 64;  /* same */
7884         if (n > nwords)
7885                 n = nwords;
7886
7887         for (i = 0; i < n; i++, addr++) {
7888                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7889                              OBQDBGEN_F);
7890                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7891                                       2, 1);
7892                 if (err)
7893                         return err;
7894                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7895         }
7896         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7897         return i;
7898 }
7899
7900 /**
7901  *      t4_cim_read - read a block from CIM internal address space
7902  *      @adap: the adapter
7903  *      @addr: the start address within the CIM address space
7904  *      @n: number of words to read
7905  *      @valp: where to store the result
7906  *
7907  *      Reads a block of 4-byte words from the CIM intenal address space.
7908  */
7909 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7910                 unsigned int *valp)
7911 {
7912         int ret = 0;
7913
7914         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7915                 return -EBUSY;
7916
7917         for ( ; !ret && n--; addr += 4) {
7918                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7919                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7920                                       0, 5, 2);
7921                 if (!ret)
7922                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7923         }
7924         return ret;
7925 }
7926
7927 /**
7928  *      t4_cim_write - write a block into CIM internal address space
7929  *      @adap: the adapter
7930  *      @addr: the start address within the CIM address space
7931  *      @n: number of words to write
7932  *      @valp: set of values to write
7933  *
7934  *      Writes a block of 4-byte words into the CIM intenal address space.
7935  */
7936 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7937                  const unsigned int *valp)
7938 {
7939         int ret = 0;
7940
7941         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7942                 return -EBUSY;
7943
7944         for ( ; !ret && n--; addr += 4) {
7945                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7946                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7947                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7948                                       0, 5, 2);
7949         }
7950         return ret;
7951 }
7952
7953 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7954                          unsigned int val)
7955 {
7956         return t4_cim_write(adap, addr, 1, &val);
7957 }
7958
7959 /**
7960  *      t4_cim_read_la - read CIM LA capture buffer
7961  *      @adap: the adapter
7962  *      @la_buf: where to store the LA data
7963  *      @wrptr: the HW write pointer within the capture buffer
7964  *
7965  *      Reads the contents of the CIM LA buffer with the most recent entry at
7966  *      the end of the returned data and with the entry at @wrptr first.
7967  *      We try to leave the LA in the running state we find it in.
7968  */
7969 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7970 {
7971         int i, ret;
7972         unsigned int cfg, val, idx;
7973
7974         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7975         if (ret)
7976                 return ret;
7977
7978         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
7979                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7980                 if (ret)
7981                         return ret;
7982         }
7983
7984         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7985         if (ret)
7986                 goto restart;
7987
7988         idx = UPDBGLAWRPTR_G(val);
7989         if (wrptr)
7990                 *wrptr = idx;
7991
7992         for (i = 0; i < adap->params.cim_la_size; i++) {
7993                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7994                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7995                 if (ret)
7996                         break;
7997                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7998                 if (ret)
7999                         break;
8000                 if (val & UPDBGLARDEN_F) {
8001                         ret = -ETIMEDOUT;
8002                         break;
8003                 }
8004                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8005                 if (ret)
8006                         break;
8007                 idx = (idx + 1) & UPDBGLARDPTR_M;
8008         }
8009 restart:
8010         if (cfg & UPDBGLAEN_F) {
8011                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8012                                       cfg & ~UPDBGLARDEN_F);
8013                 if (!ret)
8014                         ret = r;
8015         }
8016         return ret;
8017 }
8018
8019 /**
8020  *      t4_tp_read_la - read TP LA capture buffer
8021  *      @adap: the adapter
8022  *      @la_buf: where to store the LA data
8023  *      @wrptr: the HW write pointer within the capture buffer
8024  *
8025  *      Reads the contents of the TP LA buffer with the most recent entry at
8026  *      the end of the returned data and with the entry at @wrptr first.
8027  *      We leave the LA in the running state we find it in.
8028  */
8029 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8030 {
8031         bool last_incomplete;
8032         unsigned int i, cfg, val, idx;
8033
8034         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8035         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
8036                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8037                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8038
8039         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8040         idx = DBGLAWPTR_G(val);
8041         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8042         if (last_incomplete)
8043                 idx = (idx + 1) & DBGLARPTR_M;
8044         if (wrptr)
8045                 *wrptr = idx;
8046
8047         val &= 0xffff;
8048         val &= ~DBGLARPTR_V(DBGLARPTR_M);
8049         val |= adap->params.tp.la_mask;
8050
8051         for (i = 0; i < TPLA_SIZE; i++) {
8052                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8053                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8054                 idx = (idx + 1) & DBGLARPTR_M;
8055         }
8056
8057         /* Wipe out last entry if it isn't valid */
8058         if (last_incomplete)
8059                 la_buf[TPLA_SIZE - 1] = ~0ULL;
8060
8061         if (cfg & DBGLAENABLE_F)                    /* restore running state */
8062                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8063                              cfg | adap->params.tp.la_mask);
8064 }
8065
8066 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8067  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8068  * state for more than the Warning Threshold then we'll issue a warning about
8069  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8070  * appears to be hung every Warning Repeat second till the situation clears.
8071  * If the situation clears, we'll note that as well.
8072  */
8073 #define SGE_IDMA_WARN_THRESH 1
8074 #define SGE_IDMA_WARN_REPEAT 300
8075
8076 /**
8077  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8078  *      @adapter: the adapter
8079  *      @idma: the adapter IDMA Monitor state
8080  *
8081  *      Initialize the state of an SGE Ingress DMA Monitor.
8082  */
8083 void t4_idma_monitor_init(struct adapter *adapter,
8084                           struct sge_idma_monitor_state *idma)
8085 {
8086         /* Initialize the state variables for detecting an SGE Ingress DMA
8087          * hang.  The SGE has internal counters which count up on each clock
8088          * tick whenever the SGE finds its Ingress DMA State Engines in the
8089          * same state they were on the previous clock tick.  The clock used is
8090          * the Core Clock so we have a limit on the maximum "time" they can
8091          * record; typically a very small number of seconds.  For instance,
8092          * with a 600MHz Core Clock, we can only count up to a bit more than
8093          * 7s.  So we'll synthesize a larger counter in order to not run the
8094          * risk of having the "timers" overflow and give us the flexibility to
8095          * maintain a Hung SGE State Machine of our own which operates across
8096          * a longer time frame.
8097          */
8098         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8099         idma->idma_stalled[0] = 0;
8100         idma->idma_stalled[1] = 0;
8101 }
8102
8103 /**
8104  *      t4_idma_monitor - monitor SGE Ingress DMA state
8105  *      @adapter: the adapter
8106  *      @idma: the adapter IDMA Monitor state
8107  *      @hz: number of ticks/second
8108  *      @ticks: number of ticks since the last IDMA Monitor call
8109  */
8110 void t4_idma_monitor(struct adapter *adapter,
8111                      struct sge_idma_monitor_state *idma,
8112                      int hz, int ticks)
8113 {
8114         int i, idma_same_state_cnt[2];
8115
8116          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8117           * are counters inside the SGE which count up on each clock when the
8118           * SGE finds its Ingress DMA State Engines in the same states they
8119           * were in the previous clock.  The counters will peg out at
8120           * 0xffffffff without wrapping around so once they pass the 1s
8121           * threshold they'll stay above that till the IDMA state changes.
8122           */
8123         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8124         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8125         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8126
8127         for (i = 0; i < 2; i++) {
8128                 u32 debug0, debug11;
8129
8130                 /* If the Ingress DMA Same State Counter ("timer") is less
8131                  * than 1s, then we can reset our synthesized Stall Timer and
8132                  * continue.  If we have previously emitted warnings about a
8133                  * potential stalled Ingress Queue, issue a note indicating
8134                  * that the Ingress Queue has resumed forward progress.
8135                  */
8136                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8137                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8138                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8139                                          "resumed after %d seconds\n",
8140                                          i, idma->idma_qid[i],
8141                                          idma->idma_stalled[i] / hz);
8142                         idma->idma_stalled[i] = 0;
8143                         continue;
8144                 }
8145
8146                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8147                  * domain.  The first time we get here it'll be because we
8148                  * passed the 1s Threshold; each additional time it'll be
8149                  * because the RX Timer Callback is being fired on its regular
8150                  * schedule.
8151                  *
8152                  * If the stall is below our Potential Hung Ingress Queue
8153                  * Warning Threshold, continue.
8154                  */
8155                 if (idma->idma_stalled[i] == 0) {
8156                         idma->idma_stalled[i] = hz;
8157                         idma->idma_warn[i] = 0;
8158                 } else {
8159                         idma->idma_stalled[i] += ticks;
8160                         idma->idma_warn[i] -= ticks;
8161                 }
8162
8163                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8164                         continue;
8165
8166                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8167                  */
8168                 if (idma->idma_warn[i] > 0)
8169                         continue;
8170                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8171
8172                 /* Read and save the SGE IDMA State and Queue ID information.
8173                  * We do this every time in case it changes across time ...
8174                  * can't be too careful ...
8175                  */
8176                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8177                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8178                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8179
8180                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8181                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8182                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8183
8184                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8185                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8186                          i, idma->idma_qid[i], idma->idma_state[i],
8187                          idma->idma_stalled[i] / hz,
8188                          debug0, debug11);
8189                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8190         }
8191 }