2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
52 #include <asm/cacheflush.h>
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
61 #if defined(CONFIG_ARM)
62 #define FEC_ALIGNMENT 0xf
64 #define FEC_ALIGNMENT 0x3
67 #define DRIVER_NAME "fec"
69 /* Controller is ENET-MAC */
70 #define FEC_QUIRK_ENET_MAC (1 << 0)
71 /* Controller needs driver to swap frame */
72 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
73 /* Controller uses gasket */
74 #define FEC_QUIRK_USE_GASKET (1 << 2)
75 /* Controller has GBIT support */
76 #define FEC_QUIRK_HAS_GBIT (1 << 3)
78 static struct platform_device_id fec_devtype[] = {
80 /* keep it for coldfire */
85 .driver_data = FEC_QUIRK_USE_GASKET,
91 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
99 MODULE_DEVICE_TABLE(platform, fec_devtype);
102 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
103 IMX27_FEC, /* runs on i.mx27/35/51 */
108 static const struct of_device_id fec_dt_ids[] = {
109 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
110 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
111 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
112 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
115 MODULE_DEVICE_TABLE(of, fec_dt_ids);
117 static unsigned char macaddr[ETH_ALEN];
118 module_param_array(macaddr, byte, NULL, 0);
119 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
121 #if defined(CONFIG_M5272)
123 * Some hardware gets it MAC address out of local flash memory.
124 * if this is non-zero then assume it is the address to get MAC from.
126 #if defined(CONFIG_NETtel)
127 #define FEC_FLASHMAC 0xf0006006
128 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
129 #define FEC_FLASHMAC 0xf0006000
130 #elif defined(CONFIG_CANCam)
131 #define FEC_FLASHMAC 0xf0020000
132 #elif defined (CONFIG_M5272C3)
133 #define FEC_FLASHMAC (0xffe04000 + 4)
134 #elif defined(CONFIG_MOD5272)
135 #define FEC_FLASHMAC 0xffc0406b
137 #define FEC_FLASHMAC 0
139 #endif /* CONFIG_M5272 */
141 /* The number of Tx and Rx buffers. These are allocated from the page
142 * pool. The code may assume these are power of two, so it it best
143 * to keep them that size.
144 * We don't need to allocate pages for the transmitter. We just use
145 * the skbuffer directly.
147 #define FEC_ENET_RX_PAGES 8
148 #define FEC_ENET_RX_FRSIZE 2048
149 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
150 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
151 #define FEC_ENET_TX_FRSIZE 2048
152 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
153 #define TX_RING_SIZE 16 /* Must be power of two */
154 #define TX_RING_MOD_MASK 15 /* for this to work */
156 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
157 #error "FEC: descriptor ring size constants too large"
160 /* Interrupt events/masks. */
161 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
162 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
163 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
164 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
165 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
166 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
167 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
168 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
169 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
170 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
172 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
180 /* This device has up to three irqs on some platforms */
181 #define FEC_IRQ_NUM 3
184 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
185 * size bits. Other FEC hardware does not, so we need to take that into
186 * account when setting it.
188 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
189 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
190 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
192 #define OPT_FRAME_SIZE 0
195 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
196 * tx_bd_base always point to the base of the buffer descriptors. The
197 * cur_rx and cur_tx point to the currently available buffer.
198 * The dirty_tx tracks the current buffer that is being sent by the
199 * controller. The cur_tx and dirty_tx are equal under both completely
200 * empty and completely full conditions. The empty/ready indicator in
201 * the buffer descriptor determines the actual condition.
203 struct fec_enet_private {
204 /* Hardware registers of the FEC device */
207 struct net_device *netdev;
211 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
212 unsigned char *tx_bounce[TX_RING_SIZE];
213 struct sk_buff* tx_skbuff[TX_RING_SIZE];
214 struct sk_buff* rx_skbuff[RX_RING_SIZE];
218 /* CPM dual port RAM relative addresses */
220 /* Address of Rx and Tx buffers */
221 struct bufdesc *rx_bd_base;
222 struct bufdesc *tx_bd_base;
223 /* The next free ring entry */
224 struct bufdesc *cur_rx, *cur_tx;
225 /* The ring entries to be free()ed */
226 struct bufdesc *dirty_tx;
229 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
232 struct platform_device *pdev;
236 /* Phylib and MDIO interface */
237 struct mii_bus *mii_bus;
238 struct phy_device *phy_dev;
241 phy_interface_t phy_interface;
244 struct completion mdio_done;
245 int irq[FEC_IRQ_NUM];
248 /* FEC MII MMFR bits definition */
249 #define FEC_MMFR_ST (1 << 30)
250 #define FEC_MMFR_OP_READ (2 << 28)
251 #define FEC_MMFR_OP_WRITE (1 << 28)
252 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
253 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
254 #define FEC_MMFR_TA (2 << 16)
255 #define FEC_MMFR_DATA(v) (v & 0xffff)
257 #define FEC_MII_TIMEOUT 1000 /* us */
259 /* Transmitter timeout */
260 #define TX_TIMEOUT (2 * HZ)
262 static void *swap_buffer(void *bufaddr, int len)
265 unsigned int *buf = bufaddr;
267 for (i = 0; i < (len + 3) / 4; i++, buf++)
268 *buf = cpu_to_be32(*buf);
274 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
276 struct fec_enet_private *fep = netdev_priv(ndev);
277 const struct platform_device_id *id_entry =
278 platform_get_device_id(fep->pdev);
281 unsigned short status;
285 /* Link is down or autonegotiation is in progress. */
286 return NETDEV_TX_BUSY;
289 spin_lock_irqsave(&fep->hw_lock, flags);
290 /* Fill in a Tx ring entry */
293 status = bdp->cbd_sc;
295 if (status & BD_ENET_TX_READY) {
296 /* Ooops. All transmit buffers are full. Bail out.
297 * This should not happen, since ndev->tbusy should be set.
299 printk("%s: tx queue full!.\n", ndev->name);
300 spin_unlock_irqrestore(&fep->hw_lock, flags);
301 return NETDEV_TX_BUSY;
304 /* Clear all of the status flags */
305 status &= ~BD_ENET_TX_STATS;
307 /* Set buffer length and buffer pointer */
309 bdp->cbd_datlen = skb->len;
312 * On some FEC implementations data must be aligned on
313 * 4-byte boundaries. Use bounce buffers to copy data
314 * and get it aligned. Ugh.
316 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
318 index = bdp - fep->tx_bd_base;
319 memcpy(fep->tx_bounce[index], skb->data, skb->len);
320 bufaddr = fep->tx_bounce[index];
324 * Some design made an incorrect assumption on endian mode of
325 * the system that it's running on. As the result, driver has to
326 * swap every frame going to and coming from the controller.
328 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
329 swap_buffer(bufaddr, skb->len);
331 /* Save skb pointer */
332 fep->tx_skbuff[fep->skb_cur] = skb;
334 ndev->stats.tx_bytes += skb->len;
335 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
337 /* Push the data cache so the CPM does not get stale memory
340 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
341 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
343 /* Send it on its way. Tell FEC it's ready, interrupt when done,
344 * it's the last BD of the frame, and to put the CRC on the end.
346 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
347 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
348 bdp->cbd_sc = status;
350 /* Trigger transmission start */
351 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
353 /* If this was the last BD in the ring, start at the beginning again. */
354 if (status & BD_ENET_TX_WRAP)
355 bdp = fep->tx_bd_base;
359 if (bdp == fep->dirty_tx) {
361 netif_stop_queue(ndev);
366 skb_tx_timestamp(skb);
368 spin_unlock_irqrestore(&fep->hw_lock, flags);
373 /* This function is called to start or restart the FEC during a link
374 * change. This only happens when switching between half and full
378 fec_restart(struct net_device *ndev, int duplex)
380 struct fec_enet_private *fep = netdev_priv(ndev);
381 const struct platform_device_id *id_entry =
382 platform_get_device_id(fep->pdev);
385 u32 rcntl = OPT_FRAME_SIZE | 0x04;
386 u32 ecntl = 0x2; /* ETHEREN */
388 /* Whack a reset. We should wait for this. */
389 writel(1, fep->hwp + FEC_ECNTRL);
393 * enet-mac reset will reset mac address registers too,
394 * so need to reconfigure it.
396 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
397 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
398 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
399 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
402 /* Clear any outstanding interrupt. */
403 writel(0xffc00000, fep->hwp + FEC_IEVENT);
405 /* Reset all multicast. */
406 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
407 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
409 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
410 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
413 /* Set maximum receive buffer size. */
414 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
416 /* Set receive and transmit descriptor base. */
417 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
418 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
419 fep->hwp + FEC_X_DES_START);
421 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
422 fep->cur_rx = fep->rx_bd_base;
424 /* Reset SKB transmit buffers. */
425 fep->skb_cur = fep->skb_dirty = 0;
426 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
427 if (fep->tx_skbuff[i]) {
428 dev_kfree_skb_any(fep->tx_skbuff[i]);
429 fep->tx_skbuff[i] = NULL;
433 /* Enable MII mode */
436 writel(0x04, fep->hwp + FEC_X_CNTRL);
440 writel(0x0, fep->hwp + FEC_X_CNTRL);
443 fep->full_duplex = duplex;
446 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
449 * The phy interface and speed need to get configured
450 * differently on enet-mac.
452 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
453 /* Enable flow control and length check */
454 rcntl |= 0x40000000 | 0x00000020;
456 /* RGMII, RMII or MII */
457 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
459 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
464 /* 1G, 100M or 10M */
466 if (fep->phy_dev->speed == SPEED_1000)
468 else if (fep->phy_dev->speed == SPEED_100)
474 #ifdef FEC_MIIGSK_ENR
475 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
476 /* disable the gasket and wait */
477 writel(0, fep->hwp + FEC_MIIGSK_ENR);
478 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
482 * configure the gasket:
483 * RMII, 50 MHz, no loopback, no echo
484 * MII, 25 MHz, no loopback, no echo
486 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
487 1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
490 /* re-enable the gasket */
491 writel(2, fep->hwp + FEC_MIIGSK_ENR);
495 writel(rcntl, fep->hwp + FEC_R_CNTRL);
497 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
498 /* enable ENET endian swap */
500 /* enable ENET store and forward mode */
501 writel(1 << 8, fep->hwp + FEC_X_WMRK);
504 /* And last, enable the transmit and receive processing */
505 writel(ecntl, fep->hwp + FEC_ECNTRL);
506 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
508 /* Enable interrupts we wish to service */
509 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
513 fec_stop(struct net_device *ndev)
515 struct fec_enet_private *fep = netdev_priv(ndev);
516 const struct platform_device_id *id_entry =
517 platform_get_device_id(fep->pdev);
519 /* We cannot expect a graceful transmit stop without link !!! */
521 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
523 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
524 printk("fec_stop : Graceful transmit stop did not complete !\n");
527 /* Whack a reset. We should wait for this. */
528 writel(1, fep->hwp + FEC_ECNTRL);
530 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
531 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
533 /* We have to keep ENET enabled to have MII interrupt stay working */
534 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
535 writel(2, fep->hwp + FEC_ECNTRL);
540 fec_timeout(struct net_device *ndev)
542 struct fec_enet_private *fep = netdev_priv(ndev);
544 ndev->stats.tx_errors++;
546 fec_restart(ndev, fep->full_duplex);
547 netif_wake_queue(ndev);
551 fec_enet_tx(struct net_device *ndev)
553 struct fec_enet_private *fep;
555 unsigned short status;
558 fep = netdev_priv(ndev);
559 spin_lock(&fep->hw_lock);
562 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
563 if (bdp == fep->cur_tx && fep->tx_full == 0)
566 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
567 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
568 bdp->cbd_bufaddr = 0;
570 skb = fep->tx_skbuff[fep->skb_dirty];
571 /* Check for errors. */
572 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
573 BD_ENET_TX_RL | BD_ENET_TX_UN |
575 ndev->stats.tx_errors++;
576 if (status & BD_ENET_TX_HB) /* No heartbeat */
577 ndev->stats.tx_heartbeat_errors++;
578 if (status & BD_ENET_TX_LC) /* Late collision */
579 ndev->stats.tx_window_errors++;
580 if (status & BD_ENET_TX_RL) /* Retrans limit */
581 ndev->stats.tx_aborted_errors++;
582 if (status & BD_ENET_TX_UN) /* Underrun */
583 ndev->stats.tx_fifo_errors++;
584 if (status & BD_ENET_TX_CSL) /* Carrier lost */
585 ndev->stats.tx_carrier_errors++;
587 ndev->stats.tx_packets++;
590 if (status & BD_ENET_TX_READY)
591 printk("HEY! Enet xmit interrupt and TX_READY.\n");
593 /* Deferred means some collisions occurred during transmit,
594 * but we eventually sent the packet OK.
596 if (status & BD_ENET_TX_DEF)
597 ndev->stats.collisions++;
599 /* Free the sk buffer associated with this last transmit */
600 dev_kfree_skb_any(skb);
601 fep->tx_skbuff[fep->skb_dirty] = NULL;
602 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
604 /* Update pointer to next buffer descriptor to be transmitted */
605 if (status & BD_ENET_TX_WRAP)
606 bdp = fep->tx_bd_base;
610 /* Since we have freed up a buffer, the ring is no longer full
614 if (netif_queue_stopped(ndev))
615 netif_wake_queue(ndev);
619 spin_unlock(&fep->hw_lock);
623 /* During a receive, the cur_rx points to the current incoming buffer.
624 * When we update through the ring, if the next incoming buffer has
625 * not been given to the system, we just set the empty indicator,
626 * effectively tossing the packet.
629 fec_enet_rx(struct net_device *ndev)
631 struct fec_enet_private *fep = netdev_priv(ndev);
632 const struct platform_device_id *id_entry =
633 platform_get_device_id(fep->pdev);
635 unsigned short status;
644 spin_lock(&fep->hw_lock);
646 /* First, grab all of the stats for the incoming packet.
647 * These get messed up if we get called due to a busy condition.
651 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
653 /* Since we have allocated space to hold a complete frame,
654 * the last indicator should be set.
656 if ((status & BD_ENET_RX_LAST) == 0)
657 printk("FEC ENET: rcv is not +last\n");
660 goto rx_processing_done;
662 /* Check for errors. */
663 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
664 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
665 ndev->stats.rx_errors++;
666 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
667 /* Frame too long or too short. */
668 ndev->stats.rx_length_errors++;
670 if (status & BD_ENET_RX_NO) /* Frame alignment */
671 ndev->stats.rx_frame_errors++;
672 if (status & BD_ENET_RX_CR) /* CRC Error */
673 ndev->stats.rx_crc_errors++;
674 if (status & BD_ENET_RX_OV) /* FIFO overrun */
675 ndev->stats.rx_fifo_errors++;
678 /* Report late collisions as a frame error.
679 * On this error, the BD is closed, but we don't know what we
680 * have in the buffer. So, just drop this frame on the floor.
682 if (status & BD_ENET_RX_CL) {
683 ndev->stats.rx_errors++;
684 ndev->stats.rx_frame_errors++;
685 goto rx_processing_done;
688 /* Process the incoming frame. */
689 ndev->stats.rx_packets++;
690 pkt_len = bdp->cbd_datlen;
691 ndev->stats.rx_bytes += pkt_len;
692 data = (__u8*)__va(bdp->cbd_bufaddr);
694 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
695 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
697 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
698 swap_buffer(data, pkt_len);
700 /* This does 16 byte alignment, exactly what we need.
701 * The packet length includes FCS, but we don't want to
702 * include that when passing upstream as it messes up
703 * bridging applications.
705 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
707 if (unlikely(!skb)) {
708 printk("%s: Memory squeeze, dropping packet.\n",
710 ndev->stats.rx_dropped++;
712 skb_reserve(skb, NET_IP_ALIGN);
713 skb_put(skb, pkt_len - 4); /* Make room */
714 skb_copy_to_linear_data(skb, data, pkt_len - 4);
715 skb->protocol = eth_type_trans(skb, ndev);
716 if (!skb_defer_rx_timestamp(skb))
720 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
721 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
723 /* Clear the status flags for this buffer */
724 status &= ~BD_ENET_RX_STATS;
726 /* Mark the buffer empty */
727 status |= BD_ENET_RX_EMPTY;
728 bdp->cbd_sc = status;
730 /* Update BD pointer to next entry */
731 if (status & BD_ENET_RX_WRAP)
732 bdp = fep->rx_bd_base;
735 /* Doing this here will keep the FEC running while we process
736 * incoming frames. On a heavily loaded network, we should be
737 * able to keep up at the expense of system resources.
739 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
743 spin_unlock(&fep->hw_lock);
747 fec_enet_interrupt(int irq, void *dev_id)
749 struct net_device *ndev = dev_id;
750 struct fec_enet_private *fep = netdev_priv(ndev);
752 irqreturn_t ret = IRQ_NONE;
755 int_events = readl(fep->hwp + FEC_IEVENT);
756 writel(int_events, fep->hwp + FEC_IEVENT);
758 if (int_events & FEC_ENET_RXF) {
763 /* Transmit OK, or non-fatal error. Update the buffer
764 * descriptors. FEC handles all errors, we just discover
765 * them as part of the transmit process.
767 if (int_events & FEC_ENET_TXF) {
772 if (int_events & FEC_ENET_MII) {
774 complete(&fep->mdio_done);
776 } while (int_events);
783 /* ------------------------------------------------------------------------- */
784 static void __inline__ fec_get_mac(struct net_device *ndev)
786 struct fec_enet_private *fep = netdev_priv(ndev);
787 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
788 unsigned char *iap, tmpaddr[ETH_ALEN];
791 * try to get mac address in following order:
793 * 1) module parameter via kernel command line in form
794 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
800 * 2) from device tree data
802 if (!is_valid_ether_addr(iap)) {
803 struct device_node *np = fep->pdev->dev.of_node;
805 const char *mac = of_get_mac_address(np);
807 iap = (unsigned char *) mac;
813 * 3) from flash or fuse (via platform data)
815 if (!is_valid_ether_addr(iap)) {
818 iap = (unsigned char *)FEC_FLASHMAC;
821 memcpy(iap, pdata->mac, ETH_ALEN);
826 * 4) FEC mac registers set by bootloader
828 if (!is_valid_ether_addr(iap)) {
829 *((unsigned long *) &tmpaddr[0]) =
830 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
831 *((unsigned short *) &tmpaddr[4]) =
832 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
836 memcpy(ndev->dev_addr, iap, ETH_ALEN);
838 /* Adjust MAC if using macaddr */
840 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
843 /* ------------------------------------------------------------------------- */
848 static void fec_enet_adjust_link(struct net_device *ndev)
850 struct fec_enet_private *fep = netdev_priv(ndev);
851 struct phy_device *phy_dev = fep->phy_dev;
854 int status_change = 0;
856 spin_lock_irqsave(&fep->hw_lock, flags);
858 /* Prevent a state halted on mii error */
859 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
860 phy_dev->state = PHY_RESUMING;
864 /* Duplex link change */
866 if (fep->full_duplex != phy_dev->duplex) {
867 fec_restart(ndev, phy_dev->duplex);
868 /* prevent unnecessary second fec_restart() below */
869 fep->link = phy_dev->link;
874 /* Link on or off change */
875 if (phy_dev->link != fep->link) {
876 fep->link = phy_dev->link;
878 fec_restart(ndev, phy_dev->duplex);
885 spin_unlock_irqrestore(&fep->hw_lock, flags);
888 phy_print_status(phy_dev);
891 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
893 struct fec_enet_private *fep = bus->priv;
894 unsigned long time_left;
896 fep->mii_timeout = 0;
897 init_completion(&fep->mdio_done);
899 /* start a read op */
900 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
901 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
902 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
904 /* wait for end of transfer */
905 time_left = wait_for_completion_timeout(&fep->mdio_done,
906 usecs_to_jiffies(FEC_MII_TIMEOUT));
907 if (time_left == 0) {
908 fep->mii_timeout = 1;
909 printk(KERN_ERR "FEC: MDIO read timeout\n");
914 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
917 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
920 struct fec_enet_private *fep = bus->priv;
921 unsigned long time_left;
923 fep->mii_timeout = 0;
924 init_completion(&fep->mdio_done);
926 /* start a write op */
927 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
928 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
929 FEC_MMFR_TA | FEC_MMFR_DATA(value),
930 fep->hwp + FEC_MII_DATA);
932 /* wait for end of transfer */
933 time_left = wait_for_completion_timeout(&fep->mdio_done,
934 usecs_to_jiffies(FEC_MII_TIMEOUT));
935 if (time_left == 0) {
936 fep->mii_timeout = 1;
937 printk(KERN_ERR "FEC: MDIO write timeout\n");
944 static int fec_enet_mdio_reset(struct mii_bus *bus)
949 static int fec_enet_mii_probe(struct net_device *ndev)
951 struct fec_enet_private *fep = netdev_priv(ndev);
952 const struct platform_device_id *id_entry =
953 platform_get_device_id(fep->pdev);
954 struct phy_device *phy_dev = NULL;
955 char mdio_bus_id[MII_BUS_ID_SIZE];
956 char phy_name[MII_BUS_ID_SIZE + 3];
958 int dev_id = fep->pdev->id;
962 /* check for attached phy */
963 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
964 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
966 if (fep->mii_bus->phy_map[phy_id] == NULL)
968 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
972 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
976 if (phy_id >= PHY_MAX_ADDR) {
978 "%s: no PHY, assuming direct connection to switch\n",
980 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
984 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
985 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
987 if (IS_ERR(phy_dev)) {
988 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
989 return PTR_ERR(phy_dev);
992 /* mask with MAC supported features */
993 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
994 phy_dev->supported &= PHY_GBIT_FEATURES;
996 phy_dev->supported &= PHY_BASIC_FEATURES;
998 phy_dev->advertising = phy_dev->supported;
1000 fep->phy_dev = phy_dev;
1002 fep->full_duplex = 0;
1005 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1007 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1013 static int fec_enet_mii_init(struct platform_device *pdev)
1015 static struct mii_bus *fec0_mii_bus;
1016 struct net_device *ndev = platform_get_drvdata(pdev);
1017 struct fec_enet_private *fep = netdev_priv(ndev);
1018 const struct platform_device_id *id_entry =
1019 platform_get_device_id(fep->pdev);
1020 int err = -ENXIO, i;
1023 * The dual fec interfaces are not equivalent with enet-mac.
1024 * Here are the differences:
1026 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1027 * - fec0 acts as the 1588 time master while fec1 is slave
1028 * - external phys can only be configured by fec0
1030 * That is to say fec1 can not work independently. It only works
1031 * when fec0 is working. The reason behind this design is that the
1032 * second interface is added primarily for Switch mode.
1034 * Because of the last point above, both phys are attached on fec0
1035 * mdio interface in board design, and need to be configured by
1038 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id > 0) {
1039 /* fec1 uses fec0 mii_bus */
1040 fep->mii_bus = fec0_mii_bus;
1044 fep->mii_timeout = 0;
1047 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1049 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1050 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1051 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1054 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000);
1055 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1057 fep->phy_speed <<= 1;
1058 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1060 fep->mii_bus = mdiobus_alloc();
1061 if (fep->mii_bus == NULL) {
1066 fep->mii_bus->name = "fec_enet_mii_bus";
1067 fep->mii_bus->read = fec_enet_mdio_read;
1068 fep->mii_bus->write = fec_enet_mdio_write;
1069 fep->mii_bus->reset = fec_enet_mdio_reset;
1070 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
1071 fep->mii_bus->priv = fep;
1072 fep->mii_bus->parent = &pdev->dev;
1074 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1075 if (!fep->mii_bus->irq) {
1077 goto err_out_free_mdiobus;
1080 for (i = 0; i < PHY_MAX_ADDR; i++)
1081 fep->mii_bus->irq[i] = PHY_POLL;
1083 if (mdiobus_register(fep->mii_bus))
1084 goto err_out_free_mdio_irq;
1086 /* save fec0 mii_bus */
1087 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1088 fec0_mii_bus = fep->mii_bus;
1092 err_out_free_mdio_irq:
1093 kfree(fep->mii_bus->irq);
1094 err_out_free_mdiobus:
1095 mdiobus_free(fep->mii_bus);
1100 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1103 phy_disconnect(fep->phy_dev);
1104 mdiobus_unregister(fep->mii_bus);
1105 kfree(fep->mii_bus->irq);
1106 mdiobus_free(fep->mii_bus);
1109 static int fec_enet_get_settings(struct net_device *ndev,
1110 struct ethtool_cmd *cmd)
1112 struct fec_enet_private *fep = netdev_priv(ndev);
1113 struct phy_device *phydev = fep->phy_dev;
1118 return phy_ethtool_gset(phydev, cmd);
1121 static int fec_enet_set_settings(struct net_device *ndev,
1122 struct ethtool_cmd *cmd)
1124 struct fec_enet_private *fep = netdev_priv(ndev);
1125 struct phy_device *phydev = fep->phy_dev;
1130 return phy_ethtool_sset(phydev, cmd);
1133 static void fec_enet_get_drvinfo(struct net_device *ndev,
1134 struct ethtool_drvinfo *info)
1136 struct fec_enet_private *fep = netdev_priv(ndev);
1138 strcpy(info->driver, fep->pdev->dev.driver->name);
1139 strcpy(info->version, "Revision: 1.0");
1140 strcpy(info->bus_info, dev_name(&ndev->dev));
1143 static struct ethtool_ops fec_enet_ethtool_ops = {
1144 .get_settings = fec_enet_get_settings,
1145 .set_settings = fec_enet_set_settings,
1146 .get_drvinfo = fec_enet_get_drvinfo,
1147 .get_link = ethtool_op_get_link,
1150 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1152 struct fec_enet_private *fep = netdev_priv(ndev);
1153 struct phy_device *phydev = fep->phy_dev;
1155 if (!netif_running(ndev))
1161 return phy_mii_ioctl(phydev, rq, cmd);
1164 static void fec_enet_free_buffers(struct net_device *ndev)
1166 struct fec_enet_private *fep = netdev_priv(ndev);
1168 struct sk_buff *skb;
1169 struct bufdesc *bdp;
1171 bdp = fep->rx_bd_base;
1172 for (i = 0; i < RX_RING_SIZE; i++) {
1173 skb = fep->rx_skbuff[i];
1175 if (bdp->cbd_bufaddr)
1176 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1177 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1183 bdp = fep->tx_bd_base;
1184 for (i = 0; i < TX_RING_SIZE; i++)
1185 kfree(fep->tx_bounce[i]);
1188 static int fec_enet_alloc_buffers(struct net_device *ndev)
1190 struct fec_enet_private *fep = netdev_priv(ndev);
1192 struct sk_buff *skb;
1193 struct bufdesc *bdp;
1195 bdp = fep->rx_bd_base;
1196 for (i = 0; i < RX_RING_SIZE; i++) {
1197 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1199 fec_enet_free_buffers(ndev);
1202 fep->rx_skbuff[i] = skb;
1204 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1205 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1206 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1210 /* Set the last buffer to wrap. */
1212 bdp->cbd_sc |= BD_SC_WRAP;
1214 bdp = fep->tx_bd_base;
1215 for (i = 0; i < TX_RING_SIZE; i++) {
1216 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1219 bdp->cbd_bufaddr = 0;
1223 /* Set the last buffer to wrap. */
1225 bdp->cbd_sc |= BD_SC_WRAP;
1231 fec_enet_open(struct net_device *ndev)
1233 struct fec_enet_private *fep = netdev_priv(ndev);
1236 /* I should reset the ring buffers here, but I don't yet know
1237 * a simple way to do that.
1240 ret = fec_enet_alloc_buffers(ndev);
1244 /* Probe and connect to PHY when open the interface */
1245 ret = fec_enet_mii_probe(ndev);
1247 fec_enet_free_buffers(ndev);
1250 phy_start(fep->phy_dev);
1251 netif_start_queue(ndev);
1257 fec_enet_close(struct net_device *ndev)
1259 struct fec_enet_private *fep = netdev_priv(ndev);
1261 /* Don't know what to do yet. */
1263 netif_stop_queue(ndev);
1267 phy_stop(fep->phy_dev);
1268 phy_disconnect(fep->phy_dev);
1271 fec_enet_free_buffers(ndev);
1276 /* Set or clear the multicast filter for this adaptor.
1277 * Skeleton taken from sunlance driver.
1278 * The CPM Ethernet implementation allows Multicast as well as individual
1279 * MAC address filtering. Some of the drivers check to make sure it is
1280 * a group multicast address, and discard those that are not. I guess I
1281 * will do the same for now, but just remove the test if you want
1282 * individual filtering as well (do the upper net layers want or support
1283 * this kind of feature?).
1286 #define HASH_BITS 6 /* #bits in hash */
1287 #define CRC32_POLY 0xEDB88320
1289 static void set_multicast_list(struct net_device *ndev)
1291 struct fec_enet_private *fep = netdev_priv(ndev);
1292 struct netdev_hw_addr *ha;
1293 unsigned int i, bit, data, crc, tmp;
1296 if (ndev->flags & IFF_PROMISC) {
1297 tmp = readl(fep->hwp + FEC_R_CNTRL);
1299 writel(tmp, fep->hwp + FEC_R_CNTRL);
1303 tmp = readl(fep->hwp + FEC_R_CNTRL);
1305 writel(tmp, fep->hwp + FEC_R_CNTRL);
1307 if (ndev->flags & IFF_ALLMULTI) {
1308 /* Catch all multicast addresses, so set the
1311 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1312 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1317 /* Clear filter and add the addresses in hash register
1319 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1320 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1322 netdev_for_each_mc_addr(ha, ndev) {
1323 /* calculate crc32 value of mac address */
1326 for (i = 0; i < ndev->addr_len; i++) {
1328 for (bit = 0; bit < 8; bit++, data >>= 1) {
1330 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1334 /* only upper 6 bits (HASH_BITS) are used
1335 * which point to specific bit in he hash registers
1337 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1340 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1341 tmp |= 1 << (hash - 32);
1342 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1344 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1346 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1351 /* Set a MAC change in hardware. */
1353 fec_set_mac_address(struct net_device *ndev, void *p)
1355 struct fec_enet_private *fep = netdev_priv(ndev);
1356 struct sockaddr *addr = p;
1358 if (!is_valid_ether_addr(addr->sa_data))
1359 return -EADDRNOTAVAIL;
1361 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1363 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1364 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1365 fep->hwp + FEC_ADDR_LOW);
1366 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1367 fep->hwp + FEC_ADDR_HIGH);
1371 #ifdef CONFIG_NET_POLL_CONTROLLER
1373 * fec_poll_controller: FEC Poll controller function
1374 * @dev: The FEC network adapter
1376 * Polled functionality used by netconsole and others in non interrupt mode
1379 void fec_poll_controller(struct net_device *dev)
1382 struct fec_enet_private *fep = netdev_priv(dev);
1384 for (i = 0; i < FEC_IRQ_NUM; i++) {
1385 if (fep->irq[i] > 0) {
1386 disable_irq(fep->irq[i]);
1387 fec_enet_interrupt(fep->irq[i], dev);
1388 enable_irq(fep->irq[i]);
1394 static const struct net_device_ops fec_netdev_ops = {
1395 .ndo_open = fec_enet_open,
1396 .ndo_stop = fec_enet_close,
1397 .ndo_start_xmit = fec_enet_start_xmit,
1398 .ndo_set_rx_mode = set_multicast_list,
1399 .ndo_change_mtu = eth_change_mtu,
1400 .ndo_validate_addr = eth_validate_addr,
1401 .ndo_tx_timeout = fec_timeout,
1402 .ndo_set_mac_address = fec_set_mac_address,
1403 .ndo_do_ioctl = fec_enet_ioctl,
1404 #ifdef CONFIG_NET_POLL_CONTROLLER
1405 .ndo_poll_controller = fec_poll_controller,
1410 * XXX: We need to clean up on failure exits here.
1413 static int fec_enet_init(struct net_device *ndev)
1415 struct fec_enet_private *fep = netdev_priv(ndev);
1416 struct bufdesc *cbd_base;
1417 struct bufdesc *bdp;
1420 /* Allocate memory for buffer descriptors. */
1421 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1424 printk("FEC: allocate descriptor memory failed?\n");
1428 spin_lock_init(&fep->hw_lock);
1432 /* Get the Ethernet address */
1435 /* Set receive and transmit descriptor base. */
1436 fep->rx_bd_base = cbd_base;
1437 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1439 /* The FEC Ethernet specific entries in the device structure */
1440 ndev->watchdog_timeo = TX_TIMEOUT;
1441 ndev->netdev_ops = &fec_netdev_ops;
1442 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1444 /* Initialize the receive buffer descriptors. */
1445 bdp = fep->rx_bd_base;
1446 for (i = 0; i < RX_RING_SIZE; i++) {
1448 /* Initialize the BD for every fragment in the page. */
1453 /* Set the last buffer to wrap */
1455 bdp->cbd_sc |= BD_SC_WRAP;
1457 /* ...and the same for transmit */
1458 bdp = fep->tx_bd_base;
1459 for (i = 0; i < TX_RING_SIZE; i++) {
1461 /* Initialize the BD for every fragment in the page. */
1463 bdp->cbd_bufaddr = 0;
1467 /* Set the last buffer to wrap */
1469 bdp->cbd_sc |= BD_SC_WRAP;
1471 fec_restart(ndev, 0);
1477 static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1479 struct device_node *np = pdev->dev.of_node;
1482 return of_get_phy_mode(np);
1487 static void __devinit fec_reset_phy(struct platform_device *pdev)
1490 struct device_node *np = pdev->dev.of_node;
1495 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1496 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
1498 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1502 gpio_set_value(phy_reset, 1);
1504 #else /* CONFIG_OF */
1505 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1510 static inline void fec_reset_phy(struct platform_device *pdev)
1513 * In case of platform probe, the reset has been done
1517 #endif /* CONFIG_OF */
1519 static int __devinit
1520 fec_probe(struct platform_device *pdev)
1522 struct fec_enet_private *fep;
1523 struct fec_platform_data *pdata;
1524 struct net_device *ndev;
1525 int i, irq, ret = 0;
1527 const struct of_device_id *of_id;
1529 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1531 pdev->id_entry = of_id->data;
1533 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 r = request_mem_region(r->start, resource_size(r), pdev->name);
1541 /* Init network device */
1542 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1545 goto failed_alloc_etherdev;
1548 SET_NETDEV_DEV(ndev, &pdev->dev);
1550 /* setup board info structure */
1551 fep = netdev_priv(ndev);
1553 fep->hwp = ioremap(r->start, resource_size(r));
1558 goto failed_ioremap;
1561 platform_set_drvdata(pdev, ndev);
1563 ret = fec_get_phy_mode_dt(pdev);
1565 pdata = pdev->dev.platform_data;
1567 fep->phy_interface = pdata->phy;
1569 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1571 fep->phy_interface = ret;
1574 fec_reset_phy(pdev);
1576 for (i = 0; i < FEC_IRQ_NUM; i++) {
1577 irq = platform_get_irq(pdev, i);
1580 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1583 irq = platform_get_irq(pdev, i);
1584 free_irq(irq, ndev);
1590 fep->clk = clk_get(&pdev->dev, NULL);
1591 if (IS_ERR(fep->clk)) {
1592 ret = PTR_ERR(fep->clk);
1595 clk_enable(fep->clk);
1597 ret = fec_enet_init(ndev);
1601 ret = fec_enet_mii_init(pdev);
1603 goto failed_mii_init;
1605 /* Carrier starts down, phylib will bring it up */
1606 netif_carrier_off(ndev);
1608 ret = register_netdev(ndev);
1610 goto failed_register;
1615 fec_enet_mii_remove(fep);
1618 clk_disable(fep->clk);
1621 for (i = 0; i < FEC_IRQ_NUM; i++) {
1622 irq = platform_get_irq(pdev, i);
1624 free_irq(irq, ndev);
1630 failed_alloc_etherdev:
1631 release_mem_region(r->start, resource_size(r));
1636 static int __devexit
1637 fec_drv_remove(struct platform_device *pdev)
1639 struct net_device *ndev = platform_get_drvdata(pdev);
1640 struct fec_enet_private *fep = netdev_priv(ndev);
1644 fec_enet_mii_remove(fep);
1645 clk_disable(fep->clk);
1648 unregister_netdev(ndev);
1651 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1653 release_mem_region(r->start, resource_size(r));
1655 platform_set_drvdata(pdev, NULL);
1662 fec_suspend(struct device *dev)
1664 struct net_device *ndev = dev_get_drvdata(dev);
1665 struct fec_enet_private *fep = netdev_priv(ndev);
1667 if (netif_running(ndev)) {
1669 netif_device_detach(ndev);
1671 clk_disable(fep->clk);
1677 fec_resume(struct device *dev)
1679 struct net_device *ndev = dev_get_drvdata(dev);
1680 struct fec_enet_private *fep = netdev_priv(ndev);
1682 clk_enable(fep->clk);
1683 if (netif_running(ndev)) {
1684 fec_restart(ndev, fep->full_duplex);
1685 netif_device_attach(ndev);
1691 static const struct dev_pm_ops fec_pm_ops = {
1692 .suspend = fec_suspend,
1693 .resume = fec_resume,
1694 .freeze = fec_suspend,
1696 .poweroff = fec_suspend,
1697 .restore = fec_resume,
1701 static struct platform_driver fec_driver = {
1703 .name = DRIVER_NAME,
1704 .owner = THIS_MODULE,
1708 .of_match_table = fec_dt_ids,
1710 .id_table = fec_devtype,
1712 .remove = __devexit_p(fec_drv_remove),
1716 fec_enet_module_init(void)
1718 printk(KERN_INFO "FEC Ethernet Driver\n");
1720 return platform_driver_register(&fec_driver);
1724 fec_enet_cleanup(void)
1726 platform_driver_unregister(&fec_driver);
1729 module_exit(fec_enet_cleanup);
1730 module_init(fec_enet_module_init);
1732 MODULE_LICENSE("GPL");