2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
62 #include <asm/cacheflush.h>
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 #define DRIVER_NAME "fec"
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 static struct platform_device_id fec_devtype[] = {
83 /* keep it for coldfire */
88 .driver_data = FEC_QUIRK_USE_GASKET,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
101 .name = "mvf600-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC,
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
124 static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139 #if defined(CONFIG_M5272)
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
155 #define FEC_FLASHMAC 0
157 #endif /* CONFIG_M5272 */
159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
161 #define PKT_MAXBUF_SIZE 1522
162 #define PKT_MINBUF_SIZE 64
163 #define PKT_MAXBLR_SIZE 1536
165 /* FEC receive acceleration */
166 #define FEC_RACC_IPDIS (1 << 1)
167 #define FEC_RACC_PRODIS (1 << 2)
168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179 #define OPT_FRAME_SIZE 0
182 /* FEC MII MMFR bits definition */
183 #define FEC_MMFR_ST (1 << 30)
184 #define FEC_MMFR_OP_READ (2 << 28)
185 #define FEC_MMFR_OP_WRITE (1 << 28)
186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188 #define FEC_MMFR_TA (2 << 16)
189 #define FEC_MMFR_DATA(v) (v & 0xffff)
191 #define FEC_MII_TIMEOUT 30000 /* us */
193 /* Transmitter timeout */
194 #define TX_TIMEOUT (2 * HZ)
196 #define FEC_PAUSE_FLAG_AUTONEG 0x1
197 #define FEC_PAUSE_FLAG_ENABLE 0x2
199 #define COPYBREAK_DEFAULT 256
201 #define TSO_HEADER_SIZE 128
202 /* Max number of allowed TCP segments for software TSO */
203 #define FEC_MAX_TSO_SEGS 100
204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
206 #define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
239 return (new_bd >= (base + ring_size)) ?
244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
287 return entries > 0 ? entries : entries + txq->tx_ring_size;
290 static void *swap_buffer(void *bufaddr, int len)
293 unsigned int *buf = bufaddr;
295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
296 *buf = cpu_to_be32(*buf);
301 static void fec_dump(struct net_device *ndev)
303 struct fec_enet_private *fep = netdev_priv(ndev);
305 struct fec_enet_priv_tx_q *txq;
308 netdev_info(ndev, "TX ring dump\n");
309 pr_info("Nr SC addr len SKB\n");
311 txq = fep->tx_queue[0];
312 bdp = txq->tx_bd_base;
315 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
317 bdp == txq->cur_tx ? 'S' : ' ',
318 bdp == txq->dirty_tx ? 'H' : ' ',
319 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
320 txq->tx_skbuff[index]);
321 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
323 } while (bdp != txq->tx_bd_base);
326 static inline bool is_ipv4_pkt(struct sk_buff *skb)
328 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
332 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
334 /* Only run for packets requiring a checksum. */
335 if (skb->ip_summed != CHECKSUM_PARTIAL)
338 if (unlikely(skb_cow_head(skb, 0)))
341 if (is_ipv4_pkt(skb))
342 ip_hdr(skb)->check = 0;
343 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
349 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
351 struct net_device *ndev)
353 struct fec_enet_private *fep = netdev_priv(ndev);
354 const struct platform_device_id *id_entry =
355 platform_get_device_id(fep->pdev);
356 struct bufdesc *bdp = txq->cur_tx;
357 struct bufdesc_ex *ebdp;
358 int nr_frags = skb_shinfo(skb)->nr_frags;
359 unsigned short queue = skb_get_queue_mapping(skb);
361 unsigned short status;
362 unsigned int estatus = 0;
363 skb_frag_t *this_frag;
369 for (frag = 0; frag < nr_frags; frag++) {
370 this_frag = &skb_shinfo(skb)->frags[frag];
371 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
372 ebdp = (struct bufdesc_ex *)bdp;
374 status = bdp->cbd_sc;
375 status &= ~BD_ENET_TX_STATS;
376 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
377 frag_len = skb_shinfo(skb)->frags[frag].size;
379 /* Handle the last BD specially */
380 if (frag == nr_frags - 1) {
381 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
382 if (fep->bufdesc_ex) {
383 estatus |= BD_ENET_TX_INT;
384 if (unlikely(skb_shinfo(skb)->tx_flags &
385 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
386 estatus |= BD_ENET_TX_TS;
390 if (fep->bufdesc_ex) {
391 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
392 estatus |= FEC_TX_BD_FTYPE(queue);
393 if (skb->ip_summed == CHECKSUM_PARTIAL)
394 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
396 ebdp->cbd_esc = estatus;
399 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
401 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
402 if (((unsigned long) bufaddr) & fep->tx_align ||
403 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
404 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
405 bufaddr = txq->tx_bounce[index];
407 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
408 swap_buffer(bufaddr, frag_len);
411 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
413 if (dma_mapping_error(&fep->pdev->dev, addr)) {
414 dev_kfree_skb_any(skb);
416 netdev_err(ndev, "Tx DMA memory map failed\n");
417 goto dma_mapping_error;
420 bdp->cbd_bufaddr = addr;
421 bdp->cbd_datlen = frag_len;
422 bdp->cbd_sc = status;
431 for (i = 0; i < frag; i++) {
432 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
433 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
434 bdp->cbd_datlen, DMA_TO_DEVICE);
439 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
440 struct sk_buff *skb, struct net_device *ndev)
442 struct fec_enet_private *fep = netdev_priv(ndev);
443 const struct platform_device_id *id_entry =
444 platform_get_device_id(fep->pdev);
445 int nr_frags = skb_shinfo(skb)->nr_frags;
446 struct bufdesc *bdp, *last_bdp;
449 unsigned short status;
450 unsigned short buflen;
451 unsigned short queue;
452 unsigned int estatus = 0;
457 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
458 if (entries_free < MAX_SKB_FRAGS + 1) {
459 dev_kfree_skb_any(skb);
461 netdev_err(ndev, "NOT enough BD for SG!\n");
465 /* Protocol checksum off-load for TCP and UDP. */
466 if (fec_enet_clear_csum(skb, ndev)) {
467 dev_kfree_skb_any(skb);
471 /* Fill in a Tx ring entry */
473 status = bdp->cbd_sc;
474 status &= ~BD_ENET_TX_STATS;
476 /* Set buffer length and buffer pointer */
478 buflen = skb_headlen(skb);
480 queue = skb_get_queue_mapping(skb);
481 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
482 if (((unsigned long) bufaddr) & fep->tx_align ||
483 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
484 memcpy(txq->tx_bounce[index], skb->data, buflen);
485 bufaddr = txq->tx_bounce[index];
487 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
488 swap_buffer(bufaddr, buflen);
491 /* Push the data cache so the CPM does not get stale memory data. */
492 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
493 if (dma_mapping_error(&fep->pdev->dev, addr)) {
494 dev_kfree_skb_any(skb);
496 netdev_err(ndev, "Tx DMA memory map failed\n");
501 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
505 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
506 if (fep->bufdesc_ex) {
507 estatus = BD_ENET_TX_INT;
508 if (unlikely(skb_shinfo(skb)->tx_flags &
509 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
510 estatus |= BD_ENET_TX_TS;
514 if (fep->bufdesc_ex) {
516 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
518 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
520 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
522 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
523 estatus |= FEC_TX_BD_FTYPE(queue);
525 if (skb->ip_summed == CHECKSUM_PARTIAL)
526 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
529 ebdp->cbd_esc = estatus;
532 last_bdp = txq->cur_tx;
533 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
534 /* Save skb pointer */
535 txq->tx_skbuff[index] = skb;
537 bdp->cbd_datlen = buflen;
538 bdp->cbd_bufaddr = addr;
540 /* Send it on its way. Tell FEC it's ready, interrupt when done,
541 * it's the last BD of the frame, and to put the CRC on the end.
543 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
544 bdp->cbd_sc = status;
546 /* If this was the last BD in the ring, start at the beginning again. */
547 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
549 skb_tx_timestamp(skb);
553 /* Trigger transmission start */
554 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
560 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
561 struct net_device *ndev,
562 struct bufdesc *bdp, int index, char *data,
563 int size, bool last_tcp, bool is_last)
565 struct fec_enet_private *fep = netdev_priv(ndev);
566 const struct platform_device_id *id_entry =
567 platform_get_device_id(fep->pdev);
568 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
569 unsigned short queue = skb_get_queue_mapping(skb);
570 unsigned short status;
571 unsigned int estatus = 0;
574 status = bdp->cbd_sc;
575 status &= ~BD_ENET_TX_STATS;
577 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
579 if (((unsigned long) data) & fep->tx_align ||
580 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
581 memcpy(txq->tx_bounce[index], data, size);
582 data = txq->tx_bounce[index];
584 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
585 swap_buffer(data, size);
588 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
589 if (dma_mapping_error(&fep->pdev->dev, addr)) {
590 dev_kfree_skb_any(skb);
592 netdev_err(ndev, "Tx DMA memory map failed\n");
593 return NETDEV_TX_BUSY;
596 bdp->cbd_datlen = size;
597 bdp->cbd_bufaddr = addr;
599 if (fep->bufdesc_ex) {
600 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
601 estatus |= FEC_TX_BD_FTYPE(queue);
602 if (skb->ip_summed == CHECKSUM_PARTIAL)
603 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
605 ebdp->cbd_esc = estatus;
608 /* Handle the last BD specially */
610 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
612 status |= BD_ENET_TX_INTR;
614 ebdp->cbd_esc |= BD_ENET_TX_INT;
617 bdp->cbd_sc = status;
623 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
624 struct sk_buff *skb, struct net_device *ndev,
625 struct bufdesc *bdp, int index)
627 struct fec_enet_private *fep = netdev_priv(ndev);
628 const struct platform_device_id *id_entry =
629 platform_get_device_id(fep->pdev);
630 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
631 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
632 unsigned short queue = skb_get_queue_mapping(skb);
634 unsigned long dmabuf;
635 unsigned short status;
636 unsigned int estatus = 0;
638 status = bdp->cbd_sc;
639 status &= ~BD_ENET_TX_STATS;
640 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
642 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
643 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
644 if (((unsigned long)bufaddr) & fep->tx_align ||
645 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
646 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
647 bufaddr = txq->tx_bounce[index];
649 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
650 swap_buffer(bufaddr, hdr_len);
652 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
653 hdr_len, DMA_TO_DEVICE);
654 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
655 dev_kfree_skb_any(skb);
657 netdev_err(ndev, "Tx DMA memory map failed\n");
658 return NETDEV_TX_BUSY;
662 bdp->cbd_bufaddr = dmabuf;
663 bdp->cbd_datlen = hdr_len;
665 if (fep->bufdesc_ex) {
666 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
667 estatus |= FEC_TX_BD_FTYPE(queue);
668 if (skb->ip_summed == CHECKSUM_PARTIAL)
669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
671 ebdp->cbd_esc = estatus;
674 bdp->cbd_sc = status;
679 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
681 struct net_device *ndev)
683 struct fec_enet_private *fep = netdev_priv(ndev);
684 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
685 int total_len, data_left;
686 struct bufdesc *bdp = txq->cur_tx;
687 unsigned short queue = skb_get_queue_mapping(skb);
689 unsigned int index = 0;
691 const struct platform_device_id *id_entry =
692 platform_get_device_id(fep->pdev);
694 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
695 dev_kfree_skb_any(skb);
697 netdev_err(ndev, "NOT enough BD for TSO!\n");
701 /* Protocol checksum off-load for TCP and UDP. */
702 if (fec_enet_clear_csum(skb, ndev)) {
703 dev_kfree_skb_any(skb);
707 /* Initialize the TSO handler, and prepare the first payload */
708 tso_start(skb, &tso);
710 total_len = skb->len - hdr_len;
711 while (total_len > 0) {
714 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
715 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
716 total_len -= data_left;
718 /* prepare packet headers: MAC + IP + TCP */
719 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
720 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
721 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
725 while (data_left > 0) {
728 size = min_t(int, tso.size, data_left);
729 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
730 index = fec_enet_get_bd_index(txq->tx_bd_base,
732 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
741 tso_build_data(skb, &tso, size);
744 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
747 /* Save skb pointer */
748 txq->tx_skbuff[index] = skb;
750 skb_tx_timestamp(skb);
753 /* Trigger transmission start */
754 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) ||
755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
757 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
758 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
759 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
764 /* TODO: Release all used data descriptors for TSO */
769 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
771 struct fec_enet_private *fep = netdev_priv(ndev);
773 unsigned short queue;
774 struct fec_enet_priv_tx_q *txq;
775 struct netdev_queue *nq;
778 queue = skb_get_queue_mapping(skb);
779 txq = fep->tx_queue[queue];
780 nq = netdev_get_tx_queue(ndev, queue);
783 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
785 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
789 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
790 if (entries_free <= txq->tx_stop_threshold)
791 netif_tx_stop_queue(nq);
796 /* Init RX & TX buffer descriptors
798 static void fec_enet_bd_init(struct net_device *dev)
800 struct fec_enet_private *fep = netdev_priv(dev);
801 struct fec_enet_priv_tx_q *txq;
802 struct fec_enet_priv_rx_q *rxq;
807 for (q = 0; q < fep->num_rx_queues; q++) {
808 /* Initialize the receive buffer descriptors. */
809 rxq = fep->rx_queue[q];
810 bdp = rxq->rx_bd_base;
812 for (i = 0; i < rxq->rx_ring_size; i++) {
814 /* Initialize the BD for every fragment in the page. */
815 if (bdp->cbd_bufaddr)
816 bdp->cbd_sc = BD_ENET_RX_EMPTY;
819 bdp = fec_enet_get_nextdesc(bdp, fep, q);
822 /* Set the last buffer to wrap */
823 bdp = fec_enet_get_prevdesc(bdp, fep, q);
824 bdp->cbd_sc |= BD_SC_WRAP;
826 rxq->cur_rx = rxq->rx_bd_base;
829 for (q = 0; q < fep->num_tx_queues; q++) {
830 /* ...and the same for transmit */
831 txq = fep->tx_queue[q];
832 bdp = txq->tx_bd_base;
835 for (i = 0; i < txq->tx_ring_size; i++) {
836 /* Initialize the BD for every fragment in the page. */
838 if (txq->tx_skbuff[i]) {
839 dev_kfree_skb_any(txq->tx_skbuff[i]);
840 txq->tx_skbuff[i] = NULL;
842 bdp->cbd_bufaddr = 0;
843 bdp = fec_enet_get_nextdesc(bdp, fep, q);
846 /* Set the last buffer to wrap */
847 bdp = fec_enet_get_prevdesc(bdp, fep, q);
848 bdp->cbd_sc |= BD_SC_WRAP;
853 static void fec_enet_active_rxring(struct net_device *ndev)
855 struct fec_enet_private *fep = netdev_priv(ndev);
858 for (i = 0; i < fep->num_rx_queues; i++)
859 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
862 static void fec_enet_enable_ring(struct net_device *ndev)
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 struct fec_enet_priv_tx_q *txq;
866 struct fec_enet_priv_rx_q *rxq;
869 for (i = 0; i < fep->num_rx_queues; i++) {
870 rxq = fep->rx_queue[i];
871 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
875 writel(RCMR_MATCHEN | RCMR_CMP(i),
876 fep->hwp + FEC_RCMR(i));
879 for (i = 0; i < fep->num_tx_queues; i++) {
880 txq = fep->tx_queue[i];
881 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
885 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
886 fep->hwp + FEC_DMA_CFG(i));
890 static void fec_enet_reset_skb(struct net_device *ndev)
892 struct fec_enet_private *fep = netdev_priv(ndev);
893 struct fec_enet_priv_tx_q *txq;
896 for (i = 0; i < fep->num_tx_queues; i++) {
897 txq = fep->tx_queue[i];
899 for (j = 0; j < txq->tx_ring_size; j++) {
900 if (txq->tx_skbuff[j]) {
901 dev_kfree_skb_any(txq->tx_skbuff[j]);
902 txq->tx_skbuff[j] = NULL;
909 * This function is called to start or restart the FEC during a link
910 * change, transmit timeout, or to reconfigure the FEC. The network
911 * packet processing for this device must be stopped before this call.
914 fec_restart(struct net_device *ndev)
916 struct fec_enet_private *fep = netdev_priv(ndev);
917 const struct platform_device_id *id_entry =
918 platform_get_device_id(fep->pdev);
921 u32 rcntl = OPT_FRAME_SIZE | 0x04;
922 u32 ecntl = 0x2; /* ETHEREN */
924 /* Whack a reset. We should wait for this.
925 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
926 * instead of reset MAC itself.
928 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
929 writel(0, fep->hwp + FEC_ECNTRL);
931 writel(1, fep->hwp + FEC_ECNTRL);
936 * enet-mac reset will reset mac address registers too,
937 * so need to reconfigure it.
939 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
940 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
941 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
942 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
945 /* Clear any outstanding interrupt. */
946 writel(0xffc00000, fep->hwp + FEC_IEVENT);
948 /* Set maximum receive buffer size. */
949 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
951 fec_enet_bd_init(ndev);
953 fec_enet_enable_ring(ndev);
955 /* Reset tx SKB buffers. */
956 fec_enet_reset_skb(ndev);
958 /* Enable MII mode */
959 if (fep->full_duplex == DUPLEX_FULL) {
961 writel(0x04, fep->hwp + FEC_X_CNTRL);
965 writel(0x0, fep->hwp + FEC_X_CNTRL);
969 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
971 #if !defined(CONFIG_M5272)
972 /* set RX checksum */
973 val = readl(fep->hwp + FEC_RACC);
974 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
975 val |= FEC_RACC_OPTIONS;
977 val &= ~FEC_RACC_OPTIONS;
978 writel(val, fep->hwp + FEC_RACC);
982 * The phy interface and speed need to get configured
983 * differently on enet-mac.
985 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
986 /* Enable flow control and length check */
987 rcntl |= 0x40000000 | 0x00000020;
989 /* RGMII, RMII or MII */
990 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
992 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
997 /* 1G, 100M or 10M */
999 if (fep->phy_dev->speed == SPEED_1000)
1001 else if (fep->phy_dev->speed == SPEED_100)
1007 #ifdef FEC_MIIGSK_ENR
1008 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
1010 /* disable the gasket and wait */
1011 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1012 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1016 * configure the gasket:
1017 * RMII, 50 MHz, no loopback, no echo
1018 * MII, 25 MHz, no loopback, no echo
1020 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1021 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1022 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1023 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1024 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1026 /* re-enable the gasket */
1027 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1032 #if !defined(CONFIG_M5272)
1033 /* enable pause frame*/
1034 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1035 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1036 fep->phy_dev && fep->phy_dev->pause)) {
1037 rcntl |= FEC_ENET_FCE;
1039 /* set FIFO threshold parameter to reduce overrun */
1040 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1041 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1042 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1043 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1046 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1048 rcntl &= ~FEC_ENET_FCE;
1050 #endif /* !defined(CONFIG_M5272) */
1052 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1054 /* Setup multicast filter. */
1055 set_multicast_list(ndev);
1056 #ifndef CONFIG_M5272
1057 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1058 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1061 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1062 /* enable ENET endian swap */
1064 /* enable ENET store and forward mode */
1065 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1068 if (fep->bufdesc_ex)
1071 #ifndef CONFIG_M5272
1072 /* Enable the MIB statistic event counters */
1073 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1076 /* And last, enable the transmit and receive processing */
1077 writel(ecntl, fep->hwp + FEC_ECNTRL);
1078 fec_enet_active_rxring(ndev);
1080 if (fep->bufdesc_ex)
1081 fec_ptp_start_cyclecounter(ndev);
1083 /* Enable interrupts we wish to service */
1084 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1086 /* Init the interrupt coalescing */
1087 fec_enet_itr_coal_init(ndev);
1092 fec_stop(struct net_device *ndev)
1094 struct fec_enet_private *fep = netdev_priv(ndev);
1095 const struct platform_device_id *id_entry =
1096 platform_get_device_id(fep->pdev);
1097 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1099 /* We cannot expect a graceful transmit stop without link !!! */
1101 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1103 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1104 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1107 /* Whack a reset. We should wait for this.
1108 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1109 * instead of reset MAC itself.
1111 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
1112 writel(0, fep->hwp + FEC_ECNTRL);
1114 writel(1, fep->hwp + FEC_ECNTRL);
1117 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1118 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1120 /* We have to keep ENET enabled to have MII interrupt stay working */
1121 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1122 writel(2, fep->hwp + FEC_ECNTRL);
1123 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1129 fec_timeout(struct net_device *ndev)
1131 struct fec_enet_private *fep = netdev_priv(ndev);
1135 ndev->stats.tx_errors++;
1137 schedule_work(&fep->tx_timeout_work);
1140 static void fec_enet_timeout_work(struct work_struct *work)
1142 struct fec_enet_private *fep =
1143 container_of(work, struct fec_enet_private, tx_timeout_work);
1144 struct net_device *ndev = fep->netdev;
1147 if (netif_device_present(ndev) || netif_running(ndev)) {
1148 napi_disable(&fep->napi);
1149 netif_tx_lock_bh(ndev);
1151 netif_wake_queue(ndev);
1152 netif_tx_unlock_bh(ndev);
1153 napi_enable(&fep->napi);
1159 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1160 struct skb_shared_hwtstamps *hwtstamps)
1162 unsigned long flags;
1165 spin_lock_irqsave(&fep->tmreg_lock, flags);
1166 ns = timecounter_cyc2time(&fep->tc, ts);
1167 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1169 memset(hwtstamps, 0, sizeof(*hwtstamps));
1170 hwtstamps->hwtstamp = ns_to_ktime(ns);
1174 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1176 struct fec_enet_private *fep;
1177 struct bufdesc *bdp;
1178 unsigned short status;
1179 struct sk_buff *skb;
1180 struct fec_enet_priv_tx_q *txq;
1181 struct netdev_queue *nq;
1185 fep = netdev_priv(ndev);
1187 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1189 txq = fep->tx_queue[queue_id];
1190 /* get next bdp of dirty_tx */
1191 nq = netdev_get_tx_queue(ndev, queue_id);
1192 bdp = txq->dirty_tx;
1194 /* get next bdp of dirty_tx */
1195 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1197 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1199 /* current queue is empty */
1200 if (bdp == txq->cur_tx)
1203 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1205 skb = txq->tx_skbuff[index];
1206 txq->tx_skbuff[index] = NULL;
1207 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1208 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1209 bdp->cbd_datlen, DMA_TO_DEVICE);
1210 bdp->cbd_bufaddr = 0;
1212 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1216 /* Check for errors. */
1217 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1218 BD_ENET_TX_RL | BD_ENET_TX_UN |
1220 ndev->stats.tx_errors++;
1221 if (status & BD_ENET_TX_HB) /* No heartbeat */
1222 ndev->stats.tx_heartbeat_errors++;
1223 if (status & BD_ENET_TX_LC) /* Late collision */
1224 ndev->stats.tx_window_errors++;
1225 if (status & BD_ENET_TX_RL) /* Retrans limit */
1226 ndev->stats.tx_aborted_errors++;
1227 if (status & BD_ENET_TX_UN) /* Underrun */
1228 ndev->stats.tx_fifo_errors++;
1229 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1230 ndev->stats.tx_carrier_errors++;
1232 ndev->stats.tx_packets++;
1233 ndev->stats.tx_bytes += skb->len;
1236 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1238 struct skb_shared_hwtstamps shhwtstamps;
1239 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1241 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1242 skb_tstamp_tx(skb, &shhwtstamps);
1245 /* Deferred means some collisions occurred during transmit,
1246 * but we eventually sent the packet OK.
1248 if (status & BD_ENET_TX_DEF)
1249 ndev->stats.collisions++;
1251 /* Free the sk buffer associated with this last transmit */
1252 dev_kfree_skb_any(skb);
1254 txq->dirty_tx = bdp;
1256 /* Update pointer to next buffer descriptor to be transmitted */
1257 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1259 /* Since we have freed up a buffer, the ring is no longer full
1261 if (netif_queue_stopped(ndev)) {
1262 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1263 if (entries_free >= txq->tx_wake_threshold)
1264 netif_tx_wake_queue(nq);
1268 /* ERR006538: Keep the transmitter going */
1269 if (bdp != txq->cur_tx &&
1270 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1271 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1275 fec_enet_tx(struct net_device *ndev)
1277 struct fec_enet_private *fep = netdev_priv(ndev);
1279 /* First process class A queue, then Class B and Best Effort queue */
1280 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1281 clear_bit(queue_id, &fep->work_tx);
1282 fec_enet_tx_queue(ndev, queue_id);
1288 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1290 struct fec_enet_private *fep = netdev_priv(ndev);
1293 off = ((unsigned long)skb->data) & fep->rx_align;
1295 skb_reserve(skb, fep->rx_align + 1 - off);
1297 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1298 FEC_ENET_RX_FRSIZE - fep->rx_align,
1300 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1301 if (net_ratelimit())
1302 netdev_err(ndev, "Rx DMA memory map failed\n");
1309 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310 struct bufdesc *bdp, u32 length)
1312 struct fec_enet_private *fep = netdev_priv(ndev);
1313 struct sk_buff *new_skb;
1315 if (length > fep->rx_copybreak)
1318 new_skb = netdev_alloc_skb(ndev, length);
1322 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1323 FEC_ENET_RX_FRSIZE - fep->rx_align,
1325 memcpy(new_skb->data, (*skb)->data, length);
1331 /* During a receive, the cur_rx points to the current incoming buffer.
1332 * When we update through the ring, if the next incoming buffer has
1333 * not been given to the system, we just set the empty indicator,
1334 * effectively tossing the packet.
1337 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1339 struct fec_enet_private *fep = netdev_priv(ndev);
1340 const struct platform_device_id *id_entry =
1341 platform_get_device_id(fep->pdev);
1342 struct fec_enet_priv_rx_q *rxq;
1343 struct bufdesc *bdp;
1344 unsigned short status;
1345 struct sk_buff *skb_new = NULL;
1346 struct sk_buff *skb;
1349 int pkt_received = 0;
1350 struct bufdesc_ex *ebdp = NULL;
1351 bool vlan_packet_rcvd = false;
1359 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1360 rxq = fep->rx_queue[queue_id];
1362 /* First, grab all of the stats for the incoming packet.
1363 * These get messed up if we get called due to a busy condition.
1367 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1369 if (pkt_received >= budget)
1373 /* Since we have allocated space to hold a complete frame,
1374 * the last indicator should be set.
1376 if ((status & BD_ENET_RX_LAST) == 0)
1377 netdev_err(ndev, "rcv is not +last\n");
1380 /* Check for errors. */
1381 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1382 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1383 ndev->stats.rx_errors++;
1384 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1385 /* Frame too long or too short. */
1386 ndev->stats.rx_length_errors++;
1388 if (status & BD_ENET_RX_NO) /* Frame alignment */
1389 ndev->stats.rx_frame_errors++;
1390 if (status & BD_ENET_RX_CR) /* CRC Error */
1391 ndev->stats.rx_crc_errors++;
1392 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1393 ndev->stats.rx_fifo_errors++;
1396 /* Report late collisions as a frame error.
1397 * On this error, the BD is closed, but we don't know what we
1398 * have in the buffer. So, just drop this frame on the floor.
1400 if (status & BD_ENET_RX_CL) {
1401 ndev->stats.rx_errors++;
1402 ndev->stats.rx_frame_errors++;
1403 goto rx_processing_done;
1406 /* Process the incoming frame. */
1407 ndev->stats.rx_packets++;
1408 pkt_len = bdp->cbd_datlen;
1409 ndev->stats.rx_bytes += pkt_len;
1411 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1412 skb = rxq->rx_skbuff[index];
1414 /* The packet length includes FCS, but we don't want to
1415 * include that when passing upstream as it messes up
1416 * bridging applications.
1418 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4);
1419 if (!is_copybreak) {
1420 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1421 if (unlikely(!skb_new)) {
1422 ndev->stats.rx_dropped++;
1423 goto rx_processing_done;
1425 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1426 FEC_ENET_RX_FRSIZE - fep->rx_align,
1430 prefetch(skb->data - NET_IP_ALIGN);
1431 skb_put(skb, pkt_len - 4);
1433 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1434 swap_buffer(data, pkt_len);
1436 /* Extract the enhanced buffer descriptor */
1438 if (fep->bufdesc_ex)
1439 ebdp = (struct bufdesc_ex *)bdp;
1441 /* If this is a VLAN packet remove the VLAN Tag */
1442 vlan_packet_rcvd = false;
1443 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1444 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1445 /* Push and remove the vlan tag */
1446 struct vlan_hdr *vlan_header =
1447 (struct vlan_hdr *) (data + ETH_HLEN);
1448 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1450 vlan_packet_rcvd = true;
1452 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1453 data, (2 * ETH_ALEN));
1454 skb_pull(skb, VLAN_HLEN);
1457 skb->protocol = eth_type_trans(skb, ndev);
1459 /* Get receive timestamp from the skb */
1460 if (fep->hwts_rx_en && fep->bufdesc_ex)
1461 fec_enet_hwtstamp(fep, ebdp->ts,
1462 skb_hwtstamps(skb));
1464 if (fep->bufdesc_ex &&
1465 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1466 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1467 /* don't check it */
1468 skb->ip_summed = CHECKSUM_UNNECESSARY;
1470 skb_checksum_none_assert(skb);
1474 /* Handle received VLAN packets */
1475 if (vlan_packet_rcvd)
1476 __vlan_hwaccel_put_tag(skb,
1480 napi_gro_receive(&fep->napi, skb);
1483 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1484 FEC_ENET_RX_FRSIZE - fep->rx_align,
1487 rxq->rx_skbuff[index] = skb_new;
1488 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1492 /* Clear the status flags for this buffer */
1493 status &= ~BD_ENET_RX_STATS;
1495 /* Mark the buffer empty */
1496 status |= BD_ENET_RX_EMPTY;
1497 bdp->cbd_sc = status;
1499 if (fep->bufdesc_ex) {
1500 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1502 ebdp->cbd_esc = BD_ENET_RX_INT;
1507 /* Update BD pointer to next entry */
1508 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1510 /* Doing this here will keep the FEC running while we process
1511 * incoming frames. On a heavily loaded network, we should be
1512 * able to keep up at the expense of system resources.
1514 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1517 return pkt_received;
1521 fec_enet_rx(struct net_device *ndev, int budget)
1523 int pkt_received = 0;
1525 struct fec_enet_private *fep = netdev_priv(ndev);
1527 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1528 clear_bit(queue_id, &fep->work_rx);
1529 pkt_received += fec_enet_rx_queue(ndev,
1530 budget - pkt_received, queue_id);
1532 return pkt_received;
1536 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1538 if (int_events == 0)
1541 if (int_events & FEC_ENET_RXF)
1542 fep->work_rx |= (1 << 2);
1543 if (int_events & FEC_ENET_RXF_1)
1544 fep->work_rx |= (1 << 0);
1545 if (int_events & FEC_ENET_RXF_2)
1546 fep->work_rx |= (1 << 1);
1548 if (int_events & FEC_ENET_TXF)
1549 fep->work_tx |= (1 << 2);
1550 if (int_events & FEC_ENET_TXF_1)
1551 fep->work_tx |= (1 << 0);
1552 if (int_events & FEC_ENET_TXF_2)
1553 fep->work_tx |= (1 << 1);
1559 fec_enet_interrupt(int irq, void *dev_id)
1561 struct net_device *ndev = dev_id;
1562 struct fec_enet_private *fep = netdev_priv(ndev);
1563 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1565 irqreturn_t ret = IRQ_NONE;
1567 int_events = readl(fep->hwp + FEC_IEVENT);
1568 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1569 fec_enet_collect_events(fep, int_events);
1571 if (int_events & napi_mask) {
1574 /* Disable the NAPI interrupts */
1575 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1576 napi_schedule(&fep->napi);
1579 if (int_events & FEC_ENET_MII) {
1581 complete(&fep->mdio_done);
1585 fec_ptp_check_pps_event(fep);
1590 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1592 struct net_device *ndev = napi->dev;
1593 struct fec_enet_private *fep = netdev_priv(ndev);
1597 * Clear any pending transmit or receive interrupts before
1598 * processing the rings to avoid racing with the hardware.
1600 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1602 pkts = fec_enet_rx(ndev, budget);
1606 if (pkts < budget) {
1607 napi_complete(napi);
1608 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1613 /* ------------------------------------------------------------------------- */
1614 static void fec_get_mac(struct net_device *ndev)
1616 struct fec_enet_private *fep = netdev_priv(ndev);
1617 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1618 unsigned char *iap, tmpaddr[ETH_ALEN];
1621 * try to get mac address in following order:
1623 * 1) module parameter via kernel command line in form
1624 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1629 * 2) from device tree data
1631 if (!is_valid_ether_addr(iap)) {
1632 struct device_node *np = fep->pdev->dev.of_node;
1634 const char *mac = of_get_mac_address(np);
1636 iap = (unsigned char *) mac;
1641 * 3) from flash or fuse (via platform data)
1643 if (!is_valid_ether_addr(iap)) {
1646 iap = (unsigned char *)FEC_FLASHMAC;
1649 iap = (unsigned char *)&pdata->mac;
1654 * 4) FEC mac registers set by bootloader
1656 if (!is_valid_ether_addr(iap)) {
1657 *((__be32 *) &tmpaddr[0]) =
1658 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1659 *((__be16 *) &tmpaddr[4]) =
1660 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1665 * 5) random mac address
1667 if (!is_valid_ether_addr(iap)) {
1668 /* Report it and use a random ethernet address instead */
1669 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1670 eth_hw_addr_random(ndev);
1671 netdev_info(ndev, "Using random MAC address: %pM\n",
1676 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1678 /* Adjust MAC if using macaddr */
1680 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1683 /* ------------------------------------------------------------------------- */
1688 static void fec_enet_adjust_link(struct net_device *ndev)
1690 struct fec_enet_private *fep = netdev_priv(ndev);
1691 struct phy_device *phy_dev = fep->phy_dev;
1692 int status_change = 0;
1694 /* Prevent a state halted on mii error */
1695 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1696 phy_dev->state = PHY_RESUMING;
1701 * If the netdev is down, or is going down, we're not interested
1702 * in link state events, so just mark our idea of the link as down
1703 * and ignore the event.
1705 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1707 } else if (phy_dev->link) {
1709 fep->link = phy_dev->link;
1713 if (fep->full_duplex != phy_dev->duplex) {
1714 fep->full_duplex = phy_dev->duplex;
1718 if (phy_dev->speed != fep->speed) {
1719 fep->speed = phy_dev->speed;
1723 /* if any of the above changed restart the FEC */
1724 if (status_change) {
1725 napi_disable(&fep->napi);
1726 netif_tx_lock_bh(ndev);
1728 netif_wake_queue(ndev);
1729 netif_tx_unlock_bh(ndev);
1730 napi_enable(&fep->napi);
1734 napi_disable(&fep->napi);
1735 netif_tx_lock_bh(ndev);
1737 netif_tx_unlock_bh(ndev);
1738 napi_enable(&fep->napi);
1739 fep->link = phy_dev->link;
1745 phy_print_status(phy_dev);
1748 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1750 struct fec_enet_private *fep = bus->priv;
1751 unsigned long time_left;
1753 fep->mii_timeout = 0;
1754 init_completion(&fep->mdio_done);
1756 /* start a read op */
1757 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1758 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1759 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1761 /* wait for end of transfer */
1762 time_left = wait_for_completion_timeout(&fep->mdio_done,
1763 usecs_to_jiffies(FEC_MII_TIMEOUT));
1764 if (time_left == 0) {
1765 fep->mii_timeout = 1;
1766 netdev_err(fep->netdev, "MDIO read timeout\n");
1771 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1774 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1777 struct fec_enet_private *fep = bus->priv;
1778 unsigned long time_left;
1780 fep->mii_timeout = 0;
1781 init_completion(&fep->mdio_done);
1783 /* start a write op */
1784 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1785 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1786 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1787 fep->hwp + FEC_MII_DATA);
1789 /* wait for end of transfer */
1790 time_left = wait_for_completion_timeout(&fep->mdio_done,
1791 usecs_to_jiffies(FEC_MII_TIMEOUT));
1792 if (time_left == 0) {
1793 fep->mii_timeout = 1;
1794 netdev_err(fep->netdev, "MDIO write timeout\n");
1801 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1803 struct fec_enet_private *fep = netdev_priv(ndev);
1807 ret = clk_prepare_enable(fep->clk_ahb);
1810 ret = clk_prepare_enable(fep->clk_ipg);
1812 goto failed_clk_ipg;
1813 if (fep->clk_enet_out) {
1814 ret = clk_prepare_enable(fep->clk_enet_out);
1816 goto failed_clk_enet_out;
1819 mutex_lock(&fep->ptp_clk_mutex);
1820 ret = clk_prepare_enable(fep->clk_ptp);
1822 mutex_unlock(&fep->ptp_clk_mutex);
1823 goto failed_clk_ptp;
1825 fep->ptp_clk_on = true;
1827 mutex_unlock(&fep->ptp_clk_mutex);
1830 ret = clk_prepare_enable(fep->clk_ref);
1832 goto failed_clk_ref;
1835 clk_disable_unprepare(fep->clk_ahb);
1836 clk_disable_unprepare(fep->clk_ipg);
1837 if (fep->clk_enet_out)
1838 clk_disable_unprepare(fep->clk_enet_out);
1840 mutex_lock(&fep->ptp_clk_mutex);
1841 clk_disable_unprepare(fep->clk_ptp);
1842 fep->ptp_clk_on = false;
1843 mutex_unlock(&fep->ptp_clk_mutex);
1846 clk_disable_unprepare(fep->clk_ref);
1853 clk_disable_unprepare(fep->clk_ref);
1855 if (fep->clk_enet_out)
1856 clk_disable_unprepare(fep->clk_enet_out);
1857 failed_clk_enet_out:
1858 clk_disable_unprepare(fep->clk_ipg);
1860 clk_disable_unprepare(fep->clk_ahb);
1865 static int fec_enet_mii_probe(struct net_device *ndev)
1867 struct fec_enet_private *fep = netdev_priv(ndev);
1868 const struct platform_device_id *id_entry =
1869 platform_get_device_id(fep->pdev);
1870 struct phy_device *phy_dev = NULL;
1871 char mdio_bus_id[MII_BUS_ID_SIZE];
1872 char phy_name[MII_BUS_ID_SIZE + 3];
1874 int dev_id = fep->dev_id;
1876 fep->phy_dev = NULL;
1878 if (fep->phy_node) {
1879 phy_dev = of_phy_connect(ndev, fep->phy_node,
1880 &fec_enet_adjust_link, 0,
1881 fep->phy_interface);
1883 /* check for attached phy */
1884 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1885 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1887 if (fep->mii_bus->phy_map[phy_id] == NULL)
1889 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1893 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1897 if (phy_id >= PHY_MAX_ADDR) {
1898 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1899 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1903 snprintf(phy_name, sizeof(phy_name),
1904 PHY_ID_FMT, mdio_bus_id, phy_id);
1905 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1906 fep->phy_interface);
1909 if (IS_ERR(phy_dev)) {
1910 netdev_err(ndev, "could not attach to PHY\n");
1911 return PTR_ERR(phy_dev);
1914 /* mask with MAC supported features */
1915 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1916 phy_dev->supported &= PHY_GBIT_FEATURES;
1917 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1918 #if !defined(CONFIG_M5272)
1919 phy_dev->supported |= SUPPORTED_Pause;
1923 phy_dev->supported &= PHY_BASIC_FEATURES;
1925 phy_dev->advertising = phy_dev->supported;
1927 fep->phy_dev = phy_dev;
1929 fep->full_duplex = 0;
1931 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1932 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1938 static int fec_enet_mii_init(struct platform_device *pdev)
1940 static struct mii_bus *fec0_mii_bus;
1941 struct net_device *ndev = platform_get_drvdata(pdev);
1942 struct fec_enet_private *fep = netdev_priv(ndev);
1943 const struct platform_device_id *id_entry =
1944 platform_get_device_id(fep->pdev);
1945 struct device_node *node;
1946 int err = -ENXIO, i;
1949 * The dual fec interfaces are not equivalent with enet-mac.
1950 * Here are the differences:
1952 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1953 * - fec0 acts as the 1588 time master while fec1 is slave
1954 * - external phys can only be configured by fec0
1956 * That is to say fec1 can not work independently. It only works
1957 * when fec0 is working. The reason behind this design is that the
1958 * second interface is added primarily for Switch mode.
1960 * Because of the last point above, both phys are attached on fec0
1961 * mdio interface in board design, and need to be configured by
1964 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1965 /* fec1 uses fec0 mii_bus */
1966 if (mii_cnt && fec0_mii_bus) {
1967 fep->mii_bus = fec0_mii_bus;
1974 fep->mii_timeout = 0;
1977 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1979 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1980 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1981 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1984 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1985 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1987 fep->phy_speed <<= 1;
1988 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1990 fep->mii_bus = mdiobus_alloc();
1991 if (fep->mii_bus == NULL) {
1996 fep->mii_bus->name = "fec_enet_mii_bus";
1997 fep->mii_bus->read = fec_enet_mdio_read;
1998 fep->mii_bus->write = fec_enet_mdio_write;
1999 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2000 pdev->name, fep->dev_id + 1);
2001 fep->mii_bus->priv = fep;
2002 fep->mii_bus->parent = &pdev->dev;
2004 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2005 if (!fep->mii_bus->irq) {
2007 goto err_out_free_mdiobus;
2010 for (i = 0; i < PHY_MAX_ADDR; i++)
2011 fep->mii_bus->irq[i] = PHY_POLL;
2013 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2015 err = of_mdiobus_register(fep->mii_bus, node);
2018 err = mdiobus_register(fep->mii_bus);
2022 goto err_out_free_mdio_irq;
2026 /* save fec0 mii_bus */
2027 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2028 fec0_mii_bus = fep->mii_bus;
2032 err_out_free_mdio_irq:
2033 kfree(fep->mii_bus->irq);
2034 err_out_free_mdiobus:
2035 mdiobus_free(fep->mii_bus);
2040 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2042 if (--mii_cnt == 0) {
2043 mdiobus_unregister(fep->mii_bus);
2044 kfree(fep->mii_bus->irq);
2045 mdiobus_free(fep->mii_bus);
2049 static int fec_enet_get_settings(struct net_device *ndev,
2050 struct ethtool_cmd *cmd)
2052 struct fec_enet_private *fep = netdev_priv(ndev);
2053 struct phy_device *phydev = fep->phy_dev;
2058 return phy_ethtool_gset(phydev, cmd);
2061 static int fec_enet_set_settings(struct net_device *ndev,
2062 struct ethtool_cmd *cmd)
2064 struct fec_enet_private *fep = netdev_priv(ndev);
2065 struct phy_device *phydev = fep->phy_dev;
2070 return phy_ethtool_sset(phydev, cmd);
2073 static void fec_enet_get_drvinfo(struct net_device *ndev,
2074 struct ethtool_drvinfo *info)
2076 struct fec_enet_private *fep = netdev_priv(ndev);
2078 strlcpy(info->driver, fep->pdev->dev.driver->name,
2079 sizeof(info->driver));
2080 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2081 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2084 static int fec_enet_get_ts_info(struct net_device *ndev,
2085 struct ethtool_ts_info *info)
2087 struct fec_enet_private *fep = netdev_priv(ndev);
2089 if (fep->bufdesc_ex) {
2091 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2092 SOF_TIMESTAMPING_RX_SOFTWARE |
2093 SOF_TIMESTAMPING_SOFTWARE |
2094 SOF_TIMESTAMPING_TX_HARDWARE |
2095 SOF_TIMESTAMPING_RX_HARDWARE |
2096 SOF_TIMESTAMPING_RAW_HARDWARE;
2098 info->phc_index = ptp_clock_index(fep->ptp_clock);
2100 info->phc_index = -1;
2102 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2103 (1 << HWTSTAMP_TX_ON);
2105 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2106 (1 << HWTSTAMP_FILTER_ALL);
2109 return ethtool_op_get_ts_info(ndev, info);
2113 #if !defined(CONFIG_M5272)
2115 static void fec_enet_get_pauseparam(struct net_device *ndev,
2116 struct ethtool_pauseparam *pause)
2118 struct fec_enet_private *fep = netdev_priv(ndev);
2120 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2121 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2122 pause->rx_pause = pause->tx_pause;
2125 static int fec_enet_set_pauseparam(struct net_device *ndev,
2126 struct ethtool_pauseparam *pause)
2128 struct fec_enet_private *fep = netdev_priv(ndev);
2133 if (pause->tx_pause != pause->rx_pause) {
2135 "hardware only support enable/disable both tx and rx");
2139 fep->pause_flag = 0;
2141 /* tx pause must be same as rx pause */
2142 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2143 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2145 if (pause->rx_pause || pause->autoneg) {
2146 fep->phy_dev->supported |= ADVERTISED_Pause;
2147 fep->phy_dev->advertising |= ADVERTISED_Pause;
2149 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2150 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2153 if (pause->autoneg) {
2154 if (netif_running(ndev))
2156 phy_start_aneg(fep->phy_dev);
2158 if (netif_running(ndev)) {
2159 napi_disable(&fep->napi);
2160 netif_tx_lock_bh(ndev);
2162 netif_wake_queue(ndev);
2163 netif_tx_unlock_bh(ndev);
2164 napi_enable(&fep->napi);
2170 static const struct fec_stat {
2171 char name[ETH_GSTRING_LEN];
2175 { "tx_dropped", RMON_T_DROP },
2176 { "tx_packets", RMON_T_PACKETS },
2177 { "tx_broadcast", RMON_T_BC_PKT },
2178 { "tx_multicast", RMON_T_MC_PKT },
2179 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2180 { "tx_undersize", RMON_T_UNDERSIZE },
2181 { "tx_oversize", RMON_T_OVERSIZE },
2182 { "tx_fragment", RMON_T_FRAG },
2183 { "tx_jabber", RMON_T_JAB },
2184 { "tx_collision", RMON_T_COL },
2185 { "tx_64byte", RMON_T_P64 },
2186 { "tx_65to127byte", RMON_T_P65TO127 },
2187 { "tx_128to255byte", RMON_T_P128TO255 },
2188 { "tx_256to511byte", RMON_T_P256TO511 },
2189 { "tx_512to1023byte", RMON_T_P512TO1023 },
2190 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2191 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2192 { "tx_octets", RMON_T_OCTETS },
2195 { "IEEE_tx_drop", IEEE_T_DROP },
2196 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2197 { "IEEE_tx_1col", IEEE_T_1COL },
2198 { "IEEE_tx_mcol", IEEE_T_MCOL },
2199 { "IEEE_tx_def", IEEE_T_DEF },
2200 { "IEEE_tx_lcol", IEEE_T_LCOL },
2201 { "IEEE_tx_excol", IEEE_T_EXCOL },
2202 { "IEEE_tx_macerr", IEEE_T_MACERR },
2203 { "IEEE_tx_cserr", IEEE_T_CSERR },
2204 { "IEEE_tx_sqe", IEEE_T_SQE },
2205 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2206 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2209 { "rx_packets", RMON_R_PACKETS },
2210 { "rx_broadcast", RMON_R_BC_PKT },
2211 { "rx_multicast", RMON_R_MC_PKT },
2212 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2213 { "rx_undersize", RMON_R_UNDERSIZE },
2214 { "rx_oversize", RMON_R_OVERSIZE },
2215 { "rx_fragment", RMON_R_FRAG },
2216 { "rx_jabber", RMON_R_JAB },
2217 { "rx_64byte", RMON_R_P64 },
2218 { "rx_65to127byte", RMON_R_P65TO127 },
2219 { "rx_128to255byte", RMON_R_P128TO255 },
2220 { "rx_256to511byte", RMON_R_P256TO511 },
2221 { "rx_512to1023byte", RMON_R_P512TO1023 },
2222 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2223 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2224 { "rx_octets", RMON_R_OCTETS },
2227 { "IEEE_rx_drop", IEEE_R_DROP },
2228 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2229 { "IEEE_rx_crc", IEEE_R_CRC },
2230 { "IEEE_rx_align", IEEE_R_ALIGN },
2231 { "IEEE_rx_macerr", IEEE_R_MACERR },
2232 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2233 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2236 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2237 struct ethtool_stats *stats, u64 *data)
2239 struct fec_enet_private *fep = netdev_priv(dev);
2242 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2243 data[i] = readl(fep->hwp + fec_stats[i].offset);
2246 static void fec_enet_get_strings(struct net_device *netdev,
2247 u32 stringset, u8 *data)
2250 switch (stringset) {
2252 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2253 memcpy(data + i * ETH_GSTRING_LEN,
2254 fec_stats[i].name, ETH_GSTRING_LEN);
2259 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2263 return ARRAY_SIZE(fec_stats);
2268 #endif /* !defined(CONFIG_M5272) */
2270 static int fec_enet_nway_reset(struct net_device *dev)
2272 struct fec_enet_private *fep = netdev_priv(dev);
2273 struct phy_device *phydev = fep->phy_dev;
2278 return genphy_restart_aneg(phydev);
2281 /* ITR clock source is enet system clock (clk_ahb).
2282 * TCTT unit is cycle_ns * 64 cycle
2283 * So, the ICTT value = X us / (cycle_ns * 64)
2285 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2287 struct fec_enet_private *fep = netdev_priv(ndev);
2289 return us * (fep->itr_clk_rate / 64000) / 1000;
2292 /* Set threshold for interrupt coalescing */
2293 static void fec_enet_itr_coal_set(struct net_device *ndev)
2295 struct fec_enet_private *fep = netdev_priv(ndev);
2296 const struct platform_device_id *id_entry =
2297 platform_get_device_id(fep->pdev);
2300 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2303 /* Must be greater than zero to avoid unpredictable behavior */
2304 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2305 !fep->tx_time_itr || !fep->tx_pkts_itr)
2308 /* Select enet system clock as Interrupt Coalescing
2309 * timer Clock Source
2311 rx_itr = FEC_ITR_CLK_SEL;
2312 tx_itr = FEC_ITR_CLK_SEL;
2314 /* set ICFT and ICTT */
2315 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2316 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2317 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2318 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2320 rx_itr |= FEC_ITR_EN;
2321 tx_itr |= FEC_ITR_EN;
2323 writel(tx_itr, fep->hwp + FEC_TXIC0);
2324 writel(rx_itr, fep->hwp + FEC_RXIC0);
2325 writel(tx_itr, fep->hwp + FEC_TXIC1);
2326 writel(rx_itr, fep->hwp + FEC_RXIC1);
2327 writel(tx_itr, fep->hwp + FEC_TXIC2);
2328 writel(rx_itr, fep->hwp + FEC_RXIC2);
2332 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2334 struct fec_enet_private *fep = netdev_priv(ndev);
2335 const struct platform_device_id *id_entry =
2336 platform_get_device_id(fep->pdev);
2338 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2341 ec->rx_coalesce_usecs = fep->rx_time_itr;
2342 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2344 ec->tx_coalesce_usecs = fep->tx_time_itr;
2345 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2351 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2353 struct fec_enet_private *fep = netdev_priv(ndev);
2354 const struct platform_device_id *id_entry =
2355 platform_get_device_id(fep->pdev);
2359 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2362 if (ec->rx_max_coalesced_frames > 255) {
2363 pr_err("Rx coalesced frames exceed hardware limiation");
2367 if (ec->tx_max_coalesced_frames > 255) {
2368 pr_err("Tx coalesced frame exceed hardware limiation");
2372 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2373 if (cycle > 0xFFFF) {
2374 pr_err("Rx coalesed usec exceeed hardware limiation");
2378 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2379 if (cycle > 0xFFFF) {
2380 pr_err("Rx coalesed usec exceeed hardware limiation");
2384 fep->rx_time_itr = ec->rx_coalesce_usecs;
2385 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2387 fep->tx_time_itr = ec->tx_coalesce_usecs;
2388 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2390 fec_enet_itr_coal_set(ndev);
2395 static void fec_enet_itr_coal_init(struct net_device *ndev)
2397 struct ethtool_coalesce ec;
2399 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2400 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2402 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2403 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2405 fec_enet_set_coalesce(ndev, &ec);
2408 static int fec_enet_get_tunable(struct net_device *netdev,
2409 const struct ethtool_tunable *tuna,
2412 struct fec_enet_private *fep = netdev_priv(netdev);
2416 case ETHTOOL_RX_COPYBREAK:
2417 *(u32 *)data = fep->rx_copybreak;
2427 static int fec_enet_set_tunable(struct net_device *netdev,
2428 const struct ethtool_tunable *tuna,
2431 struct fec_enet_private *fep = netdev_priv(netdev);
2435 case ETHTOOL_RX_COPYBREAK:
2436 fep->rx_copybreak = *(u32 *)data;
2446 static const struct ethtool_ops fec_enet_ethtool_ops = {
2447 .get_settings = fec_enet_get_settings,
2448 .set_settings = fec_enet_set_settings,
2449 .get_drvinfo = fec_enet_get_drvinfo,
2450 .nway_reset = fec_enet_nway_reset,
2451 .get_link = ethtool_op_get_link,
2452 .get_coalesce = fec_enet_get_coalesce,
2453 .set_coalesce = fec_enet_set_coalesce,
2454 #ifndef CONFIG_M5272
2455 .get_pauseparam = fec_enet_get_pauseparam,
2456 .set_pauseparam = fec_enet_set_pauseparam,
2457 .get_strings = fec_enet_get_strings,
2458 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2459 .get_sset_count = fec_enet_get_sset_count,
2461 .get_ts_info = fec_enet_get_ts_info,
2462 .get_tunable = fec_enet_get_tunable,
2463 .set_tunable = fec_enet_set_tunable,
2466 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2468 struct fec_enet_private *fep = netdev_priv(ndev);
2469 struct phy_device *phydev = fep->phy_dev;
2471 if (!netif_running(ndev))
2477 if (fep->bufdesc_ex) {
2478 if (cmd == SIOCSHWTSTAMP)
2479 return fec_ptp_set(ndev, rq);
2480 if (cmd == SIOCGHWTSTAMP)
2481 return fec_ptp_get(ndev, rq);
2484 return phy_mii_ioctl(phydev, rq, cmd);
2487 static void fec_enet_free_buffers(struct net_device *ndev)
2489 struct fec_enet_private *fep = netdev_priv(ndev);
2491 struct sk_buff *skb;
2492 struct bufdesc *bdp;
2493 struct fec_enet_priv_tx_q *txq;
2494 struct fec_enet_priv_rx_q *rxq;
2497 for (q = 0; q < fep->num_rx_queues; q++) {
2498 rxq = fep->rx_queue[q];
2499 bdp = rxq->rx_bd_base;
2500 for (i = 0; i < rxq->rx_ring_size; i++) {
2501 skb = rxq->rx_skbuff[i];
2502 rxq->rx_skbuff[i] = NULL;
2504 dma_unmap_single(&fep->pdev->dev,
2506 FEC_ENET_RX_FRSIZE - fep->rx_align,
2510 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2514 for (q = 0; q < fep->num_tx_queues; q++) {
2515 txq = fep->tx_queue[q];
2516 bdp = txq->tx_bd_base;
2517 for (i = 0; i < txq->tx_ring_size; i++) {
2518 kfree(txq->tx_bounce[i]);
2519 txq->tx_bounce[i] = NULL;
2520 skb = txq->tx_skbuff[i];
2521 txq->tx_skbuff[i] = NULL;
2527 static void fec_enet_free_queue(struct net_device *ndev)
2529 struct fec_enet_private *fep = netdev_priv(ndev);
2531 struct fec_enet_priv_tx_q *txq;
2533 for (i = 0; i < fep->num_tx_queues; i++)
2534 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2535 txq = fep->tx_queue[i];
2536 dma_free_coherent(NULL,
2537 txq->tx_ring_size * TSO_HEADER_SIZE,
2542 for (i = 0; i < fep->num_rx_queues; i++)
2543 if (fep->rx_queue[i])
2544 kfree(fep->rx_queue[i]);
2546 for (i = 0; i < fep->num_tx_queues; i++)
2547 if (fep->tx_queue[i])
2548 kfree(fep->tx_queue[i]);
2551 static int fec_enet_alloc_queue(struct net_device *ndev)
2553 struct fec_enet_private *fep = netdev_priv(ndev);
2556 struct fec_enet_priv_tx_q *txq;
2558 for (i = 0; i < fep->num_tx_queues; i++) {
2559 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2565 fep->tx_queue[i] = txq;
2566 txq->tx_ring_size = TX_RING_SIZE;
2567 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2569 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2570 txq->tx_wake_threshold =
2571 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2573 txq->tso_hdrs = dma_alloc_coherent(NULL,
2574 txq->tx_ring_size * TSO_HEADER_SIZE,
2577 if (!txq->tso_hdrs) {
2583 for (i = 0; i < fep->num_rx_queues; i++) {
2584 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2586 if (!fep->rx_queue[i]) {
2591 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2592 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2597 fec_enet_free_queue(ndev);
2602 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2604 struct fec_enet_private *fep = netdev_priv(ndev);
2606 struct sk_buff *skb;
2607 struct bufdesc *bdp;
2608 struct fec_enet_priv_rx_q *rxq;
2610 rxq = fep->rx_queue[queue];
2611 bdp = rxq->rx_bd_base;
2612 for (i = 0; i < rxq->rx_ring_size; i++) {
2613 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2617 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2622 rxq->rx_skbuff[i] = skb;
2623 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2625 if (fep->bufdesc_ex) {
2626 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2627 ebdp->cbd_esc = BD_ENET_RX_INT;
2630 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2633 /* Set the last buffer to wrap. */
2634 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2635 bdp->cbd_sc |= BD_SC_WRAP;
2639 fec_enet_free_buffers(ndev);
2644 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2646 struct fec_enet_private *fep = netdev_priv(ndev);
2648 struct bufdesc *bdp;
2649 struct fec_enet_priv_tx_q *txq;
2651 txq = fep->tx_queue[queue];
2652 bdp = txq->tx_bd_base;
2653 for (i = 0; i < txq->tx_ring_size; i++) {
2654 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2655 if (!txq->tx_bounce[i])
2659 bdp->cbd_bufaddr = 0;
2661 if (fep->bufdesc_ex) {
2662 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2663 ebdp->cbd_esc = BD_ENET_TX_INT;
2666 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2669 /* Set the last buffer to wrap. */
2670 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2671 bdp->cbd_sc |= BD_SC_WRAP;
2676 fec_enet_free_buffers(ndev);
2680 static int fec_enet_alloc_buffers(struct net_device *ndev)
2682 struct fec_enet_private *fep = netdev_priv(ndev);
2685 for (i = 0; i < fep->num_rx_queues; i++)
2686 if (fec_enet_alloc_rxq_buffers(ndev, i))
2689 for (i = 0; i < fep->num_tx_queues; i++)
2690 if (fec_enet_alloc_txq_buffers(ndev, i))
2696 fec_enet_open(struct net_device *ndev)
2698 struct fec_enet_private *fep = netdev_priv(ndev);
2701 pinctrl_pm_select_default_state(&fep->pdev->dev);
2702 ret = fec_enet_clk_enable(ndev, true);
2706 /* I should reset the ring buffers here, but I don't yet know
2707 * a simple way to do that.
2710 ret = fec_enet_alloc_buffers(ndev);
2712 goto err_enet_alloc;
2714 /* Probe and connect to PHY when open the interface */
2715 ret = fec_enet_mii_probe(ndev);
2717 goto err_enet_mii_probe;
2720 napi_enable(&fep->napi);
2721 phy_start(fep->phy_dev);
2722 netif_tx_start_all_queues(ndev);
2727 fec_enet_free_buffers(ndev);
2729 fec_enet_clk_enable(ndev, false);
2730 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2735 fec_enet_close(struct net_device *ndev)
2737 struct fec_enet_private *fep = netdev_priv(ndev);
2739 phy_stop(fep->phy_dev);
2741 if (netif_device_present(ndev)) {
2742 napi_disable(&fep->napi);
2743 netif_tx_disable(ndev);
2747 phy_disconnect(fep->phy_dev);
2748 fep->phy_dev = NULL;
2750 fec_enet_clk_enable(ndev, false);
2751 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2752 fec_enet_free_buffers(ndev);
2757 /* Set or clear the multicast filter for this adaptor.
2758 * Skeleton taken from sunlance driver.
2759 * The CPM Ethernet implementation allows Multicast as well as individual
2760 * MAC address filtering. Some of the drivers check to make sure it is
2761 * a group multicast address, and discard those that are not. I guess I
2762 * will do the same for now, but just remove the test if you want
2763 * individual filtering as well (do the upper net layers want or support
2764 * this kind of feature?).
2767 #define HASH_BITS 6 /* #bits in hash */
2768 #define CRC32_POLY 0xEDB88320
2770 static void set_multicast_list(struct net_device *ndev)
2772 struct fec_enet_private *fep = netdev_priv(ndev);
2773 struct netdev_hw_addr *ha;
2774 unsigned int i, bit, data, crc, tmp;
2777 if (ndev->flags & IFF_PROMISC) {
2778 tmp = readl(fep->hwp + FEC_R_CNTRL);
2780 writel(tmp, fep->hwp + FEC_R_CNTRL);
2784 tmp = readl(fep->hwp + FEC_R_CNTRL);
2786 writel(tmp, fep->hwp + FEC_R_CNTRL);
2788 if (ndev->flags & IFF_ALLMULTI) {
2789 /* Catch all multicast addresses, so set the
2792 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2793 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2798 /* Clear filter and add the addresses in hash register
2800 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2801 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2803 netdev_for_each_mc_addr(ha, ndev) {
2804 /* calculate crc32 value of mac address */
2807 for (i = 0; i < ndev->addr_len; i++) {
2809 for (bit = 0; bit < 8; bit++, data >>= 1) {
2811 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2815 /* only upper 6 bits (HASH_BITS) are used
2816 * which point to specific bit in he hash registers
2818 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2821 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2822 tmp |= 1 << (hash - 32);
2823 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2825 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2827 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2832 /* Set a MAC change in hardware. */
2834 fec_set_mac_address(struct net_device *ndev, void *p)
2836 struct fec_enet_private *fep = netdev_priv(ndev);
2837 struct sockaddr *addr = p;
2840 if (!is_valid_ether_addr(addr->sa_data))
2841 return -EADDRNOTAVAIL;
2842 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2845 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2846 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2847 fep->hwp + FEC_ADDR_LOW);
2848 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2849 fep->hwp + FEC_ADDR_HIGH);
2853 #ifdef CONFIG_NET_POLL_CONTROLLER
2855 * fec_poll_controller - FEC Poll controller function
2856 * @dev: The FEC network adapter
2858 * Polled functionality used by netconsole and others in non interrupt mode
2861 static void fec_poll_controller(struct net_device *dev)
2864 struct fec_enet_private *fep = netdev_priv(dev);
2866 for (i = 0; i < FEC_IRQ_NUM; i++) {
2867 if (fep->irq[i] > 0) {
2868 disable_irq(fep->irq[i]);
2869 fec_enet_interrupt(fep->irq[i], dev);
2870 enable_irq(fep->irq[i]);
2876 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2877 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2878 netdev_features_t features)
2880 struct fec_enet_private *fep = netdev_priv(netdev);
2881 netdev_features_t changed = features ^ netdev->features;
2883 netdev->features = features;
2885 /* Receive checksum has been changed */
2886 if (changed & NETIF_F_RXCSUM) {
2887 if (features & NETIF_F_RXCSUM)
2888 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2890 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2894 static int fec_set_features(struct net_device *netdev,
2895 netdev_features_t features)
2897 struct fec_enet_private *fep = netdev_priv(netdev);
2898 netdev_features_t changed = features ^ netdev->features;
2900 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2901 napi_disable(&fep->napi);
2902 netif_tx_lock_bh(netdev);
2904 fec_enet_set_netdev_features(netdev, features);
2905 fec_restart(netdev);
2906 netif_tx_wake_all_queues(netdev);
2907 netif_tx_unlock_bh(netdev);
2908 napi_enable(&fep->napi);
2910 fec_enet_set_netdev_features(netdev, features);
2916 static const struct net_device_ops fec_netdev_ops = {
2917 .ndo_open = fec_enet_open,
2918 .ndo_stop = fec_enet_close,
2919 .ndo_start_xmit = fec_enet_start_xmit,
2920 .ndo_set_rx_mode = set_multicast_list,
2921 .ndo_change_mtu = eth_change_mtu,
2922 .ndo_validate_addr = eth_validate_addr,
2923 .ndo_tx_timeout = fec_timeout,
2924 .ndo_set_mac_address = fec_set_mac_address,
2925 .ndo_do_ioctl = fec_enet_ioctl,
2926 #ifdef CONFIG_NET_POLL_CONTROLLER
2927 .ndo_poll_controller = fec_poll_controller,
2929 .ndo_set_features = fec_set_features,
2933 * XXX: We need to clean up on failure exits here.
2936 static int fec_enet_init(struct net_device *ndev)
2938 struct fec_enet_private *fep = netdev_priv(ndev);
2939 const struct platform_device_id *id_entry =
2940 platform_get_device_id(fep->pdev);
2941 struct fec_enet_priv_tx_q *txq;
2942 struct fec_enet_priv_rx_q *rxq;
2943 struct bufdesc *cbd_base;
2948 #if defined(CONFIG_ARM)
2949 fep->rx_align = 0xf;
2950 fep->tx_align = 0xf;
2952 fep->rx_align = 0x3;
2953 fep->tx_align = 0x3;
2956 fec_enet_alloc_queue(ndev);
2958 if (fep->bufdesc_ex)
2959 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2961 fep->bufdesc_size = sizeof(struct bufdesc);
2962 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
2965 /* Allocate memory for buffer descriptors. */
2966 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
2972 memset(cbd_base, 0, bd_size);
2974 /* Get the Ethernet address */
2976 /* make sure MAC we just acquired is programmed into the hw */
2977 fec_set_mac_address(ndev, NULL);
2979 /* Set receive and transmit descriptor base. */
2980 for (i = 0; i < fep->num_rx_queues; i++) {
2981 rxq = fep->rx_queue[i];
2983 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2984 rxq->bd_dma = bd_dma;
2985 if (fep->bufdesc_ex) {
2986 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2987 cbd_base = (struct bufdesc *)
2988 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2990 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2991 cbd_base += rxq->rx_ring_size;
2995 for (i = 0; i < fep->num_tx_queues; i++) {
2996 txq = fep->tx_queue[i];
2998 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2999 txq->bd_dma = bd_dma;
3000 if (fep->bufdesc_ex) {
3001 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3002 cbd_base = (struct bufdesc *)
3003 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3005 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3006 cbd_base += txq->tx_ring_size;
3011 /* The FEC Ethernet specific entries in the device structure */
3012 ndev->watchdog_timeo = TX_TIMEOUT;
3013 ndev->netdev_ops = &fec_netdev_ops;
3014 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3016 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3017 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3019 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
3020 /* enable hw VLAN support */
3021 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3023 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
3024 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3026 /* enable hw accelerator */
3027 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3028 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3029 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3032 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
3034 fep->rx_align = 0x3f;
3037 ndev->hw_features = ndev->features;
3045 static void fec_reset_phy(struct platform_device *pdev)
3049 struct device_node *np = pdev->dev.of_node;
3054 of_property_read_u32(np, "phy-reset-duration", &msec);
3055 /* A sane reset duration should not be longer than 1s */
3059 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3060 if (!gpio_is_valid(phy_reset))
3063 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3064 GPIOF_OUT_INIT_LOW, "phy-reset");
3066 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3070 gpio_set_value(phy_reset, 1);
3072 #else /* CONFIG_OF */
3073 static void fec_reset_phy(struct platform_device *pdev)
3076 * In case of platform probe, the reset has been done
3080 #endif /* CONFIG_OF */
3083 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3085 struct device_node *np = pdev->dev.of_node;
3088 *num_tx = *num_rx = 1;
3090 if (!np || !of_device_is_available(np))
3093 /* parse the num of tx and rx queues */
3094 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3098 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3102 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3103 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3109 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3110 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3119 fec_probe(struct platform_device *pdev)
3121 struct fec_enet_private *fep;
3122 struct fec_platform_data *pdata;
3123 struct net_device *ndev;
3124 int i, irq, ret = 0;
3126 const struct of_device_id *of_id;
3128 struct device_node *np = pdev->dev.of_node, *phy_node;
3132 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3134 pdev->id_entry = of_id->data;
3136 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3138 /* Init network device */
3139 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3140 num_tx_qs, num_rx_qs);
3144 SET_NETDEV_DEV(ndev, &pdev->dev);
3146 /* setup board info structure */
3147 fep = netdev_priv(ndev);
3149 fep->num_rx_queues = num_rx_qs;
3150 fep->num_tx_queues = num_tx_qs;
3152 #if !defined(CONFIG_M5272)
3153 /* default enable pause frame auto negotiation */
3154 if (pdev->id_entry &&
3155 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
3156 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3159 /* Select default pin state */
3160 pinctrl_pm_select_default_state(&pdev->dev);
3162 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3163 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3164 if (IS_ERR(fep->hwp)) {
3165 ret = PTR_ERR(fep->hwp);
3166 goto failed_ioremap;
3170 fep->dev_id = dev_id++;
3172 fep->bufdesc_ex = 0;
3174 platform_set_drvdata(pdev, ndev);
3176 phy_node = of_parse_phandle(np, "phy-handle", 0);
3177 if (!phy_node && of_phy_is_fixed_link(np)) {
3178 ret = of_phy_register_fixed_link(np);
3181 "broken fixed-link specification\n");
3184 phy_node = of_node_get(np);
3186 fep->phy_node = phy_node;
3188 ret = of_get_phy_mode(pdev->dev.of_node);
3190 pdata = dev_get_platdata(&pdev->dev);
3192 fep->phy_interface = pdata->phy;
3194 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3196 fep->phy_interface = ret;
3199 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3200 if (IS_ERR(fep->clk_ipg)) {
3201 ret = PTR_ERR(fep->clk_ipg);
3205 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3206 if (IS_ERR(fep->clk_ahb)) {
3207 ret = PTR_ERR(fep->clk_ahb);
3211 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3213 /* enet_out is optional, depends on board */
3214 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3215 if (IS_ERR(fep->clk_enet_out))
3216 fep->clk_enet_out = NULL;
3218 fep->ptp_clk_on = false;
3219 mutex_init(&fep->ptp_clk_mutex);
3221 /* clk_ref is optional, depends on board */
3222 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3223 if (IS_ERR(fep->clk_ref))
3224 fep->clk_ref = NULL;
3226 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3228 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
3229 if (IS_ERR(fep->clk_ptp)) {
3230 fep->clk_ptp = NULL;
3231 fep->bufdesc_ex = 0;
3234 ret = fec_enet_clk_enable(ndev, true);
3238 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3239 if (!IS_ERR(fep->reg_phy)) {
3240 ret = regulator_enable(fep->reg_phy);
3243 "Failed to enable phy regulator: %d\n", ret);
3244 goto failed_regulator;
3247 fep->reg_phy = NULL;
3250 fec_reset_phy(pdev);
3252 if (fep->bufdesc_ex)
3255 ret = fec_enet_init(ndev);
3259 for (i = 0; i < FEC_IRQ_NUM; i++) {
3260 irq = platform_get_irq(pdev, i);
3267 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3268 0, pdev->name, ndev);
3273 init_completion(&fep->mdio_done);
3274 ret = fec_enet_mii_init(pdev);
3276 goto failed_mii_init;
3278 /* Carrier starts down, phylib will bring it up */
3279 netif_carrier_off(ndev);
3280 fec_enet_clk_enable(ndev, false);
3281 pinctrl_pm_select_sleep_state(&pdev->dev);
3283 ret = register_netdev(ndev);
3285 goto failed_register;
3287 if (fep->bufdesc_ex && fep->ptp_clock)
3288 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3290 fep->rx_copybreak = COPYBREAK_DEFAULT;
3291 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3295 fec_enet_mii_remove(fep);
3300 regulator_disable(fep->reg_phy);
3302 fec_enet_clk_enable(ndev, false);
3305 of_node_put(phy_node);
3313 fec_drv_remove(struct platform_device *pdev)
3315 struct net_device *ndev = platform_get_drvdata(pdev);
3316 struct fec_enet_private *fep = netdev_priv(ndev);
3318 cancel_delayed_work_sync(&fep->time_keep);
3319 cancel_work_sync(&fep->tx_timeout_work);
3320 unregister_netdev(ndev);
3321 fec_enet_mii_remove(fep);
3323 regulator_disable(fep->reg_phy);
3325 ptp_clock_unregister(fep->ptp_clock);
3326 fec_enet_clk_enable(ndev, false);
3327 of_node_put(fep->phy_node);
3333 static int __maybe_unused fec_suspend(struct device *dev)
3335 struct net_device *ndev = dev_get_drvdata(dev);
3336 struct fec_enet_private *fep = netdev_priv(ndev);
3339 if (netif_running(ndev)) {
3340 phy_stop(fep->phy_dev);
3341 napi_disable(&fep->napi);
3342 netif_tx_lock_bh(ndev);
3343 netif_device_detach(ndev);
3344 netif_tx_unlock_bh(ndev);
3349 fec_enet_clk_enable(ndev, false);
3350 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3353 regulator_disable(fep->reg_phy);
3358 static int __maybe_unused fec_resume(struct device *dev)
3360 struct net_device *ndev = dev_get_drvdata(dev);
3361 struct fec_enet_private *fep = netdev_priv(ndev);
3365 ret = regulator_enable(fep->reg_phy);
3370 pinctrl_pm_select_default_state(&fep->pdev->dev);
3371 ret = fec_enet_clk_enable(ndev, true);
3376 if (netif_running(ndev)) {
3378 netif_tx_lock_bh(ndev);
3379 netif_device_attach(ndev);
3380 netif_tx_unlock_bh(ndev);
3381 napi_enable(&fep->napi);
3382 phy_start(fep->phy_dev);
3390 regulator_disable(fep->reg_phy);
3394 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3396 static struct platform_driver fec_driver = {
3398 .name = DRIVER_NAME,
3399 .owner = THIS_MODULE,
3401 .of_match_table = fec_dt_ids,
3403 .id_table = fec_devtype,
3405 .remove = fec_drv_remove,
3408 module_platform_driver(fec_driver);
3410 MODULE_ALIAS("platform:"DRIVER_NAME);
3411 MODULE_LICENSE("GPL");