drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82562G 10/100 Network Connection
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567V Gigabit Network Connection
  44  * 82567LM-2 Gigabit Network Connection
  45  * 82567LF-2 Gigabit Network Connection
  46  * 82567V-2 Gigabit Network Connection
  47  * 82567LF-3 Gigabit Network Connection
  48  * 82567LM-3 Gigabit Network Connection
  49  * 82567LM-4 Gigabit Network Connection
  50  * 82577LM Gigabit Network Connection
  51  * 82577LC Gigabit Network Connection
  52  * 82578DM Gigabit Network Connection
  53  * 82578DC Gigabit Network Connection
  54  * 82579LM Gigabit Network Connection
  55  * 82579V Gigabit Network Connection
  56  */
  57
  58 #include "e1000.h"
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  61 /* Offset 04h HSFSTS */
  62 union ich8_hws_flash_status {
  63         struct ich8_hsfsts {
  64                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  65                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  66                 u16 dael:1;     /* bit 2 Direct Access error Log */
  67                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  68                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  69                 u16 reserved1:2;        /* bit 13:6 Reserved */
  70                 u16 reserved2:6;        /* bit 13:6 Reserved */
  71                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  72                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  73         } hsf_status;
  74         u16 regval;
  75 };
  76
  77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  78 /* Offset 06h FLCTL */
  79 union ich8_hws_flash_ctrl {
  80         struct ich8_hsflctl {
  81                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  82                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  83                 u16 reserved:5; /* 7:3 Reserved  */
  84                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  85                 u16 flockdn:6;  /* 15:10 Reserved */
  86         } hsf_ctrl;
  87         u16 regval;
  88 };
  89
  90 /* ICH Flash Region Access Permissions */
  91 union ich8_hws_flash_regacc {
  92         struct ich8_flracc {
  93                 u32 grra:8;     /* 0:7 GbE region Read Access */
  94                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  95                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  96                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  97         } hsf_flregacc;
  98         u16 regval;
  99 };
 100
 101 /* ICH Flash Protected Region */
 102 union ich8_flash_protected_range {
 103         struct ich8_pr {
 104                 u32 base:13;    /* 0:12 Protected Range Base */
 105                 u32 reserved1:2;        /* 13:14 Reserved */
 106                 u32 rpe:1;      /* 15 Read Protection Enable */
 107                 u32 limit:13;   /* 16:28 Protected Range Limit */
 108                 u32 reserved2:2;        /* 29:30 Reserved */
 109                 u32 wpe:1;      /* 31 Write Protection Enable */
 110         } range;
 111         u32 regval;
 112 };
 113
 114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 118                                                 u32 offset, u8 byte);
 119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 120                                          u8 *data);
 121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 122                                          u16 *data);
 123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 124                                          u8 size, u16 *data);
 125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 146
 147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 148 {
 149         return readw(hw->flash_address + reg);
 150 }
 151
 152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 153 {
 154         return readl(hw->flash_address + reg);
 155 }
 156
 157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 158 {
 159         writew(val, hw->flash_address + reg);
 160 }
 161
 162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 163 {
 164         writel(val, hw->flash_address + reg);
 165 }
 166
 167 #define er16flash(reg)          __er16flash(hw, (reg))
 168 #define er32flash(reg)          __er32flash(hw, (reg))
 169 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 170 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 171
 172 /**
 173  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 174  *  @hw: pointer to the HW structure
 175  *
 176  *  Test access to the PHY registers by reading the PHY ID registers.  If
 177  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 178  *  otherwise assume the read PHY ID is correct if it is valid.
 179  *
 180  *  Assumes the sw/fw/hw semaphore is already acquired.
 181  **/
 182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 183 {
 184         u16 phy_reg = 0;
 185         u32 phy_id = 0;
 186         s32 ret_val;
 187         u16 retry_count;
 188
 189         for (retry_count = 0; retry_count < 2; retry_count++) {
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF))
 192                         continue;
 193                 phy_id = (u32)(phy_reg << 16);
 194
 195                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 196                 if (ret_val || (phy_reg == 0xFFFF)) {
 197                         phy_id = 0;
 198                         continue;
 199                 }
 200                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 201                 break;
 202         }
 203
 204         if (hw->phy.id) {
 205                 if (hw->phy.id == phy_id)
 206                         return true;
 207         } else if (phy_id) {
 208                 hw->phy.id = phy_id;
 209                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 210                 return true;
 211         }
 212
 213         /* In case the PHY needs to be in mdio slow mode,
 214          * set slow mode and try to get the PHY id again.
 215          */
 216         hw->phy.ops.release(hw);
 217         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 218         if (!ret_val)
 219                 ret_val = e1000e_get_phy_id(hw);
 220         hw->phy.ops.acquire(hw);
 221
 222         return !ret_val;
 223 }
 224
 225 /**
 226  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 227  *  @hw: pointer to the HW structure
 228  *
 229  *  Workarounds/flow necessary for PHY initialization during driver load
 230  *  and resume paths.
 231  **/
 232 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 233 {
 234         u32 mac_reg, fwsm = er32(FWSM);
 235         s32 ret_val;
 236         u16 phy_reg;
 237
 238         /* Gate automatic PHY configuration by hardware on managed and
 239          * non-managed 82579 and newer adapters.
 240          */
 241         e1000_gate_hw_phy_config_ich8lan(hw, true);
 242
 243         ret_val = hw->phy.ops.acquire(hw);
 244         if (ret_val) {
 245                 e_dbg("Failed to initialize PHY flow\n");
 246                 goto out;
 247         }
 248
 249         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 250          * inaccessible and resetting the PHY is not blocked, toggle the
 251          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 252          */
 253         switch (hw->mac.type) {
 254         case e1000_pch_lpt:
 255                 if (e1000_phy_is_accessible_pchlan(hw))
 256                         break;
 257
 258                 /* Before toggling LANPHYPC, see if PHY is accessible by
 259                  * forcing MAC to SMBus mode first.
 260                  */
 261                 mac_reg = er32(CTRL_EXT);
 262                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 263                 ew32(CTRL_EXT, mac_reg);
 264
 265                 /* fall-through */
 266         case e1000_pch2lan:
 267                 if (e1000_phy_is_accessible_pchlan(hw)) {
 268                         if (hw->mac.type == e1000_pch_lpt) {
 269                                 /* Unforce SMBus mode in PHY */
 270                                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 271                                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 272                                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 273
 274                                 /* Unforce SMBus mode in MAC */
 275                                 mac_reg = er32(CTRL_EXT);
 276                                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 277                                 ew32(CTRL_EXT, mac_reg);
 278                         }
 279                         break;
 280                 }
 281
 282                 /* fall-through */
 283         case e1000_pchlan:
 284                 if ((hw->mac.type == e1000_pchlan) &&
 285                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 286                         break;
 287
 288                 if (hw->phy.ops.check_reset_block(hw)) {
 289                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 290                         break;
 291                 }
 292
 293                 e_dbg("Toggling LANPHYPC\n");
 294
 295                 /* Set Phy Config Counter to 50msec */
 296                 mac_reg = er32(FEXTNVM3);
 297                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 298                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 299                 ew32(FEXTNVM3, mac_reg);
 300
 301                 if (hw->mac.type == e1000_pch_lpt) {
 302                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 303                          * So ensure that the MAC is also out of SMBus mode
 304                          */
 305                         mac_reg = er32(CTRL_EXT);
 306                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 307                         ew32(CTRL_EXT, mac_reg);
 308                 }
 309
 310                 /* Toggle LANPHYPC Value bit */
 311                 mac_reg = er32(CTRL);
 312                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 313                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 314                 ew32(CTRL, mac_reg);
 315                 e1e_flush();
 316                 usleep_range(10, 20);
 317                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 318                 ew32(CTRL, mac_reg);
 319                 e1e_flush();
 320                 if (hw->mac.type < e1000_pch_lpt) {
 321                         msleep(50);
 322                 } else {
 323                         u16 count = 20;
 324                         do {
 325                                 usleep_range(5000, 10000);
 326                         } while (!(er32(CTRL_EXT) &
 327                                    E1000_CTRL_EXT_LPCD) && count--);
 328                 }
 329                 break;
 330         default:
 331                 break;
 332         }
 333
 334         hw->phy.ops.release(hw);
 335
 336         /* Reset the PHY before any access to it.  Doing so, ensures
 337          * that the PHY is in a known good state before we read/write
 338          * PHY registers.  The generic reset is sufficient here,
 339          * because we haven't determined the PHY type yet.
 340          */
 341         ret_val = e1000e_phy_hw_reset_generic(hw);
 342
 343 out:
 344         /* Ungate automatic PHY configuration on non-managed 82579 */
 345         if ((hw->mac.type == e1000_pch2lan) &&
 346             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 347                 usleep_range(10000, 20000);
 348                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 349         }
 350
 351         return ret_val;
 352 }
 353
 354 /**
 355  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 356  *  @hw: pointer to the HW structure
 357  *
 358  *  Initialize family-specific PHY parameters and function pointers.
 359  **/
 360 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 361 {
 362         struct e1000_phy_info *phy = &hw->phy;
 363         s32 ret_val;
 364
 365         phy->addr = 1;
 366         phy->reset_delay_us = 100;
 367
 368         phy->ops.set_page = e1000_set_page_igp;
 369         phy->ops.read_reg = e1000_read_phy_reg_hv;
 370         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 371         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 372         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 373         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 374         phy->ops.write_reg = e1000_write_phy_reg_hv;
 375         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 376         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 377         phy->ops.power_up = e1000_power_up_phy_copper;
 378         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 379         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 380
 381         phy->id = e1000_phy_unknown;
 382
 383         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 384         if (ret_val)
 385                 return ret_val;
 386
 387         if (phy->id == e1000_phy_unknown)
 388                 switch (hw->mac.type) {
 389                 default:
 390                         ret_val = e1000e_get_phy_id(hw);
 391                         if (ret_val)
 392                                 return ret_val;
 393                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 394                                 break;
 395                         /* fall-through */
 396                 case e1000_pch2lan:
 397                 case e1000_pch_lpt:
 398                         /* In case the PHY needs to be in mdio slow mode,
 399                          * set slow mode and try to get the PHY id again.
 400                          */
 401                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 402                         if (ret_val)
 403                                 return ret_val;
 404                         ret_val = e1000e_get_phy_id(hw);
 405                         if (ret_val)
 406                                 return ret_val;
 407                         break;
 408                 }
 409         phy->type = e1000e_get_phy_type_from_id(phy->id);
 410
 411         switch (phy->type) {
 412         case e1000_phy_82577:
 413         case e1000_phy_82579:
 414         case e1000_phy_i217:
 415                 phy->ops.check_polarity = e1000_check_polarity_82577;
 416                 phy->ops.force_speed_duplex =
 417                     e1000_phy_force_speed_duplex_82577;
 418                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 419                 phy->ops.get_info = e1000_get_phy_info_82577;
 420                 phy->ops.commit = e1000e_phy_sw_reset;
 421                 break;
 422         case e1000_phy_82578:
 423                 phy->ops.check_polarity = e1000_check_polarity_m88;
 424                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 425                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 426                 phy->ops.get_info = e1000e_get_phy_info_m88;
 427                 break;
 428         default:
 429                 ret_val = -E1000_ERR_PHY;
 430                 break;
 431         }
 432
 433         return ret_val;
 434 }
 435
 436 /**
 437  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 438  *  @hw: pointer to the HW structure
 439  *
 440  *  Initialize family-specific PHY parameters and function pointers.
 441  **/
 442 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 443 {
 444         struct e1000_phy_info *phy = &hw->phy;
 445         s32 ret_val;
 446         u16 i = 0;
 447
 448         phy->addr = 1;
 449         phy->reset_delay_us = 100;
 450
 451         phy->ops.power_up = e1000_power_up_phy_copper;
 452         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 453
 454         /* We may need to do this twice - once for IGP and if that fails,
 455          * we'll set BM func pointers and try again
 456          */
 457         ret_val = e1000e_determine_phy_address(hw);
 458         if (ret_val) {
 459                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 460                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 461                 ret_val = e1000e_determine_phy_address(hw);
 462                 if (ret_val) {
 463                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 464                         return ret_val;
 465                 }
 466         }
 467
 468         phy->id = 0;
 469         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 470                (i++ < 100)) {
 471                 usleep_range(1000, 2000);
 472                 ret_val = e1000e_get_phy_id(hw);
 473                 if (ret_val)
 474                         return ret_val;
 475         }
 476
 477         /* Verify phy id */
 478         switch (phy->id) {
 479         case IGP03E1000_E_PHY_ID:
 480                 phy->type = e1000_phy_igp_3;
 481                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 482                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 483                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 484                 phy->ops.get_info = e1000e_get_phy_info_igp;
 485                 phy->ops.check_polarity = e1000_check_polarity_igp;
 486                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 487                 break;
 488         case IFE_E_PHY_ID:
 489         case IFE_PLUS_E_PHY_ID:
 490         case IFE_C_E_PHY_ID:
 491                 phy->type = e1000_phy_ife;
 492                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 493                 phy->ops.get_info = e1000_get_phy_info_ife;
 494                 phy->ops.check_polarity = e1000_check_polarity_ife;
 495                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 496                 break;
 497         case BME1000_E_PHY_ID:
 498                 phy->type = e1000_phy_bm;
 499                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 500                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 501                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 502                 phy->ops.commit = e1000e_phy_sw_reset;
 503                 phy->ops.get_info = e1000e_get_phy_info_m88;
 504                 phy->ops.check_polarity = e1000_check_polarity_m88;
 505                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 506                 break;
 507         default:
 508                 return -E1000_ERR_PHY;
 509                 break;
 510         }
 511
 512         return 0;
 513 }
 514
 515 /**
 516  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 517  *  @hw: pointer to the HW structure
 518  *
 519  *  Initialize family-specific NVM parameters and function
 520  *  pointers.
 521  **/
 522 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 523 {
 524         struct e1000_nvm_info *nvm = &hw->nvm;
 525         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 526         u32 gfpreg, sector_base_addr, sector_end_addr;
 527         u16 i;
 528
 529         /* Can't read flash registers if the register set isn't mapped. */
 530         if (!hw->flash_address) {
 531                 e_dbg("ERROR: Flash registers not mapped\n");
 532                 return -E1000_ERR_CONFIG;
 533         }
 534
 535         nvm->type = e1000_nvm_flash_sw;
 536
 537         gfpreg = er32flash(ICH_FLASH_GFPREG);
 538
 539         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 540          * Add 1 to sector_end_addr since this sector is included in
 541          * the overall size.
 542          */
 543         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 544         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 545
 546         /* flash_base_addr is byte-aligned */
 547         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 548
 549         /* find total size of the NVM, then cut in half since the total
 550          * size represents two separate NVM banks.
 551          */
 552         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 553                                 << FLASH_SECTOR_ADDR_SHIFT);
 554         nvm->flash_bank_size /= 2;
 555         /* Adjust to word count */
 556         nvm->flash_bank_size /= sizeof(u16);
 557
 558         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 559
 560         /* Clear shadow ram */
 561         for (i = 0; i < nvm->word_size; i++) {
 562                 dev_spec->shadow_ram[i].modified = false;
 563                 dev_spec->shadow_ram[i].value = 0xFFFF;
 564         }
 565
 566         return 0;
 567 }
 568
 569 /**
 570  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 571  *  @hw: pointer to the HW structure
 572  *
 573  *  Initialize family-specific MAC parameters and function
 574  *  pointers.
 575  **/
 576 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 577 {
 578         struct e1000_mac_info *mac = &hw->mac;
 579
 580         /* Set media type function pointer */
 581         hw->phy.media_type = e1000_media_type_copper;
 582
 583         /* Set mta register count */
 584         mac->mta_reg_count = 32;
 585         /* Set rar entry count */
 586         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 587         if (mac->type == e1000_ich8lan)
 588                 mac->rar_entry_count--;
 589         /* FWSM register */
 590         mac->has_fwsm = true;
 591         /* ARC subsystem not supported */
 592         mac->arc_subsystem_valid = false;
 593         /* Adaptive IFS supported */
 594         mac->adaptive_ifs = true;
 595
 596         /* LED and other operations */
 597         switch (mac->type) {
 598         case e1000_ich8lan:
 599         case e1000_ich9lan:
 600         case e1000_ich10lan:
 601                 /* check management mode */
 602                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 603                 /* ID LED init */
 604                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 605                 /* blink LED */
 606                 mac->ops.blink_led = e1000e_blink_led_generic;
 607                 /* setup LED */
 608                 mac->ops.setup_led = e1000e_setup_led_generic;
 609                 /* cleanup LED */
 610                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 611                 /* turn on/off LED */
 612                 mac->ops.led_on = e1000_led_on_ich8lan;
 613                 mac->ops.led_off = e1000_led_off_ich8lan;
 614                 break;
 615         case e1000_pch2lan:
 616                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 617                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 618                 /* fall-through */
 619         case e1000_pch_lpt:
 620         case e1000_pchlan:
 621                 /* check management mode */
 622                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 623                 /* ID LED init */
 624                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 625                 /* setup LED */
 626                 mac->ops.setup_led = e1000_setup_led_pchlan;
 627                 /* cleanup LED */
 628                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 629                 /* turn on/off LED */
 630                 mac->ops.led_on = e1000_led_on_pchlan;
 631                 mac->ops.led_off = e1000_led_off_pchlan;
 632                 break;
 633         default:
 634                 break;
 635         }
 636
 637         if (mac->type == e1000_pch_lpt) {
 638                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 639                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 640                 mac->ops.setup_physical_interface =
 641                     e1000_setup_copper_link_pch_lpt;
 642         }
 643
 644         /* Enable PCS Lock-loss workaround for ICH8 */
 645         if (mac->type == e1000_ich8lan)
 646                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 647
 648         return 0;
 649 }
 650
 651 /**
 652  *  __e1000_access_emi_reg_locked - Read/write EMI register
 653  *  @hw: pointer to the HW structure
 654  *  @addr: EMI address to program
 655  *  @data: pointer to value to read/write from/to the EMI address
 656  *  @read: boolean flag to indicate read or write
 657  *
 658  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 659  **/
 660 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 661                                          u16 *data, bool read)
 662 {
 663         s32 ret_val;
 664
 665         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 666         if (ret_val)
 667                 return ret_val;
 668
 669         if (read)
 670                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 671         else
 672                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 673
 674         return ret_val;
 675 }
 676
 677 /**
 678  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 679  *  @hw: pointer to the HW structure
 680  *  @addr: EMI address to program
 681  *  @data: value to be read from the EMI address
 682  *
 683  *  Assumes the SW/FW/HW Semaphore is already acquired.
 684  **/
 685 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 686 {
 687         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 688 }
 689
 690 /**
 691  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 692  *  @hw: pointer to the HW structure
 693  *  @addr: EMI address to program
 694  *  @data: value to be written to the EMI address
 695  *
 696  *  Assumes the SW/FW/HW Semaphore is already acquired.
 697  **/
 698 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 699 {
 700         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 701 }
 702
 703 /**
 704  *  e1000_set_eee_pchlan - Enable/disable EEE support
 705  *  @hw: pointer to the HW structure
 706  *
 707  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 708  *  the link and the EEE capabilities of the link partner.  The LPI Control
 709  *  register bits will remain set only if/when link is up.
 710  **/
 711 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 712 {
 713         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 714         s32 ret_val;
 715         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 716
 717         switch (hw->phy.type) {
 718         case e1000_phy_82579:
 719                 lpa = I82579_EEE_LP_ABILITY;
 720                 pcs_status = I82579_EEE_PCS_STATUS;
 721                 adv_addr = I82579_EEE_ADVERTISEMENT;
 722                 break;
 723         case e1000_phy_i217:
 724                 lpa = I217_EEE_LP_ABILITY;
 725                 pcs_status = I217_EEE_PCS_STATUS;
 726                 adv_addr = I217_EEE_ADVERTISEMENT;
 727                 break;
 728         default:
 729                 return 0;
 730         }
 731
 732         ret_val = hw->phy.ops.acquire(hw);
 733         if (ret_val)
 734                 return ret_val;
 735
 736         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 737         if (ret_val)
 738                 goto release;
 739
 740         /* Clear bits that enable EEE in various speeds */
 741         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 742
 743         /* Enable EEE if not disabled by user */
 744         if (!dev_spec->eee_disable) {
 745                 /* Save off link partner's EEE ability */
 746                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 747                                                     &dev_spec->eee_lp_ability);
 748                 if (ret_val)
 749                         goto release;
 750
 751                 /* Read EEE advertisement */
 752                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 753                 if (ret_val)
 754                         goto release;
 755
 756                 /* Enable EEE only for speeds in which the link partner is
 757                  * EEE capable and for which we advertise EEE.
 758                  */
 759                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 760                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 761
 762                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 763                         e1e_rphy_locked(hw, MII_LPA, &data);
 764                         if (data & LPA_100FULL)
 765                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 766                         else
 767                                 /* EEE is not supported in 100Half, so ignore
 768                                  * partner's EEE in 100 ability if full-duplex
 769                                  * is not advertised.
 770                                  */
 771                                 dev_spec->eee_lp_ability &=
 772                                     ~I82579_EEE_100_SUPPORTED;
 773                 }
 774         }
 775
 776         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 777         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 778         if (ret_val)
 779                 goto release;
 780
 781         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 782 release:
 783         hw->phy.ops.release(hw);
 784
 785         return ret_val;
 786 }
 787
 788 /**
 789  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 790  *  @hw:   pointer to the HW structure
 791  *  @link: link up bool flag
 792  *
 793  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 794  *  preventing further DMA write requests.  Workaround the issue by disabling
 795  *  the de-assertion of the clock request when in 1Gpbs mode.
 796  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 797  *  speeds in order to avoid Tx hangs.
 798  **/
 799 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 800 {
 801         u32 fextnvm6 = er32(FEXTNVM6);
 802         u32 status = er32(STATUS);
 803         s32 ret_val = 0;
 804         u16 reg;
 805
 806         if (link && (status & E1000_STATUS_SPEED_1000)) {
 807                 ret_val = hw->phy.ops.acquire(hw);
 808                 if (ret_val)
 809                         return ret_val;
 810
 811                 ret_val =
 812                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 813                                                 &reg);
 814                 if (ret_val)
 815                         goto release;
 816
 817                 ret_val =
 818                     e1000e_write_kmrn_reg_locked(hw,
 819                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 820                                                  reg &
 821                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 822                 if (ret_val)
 823                         goto release;
 824
 825                 usleep_range(10, 20);
 826
 827                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 828
 829                 ret_val =
 830                     e1000e_write_kmrn_reg_locked(hw,
 831                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 832                                                  reg);
 833 release:
 834                 hw->phy.ops.release(hw);
 835         } else {
 836                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 837                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 838
 839                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 840                               (status & E1000_STATUS_FD)))
 841                         goto update_fextnvm6;
 842
 843                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 844                 if (ret_val)
 845                         return ret_val;
 846
 847                 /* Clear link status transmit timeout */
 848                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 849
 850                 if (status & E1000_STATUS_SPEED_100) {
 851                         /* Set inband Tx timeout to 5x10us for 100Half */
 852                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 853
 854                         /* Do not extend the K1 entry latency for 100Half */
 855                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 856                 } else {
 857                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 858                         reg |= 50 <<
 859                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 860
 861                         /* Extend the K1 entry latency for 10 Mbps */
 862                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 863                 }
 864
 865                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 866                 if (ret_val)
 867                         return ret_val;
 868
 869 update_fextnvm6:
 870                 ew32(FEXTNVM6, fextnvm6);
 871         }
 872
 873         return ret_val;
 874 }
 875
 876 /**
 877  *  e1000_platform_pm_pch_lpt - Set platform power management values
 878  *  @hw: pointer to the HW structure
 879  *  @link: bool indicating link status
 880  *
 881  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 882  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 883  *  when link is up (which must not exceed the maximum latency supported
 884  *  by the platform), otherwise specify there is no LTR requirement.
 885  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 886  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 887  *  Capability register set, on this device LTR is set by writing the
 888  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 889  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 890  *  message to the PMC.
 891  **/
 892 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 893 {
 894         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 895             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 896         u16 lat_enc = 0;        /* latency encoded */
 897
 898         if (link) {
 899                 u16 speed, duplex, scale = 0;
 900                 u16 max_snoop, max_nosnoop;
 901                 u16 max_ltr_enc;        /* max LTR latency encoded */
 902                 s64 lat_ns;     /* latency (ns) */
 903                 s64 value;
 904                 u32 rxa;
 905
 906                 if (!hw->adapter->max_frame_size) {
 907                         e_dbg("max_frame_size not set.\n");
 908                         return -E1000_ERR_CONFIG;
 909                 }
 910
 911                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 912                 if (!speed) {
 913                         e_dbg("Speed not set.\n");
 914                         return -E1000_ERR_CONFIG;
 915                 }
 916
 917                 /* Rx Packet Buffer Allocation size (KB) */
 918                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
 919
 920                 /* Determine the maximum latency tolerated by the device.
 921                  *
 922                  * Per the PCIe spec, the tolerated latencies are encoded as
 923                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
 924                  * a 10-bit value (0-1023) to provide a range from 1 ns to
 925                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
 926                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
 927                  */
 928                 lat_ns = ((s64)rxa * 1024 -
 929                           (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
 930                 if (lat_ns < 0)
 931                         lat_ns = 0;
 932                 else
 933                         do_div(lat_ns, speed);
 934
 935                 value = lat_ns;
 936                 while (value > PCI_LTR_VALUE_MASK) {
 937                         scale++;
 938                         value = DIV_ROUND_UP(value, (1 << 5));
 939                 }
 940                 if (scale > E1000_LTRV_SCALE_MAX) {
 941                         e_dbg("Invalid LTR latency scale %d\n", scale);
 942                         return -E1000_ERR_CONFIG;
 943                 }
 944                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
 945
 946                 /* Determine the maximum latency tolerated by the platform */
 947                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
 948                                      &max_snoop);
 949                 pci_read_config_word(hw->adapter->pdev,
 950                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
 951                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
 952
 953                 if (lat_enc > max_ltr_enc)
 954                         lat_enc = max_ltr_enc;
 955         }
 956
 957         /* Set Snoop and No-Snoop latencies the same */
 958         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
 959         ew32(LTRV, reg);
 960
 961         return 0;
 962 }
 963
 964 /**
 965  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 966  *  @hw: pointer to the HW structure
 967  *
 968  *  Checks to see of the link status of the hardware has changed.  If a
 969  *  change in link status has been detected, then we read the PHY registers
 970  *  to get the current speed/duplex if link exists.
 971  **/
 972 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 973 {
 974         struct e1000_mac_info *mac = &hw->mac;
 975         s32 ret_val;
 976         bool link;
 977         u16 phy_reg;
 978
 979         /* We only want to go out to the PHY registers to see if Auto-Neg
 980          * has completed and/or if our link status has changed.  The
 981          * get_link_status flag is set upon receiving a Link Status
 982          * Change or Rx Sequence Error interrupt.
 983          */
 984         if (!mac->get_link_status)
 985                 return 0;
 986
 987         /* First we want to see if the MII Status Register reports
 988          * link.  If so, then we want to get the current speed/duplex
 989          * of the PHY.
 990          */
 991         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 992         if (ret_val)
 993                 return ret_val;
 994
 995         if (hw->mac.type == e1000_pchlan) {
 996                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 997                 if (ret_val)
 998                         return ret_val;
 999         }
1000
1001         /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1002          * aggressive resulting in many collisions. To avoid this, increase
1003          * the IPG and reduce Rx latency in the PHY.
1004          */
1005         if ((hw->mac.type == e1000_pch2lan) && link) {
1006                 u32 reg;
1007                 reg = er32(STATUS);
1008                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1009                         reg = er32(TIPG);
1010                         reg &= ~E1000_TIPG_IPGT_MASK;
1011                         reg |= 0xFF;
1012                         ew32(TIPG, reg);
1013
1014                         /* Reduce Rx latency in analog PHY */
1015                         ret_val = hw->phy.ops.acquire(hw);
1016                         if (ret_val)
1017                                 return ret_val;
1018
1019                         ret_val =
1020                             e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1021
1022                         hw->phy.ops.release(hw);
1023
1024                         if (ret_val)
1025                                 return ret_val;
1026                 }
1027         }
1028
1029         /* Work-around I218 hang issue */
1030         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1031             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1032             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1033             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1034                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1035                 if (ret_val)
1036                         return ret_val;
1037         }
1038
1039         if (hw->mac.type == e1000_pch_lpt) {
1040                 /* Set platform power management values for
1041                  * Latency Tolerance Reporting (LTR)
1042                  */
1043                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1044                 if (ret_val)
1045                         return ret_val;
1046         }
1047
1048         /* Clear link partner's EEE ability */
1049         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1050
1051         if (!link)
1052                 return 0;       /* No link detected */
1053
1054         mac->get_link_status = false;
1055
1056         switch (hw->mac.type) {
1057         case e1000_pch2lan:
1058                 ret_val = e1000_k1_workaround_lv(hw);
1059                 if (ret_val)
1060                         return ret_val;
1061                 /* fall-thru */
1062         case e1000_pchlan:
1063                 if (hw->phy.type == e1000_phy_82578) {
1064                         ret_val = e1000_link_stall_workaround_hv(hw);
1065                         if (ret_val)
1066                                 return ret_val;
1067                 }
1068
1069                 /* Workaround for PCHx parts in half-duplex:
1070                  * Set the number of preambles removed from the packet
1071                  * when it is passed from the PHY to the MAC to prevent
1072                  * the MAC from misinterpreting the packet type.
1073                  */
1074                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1075                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1076
1077                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1078                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1079
1080                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1081                 break;
1082         default:
1083                 break;
1084         }
1085
1086         /* Check if there was DownShift, must be checked
1087          * immediately after link-up
1088          */
1089         e1000e_check_downshift(hw);
1090
1091         /* Enable/Disable EEE after link up */
1092         ret_val = e1000_set_eee_pchlan(hw);
1093         if (ret_val)
1094                 return ret_val;
1095
1096         /* If we are forcing speed/duplex, then we simply return since
1097          * we have already determined whether we have link or not.
1098          */
1099         if (!mac->autoneg)
1100                 return -E1000_ERR_CONFIG;
1101
1102         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1103          * of MAC speed/duplex configuration.  So we only need to
1104          * configure Collision Distance in the MAC.
1105          */
1106         mac->ops.config_collision_dist(hw);
1107
1108         /* Configure Flow Control now that Auto-Neg has completed.
1109          * First, we need to restore the desired flow control
1110          * settings because we may have had to re-autoneg with a
1111          * different link partner.
1112          */
1113         ret_val = e1000e_config_fc_after_link_up(hw);
1114         if (ret_val)
1115                 e_dbg("Error configuring flow control\n");
1116
1117         return ret_val;
1118 }
1119
1120 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1121 {
1122         struct e1000_hw *hw = &adapter->hw;
1123         s32 rc;
1124
1125         rc = e1000_init_mac_params_ich8lan(hw);
1126         if (rc)
1127                 return rc;
1128
1129         rc = e1000_init_nvm_params_ich8lan(hw);
1130         if (rc)
1131                 return rc;
1132
1133         switch (hw->mac.type) {
1134         case e1000_ich8lan:
1135         case e1000_ich9lan:
1136         case e1000_ich10lan:
1137                 rc = e1000_init_phy_params_ich8lan(hw);
1138                 break;
1139         case e1000_pchlan:
1140         case e1000_pch2lan:
1141         case e1000_pch_lpt:
1142                 rc = e1000_init_phy_params_pchlan(hw);
1143                 break;
1144         default:
1145                 break;
1146         }
1147         if (rc)
1148                 return rc;
1149
1150         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1151          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1152          */
1153         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1154             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1155              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1156                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1157                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1158
1159                 hw->mac.ops.blink_led = NULL;
1160         }
1161
1162         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1163             (adapter->hw.phy.type != e1000_phy_ife))
1164                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1165
1166         /* Enable workaround for 82579 w/ ME enabled */
1167         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1168             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1169                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1170
1171         return 0;
1172 }
1173
1174 static DEFINE_MUTEX(nvm_mutex);
1175
1176 /**
1177  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1178  *  @hw: pointer to the HW structure
1179  *
1180  *  Acquires the mutex for performing NVM operations.
1181  **/
1182 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1183 {
1184         mutex_lock(&nvm_mutex);
1185
1186         return 0;
1187 }
1188
1189 /**
1190  *  e1000_release_nvm_ich8lan - Release NVM mutex
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Releases the mutex used while performing NVM operations.
1194  **/
1195 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1196 {
1197         mutex_unlock(&nvm_mutex);
1198 }
1199
1200 /**
1201  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  Acquires the software control flag for performing PHY and select
1205  *  MAC CSR accesses.
1206  **/
1207 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1208 {
1209         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1210         s32 ret_val = 0;
1211
1212         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1213                              &hw->adapter->state)) {
1214                 e_dbg("contention for Phy access\n");
1215                 return -E1000_ERR_PHY;
1216         }
1217
1218         while (timeout) {
1219                 extcnf_ctrl = er32(EXTCNF_CTRL);
1220                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1221                         break;
1222
1223                 mdelay(1);
1224                 timeout--;
1225         }
1226
1227         if (!timeout) {
1228                 e_dbg("SW has already locked the resource.\n");
1229                 ret_val = -E1000_ERR_CONFIG;
1230                 goto out;
1231         }
1232
1233         timeout = SW_FLAG_TIMEOUT;
1234
1235         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1236         ew32(EXTCNF_CTRL, extcnf_ctrl);
1237
1238         while (timeout) {
1239                 extcnf_ctrl = er32(EXTCNF_CTRL);
1240                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1241                         break;
1242
1243                 mdelay(1);
1244                 timeout--;
1245         }
1246
1247         if (!timeout) {
1248                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1249                       er32(FWSM), extcnf_ctrl);
1250                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1251                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1252                 ret_val = -E1000_ERR_CONFIG;
1253                 goto out;
1254         }
1255
1256 out:
1257         if (ret_val)
1258                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1259
1260         return ret_val;
1261 }
1262
1263 /**
1264  *  e1000_release_swflag_ich8lan - Release software control flag
1265  *  @hw: pointer to the HW structure
1266  *
1267  *  Releases the software control flag for performing PHY and select
1268  *  MAC CSR accesses.
1269  **/
1270 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1271 {
1272         u32 extcnf_ctrl;
1273
1274         extcnf_ctrl = er32(EXTCNF_CTRL);
1275
1276         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1277                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1278                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1279         } else {
1280                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1281         }
1282
1283         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1284 }
1285
1286 /**
1287  *  e1000_check_mng_mode_ich8lan - Checks management mode
1288  *  @hw: pointer to the HW structure
1289  *
1290  *  This checks if the adapter has any manageability enabled.
1291  *  This is a function pointer entry point only called by read/write
1292  *  routines for the PHY and NVM parts.
1293  **/
1294 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1295 {
1296         u32 fwsm;
1297
1298         fwsm = er32(FWSM);
1299         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1300                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1301                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1302 }
1303
1304 /**
1305  *  e1000_check_mng_mode_pchlan - Checks management mode
1306  *  @hw: pointer to the HW structure
1307  *
1308  *  This checks if the adapter has iAMT enabled.
1309  *  This is a function pointer entry point only called by read/write
1310  *  routines for the PHY and NVM parts.
1311  **/
1312 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1313 {
1314         u32 fwsm;
1315
1316         fwsm = er32(FWSM);
1317         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1318             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1319 }
1320
1321 /**
1322  *  e1000_rar_set_pch2lan - Set receive address register
1323  *  @hw: pointer to the HW structure
1324  *  @addr: pointer to the receive address
1325  *  @index: receive address array register
1326  *
1327  *  Sets the receive address array register at index to the address passed
1328  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1329  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1330  *  Use SHRA[0-3] in place of those reserved for ME.
1331  **/
1332 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1333 {
1334         u32 rar_low, rar_high;
1335
1336         /* HW expects these in little endian so we reverse the byte order
1337          * from network order (big endian) to little endian
1338          */
1339         rar_low = ((u32)addr[0] |
1340                    ((u32)addr[1] << 8) |
1341                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1342
1343         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1344
1345         /* If MAC address zero, no need to set the AV bit */
1346         if (rar_low || rar_high)
1347                 rar_high |= E1000_RAH_AV;
1348
1349         if (index == 0) {
1350                 ew32(RAL(index), rar_low);
1351                 e1e_flush();
1352                 ew32(RAH(index), rar_high);
1353                 e1e_flush();
1354                 return;
1355         }
1356
1357         if (index < hw->mac.rar_entry_count) {
1358                 s32 ret_val;
1359
1360                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1361                 if (ret_val)
1362                         goto out;
1363
1364                 ew32(SHRAL(index - 1), rar_low);
1365                 e1e_flush();
1366                 ew32(SHRAH(index - 1), rar_high);
1367                 e1e_flush();
1368
1369                 e1000_release_swflag_ich8lan(hw);
1370
1371                 /* verify the register updates */
1372                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1373                     (er32(SHRAH(index - 1)) == rar_high))
1374                         return;
1375
1376                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1377                       (index - 1), er32(FWSM));
1378         }
1379
1380 out:
1381         e_dbg("Failed to write receive address at index %d\n", index);
1382 }
1383
1384 /**
1385  *  e1000_rar_set_pch_lpt - Set receive address registers
1386  *  @hw: pointer to the HW structure
1387  *  @addr: pointer to the receive address
1388  *  @index: receive address array register
1389  *
1390  *  Sets the receive address register array at index to the address passed
1391  *  in by addr. For LPT, RAR[0] is the base address register that is to
1392  *  contain the MAC address. SHRA[0-10] are the shared receive address
1393  *  registers that are shared between the Host and manageability engine (ME).
1394  **/
1395 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1396 {
1397         u32 rar_low, rar_high;
1398         u32 wlock_mac;
1399
1400         /* HW expects these in little endian so we reverse the byte order
1401          * from network order (big endian) to little endian
1402          */
1403         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1404                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1405
1406         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1407
1408         /* If MAC address zero, no need to set the AV bit */
1409         if (rar_low || rar_high)
1410                 rar_high |= E1000_RAH_AV;
1411
1412         if (index == 0) {
1413                 ew32(RAL(index), rar_low);
1414                 e1e_flush();
1415                 ew32(RAH(index), rar_high);
1416                 e1e_flush();
1417                 return;
1418         }
1419
1420         /* The manageability engine (ME) can lock certain SHRAR registers that
1421          * it is using - those registers are unavailable for use.
1422          */
1423         if (index < hw->mac.rar_entry_count) {
1424                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1425                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1426
1427                 /* Check if all SHRAR registers are locked */
1428                 if (wlock_mac == 1)
1429                         goto out;
1430
1431                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1432                         s32 ret_val;
1433
1434                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1435
1436                         if (ret_val)
1437                                 goto out;
1438
1439                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1440                         e1e_flush();
1441                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1442                         e1e_flush();
1443
1444                         e1000_release_swflag_ich8lan(hw);
1445
1446                         /* verify the register updates */
1447                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1448                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1449                                 return;
1450                 }
1451         }
1452
1453 out:
1454         e_dbg("Failed to write receive address at index %d\n", index);
1455 }
1456
1457 /**
1458  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1459  *  @hw: pointer to the HW structure
1460  *
1461  *  Checks if firmware is blocking the reset of the PHY.
1462  *  This is a function pointer entry point only called by
1463  *  reset routines.
1464  **/
1465 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1466 {
1467         u32 fwsm;
1468
1469         fwsm = er32(FWSM);
1470
1471         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1472 }
1473
1474 /**
1475  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1476  *  @hw: pointer to the HW structure
1477  *
1478  *  Assumes semaphore already acquired.
1479  *
1480  **/
1481 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1482 {
1483         u16 phy_data;
1484         u32 strap = er32(STRAP);
1485         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1486             E1000_STRAP_SMT_FREQ_SHIFT;
1487         s32 ret_val;
1488
1489         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1490
1491         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1492         if (ret_val)
1493                 return ret_val;
1494
1495         phy_data &= ~HV_SMB_ADDR_MASK;
1496         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1497         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1498
1499         if (hw->phy.type == e1000_phy_i217) {
1500                 /* Restore SMBus frequency */
1501                 if (freq--) {
1502                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1503                         phy_data |= (freq & (1 << 0)) <<
1504                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1505                         phy_data |= (freq & (1 << 1)) <<
1506                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1507                 } else {
1508                         e_dbg("Unsupported SMB frequency in PHY\n");
1509                 }
1510         }
1511
1512         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1513 }
1514
1515 /**
1516  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1517  *  @hw:   pointer to the HW structure
1518  *
1519  *  SW should configure the LCD from the NVM extended configuration region
1520  *  as a workaround for certain parts.
1521  **/
1522 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1523 {
1524         struct e1000_phy_info *phy = &hw->phy;
1525         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1526         s32 ret_val = 0;
1527         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1528
1529         /* Initialize the PHY from the NVM on ICH platforms.  This
1530          * is needed due to an issue where the NVM configuration is
1531          * not properly autoloaded after power transitions.
1532          * Therefore, after each PHY reset, we will load the
1533          * configuration data out of the NVM manually.
1534          */
1535         switch (hw->mac.type) {
1536         case e1000_ich8lan:
1537                 if (phy->type != e1000_phy_igp_3)
1538                         return ret_val;
1539
1540                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1541                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1542                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1543                         break;
1544                 }
1545                 /* Fall-thru */
1546         case e1000_pchlan:
1547         case e1000_pch2lan:
1548         case e1000_pch_lpt:
1549                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1550                 break;
1551         default:
1552                 return ret_val;
1553         }
1554
1555         ret_val = hw->phy.ops.acquire(hw);
1556         if (ret_val)
1557                 return ret_val;
1558
1559         data = er32(FEXTNVM);
1560         if (!(data & sw_cfg_mask))
1561                 goto release;
1562
1563         /* Make sure HW does not configure LCD from PHY
1564          * extended configuration before SW configuration
1565          */
1566         data = er32(EXTCNF_CTRL);
1567         if ((hw->mac.type < e1000_pch2lan) &&
1568             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1569                 goto release;
1570
1571         cnf_size = er32(EXTCNF_SIZE);
1572         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1573         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1574         if (!cnf_size)
1575                 goto release;
1576
1577         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1578         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1579
1580         if (((hw->mac.type == e1000_pchlan) &&
1581              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1582             (hw->mac.type > e1000_pchlan)) {
1583                 /* HW configures the SMBus address and LEDs when the
1584                  * OEM and LCD Write Enable bits are set in the NVM.
1585                  * When both NVM bits are cleared, SW will configure
1586                  * them instead.
1587                  */
1588                 ret_val = e1000_write_smbus_addr(hw);
1589                 if (ret_val)
1590                         goto release;
1591
1592                 data = er32(LEDCTL);
1593                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1594                                                         (u16)data);
1595                 if (ret_val)
1596                         goto release;
1597         }
1598
1599         /* Configure LCD from extended configuration region. */
1600
1601         /* cnf_base_addr is in DWORD */
1602         word_addr = (u16)(cnf_base_addr << 1);
1603
1604         for (i = 0; i < cnf_size; i++) {
1605                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1606                 if (ret_val)
1607                         goto release;
1608
1609                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1610                                          1, &reg_addr);
1611                 if (ret_val)
1612                         goto release;
1613
1614                 /* Save off the PHY page for future writes. */
1615                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1616                         phy_page = reg_data;
1617                         continue;
1618                 }
1619
1620                 reg_addr &= PHY_REG_MASK;
1621                 reg_addr |= phy_page;
1622
1623                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1624                 if (ret_val)
1625                         goto release;
1626         }
1627
1628 release:
1629         hw->phy.ops.release(hw);
1630         return ret_val;
1631 }
1632
1633 /**
1634  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1635  *  @hw:   pointer to the HW structure
1636  *  @link: link up bool flag
1637  *
1638  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1639  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1640  *  If link is down, the function will restore the default K1 setting located
1641  *  in the NVM.
1642  **/
1643 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1644 {
1645         s32 ret_val = 0;
1646         u16 status_reg = 0;
1647         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1648
1649         if (hw->mac.type != e1000_pchlan)
1650                 return 0;
1651
1652         /* Wrap the whole flow with the sw flag */
1653         ret_val = hw->phy.ops.acquire(hw);
1654         if (ret_val)
1655                 return ret_val;
1656
1657         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1658         if (link) {
1659                 if (hw->phy.type == e1000_phy_82578) {
1660                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1661                                                   &status_reg);
1662                         if (ret_val)
1663                                 goto release;
1664
1665                         status_reg &= (BM_CS_STATUS_LINK_UP |
1666                                        BM_CS_STATUS_RESOLVED |
1667                                        BM_CS_STATUS_SPEED_MASK);
1668
1669                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1670                                            BM_CS_STATUS_RESOLVED |
1671                                            BM_CS_STATUS_SPEED_1000))
1672                                 k1_enable = false;
1673                 }
1674
1675                 if (hw->phy.type == e1000_phy_82577) {
1676                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1677                         if (ret_val)
1678                                 goto release;
1679
1680                         status_reg &= (HV_M_STATUS_LINK_UP |
1681                                        HV_M_STATUS_AUTONEG_COMPLETE |
1682                                        HV_M_STATUS_SPEED_MASK);
1683
1684                         if (status_reg == (HV_M_STATUS_LINK_UP |
1685                                            HV_M_STATUS_AUTONEG_COMPLETE |
1686                                            HV_M_STATUS_SPEED_1000))
1687                                 k1_enable = false;
1688                 }
1689
1690                 /* Link stall fix for link up */
1691                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1692                 if (ret_val)
1693                         goto release;
1694
1695         } else {
1696                 /* Link stall fix for link down */
1697                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1698                 if (ret_val)
1699                         goto release;
1700         }
1701
1702         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1703
1704 release:
1705         hw->phy.ops.release(hw);
1706
1707         return ret_val;
1708 }
1709
1710 /**
1711  *  e1000_configure_k1_ich8lan - Configure K1 power state
1712  *  @hw: pointer to the HW structure
1713  *  @enable: K1 state to configure
1714  *
1715  *  Configure the K1 power state based on the provided parameter.
1716  *  Assumes semaphore already acquired.
1717  *
1718  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1719  **/
1720 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1721 {
1722         s32 ret_val;
1723         u32 ctrl_reg = 0;
1724         u32 ctrl_ext = 0;
1725         u32 reg = 0;
1726         u16 kmrn_reg = 0;
1727
1728         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1729                                               &kmrn_reg);
1730         if (ret_val)
1731                 return ret_val;
1732
1733         if (k1_enable)
1734                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1735         else
1736                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1737
1738         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1739                                                kmrn_reg);
1740         if (ret_val)
1741                 return ret_val;
1742
1743         usleep_range(20, 40);
1744         ctrl_ext = er32(CTRL_EXT);
1745         ctrl_reg = er32(CTRL);
1746
1747         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1748         reg |= E1000_CTRL_FRCSPD;
1749         ew32(CTRL, reg);
1750
1751         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1752         e1e_flush();
1753         usleep_range(20, 40);
1754         ew32(CTRL, ctrl_reg);
1755         ew32(CTRL_EXT, ctrl_ext);
1756         e1e_flush();
1757         usleep_range(20, 40);
1758
1759         return 0;
1760 }
1761
1762 /**
1763  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1764  *  @hw:       pointer to the HW structure
1765  *  @d0_state: boolean if entering d0 or d3 device state
1766  *
1767  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1768  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1769  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1770  **/
1771 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1772 {
1773         s32 ret_val = 0;
1774         u32 mac_reg;
1775         u16 oem_reg;
1776
1777         if (hw->mac.type < e1000_pchlan)
1778                 return ret_val;
1779
1780         ret_val = hw->phy.ops.acquire(hw);
1781         if (ret_val)
1782                 return ret_val;
1783
1784         if (hw->mac.type == e1000_pchlan) {
1785                 mac_reg = er32(EXTCNF_CTRL);
1786                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1787                         goto release;
1788         }
1789
1790         mac_reg = er32(FEXTNVM);
1791         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1792                 goto release;
1793
1794         mac_reg = er32(PHY_CTRL);
1795
1796         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1797         if (ret_val)
1798                 goto release;
1799
1800         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1801
1802         if (d0_state) {
1803                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1804                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1805
1806                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1807                         oem_reg |= HV_OEM_BITS_LPLU;
1808         } else {
1809                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1810                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1811                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1812
1813                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1814                                E1000_PHY_CTRL_NOND0A_LPLU))
1815                         oem_reg |= HV_OEM_BITS_LPLU;
1816         }
1817
1818         /* Set Restart auto-neg to activate the bits */
1819         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1820             !hw->phy.ops.check_reset_block(hw))
1821                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1822
1823         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1824
1825 release:
1826         hw->phy.ops.release(hw);
1827
1828         return ret_val;
1829 }
1830
1831 /**
1832  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1833  *  @hw:   pointer to the HW structure
1834  **/
1835 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1836 {
1837         s32 ret_val;
1838         u16 data;
1839
1840         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1841         if (ret_val)
1842                 return ret_val;
1843
1844         data |= HV_KMRN_MDIO_SLOW;
1845
1846         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1847
1848         return ret_val;
1849 }
1850
1851 /**
1852  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1853  *  done after every PHY reset.
1854  **/
1855 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1856 {
1857         s32 ret_val = 0;
1858         u16 phy_data;
1859
1860         if (hw->mac.type != e1000_pchlan)
1861                 return 0;
1862
1863         /* Set MDIO slow mode before any other MDIO access */
1864         if (hw->phy.type == e1000_phy_82577) {
1865                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1866                 if (ret_val)
1867                         return ret_val;
1868         }
1869
1870         if (((hw->phy.type == e1000_phy_82577) &&
1871              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1872             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1873                 /* Disable generation of early preamble */
1874                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1875                 if (ret_val)
1876                         return ret_val;
1877
1878                 /* Preamble tuning for SSC */
1879                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1880                 if (ret_val)
1881                         return ret_val;
1882         }
1883
1884         if (hw->phy.type == e1000_phy_82578) {
1885                 /* Return registers to default by doing a soft reset then
1886                  * writing 0x3140 to the control register.
1887                  */
1888                 if (hw->phy.revision < 2) {
1889                         e1000e_phy_sw_reset(hw);
1890                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
1891                 }
1892         }
1893
1894         /* Select page 0 */
1895         ret_val = hw->phy.ops.acquire(hw);
1896         if (ret_val)
1897                 return ret_val;
1898
1899         hw->phy.addr = 1;
1900         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1901         hw->phy.ops.release(hw);
1902         if (ret_val)
1903                 return ret_val;
1904
1905         /* Configure the K1 Si workaround during phy reset assuming there is
1906          * link so that it disables K1 if link is in 1Gbps.
1907          */
1908         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1909         if (ret_val)
1910                 return ret_val;
1911
1912         /* Workaround for link disconnects on a busy hub in half duplex */
1913         ret_val = hw->phy.ops.acquire(hw);
1914         if (ret_val)
1915                 return ret_val;
1916         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1917         if (ret_val)
1918                 goto release;
1919         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1920         if (ret_val)
1921                 goto release;
1922
1923         /* set MSE higher to enable link to stay up when noise is high */
1924         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1925 release:
1926         hw->phy.ops.release(hw);
1927
1928         return ret_val;
1929 }
1930
1931 /**
1932  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1933  *  @hw:   pointer to the HW structure
1934  **/
1935 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1936 {
1937         u32 mac_reg;
1938         u16 i, phy_reg = 0;
1939         s32 ret_val;
1940
1941         ret_val = hw->phy.ops.acquire(hw);
1942         if (ret_val)
1943                 return;
1944         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1945         if (ret_val)
1946                 goto release;
1947
1948         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1949         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1950                 mac_reg = er32(RAL(i));
1951                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1952                                            (u16)(mac_reg & 0xFFFF));
1953                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1954                                            (u16)((mac_reg >> 16) & 0xFFFF));
1955
1956                 mac_reg = er32(RAH(i));
1957                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1958                                            (u16)(mac_reg & 0xFFFF));
1959                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1960                                            (u16)((mac_reg & E1000_RAH_AV)
1961                                                  >> 16));
1962         }
1963
1964         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1965
1966 release:
1967         hw->phy.ops.release(hw);
1968 }
1969
1970 /**
1971  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1972  *  with 82579 PHY
1973  *  @hw: pointer to the HW structure
1974  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1975  **/
1976 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1977 {
1978         s32 ret_val = 0;
1979         u16 phy_reg, data;
1980         u32 mac_reg;
1981         u16 i;
1982
1983         if (hw->mac.type < e1000_pch2lan)
1984                 return 0;
1985
1986         /* disable Rx path while enabling/disabling workaround */
1987         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1988         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1989         if (ret_val)
1990                 return ret_val;
1991
1992         if (enable) {
1993                 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1994                  * SHRAL/H) and initial CRC values to the MAC
1995                  */
1996                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1997                         u8 mac_addr[ETH_ALEN] = { 0 };
1998                         u32 addr_high, addr_low;
1999
2000                         addr_high = er32(RAH(i));
2001                         if (!(addr_high & E1000_RAH_AV))
2002                                 continue;
2003                         addr_low = er32(RAL(i));
2004                         mac_addr[0] = (addr_low & 0xFF);
2005                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2006                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2007                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2008                         mac_addr[4] = (addr_high & 0xFF);
2009                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2010
2011                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2012                 }
2013
2014                 /* Write Rx addresses to the PHY */
2015                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2016
2017                 /* Enable jumbo frame workaround in the MAC */
2018                 mac_reg = er32(FFLT_DBG);
2019                 mac_reg &= ~(1 << 14);
2020                 mac_reg |= (7 << 15);
2021                 ew32(FFLT_DBG, mac_reg);
2022
2023                 mac_reg = er32(RCTL);
2024                 mac_reg |= E1000_RCTL_SECRC;
2025                 ew32(RCTL, mac_reg);
2026
2027                 ret_val = e1000e_read_kmrn_reg(hw,
2028                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2029                                                &data);
2030                 if (ret_val)
2031                         return ret_val;
2032                 ret_val = e1000e_write_kmrn_reg(hw,
2033                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2034                                                 data | (1 << 0));
2035                 if (ret_val)
2036                         return ret_val;
2037                 ret_val = e1000e_read_kmrn_reg(hw,
2038                                                E1000_KMRNCTRLSTA_HD_CTRL,
2039                                                &data);
2040                 if (ret_val)
2041                         return ret_val;
2042                 data &= ~(0xF << 8);
2043                 data |= (0xB << 8);
2044                 ret_val = e1000e_write_kmrn_reg(hw,
2045                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2046                                                 data);
2047                 if (ret_val)
2048                         return ret_val;
2049
2050                 /* Enable jumbo frame workaround in the PHY */
2051                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2052                 data &= ~(0x7F << 5);
2053                 data |= (0x37 << 5);
2054                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2055                 if (ret_val)
2056                         return ret_val;
2057                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2058                 data &= ~(1 << 13);
2059                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2060                 if (ret_val)
2061                         return ret_val;
2062                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2063                 data &= ~(0x3FF << 2);
2064                 data |= (0x1A << 2);
2065                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2066                 if (ret_val)
2067                         return ret_val;
2068                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2069                 if (ret_val)
2070                         return ret_val;
2071                 e1e_rphy(hw, HV_PM_CTRL, &data);
2072                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2073                 if (ret_val)
2074                         return ret_val;
2075         } else {
2076                 /* Write MAC register values back to h/w defaults */
2077                 mac_reg = er32(FFLT_DBG);
2078                 mac_reg &= ~(0xF << 14);
2079                 ew32(FFLT_DBG, mac_reg);
2080
2081                 mac_reg = er32(RCTL);
2082                 mac_reg &= ~E1000_RCTL_SECRC;
2083                 ew32(RCTL, mac_reg);
2084
2085                 ret_val = e1000e_read_kmrn_reg(hw,
2086                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2087                                                &data);
2088                 if (ret_val)
2089                         return ret_val;
2090                 ret_val = e1000e_write_kmrn_reg(hw,
2091                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2092                                                 data & ~(1 << 0));
2093                 if (ret_val)
2094                         return ret_val;
2095                 ret_val = e1000e_read_kmrn_reg(hw,
2096                                                E1000_KMRNCTRLSTA_HD_CTRL,
2097                                                &data);
2098                 if (ret_val)
2099                         return ret_val;
2100                 data &= ~(0xF << 8);
2101                 data |= (0xB << 8);
2102                 ret_val = e1000e_write_kmrn_reg(hw,
2103                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2104                                                 data);
2105                 if (ret_val)
2106                         return ret_val;
2107
2108                 /* Write PHY register values back to h/w defaults */
2109                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2110                 data &= ~(0x7F << 5);
2111                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2112                 if (ret_val)
2113                         return ret_val;
2114                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2115                 data |= (1 << 13);
2116                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2117                 if (ret_val)
2118                         return ret_val;
2119                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2120                 data &= ~(0x3FF << 2);
2121                 data |= (0x8 << 2);
2122                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2123                 if (ret_val)
2124                         return ret_val;
2125                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2126                 if (ret_val)
2127                         return ret_val;
2128                 e1e_rphy(hw, HV_PM_CTRL, &data);
2129                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2130                 if (ret_val)
2131                         return ret_val;
2132         }
2133
2134         /* re-enable Rx path after enabling/disabling workaround */
2135         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2136 }
2137
2138 /**
2139  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2140  *  done after every PHY reset.
2141  **/
2142 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2143 {
2144         s32 ret_val = 0;
2145
2146         if (hw->mac.type != e1000_pch2lan)
2147                 return 0;
2148
2149         /* Set MDIO slow mode before any other MDIO access */
2150         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2151         if (ret_val)
2152                 return ret_val;
2153
2154         ret_val = hw->phy.ops.acquire(hw);
2155         if (ret_val)
2156                 return ret_val;
2157         /* set MSE higher to enable link to stay up when noise is high */
2158         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2159         if (ret_val)
2160                 goto release;
2161         /* drop link after 5 times MSE threshold was reached */
2162         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2163 release:
2164         hw->phy.ops.release(hw);
2165
2166         return ret_val;
2167 }
2168
2169 /**
2170  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2171  *  @hw:   pointer to the HW structure
2172  *
2173  *  Workaround to set the K1 beacon duration for 82579 parts
2174  **/
2175 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2176 {
2177         s32 ret_val = 0;
2178         u16 status_reg = 0;
2179         u32 mac_reg;
2180         u16 phy_reg;
2181
2182         if (hw->mac.type != e1000_pch2lan)
2183                 return 0;
2184
2185         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2186         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2187         if (ret_val)
2188                 return ret_val;
2189
2190         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2191             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2192                 mac_reg = er32(FEXTNVM4);
2193                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2194
2195                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2196                 if (ret_val)
2197                         return ret_val;
2198
2199                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2200                         u16 pm_phy_reg;
2201
2202                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2203                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2204                         /* LV 1G Packet drop issue wa  */
2205                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2206                         if (ret_val)
2207                                 return ret_val;
2208                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2209                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2210                         if (ret_val)
2211                                 return ret_val;
2212                 } else {
2213                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2214                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2215                 }
2216                 ew32(FEXTNVM4, mac_reg);
2217                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2218         }
2219
2220         return ret_val;
2221 }
2222
2223 /**
2224  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2225  *  @hw:   pointer to the HW structure
2226  *  @gate: boolean set to true to gate, false to ungate
2227  *
2228  *  Gate/ungate the automatic PHY configuration via hardware; perform
2229  *  the configuration via software instead.
2230  **/
2231 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2232 {
2233         u32 extcnf_ctrl;
2234
2235         if (hw->mac.type < e1000_pch2lan)
2236                 return;
2237
2238         extcnf_ctrl = er32(EXTCNF_CTRL);
2239
2240         if (gate)
2241                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2242         else
2243                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2244
2245         ew32(EXTCNF_CTRL, extcnf_ctrl);
2246 }
2247
2248 /**
2249  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2250  *  @hw: pointer to the HW structure
2251  *
2252  *  Check the appropriate indication the MAC has finished configuring the
2253  *  PHY after a software reset.
2254  **/
2255 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2256 {
2257         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2258
2259         /* Wait for basic configuration completes before proceeding */
2260         do {
2261                 data = er32(STATUS);
2262                 data &= E1000_STATUS_LAN_INIT_DONE;
2263                 usleep_range(100, 200);
2264         } while ((!data) && --loop);
2265
2266         /* If basic configuration is incomplete before the above loop
2267          * count reaches 0, loading the configuration from NVM will
2268          * leave the PHY in a bad state possibly resulting in no link.
2269          */
2270         if (loop == 0)
2271                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2272
2273         /* Clear the Init Done bit for the next init event */
2274         data = er32(STATUS);
2275         data &= ~E1000_STATUS_LAN_INIT_DONE;
2276         ew32(STATUS, data);
2277 }
2278
2279 /**
2280  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2281  *  @hw: pointer to the HW structure
2282  **/
2283 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2284 {
2285         s32 ret_val = 0;
2286         u16 reg;
2287
2288         if (hw->phy.ops.check_reset_block(hw))
2289                 return 0;
2290
2291         /* Allow time for h/w to get to quiescent state after reset */
2292         usleep_range(10000, 20000);
2293
2294         /* Perform any necessary post-reset workarounds */
2295         switch (hw->mac.type) {
2296         case e1000_pchlan:
2297                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2298                 if (ret_val)
2299                         return ret_val;
2300                 break;
2301         case e1000_pch2lan:
2302                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2303                 if (ret_val)
2304                         return ret_val;
2305                 break;
2306         default:
2307                 break;
2308         }
2309
2310         /* Clear the host wakeup bit after lcd reset */
2311         if (hw->mac.type >= e1000_pchlan) {
2312                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2313                 reg &= ~BM_WUC_HOST_WU_BIT;
2314                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2315         }
2316
2317         /* Configure the LCD with the extended configuration region in NVM */
2318         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2319         if (ret_val)
2320                 return ret_val;
2321
2322         /* Configure the LCD with the OEM bits in NVM */
2323         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2324
2325         if (hw->mac.type == e1000_pch2lan) {
2326                 /* Ungate automatic PHY configuration on non-managed 82579 */
2327                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2328                         usleep_range(10000, 20000);
2329                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2330                 }
2331
2332                 /* Set EEE LPI Update Timer to 200usec */
2333                 ret_val = hw->phy.ops.acquire(hw);
2334                 if (ret_val)
2335                         return ret_val;
2336                 ret_val = e1000_write_emi_reg_locked(hw,
2337                                                      I82579_LPI_UPDATE_TIMER,
2338                                                      0x1387);
2339                 hw->phy.ops.release(hw);
2340         }
2341
2342         return ret_val;
2343 }
2344
2345 /**
2346  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2347  *  @hw: pointer to the HW structure
2348  *
2349  *  Resets the PHY
2350  *  This is a function pointer entry point called by drivers
2351  *  or other shared routines.
2352  **/
2353 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2354 {
2355         s32 ret_val = 0;
2356
2357         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2358         if ((hw->mac.type == e1000_pch2lan) &&
2359             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2360                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2361
2362         ret_val = e1000e_phy_hw_reset_generic(hw);
2363         if (ret_val)
2364                 return ret_val;
2365
2366         return e1000_post_phy_reset_ich8lan(hw);
2367 }
2368
2369 /**
2370  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2371  *  @hw: pointer to the HW structure
2372  *  @active: true to enable LPLU, false to disable
2373  *
2374  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2375  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2376  *  the phy speed. This function will manually set the LPLU bit and restart
2377  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2378  *  since it configures the same bit.
2379  **/
2380 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2381 {
2382         s32 ret_val;
2383         u16 oem_reg;
2384
2385         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2386         if (ret_val)
2387                 return ret_val;
2388
2389         if (active)
2390                 oem_reg |= HV_OEM_BITS_LPLU;
2391         else
2392                 oem_reg &= ~HV_OEM_BITS_LPLU;
2393
2394         if (!hw->phy.ops.check_reset_block(hw))
2395                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2396
2397         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2398 }
2399
2400 /**
2401  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2402  *  @hw: pointer to the HW structure
2403  *  @active: true to enable LPLU, false to disable
2404  *
2405  *  Sets the LPLU D0 state according to the active flag.  When
2406  *  activating LPLU this function also disables smart speed
2407  *  and vice versa.  LPLU will not be activated unless the
2408  *  device autonegotiation advertisement meets standards of
2409  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2410  *  This is a function pointer entry point only called by
2411  *  PHY setup routines.
2412  **/
2413 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2414 {
2415         struct e1000_phy_info *phy = &hw->phy;
2416         u32 phy_ctrl;
2417         s32 ret_val = 0;
2418         u16 data;
2419
2420         if (phy->type == e1000_phy_ife)
2421                 return 0;
2422
2423         phy_ctrl = er32(PHY_CTRL);
2424
2425         if (active) {
2426                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2427                 ew32(PHY_CTRL, phy_ctrl);
2428
2429                 if (phy->type != e1000_phy_igp_3)
2430                         return 0;
2431
2432                 /* Call gig speed drop workaround on LPLU before accessing
2433                  * any PHY registers
2434                  */
2435                 if (hw->mac.type == e1000_ich8lan)
2436                         e1000e_gig_downshift_workaround_ich8lan(hw);
2437
2438                 /* When LPLU is enabled, we should disable SmartSpeed */
2439                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2440                 if (ret_val)
2441                         return ret_val;
2442                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2443                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2444                 if (ret_val)
2445                         return ret_val;
2446         } else {
2447                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2448                 ew32(PHY_CTRL, phy_ctrl);
2449
2450                 if (phy->type != e1000_phy_igp_3)
2451                         return 0;
2452
2453                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2454                  * during Dx states where the power conservation is most
2455                  * important.  During driver activity we should enable
2456                  * SmartSpeed, so performance is maintained.
2457                  */
2458                 if (phy->smart_speed == e1000_smart_speed_on) {
2459                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2460                                            &data);
2461                         if (ret_val)
2462                                 return ret_val;
2463
2464                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2465                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2466                                            data);
2467                         if (ret_val)
2468                                 return ret_val;
2469                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2470                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2471                                            &data);
2472                         if (ret_val)
2473                                 return ret_val;
2474
2475                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2476                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2477                                            data);
2478                         if (ret_val)
2479                                 return ret_val;
2480                 }
2481         }
2482
2483         return 0;
2484 }
2485
2486 /**
2487  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2488  *  @hw: pointer to the HW structure
2489  *  @active: true to enable LPLU, false to disable
2490  *
2491  *  Sets the LPLU D3 state according to the active flag.  When
2492  *  activating LPLU this function also disables smart speed
2493  *  and vice versa.  LPLU will not be activated unless the
2494  *  device autonegotiation advertisement meets standards of
2495  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2496  *  This is a function pointer entry point only called by
2497  *  PHY setup routines.
2498  **/
2499 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2500 {
2501         struct e1000_phy_info *phy = &hw->phy;
2502         u32 phy_ctrl;
2503         s32 ret_val = 0;
2504         u16 data;
2505
2506         phy_ctrl = er32(PHY_CTRL);
2507
2508         if (!active) {
2509                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2510                 ew32(PHY_CTRL, phy_ctrl);
2511
2512                 if (phy->type != e1000_phy_igp_3)
2513                         return 0;
2514
2515                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2516                  * during Dx states where the power conservation is most
2517                  * important.  During driver activity we should enable
2518                  * SmartSpeed, so performance is maintained.
2519                  */
2520                 if (phy->smart_speed == e1000_smart_speed_on) {
2521                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2522                                            &data);
2523                         if (ret_val)
2524                                 return ret_val;
2525
2526                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2527                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2528                                            data);
2529                         if (ret_val)
2530                                 return ret_val;
2531                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2532                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2533                                            &data);
2534                         if (ret_val)
2535                                 return ret_val;
2536
2537                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2538                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2539                                            data);
2540                         if (ret_val)
2541                                 return ret_val;
2542                 }
2543         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2544                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2545                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2546                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2547                 ew32(PHY_CTRL, phy_ctrl);
2548
2549                 if (phy->type != e1000_phy_igp_3)
2550                         return 0;
2551
2552                 /* Call gig speed drop workaround on LPLU before accessing
2553                  * any PHY registers
2554                  */
2555                 if (hw->mac.type == e1000_ich8lan)
2556                         e1000e_gig_downshift_workaround_ich8lan(hw);
2557
2558                 /* When LPLU is enabled, we should disable SmartSpeed */
2559                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2560                 if (ret_val)
2561                         return ret_val;
2562
2563                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2564                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2565         }
2566
2567         return ret_val;
2568 }
2569
2570 /**
2571  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2572  *  @hw: pointer to the HW structure
2573  *  @bank:  pointer to the variable that returns the active bank
2574  *
2575  *  Reads signature byte from the NVM using the flash access registers.
2576  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2577  **/
2578 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2579 {
2580         u32 eecd;
2581         struct e1000_nvm_info *nvm = &hw->nvm;
2582         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2583         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2584         u8 sig_byte = 0;
2585         s32 ret_val;
2586
2587         switch (hw->mac.type) {
2588         case e1000_ich8lan:
2589         case e1000_ich9lan:
2590                 eecd = er32(EECD);
2591                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2592                     E1000_EECD_SEC1VAL_VALID_MASK) {
2593                         if (eecd & E1000_EECD_SEC1VAL)
2594                                 *bank = 1;
2595                         else
2596                                 *bank = 0;
2597
2598                         return 0;
2599                 }
2600                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2601                 /* fall-thru */
2602         default:
2603                 /* set bank to 0 in case flash read fails */
2604                 *bank = 0;
2605
2606                 /* Check bank 0 */
2607                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2608                                                         &sig_byte);
2609                 if (ret_val)
2610                         return ret_val;
2611                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2612                     E1000_ICH_NVM_SIG_VALUE) {
2613                         *bank = 0;
2614                         return 0;
2615                 }
2616
2617                 /* Check bank 1 */
2618                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2619                                                         bank1_offset,
2620                                                         &sig_byte);
2621                 if (ret_val)
2622                         return ret_val;
2623                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2624                     E1000_ICH_NVM_SIG_VALUE) {
2625                         *bank = 1;
2626                         return 0;
2627                 }
2628
2629                 e_dbg("ERROR: No valid NVM bank present\n");
2630                 return -E1000_ERR_NVM;
2631         }
2632 }
2633
2634 /**
2635  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2636  *  @hw: pointer to the HW structure
2637  *  @offset: The offset (in bytes) of the word(s) to read.
2638  *  @words: Size of data to read in words
2639  *  @data: Pointer to the word(s) to read at offset.
2640  *
2641  *  Reads a word(s) from the NVM using the flash access registers.
2642  **/
2643 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2644                                   u16 *data)
2645 {
2646         struct e1000_nvm_info *nvm = &hw->nvm;
2647         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2648         u32 act_offset;
2649         s32 ret_val = 0;
2650         u32 bank = 0;
2651         u16 i, word;
2652
2653         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2654             (words == 0)) {
2655                 e_dbg("nvm parameter(s) out of bounds\n");
2656                 ret_val = -E1000_ERR_NVM;
2657                 goto out;
2658         }
2659
2660         nvm->ops.acquire(hw);
2661
2662         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2663         if (ret_val) {
2664                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2665                 bank = 0;
2666         }
2667
2668         act_offset = (bank) ? nvm->flash_bank_size : 0;
2669         act_offset += offset;
2670
2671         ret_val = 0;
2672         for (i = 0; i < words; i++) {
2673                 if (dev_spec->shadow_ram[offset + i].modified) {
2674                         data[i] = dev_spec->shadow_ram[offset + i].value;
2675                 } else {
2676                         ret_val = e1000_read_flash_word_ich8lan(hw,
2677                                                                 act_offset + i,
2678                                                                 &word);
2679                         if (ret_val)
2680                                 break;
2681                         data[i] = word;
2682                 }
2683         }
2684
2685         nvm->ops.release(hw);
2686
2687 out:
2688         if (ret_val)
2689                 e_dbg("NVM read error: %d\n", ret_val);
2690
2691         return ret_val;
2692 }
2693
2694 /**
2695  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2696  *  @hw: pointer to the HW structure
2697  *
2698  *  This function does initial flash setup so that a new read/write/erase cycle
2699  *  can be started.
2700  **/
2701 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2702 {
2703         union ich8_hws_flash_status hsfsts;
2704         s32 ret_val = -E1000_ERR_NVM;
2705
2706         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2707
2708         /* Check if the flash descriptor is valid */
2709         if (!hsfsts.hsf_status.fldesvalid) {
2710                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2711                 return -E1000_ERR_NVM;
2712         }
2713
2714         /* Clear FCERR and DAEL in hw status by writing 1 */
2715         hsfsts.hsf_status.flcerr = 1;
2716         hsfsts.hsf_status.dael = 1;
2717
2718         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2719
2720         /* Either we should have a hardware SPI cycle in progress
2721          * bit to check against, in order to start a new cycle or
2722          * FDONE bit should be changed in the hardware so that it
2723          * is 1 after hardware reset, which can then be used as an
2724          * indication whether a cycle is in progress or has been
2725          * completed.
2726          */
2727
2728         if (!hsfsts.hsf_status.flcinprog) {
2729                 /* There is no cycle running at present,
2730                  * so we can start a cycle.
2731                  * Begin by setting Flash Cycle Done.
2732                  */
2733                 hsfsts.hsf_status.flcdone = 1;
2734                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2735                 ret_val = 0;
2736         } else {
2737                 s32 i;
2738
2739                 /* Otherwise poll for sometime so the current
2740                  * cycle has a chance to end before giving up.
2741                  */
2742                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2743                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2744                         if (!hsfsts.hsf_status.flcinprog) {
2745                                 ret_val = 0;
2746                                 break;
2747                         }
2748                         udelay(1);
2749                 }
2750                 if (!ret_val) {
2751                         /* Successful in waiting for previous cycle to timeout,
2752                          * now set the Flash Cycle Done.
2753                          */
2754                         hsfsts.hsf_status.flcdone = 1;
2755                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2756                 } else {
2757                         e_dbg("Flash controller busy, cannot get access\n");
2758                 }
2759         }
2760
2761         return ret_val;
2762 }
2763
2764 /**
2765  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2766  *  @hw: pointer to the HW structure
2767  *  @timeout: maximum time to wait for completion
2768  *
2769  *  This function starts a flash cycle and waits for its completion.
2770  **/
2771 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2772 {
2773         union ich8_hws_flash_ctrl hsflctl;
2774         union ich8_hws_flash_status hsfsts;
2775         u32 i = 0;
2776
2777         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2778         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2779         hsflctl.hsf_ctrl.flcgo = 1;
2780         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2781
2782         /* wait till FDONE bit is set to 1 */
2783         do {
2784                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2785                 if (hsfsts.hsf_status.flcdone)
2786                         break;
2787                 udelay(1);
2788         } while (i++ < timeout);
2789
2790         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2791                 return 0;
2792
2793         return -E1000_ERR_NVM;
2794 }
2795
2796 /**
2797  *  e1000_read_flash_word_ich8lan - Read word from flash
2798  *  @hw: pointer to the HW structure
2799  *  @offset: offset to data location
2800  *  @data: pointer to the location for storing the data
2801  *
2802  *  Reads the flash word at offset into data.  Offset is converted
2803  *  to bytes before read.
2804  **/
2805 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2806                                          u16 *data)
2807 {
2808         /* Must convert offset into bytes. */
2809         offset <<= 1;
2810
2811         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2812 }
2813
2814 /**
2815  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2816  *  @hw: pointer to the HW structure
2817  *  @offset: The offset of the byte to read.
2818  *  @data: Pointer to a byte to store the value read.
2819  *
2820  *  Reads a single byte from the NVM using the flash access registers.
2821  **/
2822 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2823                                          u8 *data)
2824 {
2825         s32 ret_val;
2826         u16 word = 0;
2827
2828         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2829         if (ret_val)
2830                 return ret_val;
2831
2832         *data = (u8)word;
2833
2834         return 0;
2835 }
2836
2837 /**
2838  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2839  *  @hw: pointer to the HW structure
2840  *  @offset: The offset (in bytes) of the byte or word to read.
2841  *  @size: Size of data to read, 1=byte 2=word
2842  *  @data: Pointer to the word to store the value read.
2843  *
2844  *  Reads a byte or word from the NVM using the flash access registers.
2845  **/
2846 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2847                                          u8 size, u16 *data)
2848 {
2849         union ich8_hws_flash_status hsfsts;
2850         union ich8_hws_flash_ctrl hsflctl;
2851         u32 flash_linear_addr;
2852         u32 flash_data = 0;
2853         s32 ret_val = -E1000_ERR_NVM;
2854         u8 count = 0;
2855
2856         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2857                 return -E1000_ERR_NVM;
2858
2859         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2860                              hw->nvm.flash_base_addr);
2861
2862         do {
2863                 udelay(1);
2864                 /* Steps */
2865                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2866                 if (ret_val)
2867                         break;
2868
2869                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2870                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2871                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2872                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2873                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2874
2875                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2876
2877                 ret_val =
2878                     e1000_flash_cycle_ich8lan(hw,
2879                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
2880
2881                 /* Check if FCERR is set to 1, if set to 1, clear it
2882                  * and try the whole sequence a few more times, else
2883                  * read in (shift in) the Flash Data0, the order is
2884                  * least significant byte first msb to lsb
2885                  */
2886                 if (!ret_val) {
2887                         flash_data = er32flash(ICH_FLASH_FDATA0);
2888                         if (size == 1)
2889                                 *data = (u8)(flash_data & 0x000000FF);
2890                         else if (size == 2)
2891                                 *data = (u16)(flash_data & 0x0000FFFF);
2892                         break;
2893                 } else {
2894                         /* If we've gotten here, then things are probably
2895                          * completely hosed, but if the error condition is
2896                          * detected, it won't hurt to give it another try...
2897                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2898                          */
2899                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2900                         if (hsfsts.hsf_status.flcerr) {
2901                                 /* Repeat for some time before giving up. */
2902                                 continue;
2903                         } else if (!hsfsts.hsf_status.flcdone) {
2904                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2905                                 break;
2906                         }
2907                 }
2908         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2909
2910         return ret_val;
2911 }
2912
2913 /**
2914  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2915  *  @hw: pointer to the HW structure
2916  *  @offset: The offset (in bytes) of the word(s) to write.
2917  *  @words: Size of data to write in words
2918  *  @data: Pointer to the word(s) to write at offset.
2919  *
2920  *  Writes a byte or word to the NVM using the flash access registers.
2921  **/
2922 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2923                                    u16 *data)
2924 {
2925         struct e1000_nvm_info *nvm = &hw->nvm;
2926         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2927         u16 i;
2928
2929         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2930             (words == 0)) {
2931                 e_dbg("nvm parameter(s) out of bounds\n");
2932                 return -E1000_ERR_NVM;
2933         }
2934
2935         nvm->ops.acquire(hw);
2936
2937         for (i = 0; i < words; i++) {
2938                 dev_spec->shadow_ram[offset + i].modified = true;
2939                 dev_spec->shadow_ram[offset + i].value = data[i];
2940         }
2941
2942         nvm->ops.release(hw);
2943
2944         return 0;
2945 }
2946
2947 /**
2948  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2949  *  @hw: pointer to the HW structure
2950  *
2951  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2952  *  which writes the checksum to the shadow ram.  The changes in the shadow
2953  *  ram are then committed to the EEPROM by processing each bank at a time
2954  *  checking for the modified bit and writing only the pending changes.
2955  *  After a successful commit, the shadow ram is cleared and is ready for
2956  *  future writes.
2957  **/
2958 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2959 {
2960         struct e1000_nvm_info *nvm = &hw->nvm;
2961         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2962         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2963         s32 ret_val;
2964         u16 data;
2965
2966         ret_val = e1000e_update_nvm_checksum_generic(hw);
2967         if (ret_val)
2968                 goto out;
2969
2970         if (nvm->type != e1000_nvm_flash_sw)
2971                 goto out;
2972
2973         nvm->ops.acquire(hw);
2974
2975         /* We're writing to the opposite bank so if we're on bank 1,
2976          * write to bank 0 etc.  We also need to erase the segment that
2977          * is going to be written
2978          */
2979         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2980         if (ret_val) {
2981                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2982                 bank = 0;
2983         }
2984
2985         if (bank == 0) {
2986                 new_bank_offset = nvm->flash_bank_size;
2987                 old_bank_offset = 0;
2988                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2989                 if (ret_val)
2990                         goto release;
2991         } else {
2992                 old_bank_offset = nvm->flash_bank_size;
2993                 new_bank_offset = 0;
2994                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2995                 if (ret_val)
2996                         goto release;
2997         }
2998
2999         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3000                 /* Determine whether to write the value stored
3001                  * in the other NVM bank or a modified value stored
3002                  * in the shadow RAM
3003                  */
3004                 if (dev_spec->shadow_ram[i].modified) {
3005                         data = dev_spec->shadow_ram[i].value;
3006                 } else {
3007                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3008                                                                 old_bank_offset,
3009                                                                 &data);
3010                         if (ret_val)
3011                                 break;
3012                 }
3013
3014                 /* If the word is 0x13, then make sure the signature bits
3015                  * (15:14) are 11b until the commit has completed.
3016                  * This will allow us to write 10b which indicates the
3017                  * signature is valid.  We want to do this after the write
3018                  * has completed so that we don't mark the segment valid
3019                  * while the write is still in progress
3020                  */
3021                 if (i == E1000_ICH_NVM_SIG_WORD)
3022                         data |= E1000_ICH_NVM_SIG_MASK;
3023
3024                 /* Convert offset to bytes. */
3025                 act_offset = (i + new_bank_offset) << 1;
3026
3027                 usleep_range(100, 200);
3028                 /* Write the bytes to the new bank. */
3029                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3030                                                                act_offset,
3031                                                                (u8)data);
3032                 if (ret_val)
3033                         break;
3034
3035                 usleep_range(100, 200);
3036                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3037                                                                act_offset + 1,
3038                                                                (u8)(data >> 8));
3039                 if (ret_val)
3040                         break;
3041         }
3042
3043         /* Don't bother writing the segment valid bits if sector
3044          * programming failed.
3045          */
3046         if (ret_val) {
3047                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3048                 e_dbg("Flash commit failed.\n");
3049                 goto release;
3050         }
3051
3052         /* Finally validate the new segment by setting bit 15:14
3053          * to 10b in word 0x13 , this can be done without an
3054          * erase as well since these bits are 11 to start with
3055          * and we need to change bit 14 to 0b
3056          */
3057         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3058         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3059         if (ret_val)
3060                 goto release;
3061
3062         data &= 0xBFFF;
3063         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3064                                                        act_offset * 2 + 1,
3065                                                        (u8)(data >> 8));
3066         if (ret_val)
3067                 goto release;
3068
3069         /* And invalidate the previously valid segment by setting
3070          * its signature word (0x13) high_byte to 0b. This can be
3071          * done without an erase because flash erase sets all bits
3072          * to 1's. We can write 1's to 0's without an erase
3073          */
3074         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3075         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3076         if (ret_val)
3077                 goto release;
3078
3079         /* Great!  Everything worked, we can now clear the cached entries. */
3080         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3081                 dev_spec->shadow_ram[i].modified = false;
3082                 dev_spec->shadow_ram[i].value = 0xFFFF;
3083         }
3084
3085 release:
3086         nvm->ops.release(hw);
3087
3088         /* Reload the EEPROM, or else modifications will not appear
3089          * until after the next adapter reset.
3090          */
3091         if (!ret_val) {
3092                 nvm->ops.reload(hw);
3093                 usleep_range(10000, 20000);
3094         }
3095
3096 out:
3097         if (ret_val)
3098                 e_dbg("NVM update error: %d\n", ret_val);
3099
3100         return ret_val;
3101 }
3102
3103 /**
3104  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3105  *  @hw: pointer to the HW structure
3106  *
3107  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3108  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3109  *  calculated, in which case we need to calculate the checksum and set bit 6.
3110  **/
3111 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3112 {
3113         s32 ret_val;
3114         u16 data;
3115         u16 word;
3116         u16 valid_csum_mask;
3117
3118         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3119          * the checksum needs to be fixed.  This bit is an indication that
3120          * the NVM was prepared by OEM software and did not calculate
3121          * the checksum...a likely scenario.
3122          */
3123         switch (hw->mac.type) {
3124         case e1000_pch_lpt:
3125                 word = NVM_COMPAT;
3126                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3127                 break;
3128         default:
3129                 word = NVM_FUTURE_INIT_WORD1;
3130                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3131                 break;
3132         }
3133
3134         ret_val = e1000_read_nvm(hw, word, 1, &data);
3135         if (ret_val)
3136                 return ret_val;
3137
3138         if (!(data & valid_csum_mask)) {
3139                 data |= valid_csum_mask;
3140                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3141                 if (ret_val)
3142                         return ret_val;
3143                 ret_val = e1000e_update_nvm_checksum(hw);
3144                 if (ret_val)
3145                         return ret_val;
3146         }
3147
3148         return e1000e_validate_nvm_checksum_generic(hw);
3149 }
3150
3151 /**
3152  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3153  *  @hw: pointer to the HW structure
3154  *
3155  *  To prevent malicious write/erase of the NVM, set it to be read-only
3156  *  so that the hardware ignores all write/erase cycles of the NVM via
3157  *  the flash control registers.  The shadow-ram copy of the NVM will
3158  *  still be updated, however any updates to this copy will not stick
3159  *  across driver reloads.
3160  **/
3161 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3162 {
3163         struct e1000_nvm_info *nvm = &hw->nvm;
3164         union ich8_flash_protected_range pr0;
3165         union ich8_hws_flash_status hsfsts;
3166         u32 gfpreg;
3167
3168         nvm->ops.acquire(hw);
3169
3170         gfpreg = er32flash(ICH_FLASH_GFPREG);
3171
3172         /* Write-protect GbE Sector of NVM */
3173         pr0.regval = er32flash(ICH_FLASH_PR0);
3174         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3175         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3176         pr0.range.wpe = true;
3177         ew32flash(ICH_FLASH_PR0, pr0.regval);
3178
3179         /* Lock down a subset of GbE Flash Control Registers, e.g.
3180          * PR0 to prevent the write-protection from being lifted.
3181          * Once FLOCKDN is set, the registers protected by it cannot
3182          * be written until FLOCKDN is cleared by a hardware reset.
3183          */
3184         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3185         hsfsts.hsf_status.flockdn = true;
3186         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3187
3188         nvm->ops.release(hw);
3189 }
3190
3191 /**
3192  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3193  *  @hw: pointer to the HW structure
3194  *  @offset: The offset (in bytes) of the byte/word to read.
3195  *  @size: Size of data to read, 1=byte 2=word
3196  *  @data: The byte(s) to write to the NVM.
3197  *
3198  *  Writes one/two bytes to the NVM using the flash access registers.
3199  **/
3200 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3201                                           u8 size, u16 data)
3202 {
3203         union ich8_hws_flash_status hsfsts;
3204         union ich8_hws_flash_ctrl hsflctl;
3205         u32 flash_linear_addr;
3206         u32 flash_data = 0;
3207         s32 ret_val;
3208         u8 count = 0;
3209
3210         if (size < 1 || size > 2 || data > size * 0xff ||
3211             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3212                 return -E1000_ERR_NVM;
3213
3214         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3215                              hw->nvm.flash_base_addr);
3216
3217         do {
3218                 udelay(1);
3219                 /* Steps */
3220                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3221                 if (ret_val)
3222                         break;
3223
3224                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3225                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3226                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3227                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3228                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3229
3230                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3231
3232                 if (size == 1)
3233                         flash_data = (u32)data & 0x00FF;
3234                 else
3235                         flash_data = (u32)data;
3236
3237                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3238
3239                 /* check if FCERR is set to 1 , if set to 1, clear it
3240                  * and try the whole sequence a few more times else done
3241                  */
3242                 ret_val =
3243                     e1000_flash_cycle_ich8lan(hw,
3244                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3245                 if (!ret_val)
3246                         break;
3247
3248                 /* If we're here, then things are most likely
3249                  * completely hosed, but if the error condition
3250                  * is detected, it won't hurt to give it another
3251                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3252                  */
3253                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3254                 if (hsfsts.hsf_status.flcerr)
3255                         /* Repeat for some time before giving up. */
3256                         continue;
3257                 if (!hsfsts.hsf_status.flcdone) {
3258                         e_dbg("Timeout error - flash cycle did not complete.\n");
3259                         break;
3260                 }
3261         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3262
3263         return ret_val;
3264 }
3265
3266 /**
3267  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3268  *  @hw: pointer to the HW structure
3269  *  @offset: The index of the byte to read.
3270  *  @data: The byte to write to the NVM.
3271  *
3272  *  Writes a single byte to the NVM using the flash access registers.
3273  **/
3274 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3275                                           u8 data)
3276 {
3277         u16 word = (u16)data;
3278
3279         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3280 }
3281
3282 /**
3283  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3284  *  @hw: pointer to the HW structure
3285  *  @offset: The offset of the byte to write.
3286  *  @byte: The byte to write to the NVM.
3287  *
3288  *  Writes a single byte to the NVM using the flash access registers.
3289  *  Goes through a retry algorithm before giving up.
3290  **/
3291 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3292                                                 u32 offset, u8 byte)
3293 {
3294         s32 ret_val;
3295         u16 program_retries;
3296
3297         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3298         if (!ret_val)
3299                 return ret_val;
3300
3301         for (program_retries = 0; program_retries < 100; program_retries++) {
3302                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3303                 usleep_range(100, 200);
3304                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3305                 if (!ret_val)
3306                         break;
3307         }
3308         if (program_retries == 100)
3309                 return -E1000_ERR_NVM;
3310
3311         return 0;
3312 }
3313
3314 /**
3315  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3316  *  @hw: pointer to the HW structure
3317  *  @bank: 0 for first bank, 1 for second bank, etc.
3318  *
3319  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3320  *  bank N is 4096 * N + flash_reg_addr.
3321  **/
3322 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3323 {
3324         struct e1000_nvm_info *nvm = &hw->nvm;
3325         union ich8_hws_flash_status hsfsts;
3326         union ich8_hws_flash_ctrl hsflctl;
3327         u32 flash_linear_addr;
3328         /* bank size is in 16bit words - adjust to bytes */
3329         u32 flash_bank_size = nvm->flash_bank_size * 2;
3330         s32 ret_val;
3331         s32 count = 0;
3332         s32 j, iteration, sector_size;
3333
3334         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3335
3336         /* Determine HW Sector size: Read BERASE bits of hw flash status
3337          * register
3338          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3339          *     consecutive sectors.  The start index for the nth Hw sector
3340          *     can be calculated as = bank * 4096 + n * 256
3341          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3342          *     The start index for the nth Hw sector can be calculated
3343          *     as = bank * 4096
3344          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3345          *     (ich9 only, otherwise error condition)
3346          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3347          */
3348         switch (hsfsts.hsf_status.berasesz) {
3349         case 0:
3350                 /* Hw sector size 256 */
3351                 sector_size = ICH_FLASH_SEG_SIZE_256;
3352                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3353                 break;
3354         case 1:
3355                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3356                 iteration = 1;
3357                 break;
3358         case 2:
3359                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3360                 iteration = 1;
3361                 break;
3362         case 3:
3363                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3364                 iteration = 1;
3365                 break;
3366         default:
3367                 return -E1000_ERR_NVM;
3368         }
3369
3370         /* Start with the base address, then add the sector offset. */
3371         flash_linear_addr = hw->nvm.flash_base_addr;
3372         flash_linear_addr += (bank) ? flash_bank_size : 0;
3373
3374         for (j = 0; j < iteration; j++) {
3375                 do {
3376                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3377
3378                         /* Steps */
3379                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3380                         if (ret_val)
3381                                 return ret_val;
3382
3383                         /* Write a value 11 (block Erase) in Flash
3384                          * Cycle field in hw flash control
3385                          */
3386                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3387                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3388                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3389
3390                         /* Write the last 24 bits of an index within the
3391                          * block into Flash Linear address field in Flash
3392                          * Address.
3393                          */
3394                         flash_linear_addr += (j * sector_size);
3395                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3396
3397                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3398                         if (!ret_val)
3399                                 break;
3400
3401                         /* Check if FCERR is set to 1.  If 1,
3402                          * clear it and try the whole sequence
3403                          * a few more times else Done
3404                          */
3405                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3406                         if (hsfsts.hsf_status.flcerr)
3407                                 /* repeat for some time before giving up */
3408                                 continue;
3409                         else if (!hsfsts.hsf_status.flcdone)
3410                                 return ret_val;
3411                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3412         }
3413
3414         return 0;
3415 }
3416
3417 /**
3418  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3419  *  @hw: pointer to the HW structure
3420  *  @data: Pointer to the LED settings
3421  *
3422  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3423  *  settings is all 0's or F's, set the LED default to a valid LED default
3424  *  setting.
3425  **/
3426 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3427 {
3428         s32 ret_val;
3429
3430         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3431         if (ret_val) {
3432                 e_dbg("NVM Read Error\n");
3433                 return ret_val;
3434         }
3435
3436         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3437                 *data = ID_LED_DEFAULT_ICH8LAN;
3438
3439         return 0;
3440 }
3441
3442 /**
3443  *  e1000_id_led_init_pchlan - store LED configurations
3444  *  @hw: pointer to the HW structure
3445  *
3446  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3447  *  the PHY LED configuration register.
3448  *
3449  *  PCH also does not have an "always on" or "always off" mode which
3450  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3451  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3452  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3453  *  link based on logic in e1000_led_[on|off]_pchlan().
3454  **/
3455 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3456 {
3457         struct e1000_mac_info *mac = &hw->mac;
3458         s32 ret_val;
3459         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3460         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3461         u16 data, i, temp, shift;
3462
3463         /* Get default ID LED modes */
3464         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3465         if (ret_val)
3466                 return ret_val;
3467
3468         mac->ledctl_default = er32(LEDCTL);
3469         mac->ledctl_mode1 = mac->ledctl_default;
3470         mac->ledctl_mode2 = mac->ledctl_default;
3471
3472         for (i = 0; i < 4; i++) {
3473                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3474                 shift = (i * 5);
3475                 switch (temp) {
3476                 case ID_LED_ON1_DEF2:
3477                 case ID_LED_ON1_ON2:
3478                 case ID_LED_ON1_OFF2:
3479                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3480                         mac->ledctl_mode1 |= (ledctl_on << shift);
3481                         break;
3482                 case ID_LED_OFF1_DEF2:
3483                 case ID_LED_OFF1_ON2:
3484                 case ID_LED_OFF1_OFF2:
3485                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3486                         mac->ledctl_mode1 |= (ledctl_off << shift);
3487                         break;
3488                 default:
3489                         /* Do nothing */
3490                         break;
3491                 }
3492                 switch (temp) {
3493                 case ID_LED_DEF1_ON2:
3494                 case ID_LED_ON1_ON2:
3495                 case ID_LED_OFF1_ON2:
3496                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3497                         mac->ledctl_mode2 |= (ledctl_on << shift);
3498                         break;
3499                 case ID_LED_DEF1_OFF2:
3500                 case ID_LED_ON1_OFF2:
3501                 case ID_LED_OFF1_OFF2:
3502                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3503                         mac->ledctl_mode2 |= (ledctl_off << shift);
3504                         break;
3505                 default:
3506                         /* Do nothing */
3507                         break;
3508                 }
3509         }
3510
3511         return 0;
3512 }
3513
3514 /**
3515  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3516  *  @hw: pointer to the HW structure
3517  *
3518  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3519  *  register, so the the bus width is hard coded.
3520  **/
3521 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3522 {
3523         struct e1000_bus_info *bus = &hw->bus;
3524         s32 ret_val;
3525
3526         ret_val = e1000e_get_bus_info_pcie(hw);
3527
3528         /* ICH devices are "PCI Express"-ish.  They have
3529          * a configuration space, but do not contain
3530          * PCI Express Capability registers, so bus width
3531          * must be hardcoded.
3532          */
3533         if (bus->width == e1000_bus_width_unknown)
3534                 bus->width = e1000_bus_width_pcie_x1;
3535
3536         return ret_val;
3537 }
3538
3539 /**
3540  *  e1000_reset_hw_ich8lan - Reset the hardware
3541  *  @hw: pointer to the HW structure
3542  *
3543  *  Does a full reset of the hardware which includes a reset of the PHY and
3544  *  MAC.
3545  **/
3546 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3547 {
3548         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3549         u16 kum_cfg;
3550         u32 ctrl, reg;
3551         s32 ret_val;
3552
3553         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3554          * on the last TLP read/write transaction when MAC is reset.
3555          */
3556         ret_val = e1000e_disable_pcie_master(hw);
3557         if (ret_val)
3558                 e_dbg("PCI-E Master disable polling has failed.\n");
3559
3560         e_dbg("Masking off all interrupts\n");
3561         ew32(IMC, 0xffffffff);
3562
3563         /* Disable the Transmit and Receive units.  Then delay to allow
3564          * any pending transactions to complete before we hit the MAC
3565          * with the global reset.
3566          */
3567         ew32(RCTL, 0);
3568         ew32(TCTL, E1000_TCTL_PSP);
3569         e1e_flush();
3570
3571         usleep_range(10000, 20000);
3572
3573         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3574         if (hw->mac.type == e1000_ich8lan) {
3575                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3576                 ew32(PBA, E1000_PBA_8K);
3577                 /* Set Packet Buffer Size to 16k. */
3578                 ew32(PBS, E1000_PBS_16K);
3579         }
3580
3581         if (hw->mac.type == e1000_pchlan) {
3582                 /* Save the NVM K1 bit setting */
3583                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3584                 if (ret_val)
3585                         return ret_val;
3586
3587                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3588                         dev_spec->nvm_k1_enabled = true;
3589                 else
3590                         dev_spec->nvm_k1_enabled = false;
3591         }
3592
3593         ctrl = er32(CTRL);
3594
3595         if (!hw->phy.ops.check_reset_block(hw)) {
3596                 /* Full-chip reset requires MAC and PHY reset at the same
3597                  * time to make sure the interface between MAC and the
3598                  * external PHY is reset.
3599                  */
3600                 ctrl |= E1000_CTRL_PHY_RST;
3601
3602                 /* Gate automatic PHY configuration by hardware on
3603                  * non-managed 82579
3604                  */
3605                 if ((hw->mac.type == e1000_pch2lan) &&
3606                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3607                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3608         }
3609         ret_val = e1000_acquire_swflag_ich8lan(hw);
3610         e_dbg("Issuing a global reset to ich8lan\n");
3611         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3612         /* cannot issue a flush here because it hangs the hardware */
3613         msleep(20);
3614
3615         /* Set Phy Config Counter to 50msec */
3616         if (hw->mac.type == e1000_pch2lan) {
3617                 reg = er32(FEXTNVM3);
3618                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3619                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3620                 ew32(FEXTNVM3, reg);
3621         }
3622
3623         if (!ret_val)
3624                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3625
3626         if (ctrl & E1000_CTRL_PHY_RST) {
3627                 ret_val = hw->phy.ops.get_cfg_done(hw);
3628                 if (ret_val)
3629                         return ret_val;
3630
3631                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3632                 if (ret_val)
3633                         return ret_val;
3634         }
3635
3636         /* For PCH, this write will make sure that any noise
3637          * will be detected as a CRC error and be dropped rather than show up
3638          * as a bad packet to the DMA engine.
3639          */
3640         if (hw->mac.type == e1000_pchlan)
3641                 ew32(CRC_OFFSET, 0x65656565);
3642
3643         ew32(IMC, 0xffffffff);
3644         er32(ICR);
3645
3646         reg = er32(KABGTXD);
3647         reg |= E1000_KABGTXD_BGSQLBIAS;
3648         ew32(KABGTXD, reg);
3649
3650         return 0;
3651 }
3652
3653 /**
3654  *  e1000_init_hw_ich8lan - Initialize the hardware
3655  *  @hw: pointer to the HW structure
3656  *
3657  *  Prepares the hardware for transmit and receive by doing the following:
3658  *   - initialize hardware bits
3659  *   - initialize LED identification
3660  *   - setup receive address registers
3661  *   - setup flow control
3662  *   - setup transmit descriptors
3663  *   - clear statistics
3664  **/
3665 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3666 {
3667         struct e1000_mac_info *mac = &hw->mac;
3668         u32 ctrl_ext, txdctl, snoop;
3669         s32 ret_val;
3670         u16 i;
3671
3672         e1000_initialize_hw_bits_ich8lan(hw);
3673
3674         /* Initialize identification LED */
3675         ret_val = mac->ops.id_led_init(hw);
3676         /* An error is not fatal and we should not stop init due to this */
3677         if (ret_val)
3678                 e_dbg("Error initializing identification LED\n");
3679
3680         /* Setup the receive address. */
3681         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3682
3683         /* Zero out the Multicast HASH table */
3684         e_dbg("Zeroing the MTA\n");
3685         for (i = 0; i < mac->mta_reg_count; i++)
3686                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3687
3688         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3689          * the ME.  Disable wakeup by clearing the host wakeup bit.
3690          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3691          */
3692         if (hw->phy.type == e1000_phy_82578) {
3693                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3694                 i &= ~BM_WUC_HOST_WU_BIT;
3695                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3696                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3697                 if (ret_val)
3698                         return ret_val;
3699         }
3700
3701         /* Setup link and flow control */
3702         ret_val = mac->ops.setup_link(hw);
3703
3704         /* Set the transmit descriptor write-back policy for both queues */
3705         txdctl = er32(TXDCTL(0));
3706         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3707                   E1000_TXDCTL_FULL_TX_DESC_WB);
3708         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3709                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3710         ew32(TXDCTL(0), txdctl);
3711         txdctl = er32(TXDCTL(1));
3712         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3713                   E1000_TXDCTL_FULL_TX_DESC_WB);
3714         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3715                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3716         ew32(TXDCTL(1), txdctl);
3717
3718         /* ICH8 has opposite polarity of no_snoop bits.
3719          * By default, we should use snoop behavior.
3720          */
3721         if (mac->type == e1000_ich8lan)
3722                 snoop = PCIE_ICH8_SNOOP_ALL;
3723         else
3724                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
3725         e1000e_set_pcie_no_snoop(hw, snoop);
3726
3727         ctrl_ext = er32(CTRL_EXT);
3728         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3729         ew32(CTRL_EXT, ctrl_ext);
3730
3731         /* Clear all of the statistics registers (clear on read).  It is
3732          * important that we do this after we have tried to establish link
3733          * because the symbol error count will increment wildly if there
3734          * is no link.
3735          */
3736         e1000_clear_hw_cntrs_ich8lan(hw);
3737
3738         return ret_val;
3739 }
3740
3741 /**
3742  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3743  *  @hw: pointer to the HW structure
3744  *
3745  *  Sets/Clears required hardware bits necessary for correctly setting up the
3746  *  hardware for transmit and receive.
3747  **/
3748 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3749 {
3750         u32 reg;
3751
3752         /* Extended Device Control */
3753         reg = er32(CTRL_EXT);
3754         reg |= (1 << 22);
3755         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3756         if (hw->mac.type >= e1000_pchlan)
3757                 reg |= E1000_CTRL_EXT_PHYPDEN;
3758         ew32(CTRL_EXT, reg);
3759
3760         /* Transmit Descriptor Control 0 */
3761         reg = er32(TXDCTL(0));
3762         reg |= (1 << 22);
3763         ew32(TXDCTL(0), reg);
3764
3765         /* Transmit Descriptor Control 1 */
3766         reg = er32(TXDCTL(1));
3767         reg |= (1 << 22);
3768         ew32(TXDCTL(1), reg);
3769
3770         /* Transmit Arbitration Control 0 */
3771         reg = er32(TARC(0));
3772         if (hw->mac.type == e1000_ich8lan)
3773                 reg |= (1 << 28) | (1 << 29);
3774         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3775         ew32(TARC(0), reg);
3776
3777         /* Transmit Arbitration Control 1 */
3778         reg = er32(TARC(1));
3779         if (er32(TCTL) & E1000_TCTL_MULR)
3780                 reg &= ~(1 << 28);
3781         else
3782                 reg |= (1 << 28);
3783         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3784         ew32(TARC(1), reg);
3785
3786         /* Device Status */
3787         if (hw->mac.type == e1000_ich8lan) {
3788                 reg = er32(STATUS);
3789                 reg &= ~(1 << 31);
3790                 ew32(STATUS, reg);
3791         }
3792
3793         /* work-around descriptor data corruption issue during nfs v2 udp
3794          * traffic, just disable the nfs filtering capability
3795          */
3796         reg = er32(RFCTL);
3797         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3798
3799         /* Disable IPv6 extension header parsing because some malformed
3800          * IPv6 headers can hang the Rx.
3801          */
3802         if (hw->mac.type == e1000_ich8lan)
3803                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3804         ew32(RFCTL, reg);
3805
3806         /* Enable ECC on Lynxpoint */
3807         if (hw->mac.type == e1000_pch_lpt) {
3808                 reg = er32(PBECCSTS);
3809                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3810                 ew32(PBECCSTS, reg);
3811
3812                 reg = er32(CTRL);
3813                 reg |= E1000_CTRL_MEHE;
3814                 ew32(CTRL, reg);
3815         }
3816 }
3817
3818 /**
3819  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3820  *  @hw: pointer to the HW structure
3821  *
3822  *  Determines which flow control settings to use, then configures flow
3823  *  control.  Calls the appropriate media-specific link configuration
3824  *  function.  Assuming the adapter has a valid link partner, a valid link
3825  *  should be established.  Assumes the hardware has previously been reset
3826  *  and the transmitter and receiver are not enabled.
3827  **/
3828 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3829 {
3830         s32 ret_val;
3831
3832         if (hw->phy.ops.check_reset_block(hw))
3833                 return 0;
3834
3835         /* ICH parts do not have a word in the NVM to determine
3836          * the default flow control setting, so we explicitly
3837          * set it to full.
3838          */
3839         if (hw->fc.requested_mode == e1000_fc_default) {
3840                 /* Workaround h/w hang when Tx flow control enabled */
3841                 if (hw->mac.type == e1000_pchlan)
3842                         hw->fc.requested_mode = e1000_fc_rx_pause;
3843                 else
3844                         hw->fc.requested_mode = e1000_fc_full;
3845         }
3846
3847         /* Save off the requested flow control mode for use later.  Depending
3848          * on the link partner's capabilities, we may or may not use this mode.
3849          */
3850         hw->fc.current_mode = hw->fc.requested_mode;
3851
3852         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
3853
3854         /* Continue to configure the copper link. */
3855         ret_val = hw->mac.ops.setup_physical_interface(hw);
3856         if (ret_val)
3857                 return ret_val;
3858
3859         ew32(FCTTV, hw->fc.pause_time);
3860         if ((hw->phy.type == e1000_phy_82578) ||
3861             (hw->phy.type == e1000_phy_82579) ||
3862             (hw->phy.type == e1000_phy_i217) ||
3863             (hw->phy.type == e1000_phy_82577)) {
3864                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3865
3866                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3867                                    hw->fc.pause_time);
3868                 if (ret_val)
3869                         return ret_val;
3870         }
3871
3872         return e1000e_set_fc_watermarks(hw);
3873 }
3874
3875 /**
3876  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3877  *  @hw: pointer to the HW structure
3878  *
3879  *  Configures the kumeran interface to the PHY to wait the appropriate time
3880  *  when polling the PHY, then call the generic setup_copper_link to finish
3881  *  configuring the copper link.
3882  **/
3883 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3884 {
3885         u32 ctrl;
3886         s32 ret_val;
3887         u16 reg_data;
3888
3889         ctrl = er32(CTRL);
3890         ctrl |= E1000_CTRL_SLU;
3891         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3892         ew32(CTRL, ctrl);
3893
3894         /* Set the mac to wait the maximum time between each iteration
3895          * and increase the max iterations when polling the phy;
3896          * this fixes erroneous timeouts at 10Mbps.
3897          */
3898         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3899         if (ret_val)
3900                 return ret_val;
3901         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3902                                        &reg_data);
3903         if (ret_val)
3904                 return ret_val;
3905         reg_data |= 0x3F;
3906         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3907                                         reg_data);
3908         if (ret_val)
3909                 return ret_val;
3910
3911         switch (hw->phy.type) {
3912         case e1000_phy_igp_3:
3913                 ret_val = e1000e_copper_link_setup_igp(hw);
3914                 if (ret_val)
3915                         return ret_val;
3916                 break;
3917         case e1000_phy_bm:
3918         case e1000_phy_82578:
3919                 ret_val = e1000e_copper_link_setup_m88(hw);
3920                 if (ret_val)
3921                         return ret_val;
3922                 break;
3923         case e1000_phy_82577:
3924         case e1000_phy_82579:
3925                 ret_val = e1000_copper_link_setup_82577(hw);
3926                 if (ret_val)
3927                         return ret_val;
3928                 break;
3929         case e1000_phy_ife:
3930                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3931                 if (ret_val)
3932                         return ret_val;
3933
3934                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3935
3936                 switch (hw->phy.mdix) {
3937                 case 1:
3938                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3939                         break;
3940                 case 2:
3941                         reg_data |= IFE_PMC_FORCE_MDIX;
3942                         break;
3943                 case 0:
3944                 default:
3945                         reg_data |= IFE_PMC_AUTO_MDIX;
3946                         break;
3947                 }
3948                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3949                 if (ret_val)
3950                         return ret_val;
3951                 break;
3952         default:
3953                 break;
3954         }
3955
3956         return e1000e_setup_copper_link(hw);
3957 }
3958
3959 /**
3960  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
3961  *  @hw: pointer to the HW structure
3962  *
3963  *  Calls the PHY specific link setup function and then calls the
3964  *  generic setup_copper_link to finish configuring the link for
3965  *  Lynxpoint PCH devices
3966  **/
3967 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
3968 {
3969         u32 ctrl;
3970         s32 ret_val;
3971
3972         ctrl = er32(CTRL);
3973         ctrl |= E1000_CTRL_SLU;
3974         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3975         ew32(CTRL, ctrl);
3976
3977         ret_val = e1000_copper_link_setup_82577(hw);
3978         if (ret_val)
3979                 return ret_val;
3980
3981         return e1000e_setup_copper_link(hw);
3982 }
3983
3984 /**
3985  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3986  *  @hw: pointer to the HW structure
3987  *  @speed: pointer to store current link speed
3988  *  @duplex: pointer to store the current link duplex
3989  *
3990  *  Calls the generic get_speed_and_duplex to retrieve the current link
3991  *  information and then calls the Kumeran lock loss workaround for links at
3992  *  gigabit speeds.
3993  **/
3994 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3995                                           u16 *duplex)
3996 {
3997         s32 ret_val;
3998
3999         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4000         if (ret_val)
4001                 return ret_val;
4002
4003         if ((hw->mac.type == e1000_ich8lan) &&
4004             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4005                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4006         }
4007
4008         return ret_val;
4009 }
4010
4011 /**
4012  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4013  *  @hw: pointer to the HW structure
4014  *
4015  *  Work-around for 82566 Kumeran PCS lock loss:
4016  *  On link status change (i.e. PCI reset, speed change) and link is up and
4017  *  speed is gigabit-
4018  *    0) if workaround is optionally disabled do nothing
4019  *    1) wait 1ms for Kumeran link to come up
4020  *    2) check Kumeran Diagnostic register PCS lock loss bit
4021  *    3) if not set the link is locked (all is good), otherwise...
4022  *    4) reset the PHY
4023  *    5) repeat up to 10 times
4024  *  Note: this is only called for IGP3 copper when speed is 1gb.
4025  **/
4026 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4027 {
4028         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4029         u32 phy_ctrl;
4030         s32 ret_val;
4031         u16 i, data;
4032         bool link;
4033
4034         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4035                 return 0;
4036
4037         /* Make sure link is up before proceeding.  If not just return.
4038          * Attempting this while link is negotiating fouled up link
4039          * stability
4040          */
4041         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4042         if (!link)
4043                 return 0;
4044
4045         for (i = 0; i < 10; i++) {
4046                 /* read once to clear */
4047                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4048                 if (ret_val)
4049                         return ret_val;
4050                 /* and again to get new status */
4051                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4052                 if (ret_val)
4053                         return ret_val;
4054
4055                 /* check for PCS lock */
4056                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4057                         return 0;
4058
4059                 /* Issue PHY reset */
4060                 e1000_phy_hw_reset(hw);
4061                 mdelay(5);
4062         }
4063         /* Disable GigE link negotiation */
4064         phy_ctrl = er32(PHY_CTRL);
4065         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4066                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4067         ew32(PHY_CTRL, phy_ctrl);
4068
4069         /* Call gig speed drop workaround on Gig disable before accessing
4070          * any PHY registers
4071          */
4072         e1000e_gig_downshift_workaround_ich8lan(hw);
4073
4074         /* unable to acquire PCS lock */
4075         return -E1000_ERR_PHY;
4076 }
4077
4078 /**
4079  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4080  *  @hw: pointer to the HW structure
4081  *  @state: boolean value used to set the current Kumeran workaround state
4082  *
4083  *  If ICH8, set the current Kumeran workaround state (enabled - true
4084  *  /disabled - false).
4085  **/
4086 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4087                                                   bool state)
4088 {
4089         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4090
4091         if (hw->mac.type != e1000_ich8lan) {
4092                 e_dbg("Workaround applies to ICH8 only.\n");
4093                 return;
4094         }
4095
4096         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4097 }
4098
4099 /**
4100  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4101  *  @hw: pointer to the HW structure
4102  *
4103  *  Workaround for 82566 power-down on D3 entry:
4104  *    1) disable gigabit link
4105  *    2) write VR power-down enable
4106  *    3) read it back
4107  *  Continue if successful, else issue LCD reset and repeat
4108  **/
4109 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4110 {
4111         u32 reg;
4112         u16 data;
4113         u8 retry = 0;
4114
4115         if (hw->phy.type != e1000_phy_igp_3)
4116                 return;
4117
4118         /* Try the workaround twice (if needed) */
4119         do {
4120                 /* Disable link */
4121                 reg = er32(PHY_CTRL);
4122                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4123                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4124                 ew32(PHY_CTRL, reg);
4125
4126                 /* Call gig speed drop workaround on Gig disable before
4127                  * accessing any PHY registers
4128                  */
4129                 if (hw->mac.type == e1000_ich8lan)
4130                         e1000e_gig_downshift_workaround_ich8lan(hw);
4131
4132                 /* Write VR power-down enable */
4133                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4134                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4135                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4136
4137                 /* Read it back and test */
4138                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4139                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4140                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4141                         break;
4142
4143                 /* Issue PHY reset and repeat at most one more time */
4144                 reg = er32(CTRL);
4145                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4146                 retry++;
4147         } while (retry);
4148 }
4149
4150 /**
4151  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4152  *  @hw: pointer to the HW structure
4153  *
4154  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4155  *  LPLU, Gig disable, MDIC PHY reset):
4156  *    1) Set Kumeran Near-end loopback
4157  *    2) Clear Kumeran Near-end loopback
4158  *  Should only be called for ICH8[m] devices with any 1G Phy.
4159  **/
4160 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4161 {
4162         s32 ret_val;
4163         u16 reg_data;
4164
4165         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4166                 return;
4167
4168         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4169                                        &reg_data);
4170         if (ret_val)
4171                 return;
4172         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4173         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4174                                         reg_data);
4175         if (ret_val)
4176                 return;
4177         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4178         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4179 }
4180
4181 /**
4182  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4183  *  @hw: pointer to the HW structure
4184  *
4185  *  During S0 to Sx transition, it is possible the link remains at gig
4186  *  instead of negotiating to a lower speed.  Before going to Sx, set
4187  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4188  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4189  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4190  *  needs to be written.
4191  *  Parts that support (and are linked to a partner which support) EEE in
4192  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4193  *  than 10Mbps w/o EEE.
4194  **/
4195 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4196 {
4197         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4198         u32 phy_ctrl;
4199         s32 ret_val;
4200
4201         phy_ctrl = er32(PHY_CTRL);
4202         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4203
4204         if (hw->phy.type == e1000_phy_i217) {
4205                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4206
4207                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4208                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4209                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4210                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4211                         u32 fextnvm6 = er32(FEXTNVM6);
4212
4213                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4214                 }
4215
4216                 ret_val = hw->phy.ops.acquire(hw);
4217                 if (ret_val)
4218                         goto out;
4219
4220                 if (!dev_spec->eee_disable) {
4221                         u16 eee_advert;
4222
4223                         ret_val =
4224                             e1000_read_emi_reg_locked(hw,
4225                                                       I217_EEE_ADVERTISEMENT,
4226                                                       &eee_advert);
4227                         if (ret_val)
4228                                 goto release;
4229
4230                         /* Disable LPLU if both link partners support 100BaseT
4231                          * EEE and 100Full is advertised on both ends of the
4232                          * link.
4233                          */
4234                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4235                             (dev_spec->eee_lp_ability &
4236                              I82579_EEE_100_SUPPORTED) &&
4237                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4238                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4239                                               E1000_PHY_CTRL_NOND0A_LPLU);
4240                 }
4241
4242                 /* For i217 Intel Rapid Start Technology support,
4243                  * when the system is going into Sx and no manageability engine
4244                  * is present, the driver must configure proxy to reset only on
4245                  * power good.  LPI (Low Power Idle) state must also reset only
4246                  * on power good, as well as the MTA (Multicast table array).
4247                  * The SMBus release must also be disabled on LCD reset.
4248                  */
4249                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4250                         /* Enable proxy to reset only on power good. */
4251                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4252                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4253                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4254
4255                         /* Set bit enable LPI (EEE) to reset only on
4256                          * power good.
4257                          */
4258                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4259                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4260                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4261
4262                         /* Disable the SMB release on LCD reset. */
4263                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4264                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4265                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4266                 }
4267
4268                 /* Enable MTA to reset for Intel Rapid Start Technology
4269                  * Support
4270                  */
4271                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4272                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4273                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4274
4275 release:
4276                 hw->phy.ops.release(hw);
4277         }
4278 out:
4279         ew32(PHY_CTRL, phy_ctrl);
4280
4281         if (hw->mac.type == e1000_ich8lan)
4282                 e1000e_gig_downshift_workaround_ich8lan(hw);
4283
4284         if (hw->mac.type >= e1000_pchlan) {
4285                 e1000_oem_bits_config_ich8lan(hw, false);
4286
4287                 /* Reset PHY to activate OEM bits on 82577/8 */
4288                 if (hw->mac.type == e1000_pchlan)
4289                         e1000e_phy_hw_reset_generic(hw);
4290
4291                 ret_val = hw->phy.ops.acquire(hw);
4292                 if (ret_val)
4293                         return;
4294                 e1000_write_smbus_addr(hw);
4295                 hw->phy.ops.release(hw);
4296         }
4297 }
4298
4299 /**
4300  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4301  *  @hw: pointer to the HW structure
4302  *
4303  *  During Sx to S0 transitions on non-managed devices or managed devices
4304  *  on which PHY resets are not blocked, if the PHY registers cannot be
4305  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4306  *  the PHY.
4307  *  On i217, setup Intel Rapid Start Technology.
4308  **/
4309 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4310 {
4311         s32 ret_val;
4312
4313         if (hw->mac.type < e1000_pch2lan)
4314                 return;
4315
4316         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4317         if (ret_val) {
4318                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4319                 return;
4320         }
4321
4322         /* For i217 Intel Rapid Start Technology support when the system
4323          * is transitioning from Sx and no manageability engine is present
4324          * configure SMBus to restore on reset, disable proxy, and enable
4325          * the reset on MTA (Multicast table array).
4326          */
4327         if (hw->phy.type == e1000_phy_i217) {
4328                 u16 phy_reg;
4329
4330                 ret_val = hw->phy.ops.acquire(hw);
4331                 if (ret_val) {
4332                         e_dbg("Failed to setup iRST\n");
4333                         return;
4334                 }
4335
4336                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4337                         /* Restore clear on SMB if no manageability engine
4338                          * is present
4339                          */
4340                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4341                         if (ret_val)
4342                                 goto release;
4343                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4344                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4345
4346                         /* Disable Proxy */
4347                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4348                 }
4349                 /* Enable reset on MTA */
4350                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4351                 if (ret_val)
4352                         goto release;
4353                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4354                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4355 release:
4356                 if (ret_val)
4357                         e_dbg("Error %d in resume workarounds\n", ret_val);
4358                 hw->phy.ops.release(hw);
4359         }
4360 }
4361
4362 /**
4363  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4364  *  @hw: pointer to the HW structure
4365  *
4366  *  Return the LED back to the default configuration.
4367  **/
4368 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4369 {
4370         if (hw->phy.type == e1000_phy_ife)
4371                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4372
4373         ew32(LEDCTL, hw->mac.ledctl_default);
4374         return 0;
4375 }
4376
4377 /**
4378  *  e1000_led_on_ich8lan - Turn LEDs on
4379  *  @hw: pointer to the HW structure
4380  *
4381  *  Turn on the LEDs.
4382  **/
4383 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4384 {
4385         if (hw->phy.type == e1000_phy_ife)
4386                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4387                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4388
4389         ew32(LEDCTL, hw->mac.ledctl_mode2);
4390         return 0;
4391 }
4392
4393 /**
4394  *  e1000_led_off_ich8lan - Turn LEDs off
4395  *  @hw: pointer to the HW structure
4396  *
4397  *  Turn off the LEDs.
4398  **/
4399 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4400 {
4401         if (hw->phy.type == e1000_phy_ife)
4402                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4403                                 (IFE_PSCL_PROBE_MODE |
4404                                  IFE_PSCL_PROBE_LEDS_OFF));
4405
4406         ew32(LEDCTL, hw->mac.ledctl_mode1);
4407         return 0;
4408 }
4409
4410 /**
4411  *  e1000_setup_led_pchlan - Configures SW controllable LED
4412  *  @hw: pointer to the HW structure
4413  *
4414  *  This prepares the SW controllable LED for use.
4415  **/
4416 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4417 {
4418         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4419 }
4420
4421 /**
4422  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4423  *  @hw: pointer to the HW structure
4424  *
4425  *  Return the LED back to the default configuration.
4426  **/
4427 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4428 {
4429         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4430 }
4431
4432 /**
4433  *  e1000_led_on_pchlan - Turn LEDs on
4434  *  @hw: pointer to the HW structure
4435  *
4436  *  Turn on the LEDs.
4437  **/
4438 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4439 {
4440         u16 data = (u16)hw->mac.ledctl_mode2;
4441         u32 i, led;
4442
4443         /* If no link, then turn LED on by setting the invert bit
4444          * for each LED that's mode is "link_up" in ledctl_mode2.
4445          */
4446         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4447                 for (i = 0; i < 3; i++) {
4448                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4449                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4450                             E1000_LEDCTL_MODE_LINK_UP)
4451                                 continue;
4452                         if (led & E1000_PHY_LED0_IVRT)
4453                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4454                         else
4455                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4456                 }
4457         }
4458
4459         return e1e_wphy(hw, HV_LED_CONFIG, data);
4460 }
4461
4462 /**
4463  *  e1000_led_off_pchlan - Turn LEDs off
4464  *  @hw: pointer to the HW structure
4465  *
4466  *  Turn off the LEDs.
4467  **/
4468 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4469 {
4470         u16 data = (u16)hw->mac.ledctl_mode1;
4471         u32 i, led;
4472
4473         /* If no link, then turn LED off by clearing the invert bit
4474          * for each LED that's mode is "link_up" in ledctl_mode1.
4475          */
4476         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4477                 for (i = 0; i < 3; i++) {
4478                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4479                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4480                             E1000_LEDCTL_MODE_LINK_UP)
4481                                 continue;
4482                         if (led & E1000_PHY_LED0_IVRT)
4483                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4484                         else
4485                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4486                 }
4487         }
4488
4489         return e1e_wphy(hw, HV_LED_CONFIG, data);
4490 }
4491
4492 /**
4493  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4494  *  @hw: pointer to the HW structure
4495  *
4496  *  Read appropriate register for the config done bit for completion status
4497  *  and configure the PHY through s/w for EEPROM-less parts.
4498  *
4499  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4500  *  config done bit, so only an error is logged and continues.  If we were
4501  *  to return with error, EEPROM-less silicon would not be able to be reset
4502  *  or change link.
4503  **/
4504 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4505 {
4506         s32 ret_val = 0;
4507         u32 bank = 0;
4508         u32 status;
4509
4510         e1000e_get_cfg_done_generic(hw);
4511
4512         /* Wait for indication from h/w that it has completed basic config */
4513         if (hw->mac.type >= e1000_ich10lan) {
4514                 e1000_lan_init_done_ich8lan(hw);
4515         } else {
4516                 ret_val = e1000e_get_auto_rd_done(hw);
4517                 if (ret_val) {
4518                         /* When auto config read does not complete, do not
4519                          * return with an error. This can happen in situations
4520                          * where there is no eeprom and prevents getting link.
4521                          */
4522                         e_dbg("Auto Read Done did not complete\n");
4523                         ret_val = 0;
4524                 }
4525         }
4526
4527         /* Clear PHY Reset Asserted bit */
4528         status = er32(STATUS);
4529         if (status & E1000_STATUS_PHYRA)
4530                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4531         else
4532                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4533
4534         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4535         if (hw->mac.type <= e1000_ich9lan) {
4536                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4537                     (hw->phy.type == e1000_phy_igp_3)) {
4538                         e1000e_phy_init_script_igp3(hw);
4539                 }
4540         } else {
4541                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4542                         /* Maybe we should do a basic PHY config */
4543                         e_dbg("EEPROM not present\n");
4544                         ret_val = -E1000_ERR_CONFIG;
4545                 }
4546         }
4547
4548         return ret_val;
4549 }
4550
4551 /**
4552  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4553  * @hw: pointer to the HW structure
4554  *
4555  * In the case of a PHY power down to save power, or to turn off link during a
4556  * driver unload, or wake on lan is not enabled, remove the link.
4557  **/
4558 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4559 {
4560         /* If the management interface is not enabled, then power down */
4561         if (!(hw->mac.ops.check_mng_mode(hw) ||
4562               hw->phy.ops.check_reset_block(hw)))
4563                 e1000_power_down_phy_copper(hw);
4564 }
4565
4566 /**
4567  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4568  *  @hw: pointer to the HW structure
4569  *
4570  *  Clears hardware counters specific to the silicon family and calls
4571  *  clear_hw_cntrs_generic to clear all general purpose counters.
4572  **/
4573 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4574 {
4575         u16 phy_data;
4576         s32 ret_val;
4577
4578         e1000e_clear_hw_cntrs_base(hw);
4579
4580         er32(ALGNERRC);
4581         er32(RXERRC);
4582         er32(TNCRS);
4583         er32(CEXTERR);
4584         er32(TSCTC);
4585         er32(TSCTFC);
4586
4587         er32(MGTPRC);
4588         er32(MGTPDC);
4589         er32(MGTPTC);
4590
4591         er32(IAC);
4592         er32(ICRXOC);
4593
4594         /* Clear PHY statistics registers */
4595         if ((hw->phy.type == e1000_phy_82578) ||
4596             (hw->phy.type == e1000_phy_82579) ||
4597             (hw->phy.type == e1000_phy_i217) ||
4598             (hw->phy.type == e1000_phy_82577)) {
4599                 ret_val = hw->phy.ops.acquire(hw);
4600                 if (ret_val)
4601                         return;
4602                 ret_val = hw->phy.ops.set_page(hw,
4603                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4604                 if (ret_val)
4605                         goto release;
4606                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4607                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4608                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4609                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4610                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4611                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4612                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4613                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4614                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4615                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4616                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4617                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4618                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4619                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4620 release:
4621                 hw->phy.ops.release(hw);
4622         }
4623 }
4624
4625 static const struct e1000_mac_operations ich8_mac_ops = {
4626         /* check_mng_mode dependent on mac type */
4627         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4628         /* cleanup_led dependent on mac type */
4629         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4630         .get_bus_info           = e1000_get_bus_info_ich8lan,
4631         .set_lan_id             = e1000_set_lan_id_single_port,
4632         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4633         /* led_on dependent on mac type */
4634         /* led_off dependent on mac type */
4635         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4636         .reset_hw               = e1000_reset_hw_ich8lan,
4637         .init_hw                = e1000_init_hw_ich8lan,
4638         .setup_link             = e1000_setup_link_ich8lan,
4639         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4640         /* id_led_init dependent on mac type */
4641         .config_collision_dist  = e1000e_config_collision_dist_generic,
4642         .rar_set                = e1000e_rar_set_generic,
4643 };
4644
4645 static const struct e1000_phy_operations ich8_phy_ops = {
4646         .acquire                = e1000_acquire_swflag_ich8lan,
4647         .check_reset_block      = e1000_check_reset_block_ich8lan,
4648         .commit                 = NULL,
4649         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4650         .get_cable_length       = e1000e_get_cable_length_igp_2,
4651         .read_reg               = e1000e_read_phy_reg_igp,
4652         .release                = e1000_release_swflag_ich8lan,
4653         .reset                  = e1000_phy_hw_reset_ich8lan,
4654         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4655         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4656         .write_reg              = e1000e_write_phy_reg_igp,
4657 };
4658
4659 static const struct e1000_nvm_operations ich8_nvm_ops = {
4660         .acquire                = e1000_acquire_nvm_ich8lan,
4661         .read                   = e1000_read_nvm_ich8lan,
4662         .release                = e1000_release_nvm_ich8lan,
4663         .reload                 = e1000e_reload_nvm_generic,
4664         .update                 = e1000_update_nvm_checksum_ich8lan,
4665         .valid_led_default      = e1000_valid_led_default_ich8lan,
4666         .validate               = e1000_validate_nvm_checksum_ich8lan,
4667         .write                  = e1000_write_nvm_ich8lan,
4668 };
4669
4670 const struct e1000_info e1000_ich8_info = {
4671         .mac                    = e1000_ich8lan,
4672         .flags                  = FLAG_HAS_WOL
4673                                   | FLAG_IS_ICH
4674                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4675                                   | FLAG_HAS_AMT
4676                                   | FLAG_HAS_FLASH
4677                                   | FLAG_APME_IN_WUC,
4678         .pba                    = 8,
4679         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4680         .get_variants           = e1000_get_variants_ich8lan,
4681         .mac_ops                = &ich8_mac_ops,
4682         .phy_ops                = &ich8_phy_ops,
4683         .nvm_ops                = &ich8_nvm_ops,
4684 };
4685
4686 const struct e1000_info e1000_ich9_info = {
4687         .mac                    = e1000_ich9lan,
4688         .flags                  = FLAG_HAS_JUMBO_FRAMES
4689                                   | FLAG_IS_ICH
4690                                   | FLAG_HAS_WOL
4691                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4692                                   | FLAG_HAS_AMT
4693                                   | FLAG_HAS_FLASH
4694                                   | FLAG_APME_IN_WUC,
4695         .pba                    = 18,
4696         .max_hw_frame_size      = DEFAULT_JUMBO,
4697         .get_variants           = e1000_get_variants_ich8lan,
4698         .mac_ops                = &ich8_mac_ops,
4699         .phy_ops                = &ich8_phy_ops,
4700         .nvm_ops                = &ich8_nvm_ops,
4701 };
4702
4703 const struct e1000_info e1000_ich10_info = {
4704         .mac                    = e1000_ich10lan,
4705         .flags                  = FLAG_HAS_JUMBO_FRAMES
4706                                   | FLAG_IS_ICH
4707                                   | FLAG_HAS_WOL
4708                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4709                                   | FLAG_HAS_AMT
4710                                   | FLAG_HAS_FLASH
4711                                   | FLAG_APME_IN_WUC,
4712         .pba                    = 18,
4713         .max_hw_frame_size      = DEFAULT_JUMBO,
4714         .get_variants           = e1000_get_variants_ich8lan,
4715         .mac_ops                = &ich8_mac_ops,
4716         .phy_ops                = &ich8_phy_ops,
4717         .nvm_ops                = &ich8_nvm_ops,
4718 };
4719
4720 const struct e1000_info e1000_pch_info = {
4721         .mac                    = e1000_pchlan,
4722         .flags                  = FLAG_IS_ICH
4723                                   | FLAG_HAS_WOL
4724                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4725                                   | FLAG_HAS_AMT
4726                                   | FLAG_HAS_FLASH
4727                                   | FLAG_HAS_JUMBO_FRAMES
4728                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4729                                   | FLAG_APME_IN_WUC,
4730         .flags2                 = FLAG2_HAS_PHY_STATS,
4731         .pba                    = 26,
4732         .max_hw_frame_size      = 4096,
4733         .get_variants           = e1000_get_variants_ich8lan,
4734         .mac_ops                = &ich8_mac_ops,
4735         .phy_ops                = &ich8_phy_ops,
4736         .nvm_ops                = &ich8_nvm_ops,
4737 };
4738
4739 const struct e1000_info e1000_pch2_info = {
4740         .mac                    = e1000_pch2lan,
4741         .flags                  = FLAG_IS_ICH
4742                                   | FLAG_HAS_WOL
4743                                   | FLAG_HAS_HW_TIMESTAMP
4744                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4745                                   | FLAG_HAS_AMT
4746                                   | FLAG_HAS_FLASH
4747                                   | FLAG_HAS_JUMBO_FRAMES
4748                                   | FLAG_APME_IN_WUC,
4749         .flags2                 = FLAG2_HAS_PHY_STATS
4750                                   | FLAG2_HAS_EEE,
4751         .pba                    = 26,
4752         .max_hw_frame_size      = 9018,
4753         .get_variants           = e1000_get_variants_ich8lan,
4754         .mac_ops                = &ich8_mac_ops,
4755         .phy_ops                = &ich8_phy_ops,
4756         .nvm_ops                = &ich8_nvm_ops,
4757 };
4758
4759 const struct e1000_info e1000_pch_lpt_info = {
4760         .mac                    = e1000_pch_lpt,
4761         .flags                  = FLAG_IS_ICH
4762                                   | FLAG_HAS_WOL
4763                                   | FLAG_HAS_HW_TIMESTAMP
4764                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4765                                   | FLAG_HAS_AMT
4766                                   | FLAG_HAS_FLASH
4767                                   | FLAG_HAS_JUMBO_FRAMES
4768                                   | FLAG_APME_IN_WUC,
4769         .flags2                 = FLAG2_HAS_PHY_STATS
4770                                   | FLAG2_HAS_EEE,
4771         .pba                    = 26,
4772         .max_hw_frame_size      = 9018,
4773         .get_variants           = e1000_get_variants_ich8lan,
4774         .mac_ops                = &ich8_mac_ops,
4775         .phy_ops                = &ich8_phy_ops,
4776         .nvm_ops                = &ich8_nvm_ops,
4777 };