1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_VF 0x154C
48 #define I40E_DEV_ID_VF_HV 0x1571
50 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
51 (d) == I40E_DEV_ID_QSFP_B || \
52 (d) == I40E_DEV_ID_QSFP_C)
54 /* I40E_MASK is a macro used on 32 bit registers */
55 #define I40E_MASK(mask, shift) (mask << shift)
57 #define I40E_MAX_VSI_QP 16
58 #define I40E_MAX_VF_VSI 3
59 #define I40E_MAX_CHAINED_RX_BUFFERS 5
60 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62 /* Max default timeout in ms, */
63 #define I40E_MAX_NVM_TIMEOUT 18000
65 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
66 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
68 /* forward declaration */
70 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72 /* Data type manipulation macros. */
74 #define I40E_DESC_UNUSED(R) \
75 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
76 (R)->next_to_clean - (R)->next_to_use - 1)
78 /* bitfields for Tx queue mapping in QTX_CTL */
79 #define I40E_QTX_CTL_VF_QUEUE 0x0
80 #define I40E_QTX_CTL_VM_QUEUE 0x1
81 #define I40E_QTX_CTL_PF_QUEUE 0x2
83 /* debug masks - set these bits in hw->debug_mask to control output */
84 enum i40e_debug_mask {
85 I40E_DEBUG_INIT = 0x00000001,
86 I40E_DEBUG_RELEASE = 0x00000002,
88 I40E_DEBUG_LINK = 0x00000010,
89 I40E_DEBUG_PHY = 0x00000020,
90 I40E_DEBUG_HMC = 0x00000040,
91 I40E_DEBUG_NVM = 0x00000080,
92 I40E_DEBUG_LAN = 0x00000100,
93 I40E_DEBUG_FLOW = 0x00000200,
94 I40E_DEBUG_DCB = 0x00000400,
95 I40E_DEBUG_DIAG = 0x00000800,
96 I40E_DEBUG_FD = 0x00001000,
98 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
99 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
100 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
101 I40E_DEBUG_AQ_COMMAND = 0x06000000,
102 I40E_DEBUG_AQ = 0x0F000000,
104 I40E_DEBUG_USER = 0xF0000000,
106 I40E_DEBUG_ALL = 0xFFFFFFFF
109 /* These are structs for managing the hardware information and the operations.
110 * The structures of function pointers are filled out at init time when we
111 * know for sure exactly which hardware we're working with. This gives us the
112 * flexibility of using the same main driver code but adapting to slightly
113 * different hardware needs as new parts are developed. For this architecture,
114 * the Firmware and AdminQ are intended to insulate the driver from most of the
115 * future changes, but these structures will also do part of the job.
118 I40E_MAC_UNKNOWN = 0,
125 enum i40e_media_type {
126 I40E_MEDIA_TYPE_UNKNOWN = 0,
127 I40E_MEDIA_TYPE_FIBER,
128 I40E_MEDIA_TYPE_BASET,
129 I40E_MEDIA_TYPE_BACKPLANE,
132 I40E_MEDIA_TYPE_VIRTUAL
144 enum i40e_set_fc_aq_failures {
145 I40E_SET_FC_AQ_FAIL_NONE = 0,
146 I40E_SET_FC_AQ_FAIL_GET = 1,
147 I40E_SET_FC_AQ_FAIL_SET = 2,
148 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
149 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
161 I40E_VSI_TYPE_UNKNOWN
164 enum i40e_queue_type {
165 I40E_QUEUE_TYPE_RX = 0,
167 I40E_QUEUE_TYPE_PE_CEQ,
168 I40E_QUEUE_TYPE_UNKNOWN
171 struct i40e_link_status {
172 enum i40e_aq_phy_type phy_type;
173 enum i40e_aq_link_speed link_speed;
179 /* is Link Status Event notification to SW enabled */
186 struct i40e_phy_info {
187 struct i40e_link_status link_info;
188 struct i40e_link_status link_info_old;
189 u32 autoneg_advertised;
193 enum i40e_media_type media_type;
196 #define I40E_HW_CAP_MAX_GPIO 30
197 /* Capabilities of a PF or a VF or the whole device */
198 struct i40e_hw_capabilities {
200 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
201 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
202 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
210 bool evb_802_1_qbg; /* Edge Virtual Bridging */
211 bool evb_802_1_qbh; /* Bridge Port Extension */
219 u32 fd_filters_guaranteed;
220 u32 fd_filters_best_effort;
223 u32 rss_table_entry_width;
224 bool led[I40E_HW_CAP_MAX_GPIO];
225 bool sdp[I40E_HW_CAP_MAX_GPIO];
227 u32 num_flow_director_filters;
234 u32 num_msix_vectors;
235 u32 num_msix_vectors_vf;
245 struct i40e_mac_info {
246 enum i40e_mac_type type;
248 u8 perm_addr[ETH_ALEN];
249 u8 san_addr[ETH_ALEN];
250 u8 port_addr[ETH_ALEN];
254 enum i40e_aq_resources_ids {
255 I40E_NVM_RESOURCE_ID = 1
258 enum i40e_aq_resource_access_type {
259 I40E_RESOURCE_READ = 1,
263 struct i40e_nvm_info {
264 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
265 u64 hw_semaphore_wait; /* - || - */
266 u32 timeout; /* [ms] */
267 u16 sr_size; /* Shadow RAM size in words */
268 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
269 u16 version; /* NVM package version */
270 u32 eetrack; /* NVM data version */
273 /* definitions used in NVM update support */
275 enum i40e_nvmupd_cmd {
277 I40E_NVMUPD_READ_CON,
278 I40E_NVMUPD_READ_SNT,
279 I40E_NVMUPD_READ_LCB,
281 I40E_NVMUPD_WRITE_ERA,
282 I40E_NVMUPD_WRITE_CON,
283 I40E_NVMUPD_WRITE_SNT,
284 I40E_NVMUPD_WRITE_LCB,
285 I40E_NVMUPD_WRITE_SA,
286 I40E_NVMUPD_CSUM_CON,
288 I40E_NVMUPD_CSUM_LCB,
291 enum i40e_nvmupd_state {
292 I40E_NVMUPD_STATE_INIT,
293 I40E_NVMUPD_STATE_READING,
294 I40E_NVMUPD_STATE_WRITING
297 /* nvm_access definition and its masks/shifts need to be accessible to
298 * application, core driver, and shared code. Where is the right file?
300 #define I40E_NVM_READ 0xB
301 #define I40E_NVM_WRITE 0xC
303 #define I40E_NVM_MOD_PNT_MASK 0xFF
305 #define I40E_NVM_TRANS_SHIFT 8
306 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
307 #define I40E_NVM_CON 0x0
308 #define I40E_NVM_SNT 0x1
309 #define I40E_NVM_LCB 0x2
310 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
311 #define I40E_NVM_ERA 0x4
312 #define I40E_NVM_CSUM 0x8
314 #define I40E_NVM_ADAPT_SHIFT 16
315 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
317 #define I40E_NVMUPD_MAX_DATA 4096
318 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
320 struct i40e_nvm_access {
323 u32 offset; /* in bytes */
324 u32 data_size; /* in bytes */
330 i40e_bus_type_unknown = 0,
333 i40e_bus_type_pci_express,
334 i40e_bus_type_reserved
338 enum i40e_bus_speed {
339 i40e_bus_speed_unknown = 0,
340 i40e_bus_speed_33 = 33,
341 i40e_bus_speed_66 = 66,
342 i40e_bus_speed_100 = 100,
343 i40e_bus_speed_120 = 120,
344 i40e_bus_speed_133 = 133,
345 i40e_bus_speed_2500 = 2500,
346 i40e_bus_speed_5000 = 5000,
347 i40e_bus_speed_8000 = 8000,
348 i40e_bus_speed_reserved
352 enum i40e_bus_width {
353 i40e_bus_width_unknown = 0,
354 i40e_bus_width_pcie_x1 = 1,
355 i40e_bus_width_pcie_x2 = 2,
356 i40e_bus_width_pcie_x4 = 4,
357 i40e_bus_width_pcie_x8 = 8,
358 i40e_bus_width_32 = 32,
359 i40e_bus_width_64 = 64,
360 i40e_bus_width_reserved
364 struct i40e_bus_info {
365 enum i40e_bus_speed speed;
366 enum i40e_bus_width width;
367 enum i40e_bus_type type;
374 /* Flow control (FC) parameters */
375 struct i40e_fc_info {
376 enum i40e_fc_mode current_mode; /* FC mode in effect */
377 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
380 #define I40E_MAX_TRAFFIC_CLASS 8
381 #define I40E_MAX_USER_PRIORITY 8
382 #define I40E_DCBX_MAX_APPS 32
383 #define I40E_LLDPDU_SIZE 1500
385 /* IEEE 802.1Qaz ETS Configuration data */
386 struct i40e_ieee_ets_config {
390 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
391 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
392 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
395 /* IEEE 802.1Qaz ETS Recommendation data */
396 struct i40e_ieee_ets_recommend {
397 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
398 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
399 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
402 /* IEEE 802.1Qaz PFC Configuration data */
403 struct i40e_ieee_pfc_config {
410 /* IEEE 802.1Qaz Application Priority data */
411 struct i40e_ieee_app_priority_table {
417 struct i40e_dcbx_config {
419 struct i40e_ieee_ets_config etscfg;
420 struct i40e_ieee_ets_recommend etsrec;
421 struct i40e_ieee_pfc_config pfc;
422 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
425 /* Port hardware description */
430 /* function pointer structs */
431 struct i40e_phy_info phy;
432 struct i40e_mac_info mac;
433 struct i40e_bus_info bus;
434 struct i40e_nvm_info nvm;
435 struct i40e_fc_info fc;
440 u16 subsystem_device_id;
441 u16 subsystem_vendor_id;
444 bool adapter_stopped;
446 /* capabilities for entire device and PCI func */
447 struct i40e_hw_capabilities dev_caps;
448 struct i40e_hw_capabilities func_caps;
450 /* Flow Director shared filter space */
451 u16 fdir_shared_filter_count;
453 /* device profile info */
457 /* Closest numa node to the device */
460 /* Admin Queue info */
461 struct i40e_adminq_info aq;
463 /* state of nvm update process */
464 enum i40e_nvmupd_state nvmupd_state;
467 struct i40e_hmc_info hmc; /* HMC info struct */
469 /* LLDP/DCBX Status */
473 struct i40e_dcbx_config local_dcbx_config;
474 struct i40e_dcbx_config remote_dcbx_config;
480 struct i40e_driver_version {
485 u8 driver_string[32];
489 union i40e_16byte_rx_desc {
491 __le64 pkt_addr; /* Packet buffer address */
492 __le64 hdr_addr; /* Header buffer address */
498 __le16 mirroring_status;
504 __le32 rss; /* RSS Hash */
505 __le32 fd_id; /* Flow director filter id */
506 __le32 fcoe_param; /* FCoE DDP Context id */
510 /* ext status/error/pktype/length */
511 __le64 status_error_len;
513 } wb; /* writeback */
516 union i40e_32byte_rx_desc {
518 __le64 pkt_addr; /* Packet buffer address */
519 __le64 hdr_addr; /* Header buffer address */
520 /* bit 0 of hdr_buffer_addr is DD bit */
528 __le16 mirroring_status;
534 __le32 rss; /* RSS Hash */
535 __le32 fcoe_param; /* FCoE DDP Context id */
536 /* Flow director filter id in case of
537 * Programming status desc WB
543 /* status/error/pktype/length */
544 __le64 status_error_len;
547 __le16 ext_status; /* extended status */
554 __le32 flex_bytes_lo;
558 __le32 flex_bytes_hi;
562 } wb; /* writeback */
565 enum i40e_rx_desc_status_bits {
566 /* Note: These are predefined bit offsets */
567 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
568 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
569 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
570 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
571 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
572 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
573 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
574 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
575 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
576 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
577 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
578 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
579 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
580 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
581 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
582 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
585 #define I40E_RXD_QW1_STATUS_SHIFT 0
586 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
587 << I40E_RXD_QW1_STATUS_SHIFT)
589 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
590 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
591 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
593 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
594 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
595 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
597 enum i40e_rx_desc_fltstat_values {
598 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
599 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
600 I40E_RX_DESC_FLTSTAT_RSV = 2,
601 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
604 #define I40E_RXD_QW1_ERROR_SHIFT 19
605 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
607 enum i40e_rx_desc_error_bits {
608 /* Note: These are predefined bit offsets */
609 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
610 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
611 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
612 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
613 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
614 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
615 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
616 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
617 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
620 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
621 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
622 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
623 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
624 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
625 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
628 #define I40E_RXD_QW1_PTYPE_SHIFT 30
629 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
631 /* Packet type non-ip values */
632 enum i40e_rx_l2_ptype {
633 I40E_RX_PTYPE_L2_RESERVED = 0,
634 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
635 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
636 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
637 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
638 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
639 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
640 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
641 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
642 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
643 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
644 I40E_RX_PTYPE_L2_ARP = 11,
645 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
646 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
647 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
648 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
649 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
650 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
651 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
652 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
653 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
654 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
655 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
656 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
657 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
658 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
661 struct i40e_rx_ptype_decoded {
668 u32 tunnel_end_prot:2;
669 u32 tunnel_end_frag:1;
674 enum i40e_rx_ptype_outer_ip {
675 I40E_RX_PTYPE_OUTER_L2 = 0,
676 I40E_RX_PTYPE_OUTER_IP = 1
679 enum i40e_rx_ptype_outer_ip_ver {
680 I40E_RX_PTYPE_OUTER_NONE = 0,
681 I40E_RX_PTYPE_OUTER_IPV4 = 0,
682 I40E_RX_PTYPE_OUTER_IPV6 = 1
685 enum i40e_rx_ptype_outer_fragmented {
686 I40E_RX_PTYPE_NOT_FRAG = 0,
687 I40E_RX_PTYPE_FRAG = 1
690 enum i40e_rx_ptype_tunnel_type {
691 I40E_RX_PTYPE_TUNNEL_NONE = 0,
692 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
693 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
694 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
695 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
698 enum i40e_rx_ptype_tunnel_end_prot {
699 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
700 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
701 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
704 enum i40e_rx_ptype_inner_prot {
705 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
706 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
707 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
708 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
709 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
710 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
713 enum i40e_rx_ptype_payload_layer {
714 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
715 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
716 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
717 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
720 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
721 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
722 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
724 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
725 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
726 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
728 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
729 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
730 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
732 enum i40e_rx_desc_ext_status_bits {
733 /* Note: These are predefined bit offsets */
734 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
735 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
736 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
737 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
738 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
739 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
740 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
743 enum i40e_rx_desc_pe_status_bits {
744 /* Note: These are predefined bit offsets */
745 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
746 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
747 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
748 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
749 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
750 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
751 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
752 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
753 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
756 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
757 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
759 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
760 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
761 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
763 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
764 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
765 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
767 enum i40e_rx_prog_status_desc_status_bits {
768 /* Note: These are predefined bit offsets */
769 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
770 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
773 enum i40e_rx_prog_status_desc_prog_id_masks {
774 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
775 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
776 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
779 enum i40e_rx_prog_status_desc_error_bits {
780 /* Note: These are predefined bit offsets */
781 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
782 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
783 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
784 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
788 struct i40e_tx_desc {
789 __le64 buffer_addr; /* Address of descriptor's data buf */
790 __le64 cmd_type_offset_bsz;
793 #define I40E_TXD_QW1_DTYPE_SHIFT 0
794 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
796 enum i40e_tx_desc_dtype_value {
797 I40E_TX_DESC_DTYPE_DATA = 0x0,
798 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
799 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
800 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
801 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
802 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
803 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
804 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
805 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
806 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
809 #define I40E_TXD_QW1_CMD_SHIFT 4
810 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
812 enum i40e_tx_desc_cmd_bits {
813 I40E_TX_DESC_CMD_EOP = 0x0001,
814 I40E_TX_DESC_CMD_RS = 0x0002,
815 I40E_TX_DESC_CMD_ICRC = 0x0004,
816 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
817 I40E_TX_DESC_CMD_DUMMY = 0x0010,
818 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
819 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
820 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
821 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
822 I40E_TX_DESC_CMD_FCOET = 0x0080,
823 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
824 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
825 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
826 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
827 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
828 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
829 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
830 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
833 #define I40E_TXD_QW1_OFFSET_SHIFT 16
834 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
835 I40E_TXD_QW1_OFFSET_SHIFT)
837 enum i40e_tx_desc_length_fields {
838 /* Note: These are predefined bit offsets */
839 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
840 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
841 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
844 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
845 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
846 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
848 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
849 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
851 /* Context descriptors */
852 struct i40e_tx_context_desc {
853 __le32 tunneling_params;
856 __le64 type_cmd_tso_mss;
859 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
860 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
862 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
863 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
865 enum i40e_tx_ctx_desc_cmd_bits {
866 I40E_TX_CTX_DESC_TSO = 0x01,
867 I40E_TX_CTX_DESC_TSYN = 0x02,
868 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
869 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
870 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
871 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
872 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
873 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
874 I40E_TX_CTX_DESC_SWPE = 0x40
877 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
878 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
879 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
881 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
882 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
883 I40E_TXD_CTX_QW1_MSS_SHIFT)
885 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
886 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
888 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
889 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
890 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
892 enum i40e_tx_ctx_desc_eipt_offload {
893 I40E_TX_CTX_EXT_IP_NONE = 0x0,
894 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
895 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
896 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
899 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
900 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
901 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
903 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
904 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
906 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
907 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
909 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
910 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
911 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
913 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
915 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
916 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
917 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
919 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
920 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
921 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
923 struct i40e_filter_program_desc {
924 __le32 qindex_flex_ptype_vsi;
926 __le32 dtype_cmd_cntindex;
929 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
930 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
931 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
932 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
933 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
934 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
935 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
936 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
937 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
939 /* Packet Classifier Types for filters */
940 enum i40e_filter_pctype {
941 /* Note: Values 0-30 are reserved for future use */
942 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
943 /* Note: Value 32 is reserved for future use */
944 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
945 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
946 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
947 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
948 /* Note: Values 37-40 are reserved for future use */
949 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
950 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
951 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
952 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
953 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
954 /* Note: Value 47 is reserved for future use */
955 I40E_FILTER_PCTYPE_FCOE_OX = 48,
956 I40E_FILTER_PCTYPE_FCOE_RX = 49,
957 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
958 /* Note: Values 51-62 are reserved for future use */
959 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
962 enum i40e_filter_program_desc_dest {
963 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
964 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
965 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
968 enum i40e_filter_program_desc_fd_status {
969 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
970 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
971 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
972 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
975 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
976 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
977 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
979 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
980 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
981 I40E_TXD_FLTR_QW1_CMD_SHIFT)
983 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
984 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
986 enum i40e_filter_program_desc_pcmd {
987 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
988 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
991 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
992 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
994 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
995 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
996 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
998 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
999 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1000 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1001 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1003 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1004 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1005 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1007 enum i40e_filter_type {
1008 I40E_FLOW_DIRECTOR_FLTR = 0,
1009 I40E_PE_QUAD_HASH_FLTR = 1,
1010 I40E_ETHERTYPE_FLTR,
1016 struct i40e_vsi_context {
1021 u16 vsis_unallocated;
1026 struct i40e_aqc_vsi_properties_data info;
1029 struct i40e_veb_context {
1034 u16 vebs_unallocated;
1036 struct i40e_aqc_get_veb_parameters_completion info;
1039 /* Statistics collected by each port, VSI, VEB, and S-channel */
1040 struct i40e_eth_stats {
1041 u64 rx_bytes; /* gorc */
1042 u64 rx_unicast; /* uprc */
1043 u64 rx_multicast; /* mprc */
1044 u64 rx_broadcast; /* bprc */
1045 u64 rx_discards; /* rdpc */
1046 u64 rx_unknown_protocol; /* rupp */
1047 u64 tx_bytes; /* gotc */
1048 u64 tx_unicast; /* uptc */
1049 u64 tx_multicast; /* mptc */
1050 u64 tx_broadcast; /* bptc */
1051 u64 tx_discards; /* tdpc */
1052 u64 tx_errors; /* tepc */
1056 /* Statistics collected per function for FCoE */
1057 struct i40e_fcoe_stats {
1058 u64 rx_fcoe_packets; /* fcoeprc */
1059 u64 rx_fcoe_dwords; /* focedwrc */
1060 u64 rx_fcoe_dropped; /* fcoerpdc */
1061 u64 tx_fcoe_packets; /* fcoeptc */
1062 u64 tx_fcoe_dwords; /* focedwtc */
1063 u64 fcoe_bad_fccrc; /* fcoecrc */
1064 u64 fcoe_last_error; /* fcoelast */
1065 u64 fcoe_ddp_count; /* fcoeddpc */
1068 /* offset to per function FCoE statistics block */
1069 #define I40E_FCOE_VF_STAT_OFFSET 0
1070 #define I40E_FCOE_PF_STAT_OFFSET 128
1071 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1074 /* Statistics collected by the MAC */
1075 struct i40e_hw_port_stats {
1076 /* eth stats collected by the port */
1077 struct i40e_eth_stats eth;
1079 /* additional port specific stats */
1080 u64 tx_dropped_link_down; /* tdold */
1081 u64 crc_errors; /* crcerrs */
1082 u64 illegal_bytes; /* illerrc */
1083 u64 error_bytes; /* errbc */
1084 u64 mac_local_faults; /* mlfc */
1085 u64 mac_remote_faults; /* mrfc */
1086 u64 rx_length_errors; /* rlec */
1087 u64 link_xon_rx; /* lxonrxc */
1088 u64 link_xoff_rx; /* lxoffrxc */
1089 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1090 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1091 u64 link_xon_tx; /* lxontxc */
1092 u64 link_xoff_tx; /* lxofftxc */
1093 u64 priority_xon_tx[8]; /* pxontxc[8] */
1094 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1095 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1096 u64 rx_size_64; /* prc64 */
1097 u64 rx_size_127; /* prc127 */
1098 u64 rx_size_255; /* prc255 */
1099 u64 rx_size_511; /* prc511 */
1100 u64 rx_size_1023; /* prc1023 */
1101 u64 rx_size_1522; /* prc1522 */
1102 u64 rx_size_big; /* prc9522 */
1103 u64 rx_undersize; /* ruc */
1104 u64 rx_fragments; /* rfc */
1105 u64 rx_oversize; /* roc */
1106 u64 rx_jabber; /* rjc */
1107 u64 tx_size_64; /* ptc64 */
1108 u64 tx_size_127; /* ptc127 */
1109 u64 tx_size_255; /* ptc255 */
1110 u64 tx_size_511; /* ptc511 */
1111 u64 tx_size_1023; /* ptc1023 */
1112 u64 tx_size_1522; /* ptc1522 */
1113 u64 tx_size_big; /* ptc9522 */
1114 u64 mac_short_packet_dropped; /* mspdc */
1115 u64 checksum_error; /* xec */
1116 /* flow director stats */
1122 u64 tx_lpi_count; /* etlpic */
1123 u64 rx_lpi_count; /* erlpic */
1126 /* Checksum and Shadow RAM pointers */
1127 #define I40E_SR_NVM_CONTROL_WORD 0x00
1128 #define I40E_SR_EMP_MODULE_PTR 0x0F
1129 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1130 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1131 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1132 #define I40E_SR_NVM_EETRACK_LO 0x2D
1133 #define I40E_SR_NVM_EETRACK_HI 0x2E
1134 #define I40E_SR_VPD_PTR 0x2F
1135 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1136 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1138 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1139 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1140 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1141 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1142 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1144 /* Shadow RAM related */
1145 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1146 #define I40E_SR_WORDS_IN_1KB 512
1147 /* Checksum should be calculated such that after adding all the words,
1148 * including the checksum word itself, the sum should be 0xBABA.
1150 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1152 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1155 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1157 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1158 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1159 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1160 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1161 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1162 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1163 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1164 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1165 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1166 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1167 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1168 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1169 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1170 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1173 /* FCoE DDP Context descriptor */
1174 struct i40e_fcoe_ddp_context_desc {
1176 __le64 type_cmd_foff_lsize;
1179 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1180 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1181 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1183 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1184 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1185 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1187 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1188 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1189 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1190 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1191 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1192 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1193 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1196 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1197 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1198 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1200 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1201 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1202 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1204 /* FCoE DDP/DWO Queue Context descriptor */
1205 struct i40e_fcoe_queue_context_desc {
1206 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1207 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1210 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1211 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1212 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1214 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1215 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1216 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1218 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1219 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1220 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1222 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1223 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1224 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1226 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1227 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1228 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1231 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1232 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1233 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1235 /* FCoE DDP/DWO Filter Context descriptor */
1236 struct i40e_fcoe_filter_context_desc {
1240 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1241 __le16 rsvd_dmaindx;
1243 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1244 __le64 flags_rsvd_lanq;
1247 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1248 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1249 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1251 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1252 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1253 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1254 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1255 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1256 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1257 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1260 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1261 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1262 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1264 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1265 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1266 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1268 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1269 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1270 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1272 #endif /* I40E_FCOE */
1273 enum i40e_switch_element_types {
1274 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1275 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1276 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1277 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1278 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1279 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1280 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1281 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1282 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1285 /* Supported EtherType filters */
1286 enum i40e_ether_type_index {
1287 I40E_ETHER_TYPE_1588 = 0,
1288 I40E_ETHER_TYPE_FIP = 1,
1289 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1290 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1291 I40E_ETHER_TYPE_LLDP = 4,
1292 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1293 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1294 I40E_ETHER_TYPE_QCN_CNM = 7,
1295 I40E_ETHER_TYPE_8021X = 8,
1296 I40E_ETHER_TYPE_ARP = 9,
1297 I40E_ETHER_TYPE_RSV1 = 10,
1298 I40E_ETHER_TYPE_RSV2 = 11,
1301 /* Filter context base size is 1K */
1302 #define I40E_HASH_FILTER_BASE_SIZE 1024
1303 /* Supported Hash filter values */
1304 enum i40e_hash_filter_size {
1305 I40E_HASH_FILTER_SIZE_1K = 0,
1306 I40E_HASH_FILTER_SIZE_2K = 1,
1307 I40E_HASH_FILTER_SIZE_4K = 2,
1308 I40E_HASH_FILTER_SIZE_8K = 3,
1309 I40E_HASH_FILTER_SIZE_16K = 4,
1310 I40E_HASH_FILTER_SIZE_32K = 5,
1311 I40E_HASH_FILTER_SIZE_64K = 6,
1312 I40E_HASH_FILTER_SIZE_128K = 7,
1313 I40E_HASH_FILTER_SIZE_256K = 8,
1314 I40E_HASH_FILTER_SIZE_512K = 9,
1315 I40E_HASH_FILTER_SIZE_1M = 10,
1318 /* DMA context base size is 0.5K */
1319 #define I40E_DMA_CNTX_BASE_SIZE 512
1320 /* Supported DMA context values */
1321 enum i40e_dma_cntx_size {
1322 I40E_DMA_CNTX_SIZE_512 = 0,
1323 I40E_DMA_CNTX_SIZE_1K = 1,
1324 I40E_DMA_CNTX_SIZE_2K = 2,
1325 I40E_DMA_CNTX_SIZE_4K = 3,
1326 I40E_DMA_CNTX_SIZE_8K = 4,
1327 I40E_DMA_CNTX_SIZE_16K = 5,
1328 I40E_DMA_CNTX_SIZE_32K = 6,
1329 I40E_DMA_CNTX_SIZE_64K = 7,
1330 I40E_DMA_CNTX_SIZE_128K = 8,
1331 I40E_DMA_CNTX_SIZE_256K = 9,
1334 /* Supported Hash look up table (LUT) sizes */
1335 enum i40e_hash_lut_size {
1336 I40E_HASH_LUT_SIZE_128 = 0,
1337 I40E_HASH_LUT_SIZE_512 = 1,
1340 /* Structure to hold a per PF filter control settings */
1341 struct i40e_filter_control_settings {
1342 /* number of PE Quad Hash filter buckets */
1343 enum i40e_hash_filter_size pe_filt_num;
1344 /* number of PE Quad Hash contexts */
1345 enum i40e_dma_cntx_size pe_cntx_num;
1346 /* number of FCoE filter buckets */
1347 enum i40e_hash_filter_size fcoe_filt_num;
1348 /* number of FCoE DDP contexts */
1349 enum i40e_dma_cntx_size fcoe_cntx_num;
1350 /* size of the Hash LUT */
1351 enum i40e_hash_lut_size hash_lut_size;
1352 /* enable FDIR filters for PF and its VFs */
1354 /* enable Ethertype filters for PF and its VFs */
1355 bool enable_ethtype;
1356 /* enable MAC/VLAN filters for PF and its VFs */
1357 bool enable_macvlan;
1360 /* Structure to hold device level control filter counts */
1361 struct i40e_control_filter_stats {
1362 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1363 u16 etype_used; /* Used perfect EtherType filters */
1364 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1365 u16 etype_free; /* Un-used perfect EtherType filters */
1368 enum i40e_reset_type {
1370 I40E_RESET_CORER = 1,
1371 I40E_RESET_GLOBR = 2,
1372 I40E_RESET_EMPR = 3,
1375 /* RSS Hash Table Size */
1376 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1377 #endif /* _I40E_TYPE_H_ */