drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2016 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  31
  32 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_mac_info *mac = &hw->mac;
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so simular */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  41                 phy->ops.set_phy_power = NULL;
  42
  43         return 0;
  44 }
  45
  46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  47  *  @hw: pointer to hardware structure
  48  **/
  49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  50 {
  51         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  52
  53         if (hw->bus.lan_id) {
  54                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  55                 esdp |= IXGBE_ESDP_SDP1_DIR;
  56         }
  57         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  58         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  59         IXGBE_WRITE_FLUSH(hw);
  60 }
  61
  62 /**
  63  * ixgbe_read_cs4227 - Read CS4227 register
  64  * @hw: pointer to hardware structure
  65  * @reg: register number to write
  66  * @value: pointer to receive value read
  67  *
  68  * Returns status code
  69  */
  70 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  71 {
  72         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  73                                                       value);
  74 }
  75
  76 /**
  77  * ixgbe_write_cs4227 - Write CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: value to write to register
  81  *
  82  * Returns status code
  83  */
  84 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  85 {
  86         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  87                                                        value);
  88 }
  89
  90 /**
  91  * ixgbe_read_pe - Read register from port expander
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to read
  94  * @value: pointer to receive read value
  95  *
  96  * Returns status code
  97  */
  98 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  99 {
 100         s32 status;
 101
 102         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 103         if (status)
 104                 hw_err(hw, "port expander access failed with %d\n", status);
 105         return status;
 106 }
 107
 108 /**
 109  * ixgbe_write_pe - Write register to port expander
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write
 113  *
 114  * Returns status code
 115  */
 116 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 117 {
 118         s32 status;
 119
 120         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 121                                                        value);
 122         if (status)
 123                 hw_err(hw, "port expander access failed with %d\n", status);
 124         return status;
 125 }
 126
 127 /**
 128  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 129  * @hw: pointer to hardware structure
 130  *
 131  * This function assumes that the caller has acquired the proper semaphore.
 132  * Returns error code
 133  */
 134 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 135 {
 136         s32 status;
 137         u32 retry;
 138         u16 value;
 139         u8 reg;
 140
 141         /* Trigger hard reset. */
 142         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 143         if (status)
 144                 return status;
 145         reg |= IXGBE_PE_BIT1;
 146         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 147         if (status)
 148                 return status;
 149
 150         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 151         if (status)
 152                 return status;
 153         reg &= ~IXGBE_PE_BIT1;
 154         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 155         if (status)
 156                 return status;
 157
 158         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 159         if (status)
 160                 return status;
 161         reg &= ~IXGBE_PE_BIT1;
 162         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 163         if (status)
 164                 return status;
 165
 166         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 167
 168         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 169         if (status)
 170                 return status;
 171         reg |= IXGBE_PE_BIT1;
 172         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 173         if (status)
 174                 return status;
 175
 176         /* Wait for the reset to complete. */
 177         msleep(IXGBE_CS4227_RESET_DELAY);
 178         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 179                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 180                                            &value);
 181                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 182                         break;
 183                 msleep(IXGBE_CS4227_CHECK_DELAY);
 184         }
 185         if (retry == IXGBE_CS4227_RETRIES) {
 186                 hw_err(hw, "CS4227 reset did not complete\n");
 187                 return IXGBE_ERR_PHY;
 188         }
 189
 190         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 191         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 192                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 193                 return IXGBE_ERR_PHY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 201  * @hw: pointer to hardware structure
 202  */
 203 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 204 {
 205         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 206         s32 status;
 207         u16 value;
 208         u8 retry;
 209
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 212                 if (status) {
 213                         hw_err(hw, "semaphore failed with %d\n", status);
 214                         msleep(IXGBE_CS4227_CHECK_DELAY);
 215                         continue;
 216                 }
 217
 218                 /* Get status of reset flow. */
 219                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 220                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 221                         goto out;
 222
 223                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 224                         break;
 225
 226                 /* Reset is pending. Wait and check again. */
 227                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 228                 msleep(IXGBE_CS4227_CHECK_DELAY);
 229         }
 230         /* If still pending, assume other instance failed. */
 231         if (retry == IXGBE_CS4227_RETRIES) {
 232                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 233                 if (status) {
 234                         hw_err(hw, "semaphore failed with %d\n", status);
 235                         return;
 236                 }
 237         }
 238
 239         /* Reset the CS4227. */
 240         status = ixgbe_reset_cs4227(hw);
 241         if (status) {
 242                 hw_err(hw, "CS4227 reset failed: %d", status);
 243                 goto out;
 244         }
 245
 246         /* Reset takes so long, temporarily release semaphore in case the
 247          * other driver instance is waiting for the reset indication.
 248          */
 249         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 250                            IXGBE_CS4227_RESET_PENDING);
 251         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 252         usleep_range(10000, 12000);
 253         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254         if (status) {
 255                 hw_err(hw, "semaphore failed with %d", status);
 256                 return;
 257         }
 258
 259         /* Record completion for next time. */
 260         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 261                                     IXGBE_CS4227_RESET_COMPLETE);
 262
 263 out:
 264         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 265         msleep(hw->eeprom.semaphore_delay);
 266 }
 267
 268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 269  *  @hw: pointer to hardware structure
 270  *
 271  *  Returns error code
 272  */
 273 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 274 {
 275         switch (hw->device_id) {
 276         case IXGBE_DEV_ID_X550EM_A_SFP:
 277                 if (hw->bus.lan_id)
 278                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 279                 else
 280                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 281                 return ixgbe_identify_module_generic(hw);
 282         case IXGBE_DEV_ID_X550EM_X_SFP:
 283                 /* set up for CS4227 usage */
 284                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 285                 ixgbe_setup_mux_ctl(hw);
 286                 ixgbe_check_cs4227(hw);
 287                 /* Fallthrough */
 288         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 289                 return ixgbe_identify_module_generic(hw);
 290         case IXGBE_DEV_ID_X550EM_X_KX4:
 291                 hw->phy.type = ixgbe_phy_x550em_kx4;
 292                 break;
 293         case IXGBE_DEV_ID_X550EM_X_KR:
 294                 hw->phy.type = ixgbe_phy_x550em_kr;
 295                 break;
 296         case IXGBE_DEV_ID_X550EM_X_1G_T:
 297         case IXGBE_DEV_ID_X550EM_X_10G_T:
 298                 return ixgbe_identify_phy_generic(hw);
 299         default:
 300                 break;
 301         }
 302         return 0;
 303 }
 304
 305 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 306                                      u32 device_type, u16 *phy_data)
 307 {
 308         return IXGBE_NOT_IMPLEMENTED;
 309 }
 310
 311 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 312                                       u32 device_type, u16 phy_data)
 313 {
 314         return IXGBE_NOT_IMPLEMENTED;
 315 }
 316
 317 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 318  *  @hw: pointer to hardware structure
 319  *
 320  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 321  *  ixgbe_hw struct in order to set up EEPROM access.
 322  **/
 323 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 324 {
 325         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 326         u32 eec;
 327         u16 eeprom_size;
 328
 329         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 330                 eeprom->semaphore_delay = 10;
 331                 eeprom->type = ixgbe_flash;
 332
 333                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 334                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 335                                     IXGBE_EEC_SIZE_SHIFT);
 336                 eeprom->word_size = 1 << (eeprom_size +
 337                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 338
 339                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 340                        eeprom->type, eeprom->word_size);
 341         }
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * ixgbe_iosf_wait - Wait for IOSF command completion
 348  * @hw: pointer to hardware structure
 349  * @ctrl: pointer to location to receive final IOSF control value
 350  *
 351  * Return: failing status on timeout
 352  *
 353  * Note: ctrl can be NULL if the IOSF control register value is not needed
 354  */
 355 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 356 {
 357         u32 i, command;
 358
 359         /* Check every 10 usec to see if the address cycle completed.
 360          * The SB IOSF BUSY bit will clear when the operation is
 361          * complete.
 362          */
 363         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 364                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 365                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 366                         break;
 367                 udelay(10);
 368         }
 369         if (ctrl)
 370                 *ctrl = command;
 371         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 372                 hw_dbg(hw, "IOSF wait timed out\n");
 373                 return IXGBE_ERR_PHY;
 374         }
 375
 376         return 0;
 377 }
 378
 379 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 380  *  IOSF device
 381  *  @hw: pointer to hardware structure
 382  *  @reg_addr: 32 bit PHY register to write
 383  *  @device_type: 3 bit device type
 384  *  @phy_data: Pointer to read data from the register
 385  **/
 386 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 387                                        u32 device_type, u32 *data)
 388 {
 389         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 390         u32 command, error;
 391         s32 ret;
 392
 393         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 394         if (ret)
 395                 return ret;
 396
 397         ret = ixgbe_iosf_wait(hw, NULL);
 398         if (ret)
 399                 goto out;
 400
 401         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 402                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 403
 404         /* Write IOSF control register */
 405         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 406
 407         ret = ixgbe_iosf_wait(hw, &command);
 408
 409         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 410                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 411                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 412                 hw_dbg(hw, "Failed to read, error %x\n", error);
 413                 return IXGBE_ERR_PHY;
 414         }
 415
 416         if (!ret)
 417                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 418
 419 out:
 420         hw->mac.ops.release_swfw_sync(hw, gssr);
 421         return ret;
 422 }
 423
 424 /**
 425  * ixgbe_get_phy_token - Get the token for shared PHY access
 426  * @hw: Pointer to hardware structure
 427  */
 428 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 429 {
 430         struct ixgbe_hic_phy_token_req token_cmd;
 431         s32 status;
 432
 433         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 434         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 435         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 436         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 437         token_cmd.port_number = hw->bus.lan_id;
 438         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 439         token_cmd.pad = 0;
 440         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 441                                               IXGBE_HI_COMMAND_TIMEOUT,
 442                                               true);
 443         if (status)
 444                 return status;
 445         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 446                 return 0;
 447         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 448                 return IXGBE_ERR_FW_RESP_INVALID;
 449
 450         return IXGBE_ERR_TOKEN_RETRY;
 451 }
 452
 453 /**
 454  * ixgbe_put_phy_token - Put the token for shared PHY access
 455  * @hw: Pointer to hardware structure
 456  */
 457 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 458 {
 459         struct ixgbe_hic_phy_token_req token_cmd;
 460         s32 status;
 461
 462         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 463         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 464         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 465         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 466         token_cmd.port_number = hw->bus.lan_id;
 467         token_cmd.command_type = FW_PHY_TOKEN_REL;
 468         token_cmd.pad = 0;
 469         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 470                                               IXGBE_HI_COMMAND_TIMEOUT,
 471                                               true);
 472         if (status)
 473                 return status;
 474         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 475                 return 0;
 476         return IXGBE_ERR_FW_RESP_INVALID;
 477 }
 478
 479 /**
 480  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 481  *  @hw: pointer to hardware structure
 482  *  @reg_addr: 32 bit PHY register to write
 483  *  @device_type: 3 bit device type
 484  *  @data: Data to write to the register
 485  **/
 486 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 487                                          __always_unused u32 device_type,
 488                                          u32 data)
 489 {
 490         struct ixgbe_hic_internal_phy_req write_cmd;
 491
 492         memset(&write_cmd, 0, sizeof(write_cmd));
 493         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 494         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 495         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 496         write_cmd.port_number = hw->bus.lan_id;
 497         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 498         write_cmd.address = cpu_to_be16(reg_addr);
 499         write_cmd.write_data = cpu_to_be32(data);
 500
 501         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 502                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 503 }
 504
 505 /**
 506  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 507  *  @hw: pointer to hardware structure
 508  *  @reg_addr: 32 bit PHY register to write
 509  *  @device_type: 3 bit device type
 510  *  @data: Pointer to read data from the register
 511  **/
 512 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 513                                         __always_unused u32 device_type,
 514                                         u32 *data)
 515 {
 516         union {
 517                 struct ixgbe_hic_internal_phy_req cmd;
 518                 struct ixgbe_hic_internal_phy_resp rsp;
 519         } hic;
 520         s32 status;
 521
 522         memset(&hic, 0, sizeof(hic));
 523         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 524         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 525         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 526         hic.cmd.port_number = hw->bus.lan_id;
 527         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 528         hic.cmd.address = cpu_to_be16(reg_addr);
 529
 530         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 531                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 532
 533         /* Extract the register value from the response. */
 534         *data = be32_to_cpu(hic.rsp.read_data);
 535
 536         return status;
 537 }
 538
 539 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 540  *  command assuming that the semaphore is already obtained.
 541  *  @hw: pointer to hardware structure
 542  *  @offset: offset of  word in the EEPROM to read
 543  *  @data: word read from the EEPROM
 544  *
 545  *  Reads a 16 bit word from the EEPROM using the hostif.
 546  **/
 547 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 548                                           u16 *data)
 549 {
 550         s32 status;
 551         struct ixgbe_hic_read_shadow_ram buffer;
 552
 553         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 554         buffer.hdr.req.buf_lenh = 0;
 555         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 556         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 557
 558         /* convert offset from words to bytes */
 559         buffer.address = cpu_to_be32(offset * 2);
 560         /* one word */
 561         buffer.length = cpu_to_be16(sizeof(u16));
 562
 563         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 564                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 565         if (status)
 566                 return status;
 567
 568         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 569                                           FW_NVM_DATA_OFFSET);
 570
 571         return 0;
 572 }
 573
 574 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 575  *  @hw: pointer to hardware structure
 576  *  @offset: offset of  word in the EEPROM to read
 577  *  @words: number of words
 578  *  @data: word(s) read from the EEPROM
 579  *
 580  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 581  **/
 582 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 583                                             u16 offset, u16 words, u16 *data)
 584 {
 585         struct ixgbe_hic_read_shadow_ram buffer;
 586         u32 current_word = 0;
 587         u16 words_to_read;
 588         s32 status;
 589         u32 i;
 590
 591         /* Take semaphore for the entire operation. */
 592         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 593         if (status) {
 594                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 595                 return status;
 596         }
 597
 598         while (words) {
 599                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 600                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 601                 else
 602                         words_to_read = words;
 603
 604                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 605                 buffer.hdr.req.buf_lenh = 0;
 606                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 607                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 608
 609                 /* convert offset from words to bytes */
 610                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 611                 buffer.length = cpu_to_be16(words_to_read * 2);
 612
 613                 status = ixgbe_host_interface_command(hw, &buffer,
 614                                                       sizeof(buffer),
 615                                                       IXGBE_HI_COMMAND_TIMEOUT,
 616                                                       false);
 617                 if (status) {
 618                         hw_dbg(hw, "Host interface command failed\n");
 619                         goto out;
 620                 }
 621
 622                 for (i = 0; i < words_to_read; i++) {
 623                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 624                                   2 * i;
 625                         u32 value = IXGBE_READ_REG(hw, reg);
 626
 627                         data[current_word] = (u16)(value & 0xffff);
 628                         current_word++;
 629                         i++;
 630                         if (i < words_to_read) {
 631                                 value >>= 16;
 632                                 data[current_word] = (u16)(value & 0xffff);
 633                                 current_word++;
 634                         }
 635                 }
 636                 words -= words_to_read;
 637         }
 638
 639 out:
 640         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 641         return status;
 642 }
 643
 644 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 645  *  @hw: pointer to hardware structure
 646  *  @ptr: pointer offset in eeprom
 647  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 648  *  @csum: address of checksum to update
 649  *
 650  *  Returns error status for any failure
 651  **/
 652 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 653                                    u16 size, u16 *csum, u16 *buffer,
 654                                    u32 buffer_size)
 655 {
 656         u16 buf[256];
 657         s32 status;
 658         u16 length, bufsz, i, start;
 659         u16 *local_buffer;
 660
 661         bufsz = sizeof(buf) / sizeof(buf[0]);
 662
 663         /* Read a chunk at the pointer location */
 664         if (!buffer) {
 665                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 666                 if (status) {
 667                         hw_dbg(hw, "Failed to read EEPROM image\n");
 668                         return status;
 669                 }
 670                 local_buffer = buf;
 671         } else {
 672                 if (buffer_size < ptr)
 673                         return  IXGBE_ERR_PARAM;
 674                 local_buffer = &buffer[ptr];
 675         }
 676
 677         if (size) {
 678                 start = 0;
 679                 length = size;
 680         } else {
 681                 start = 1;
 682                 length = local_buffer[0];
 683
 684                 /* Skip pointer section if length is invalid. */
 685                 if (length == 0xFFFF || length == 0 ||
 686                     (ptr + length) >= hw->eeprom.word_size)
 687                         return 0;
 688         }
 689
 690         if (buffer && ((u32)start + (u32)length > buffer_size))
 691                 return IXGBE_ERR_PARAM;
 692
 693         for (i = start; length; i++, length--) {
 694                 if (i == bufsz && !buffer) {
 695                         ptr += bufsz;
 696                         i = 0;
 697                         if (length < bufsz)
 698                                 bufsz = length;
 699
 700                         /* Read a chunk at the pointer location */
 701                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 702                                                                   bufsz, buf);
 703                         if (status) {
 704                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 705                                 return status;
 706                         }
 707                 }
 708                 *csum += local_buffer[i];
 709         }
 710         return 0;
 711 }
 712
 713 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 714  *  @hw: pointer to hardware structure
 715  *  @buffer: pointer to buffer containing calculated checksum
 716  *  @buffer_size: size of buffer
 717  *
 718  *  Returns a negative error code on error, or the 16-bit checksum
 719  **/
 720 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 721                                     u32 buffer_size)
 722 {
 723         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 724         u16 *local_buffer;
 725         s32 status;
 726         u16 checksum = 0;
 727         u16 pointer, i, size;
 728
 729         hw->eeprom.ops.init_params(hw);
 730
 731         if (!buffer) {
 732                 /* Read pointer area */
 733                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 734                                                 IXGBE_EEPROM_LAST_WORD + 1,
 735                                                 eeprom_ptrs);
 736                 if (status) {
 737                         hw_dbg(hw, "Failed to read EEPROM image\n");
 738                         return status;
 739                 }
 740                 local_buffer = eeprom_ptrs;
 741         } else {
 742                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 743                         return IXGBE_ERR_PARAM;
 744                 local_buffer = buffer;
 745         }
 746
 747         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 748          * checksum word itself
 749          */
 750         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 751                 if (i != IXGBE_EEPROM_CHECKSUM)
 752                         checksum += local_buffer[i];
 753
 754         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 755          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 756          */
 757         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 758                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 759                         continue;
 760
 761                 pointer = local_buffer[i];
 762
 763                 /* Skip pointer section if the pointer is invalid. */
 764                 if (pointer == 0xFFFF || pointer == 0 ||
 765                     pointer >= hw->eeprom.word_size)
 766                         continue;
 767
 768                 switch (i) {
 769                 case IXGBE_PCIE_GENERAL_PTR:
 770                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 771                         break;
 772                 case IXGBE_PCIE_CONFIG0_PTR:
 773                 case IXGBE_PCIE_CONFIG1_PTR:
 774                         size = IXGBE_PCIE_CONFIG_SIZE;
 775                         break;
 776                 default:
 777                         size = 0;
 778                         break;
 779                 }
 780
 781                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 782                                                  buffer, buffer_size);
 783                 if (status)
 784                         return status;
 785         }
 786
 787         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 788
 789         return (s32)checksum;
 790 }
 791
 792 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 793  *  @hw: pointer to hardware structure
 794  *
 795  *  Returns a negative error code on error, or the 16-bit checksum
 796  **/
 797 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 798 {
 799         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 800 }
 801
 802 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 803  *  @hw: pointer to hardware structure
 804  *  @offset: offset of  word in the EEPROM to read
 805  *  @data: word read from the EEPROM
 806  *
 807  *   Reads a 16 bit word from the EEPROM using the hostif.
 808  **/
 809 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 810 {
 811         s32 status = 0;
 812
 813         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 814                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 815                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 816         } else {
 817                 status = IXGBE_ERR_SWFW_SYNC;
 818         }
 819
 820         return status;
 821 }
 822
 823 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 824  *  @hw: pointer to hardware structure
 825  *  @checksum_val: calculated checksum
 826  *
 827  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 828  *  caller does not need checksum_val, the value can be NULL.
 829  **/
 830 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 831                                                u16 *checksum_val)
 832 {
 833         s32 status;
 834         u16 checksum;
 835         u16 read_checksum = 0;
 836
 837         /* Read the first word from the EEPROM. If this times out or fails, do
 838          * not continue or we could be in for a very long wait while every
 839          * EEPROM read fails
 840          */
 841         status = hw->eeprom.ops.read(hw, 0, &checksum);
 842         if (status) {
 843                 hw_dbg(hw, "EEPROM read failed\n");
 844                 return status;
 845         }
 846
 847         status = hw->eeprom.ops.calc_checksum(hw);
 848         if (status < 0)
 849                 return status;
 850
 851         checksum = (u16)(status & 0xffff);
 852
 853         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 854                                            &read_checksum);
 855         if (status)
 856                 return status;
 857
 858         /* Verify read checksum from EEPROM is the same as
 859          * calculated checksum
 860          */
 861         if (read_checksum != checksum) {
 862                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 863                 hw_dbg(hw, "Invalid EEPROM checksum");
 864         }
 865
 866         /* If the user cares, return the calculated checksum */
 867         if (checksum_val)
 868                 *checksum_val = checksum;
 869
 870         return status;
 871 }
 872
 873 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 874  *  @hw: pointer to hardware structure
 875  *  @offset: offset of  word in the EEPROM to write
 876  *  @data: word write to the EEPROM
 877  *
 878  *  Write a 16 bit word to the EEPROM using the hostif.
 879  **/
 880 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 881                                            u16 data)
 882 {
 883         s32 status;
 884         struct ixgbe_hic_write_shadow_ram buffer;
 885
 886         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 887         buffer.hdr.req.buf_lenh = 0;
 888         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 889         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 890
 891         /* one word */
 892         buffer.length = cpu_to_be16(sizeof(u16));
 893         buffer.data = data;
 894         buffer.address = cpu_to_be32(offset * 2);
 895
 896         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 897                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 898         return status;
 899 }
 900
 901 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 902  *  @hw: pointer to hardware structure
 903  *  @offset: offset of  word in the EEPROM to write
 904  *  @data: word write to the EEPROM
 905  *
 906  *  Write a 16 bit word to the EEPROM using the hostif.
 907  **/
 908 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 909 {
 910         s32 status = 0;
 911
 912         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 913                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 914                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 915         } else {
 916                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 917                 status = IXGBE_ERR_SWFW_SYNC;
 918         }
 919
 920         return status;
 921 }
 922
 923 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 924  *  @hw: pointer to hardware structure
 925  *
 926  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 927  **/
 928 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 929 {
 930         s32 status = 0;
 931         union ixgbe_hic_hdr2 buffer;
 932
 933         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 934         buffer.req.buf_lenh = 0;
 935         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 936         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 937
 938         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 939                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 940         return status;
 941 }
 942
 943 /**
 944  * ixgbe_get_bus_info_X550em - Set PCI bus info
 945  * @hw: pointer to hardware structure
 946  *
 947  * Sets bus link width and speed to unknown because X550em is
 948  * not a PCI device.
 949  **/
 950 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 951 {
 952         hw->bus.type  = ixgbe_bus_type_internal;
 953         hw->bus.width = ixgbe_bus_width_unknown;
 954         hw->bus.speed = ixgbe_bus_speed_unknown;
 955
 956         hw->mac.ops.set_lan_id(hw);
 957
 958         return 0;
 959 }
 960
 961 /** ixgbe_disable_rx_x550 - Disable RX unit
 962  *
 963  *  Enables the Rx DMA unit for x550
 964  **/
 965 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 966 {
 967         u32 rxctrl, pfdtxgswc;
 968         s32 status;
 969         struct ixgbe_hic_disable_rxen fw_cmd;
 970
 971         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 972         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 973                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 974                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 975                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 976                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 977                         hw->mac.set_lben = true;
 978                 } else {
 979                         hw->mac.set_lben = false;
 980                 }
 981
 982                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 983                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 984                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 985                 fw_cmd.port_number = hw->bus.lan_id;
 986
 987                 status = ixgbe_host_interface_command(hw, &fw_cmd,
 988                                         sizeof(struct ixgbe_hic_disable_rxen),
 989                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 990
 991                 /* If we fail - disable RX using register write */
 992                 if (status) {
 993                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 994                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 995                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 996                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 997                         }
 998                 }
 999         }
1000 }
1001
1002 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1003  *  @hw: pointer to hardware structure
1004  *
1005  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1006  *  checksum and updates the EEPROM and instructs the hardware to update
1007  *  the flash.
1008  **/
1009 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1010 {
1011         s32 status;
1012         u16 checksum = 0;
1013
1014         /* Read the first word from the EEPROM. If this times out or fails, do
1015          * not continue or we could be in for a very long wait while every
1016          * EEPROM read fails
1017          */
1018         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1019         if (status) {
1020                 hw_dbg(hw, "EEPROM read failed\n");
1021                 return status;
1022         }
1023
1024         status = ixgbe_calc_eeprom_checksum_X550(hw);
1025         if (status < 0)
1026                 return status;
1027
1028         checksum = (u16)(status & 0xffff);
1029
1030         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1031                                             checksum);
1032         if (status)
1033                 return status;
1034
1035         status = ixgbe_update_flash_X550(hw);
1036
1037         return status;
1038 }
1039
1040 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1041  *  @hw: pointer to hardware structure
1042  *  @offset: offset of  word in the EEPROM to write
1043  *  @words: number of words
1044  *  @data: word(s) write to the EEPROM
1045  *
1046  *
1047  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1048  **/
1049 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1050                                              u16 offset, u16 words,
1051                                              u16 *data)
1052 {
1053         s32 status = 0;
1054         u32 i = 0;
1055
1056         /* Take semaphore for the entire operation. */
1057         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1058         if (status) {
1059                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1060                 return status;
1061         }
1062
1063         for (i = 0; i < words; i++) {
1064                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1065                                                          data[i]);
1066                 if (status) {
1067                         hw_dbg(hw, "Eeprom buffered write failed\n");
1068                         break;
1069                 }
1070         }
1071
1072         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1073
1074         return status;
1075 }
1076
1077 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1078  *  IOSF device
1079  *
1080  *  @hw: pointer to hardware structure
1081  *  @reg_addr: 32 bit PHY register to write
1082  *  @device_type: 3 bit device type
1083  *  @data: Data to write to the register
1084  **/
1085 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1086                                         u32 device_type, u32 data)
1087 {
1088         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1089         u32 command, error;
1090         s32 ret;
1091
1092         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1093         if (ret)
1094                 return ret;
1095
1096         ret = ixgbe_iosf_wait(hw, NULL);
1097         if (ret)
1098                 goto out;
1099
1100         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1101                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1102
1103         /* Write IOSF control register */
1104         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1105
1106         /* Write IOSF data register */
1107         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1108
1109         ret = ixgbe_iosf_wait(hw, &command);
1110
1111         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1112                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1113                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1114                 hw_dbg(hw, "Failed to write, error %x\n", error);
1115                 return IXGBE_ERR_PHY;
1116         }
1117
1118 out:
1119         hw->mac.ops.release_swfw_sync(hw, gssr);
1120         return ret;
1121 }
1122
1123 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1124  *  @hw: pointer to hardware structure
1125  *  @speed: the link speed to force
1126  *
1127  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1128  *  internal and external PHY at a specific speed, without autonegotiation.
1129  **/
1130 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1131 {
1132         s32 status;
1133         u32 reg_val;
1134
1135         /* Disable AN and force speed to 10G Serial. */
1136         status = ixgbe_read_iosf_sb_reg_x550(hw,
1137                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1138                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1139         if (status)
1140                 return status;
1141
1142         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1143         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1144
1145         /* Select forced link speed for internal PHY. */
1146         switch (*speed) {
1147         case IXGBE_LINK_SPEED_10GB_FULL:
1148                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1149                 break;
1150         case IXGBE_LINK_SPEED_1GB_FULL:
1151                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1152                 break;
1153         default:
1154                 /* Other link speeds are not supported by internal KR PHY. */
1155                 return IXGBE_ERR_LINK_SETUP;
1156         }
1157
1158         status = ixgbe_write_iosf_sb_reg_x550(hw,
1159                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1160                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1161         if (status)
1162                 return status;
1163
1164         /* Disable training protocol FSM. */
1165         status = ixgbe_read_iosf_sb_reg_x550(hw,
1166                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1167                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1168         if (status)
1169                 return status;
1170
1171         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1172         status = ixgbe_write_iosf_sb_reg_x550(hw,
1173                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1174                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1175         if (status)
1176                 return status;
1177
1178         /* Disable Flex from training TXFFE. */
1179         status = ixgbe_read_iosf_sb_reg_x550(hw,
1180                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1181                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1182         if (status)
1183                 return status;
1184
1185         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1186         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1187         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1188         status = ixgbe_write_iosf_sb_reg_x550(hw,
1189                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1190                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1191         if (status)
1192                 return status;
1193
1194         status = ixgbe_read_iosf_sb_reg_x550(hw,
1195                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1196                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1197         if (status)
1198                 return status;
1199
1200         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1201         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1202         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1203         status = ixgbe_write_iosf_sb_reg_x550(hw,
1204                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1205                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1206         if (status)
1207                 return status;
1208
1209         /* Enable override for coefficients. */
1210         status = ixgbe_read_iosf_sb_reg_x550(hw,
1211                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1212                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1213         if (status)
1214                 return status;
1215
1216         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1217         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1218         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1219         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1220         status = ixgbe_write_iosf_sb_reg_x550(hw,
1221                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1222                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1223         if (status)
1224                 return status;
1225
1226         /* Toggle port SW reset by AN reset. */
1227         status = ixgbe_read_iosf_sb_reg_x550(hw,
1228                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1229                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1230         if (status)
1231                 return status;
1232
1233         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1234         status = ixgbe_write_iosf_sb_reg_x550(hw,
1235                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1236                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1237
1238         return status;
1239 }
1240
1241 /**
1242  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1243  *  @hw: pointer to hardware structure
1244  *  @linear: true if SFP module is linear
1245  */
1246 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1247 {
1248         switch (hw->phy.sfp_type) {
1249         case ixgbe_sfp_type_not_present:
1250                 return IXGBE_ERR_SFP_NOT_PRESENT;
1251         case ixgbe_sfp_type_da_cu_core0:
1252         case ixgbe_sfp_type_da_cu_core1:
1253                 *linear = true;
1254                 break;
1255         case ixgbe_sfp_type_srlr_core0:
1256         case ixgbe_sfp_type_srlr_core1:
1257         case ixgbe_sfp_type_da_act_lmt_core0:
1258         case ixgbe_sfp_type_da_act_lmt_core1:
1259         case ixgbe_sfp_type_1g_sx_core0:
1260         case ixgbe_sfp_type_1g_sx_core1:
1261         case ixgbe_sfp_type_1g_lx_core0:
1262         case ixgbe_sfp_type_1g_lx_core1:
1263                 *linear = false;
1264                 break;
1265         case ixgbe_sfp_type_unknown:
1266         case ixgbe_sfp_type_1g_cu_core0:
1267         case ixgbe_sfp_type_1g_cu_core1:
1268         default:
1269                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1270         }
1271
1272         return 0;
1273 }
1274
1275 /**
1276  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1277  *  @hw: pointer to hardware structure
1278  *
1279  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1280  */
1281 static s32
1282 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1283                                 ixgbe_link_speed speed,
1284                                 __always_unused bool autoneg_wait_to_complete)
1285 {
1286         s32 status;
1287         u16 slice, value;
1288         bool setup_linear = false;
1289
1290         /* Check if SFP module is supported and linear */
1291         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1292
1293         /* If no SFP module present, then return success. Return success since
1294          * there is no reason to configure CS4227 and SFP not present error is
1295          * not accepted in the setup MAC link flow.
1296          */
1297         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1298                 return 0;
1299
1300         if (status)
1301                 return status;
1302
1303         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1304                 /* Configure CS4227 LINE side to 10G SR. */
1305                 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1306                 value = IXGBE_CS4227_SPEED_10G;
1307                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1308                                                           slice, value);
1309                 if (status)
1310                         goto i2c_err;
1311
1312                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1313                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1314                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1315                                                           slice, value);
1316                 if (status)
1317                         goto i2c_err;
1318
1319                 /* Configure CS4227 for HOST connection rate then type. */
1320                 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1321                 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1322                         IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1323                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1324                                                           slice, value);
1325                 if (status)
1326                         goto i2c_err;
1327
1328                 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1329                 if (setup_linear)
1330                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1331                 else
1332                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1333                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1334                                                           slice, value);
1335                 if (status)
1336                         goto i2c_err;
1337
1338                 /* Setup XFI internal link. */
1339                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1340                 if (status) {
1341                         hw_dbg(hw, "setup_ixfi failed with %d\n", status);
1342                         return status;
1343                 }
1344         } else {
1345                 /* Configure internal PHY for KR/KX. */
1346                 status = ixgbe_setup_kr_speed_x550em(hw, speed);
1347                 if (status) {
1348                         hw_dbg(hw, "setup_kr_speed failed with %d\n", status);
1349                         return status;
1350                 }
1351
1352                 /* Configure CS4227 LINE side to proper mode. */
1353                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1354                 if (setup_linear)
1355                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1356                 else
1357                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1358                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1359                                                           slice, value);
1360                 if (status)
1361                         goto i2c_err;
1362         }
1363
1364         return 0;
1365
1366 i2c_err:
1367         hw_dbg(hw, "combined i2c access failed with %d\n", status);
1368         return status;
1369 }
1370
1371 /**
1372  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1373  * @hw: pointer to hardware structure
1374  *
1375  * Configure the the integrated PHY for native SFP support.
1376  */
1377 static s32
1378 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1379                            __always_unused bool autoneg_wait_to_complete)
1380 {
1381         bool setup_linear = false;
1382         u32 reg_phy_int;
1383         s32 rc;
1384
1385         /* Check if SFP module is supported and linear */
1386         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1387
1388         /* If no SFP module present, then return success. Return success since
1389          * SFP not present error is not excepted in the setup MAC link flow.
1390          */
1391         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1392                 return 0;
1393
1394         if (!rc)
1395                 return rc;
1396
1397         /* Configure internal PHY for native SFI */
1398         rc = hw->mac.ops.read_iosf_sb_reg(hw,
1399                                           IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1400                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
1401                                           &reg_phy_int);
1402         if (rc)
1403                 return rc;
1404
1405         if (setup_linear) {
1406                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
1407                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
1408         } else {
1409                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
1410                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
1411         }
1412
1413         rc = hw->mac.ops.write_iosf_sb_reg(hw,
1414                                            IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1415                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
1416                                            reg_phy_int);
1417         if (rc)
1418                 return rc;
1419
1420         /* Setup XFI/SFI internal link */
1421         return ixgbe_setup_ixfi_x550em(hw, &speed);
1422 }
1423
1424 /**
1425  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1426  * @hw: pointer to hardware structure
1427  *
1428  * Configure the the integrated PHY for SFP support.
1429  */
1430 static s32
1431 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1432                                __always_unused bool autoneg_wait_to_complete)
1433 {
1434         u32 reg_slice, slice_offset;
1435         bool setup_linear = false;
1436         u16 reg_phy_ext;
1437         s32 rc;
1438
1439         /* Check if SFP module is supported and linear */
1440         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1441
1442         /* If no SFP module present, then return success. Return success since
1443          * SFP not present error is not excepted in the setup MAC link flow.
1444          */
1445         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1446                 return 0;
1447
1448         if (!rc)
1449                 return rc;
1450
1451         /* Configure internal PHY for KR/KX. */
1452         ixgbe_setup_kr_speed_x550em(hw, speed);
1453
1454         if (!hw->phy.mdio.prtad || hw->phy.mdio.prtad == 0xFFFF)
1455                 return IXGBE_ERR_PHY_ADDR_INVALID;
1456
1457         /* Get external PHY device id */
1458         rc = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
1459                                   IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1460         if (rc)
1461                 return rc;
1462
1463         /* When configuring quad port CS4223, the MAC instance is part
1464          * of the slice offset.
1465          */
1466         if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
1467                 slice_offset = (hw->bus.lan_id +
1468                                 (hw->bus.instance_id << 1)) << 12;
1469         else
1470                 slice_offset = hw->bus.lan_id << 12;
1471
1472         /* Configure CS4227/CS4223 LINE side to proper mode. */
1473         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1474         if (setup_linear)
1475                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1476         else
1477                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1478         return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
1479                                      reg_phy_ext);
1480 }
1481
1482 /**
1483  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1484  * @hw: pointer to hardware structure
1485  * @speed: new link speed
1486  * @autoneg_wait_to_complete: true when waiting for completion is needed
1487  *
1488  * Setup internal/external PHY link speed based on link speed, then set
1489  * external PHY auto advertised link speed.
1490  *
1491  * Returns error status for any failure
1492  **/
1493 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1494                                          ixgbe_link_speed speed,
1495                                          bool autoneg_wait)
1496 {
1497         s32 status;
1498         ixgbe_link_speed force_speed;
1499
1500         /* Setup internal/external PHY link speed to iXFI (10G), unless
1501          * only 1G is auto advertised then setup KX link.
1502          */
1503         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1504                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1505         else
1506                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1507
1508         /* If internal link mode is XFI, then setup XFI internal link. */
1509         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1510                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1511
1512                 if (status)
1513                         return status;
1514         }
1515
1516         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1517 }
1518
1519 /** ixgbe_check_link_t_X550em - Determine link and speed status
1520   * @hw: pointer to hardware structure
1521   * @speed: pointer to link speed
1522   * @link_up: true when link is up
1523   * @link_up_wait_to_complete: bool used to wait for link up or not
1524   *
1525   * Check that both the MAC and X557 external PHY have link.
1526   **/
1527 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1528                                      ixgbe_link_speed *speed,
1529                                      bool *link_up,
1530                                      bool link_up_wait_to_complete)
1531 {
1532         u32 status;
1533         u16 autoneg_status;
1534
1535         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1536                 return IXGBE_ERR_CONFIG;
1537
1538         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1539                                               link_up_wait_to_complete);
1540
1541         /* If check link fails or MAC link is not up, then return */
1542         if (status || !(*link_up))
1543                 return status;
1544
1545          /* MAC link is up, so check external PHY link.
1546           * Read this twice back to back to indicate current status.
1547           */
1548         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1549                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1550                                       &autoneg_status);
1551         if (status)
1552                 return status;
1553
1554         /* If external PHY link is not up, then indicate link not up */
1555         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1556                 *link_up = false;
1557
1558         return 0;
1559 }
1560
1561 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1562  *  @hw: pointer to hardware structure
1563  **/
1564 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1565 {
1566         struct ixgbe_mac_info *mac = &hw->mac;
1567
1568         switch (mac->ops.get_media_type(hw)) {
1569         case ixgbe_media_type_fiber:
1570                 /* CS4227 does not support autoneg, so disable the laser control
1571                  * functions for SFP+ fiber
1572                  */
1573                 mac->ops.disable_tx_laser = NULL;
1574                 mac->ops.enable_tx_laser = NULL;
1575                 mac->ops.flap_tx_laser = NULL;
1576                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1577                 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1578                 switch (hw->device_id) {
1579                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1580                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
1581                         break;
1582                 case IXGBE_DEV_ID_X550EM_A_SFP:
1583                         mac->ops.setup_mac_link =
1584                                                 ixgbe_setup_mac_link_sfp_x550a;
1585                         break;
1586                 default:
1587                         mac->ops.setup_mac_link =
1588                                                 ixgbe_setup_mac_link_sfp_x550em;
1589                         break;
1590                 }
1591                 mac->ops.set_rate_select_speed =
1592                                         ixgbe_set_soft_rate_select_speed;
1593                 break;
1594         case ixgbe_media_type_copper:
1595                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1596                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1597                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1598                 return;
1599         case ixgbe_media_type_backplane:
1600                 break;
1601         default:
1602                 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1603                 break;
1604         }
1605 }
1606
1607 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1608  * @hw: pointer to hardware structure
1609  */
1610 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1611 {
1612         s32 status;
1613         bool linear;
1614
1615         /* Check if SFP module is supported */
1616         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1617         if (status)
1618                 return status;
1619
1620         ixgbe_init_mac_link_ops_X550em(hw);
1621         hw->phy.ops.reset = NULL;
1622
1623         return 0;
1624 }
1625
1626 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1627  * @hw: pointer to hardware structure
1628  * @speed: pointer to link speed
1629  * @autoneg: true when autoneg or autotry is enabled
1630  **/
1631 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1632                                               ixgbe_link_speed *speed,
1633                                               bool *autoneg)
1634 {
1635         /* SFP */
1636         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1637                 /* CS4227 SFP must not enable auto-negotiation */
1638                 *autoneg = false;
1639
1640                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1641                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1642                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1643                         return 0;
1644                 }
1645
1646                 /* Link capabilities are based on SFP */
1647                 if (hw->phy.multispeed_fiber)
1648                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1649                                  IXGBE_LINK_SPEED_1GB_FULL;
1650                 else
1651                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1652         } else {
1653                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1654                          IXGBE_LINK_SPEED_1GB_FULL;
1655                 *autoneg = true;
1656         }
1657         return 0;
1658 }
1659
1660 /**
1661  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1662  * @hw: pointer to hardware structure
1663  * @lsc: pointer to boolean flag which indicates whether external Base T
1664  *       PHY interrupt is lsc
1665  *
1666  * Determime if external Base T PHY interrupt cause is high temperature
1667  * failure alarm or link status change.
1668  *
1669  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1670  * failure alarm, else return PHY access status.
1671  **/
1672 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1673 {
1674         u32 status;
1675         u16 reg;
1676
1677         *lsc = false;
1678
1679         /* Vendor alarm triggered */
1680         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1681                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1682                                       &reg);
1683
1684         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1685                 return status;
1686
1687         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1688         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1689                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1690                                       &reg);
1691
1692         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1693                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1694                 return status;
1695
1696         /* Global alarm triggered */
1697         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1698                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1699                                       &reg);
1700
1701         if (status)
1702                 return status;
1703
1704         /* If high temperature failure, then return over temp error and exit */
1705         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1706                 /* power down the PHY in case the PHY FW didn't already */
1707                 ixgbe_set_copper_phy_power(hw, false);
1708                 return IXGBE_ERR_OVERTEMP;
1709         }
1710         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1711                 /*  device fault alarm triggered */
1712                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1713                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1714                                           &reg);
1715                 if (status)
1716                         return status;
1717
1718                 /* if device fault was due to high temp alarm handle and exit */
1719                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1720                         /* power down the PHY in case the PHY FW didn't */
1721                         ixgbe_set_copper_phy_power(hw, false);
1722                         return IXGBE_ERR_OVERTEMP;
1723                 }
1724         }
1725
1726         /* Vendor alarm 2 triggered */
1727         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1728                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1729
1730         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1731                 return status;
1732
1733         /* link connect/disconnect event occurred */
1734         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1735                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1736
1737         if (status)
1738                 return status;
1739
1740         /* Indicate LSC */
1741         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1742                 *lsc = true;
1743
1744         return 0;
1745 }
1746
1747 /**
1748  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1749  * @hw: pointer to hardware structure
1750  *
1751  * Enable link status change and temperature failure alarm for the external
1752  * Base T PHY
1753  *
1754  * Returns PHY access status
1755  **/
1756 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1757 {
1758         u32 status;
1759         u16 reg;
1760         bool lsc;
1761
1762         /* Clear interrupt flags */
1763         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1764
1765         /* Enable link status change alarm */
1766         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1767                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1768         if (status)
1769                 return status;
1770
1771         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1772
1773         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1774                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1775         if (status)
1776                 return status;
1777
1778         /* Enable high temperature failure and global fault alarms */
1779         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1780                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1781                                       &reg);
1782         if (status)
1783                 return status;
1784
1785         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1786                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1787
1788         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1789                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1790                                        reg);
1791         if (status)
1792                 return status;
1793
1794         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1795         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1796                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1797                                       &reg);
1798         if (status)
1799                 return status;
1800
1801         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1802                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1803
1804         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1805                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1806                                        reg);
1807         if (status)
1808                 return status;
1809
1810         /* Enable chip-wide vendor alarm */
1811         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1812                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1813                                       &reg);
1814         if (status)
1815                 return status;
1816
1817         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1818
1819         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1820                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1821                                        reg);
1822
1823         return status;
1824 }
1825
1826 /**
1827  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1828  * @hw: pointer to hardware structure
1829  *
1830  * Handle external Base T PHY interrupt. If high temperature
1831  * failure alarm then return error, else if link status change
1832  * then setup internal/external PHY link
1833  *
1834  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1835  * failure alarm, else return PHY access status.
1836  **/
1837 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1838 {
1839         struct ixgbe_phy_info *phy = &hw->phy;
1840         bool lsc;
1841         u32 status;
1842
1843         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1844         if (status)
1845                 return status;
1846
1847         if (lsc && phy->ops.setup_internal_link)
1848                 return phy->ops.setup_internal_link(hw);
1849
1850         return 0;
1851 }
1852
1853 /**
1854  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1855  * @hw: pointer to hardware structure
1856  * @speed: link speed
1857  *
1858  * Configures the integrated KR PHY.
1859  **/
1860 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1861                                        ixgbe_link_speed speed)
1862 {
1863         s32 status;
1864         u32 reg_val;
1865
1866         status = hw->mac.ops.read_iosf_sb_reg(hw,
1867                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1868                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1869         if (status)
1870                 return status;
1871
1872         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1873         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1874                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1875         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1876                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1877
1878         /* Advertise 10G support. */
1879         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1880                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1881
1882         /* Advertise 1G support. */
1883         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1884                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1885
1886         /* Restart auto-negotiation. */
1887         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1888         status = hw->mac.ops.write_iosf_sb_reg(hw,
1889                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1890                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1891
1892         return status;
1893 }
1894
1895 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1896  *  @hw: pointer to hardware structure
1897  *
1898  *   Configures the integrated KX4 PHY.
1899  **/
1900 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1901 {
1902         s32 status;
1903         u32 reg_val;
1904
1905         status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1906                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1907                                               hw->bus.lan_id, &reg_val);
1908         if (status)
1909                 return status;
1910
1911         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1912                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1913
1914         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1915
1916         /* Advertise 10G support. */
1917         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1918                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1919
1920         /* Advertise 1G support. */
1921         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1922                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1923
1924         /* Restart auto-negotiation. */
1925         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1926         status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1927                                                IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1928                                                hw->bus.lan_id, reg_val);
1929
1930         return status;
1931 }
1932
1933 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1934  *   @hw: pointer to hardware structure
1935  *
1936  *   Configures the integrated KR PHY.
1937  **/
1938 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1939 {
1940         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1941 }
1942
1943 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1944  *  @hw: address of hardware structure
1945  *  @link_up: address of boolean to indicate link status
1946  *
1947  *  Returns error code if unable to get link status.
1948  **/
1949 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1950 {
1951         u32 ret;
1952         u16 autoneg_status;
1953
1954         *link_up = false;
1955
1956         /* read this twice back to back to indicate current status */
1957         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1958                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1959                                    &autoneg_status);
1960         if (ret)
1961                 return ret;
1962
1963         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1964                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1965                                    &autoneg_status);
1966         if (ret)
1967                 return ret;
1968
1969         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1970
1971         return 0;
1972 }
1973
1974 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1975  *  @hw: point to hardware structure
1976  *
1977  *  Configures the link between the integrated KR PHY and the external X557 PHY
1978  *  The driver will call this function when it gets a link status change
1979  *  interrupt from the X557 PHY. This function configures the link speed
1980  *  between the PHYs to match the link speed of the BASE-T link.
1981  *
1982  * A return of a non-zero value indicates an error, and the base driver should
1983  * not report link up.
1984  **/
1985 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1986 {
1987         ixgbe_link_speed force_speed;
1988         bool link_up;
1989         u32 status;
1990         u16 speed;
1991
1992         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1993                 return IXGBE_ERR_CONFIG;
1994
1995         if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1996                 speed = IXGBE_LINK_SPEED_10GB_FULL |
1997                         IXGBE_LINK_SPEED_1GB_FULL;
1998                 return ixgbe_setup_kr_speed_x550em(hw, speed);
1999         }
2000
2001         /* If link is not up, then there is no setup necessary so return  */
2002         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2003         if (status)
2004                 return status;
2005
2006         if (!link_up)
2007                 return 0;
2008
2009         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2010                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2011                                       &speed);
2012         if (status)
2013                 return status;
2014
2015         /* If link is not still up, then no setup is necessary so return */
2016         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2017         if (status)
2018                 return status;
2019
2020         if (!link_up)
2021                 return 0;
2022
2023         /* clear everything but the speed and duplex bits */
2024         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2025
2026         switch (speed) {
2027         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2028                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2029                 break;
2030         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2031                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2032                 break;
2033         default:
2034                 /* Internal PHY does not support anything else */
2035                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2036         }
2037
2038         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2039 }
2040
2041 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2042  *  @hw: pointer to hardware structure
2043  **/
2044 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2045 {
2046         s32 status;
2047
2048         status = ixgbe_reset_phy_generic(hw);
2049
2050         if (status)
2051                 return status;
2052
2053         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2054         return ixgbe_enable_lasi_ext_t_x550em(hw);
2055 }
2056
2057 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2058  *  @hw: pointer to hardware structure
2059  *  @lcd_speed: pointer to lowest common link speed
2060  *
2061  *  Determine lowest common link speed with link partner.
2062  **/
2063 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2064                                   ixgbe_link_speed *lcd_speed)
2065 {
2066         u16 an_lp_status;
2067         s32 status;
2068         u16 word = hw->eeprom.ctrl_word_3;
2069
2070         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2071
2072         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2073                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2074                                       &an_lp_status);
2075         if (status)
2076                 return status;
2077
2078         /* If link partner advertised 1G, return 1G */
2079         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2080                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2081                 return status;
2082         }
2083
2084         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2085         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2086             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2087                 return status;
2088
2089         /* Link partner not capable of lower speeds, return 10G */
2090         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2091         return status;
2092 }
2093
2094 /**
2095  * ixgbe_setup_fc_x550em - Set up flow control
2096  * @hw: pointer to hardware structure
2097  */
2098 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2099 {
2100         bool pause, asm_dir;
2101         u32 reg_val;
2102         s32 rc;
2103
2104         /* Validate the requested mode */
2105         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2106                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2107                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2108         }
2109
2110         /* 10gig parts do not have a word in the EEPROM to determine the
2111          * default flow control setting, so we explicitly set it to full.
2112          */
2113         if (hw->fc.requested_mode == ixgbe_fc_default)
2114                 hw->fc.requested_mode = ixgbe_fc_full;
2115
2116         /* Determine PAUSE and ASM_DIR bits. */
2117         switch (hw->fc.requested_mode) {
2118         case ixgbe_fc_none:
2119                 pause = false;
2120                 asm_dir = false;
2121                 break;
2122         case ixgbe_fc_tx_pause:
2123                 pause = false;
2124                 asm_dir = true;
2125                 break;
2126         case ixgbe_fc_rx_pause:
2127                 /* Rx Flow control is enabled and Tx Flow control is
2128                  * disabled by software override. Since there really
2129                  * isn't a way to advertise that we are capable of RX
2130                  * Pause ONLY, we will advertise that we support both
2131                  * symmetric and asymmetric Rx PAUSE, as such we fall
2132                  * through to the fc_full statement.  Later, we will
2133                  * disable the adapter's ability to send PAUSE frames.
2134                  */
2135                 /* Fallthrough */
2136         case ixgbe_fc_full:
2137                 pause = true;
2138                 asm_dir = true;
2139                 break;
2140         default:
2141                 hw_err(hw, "Flow control param set incorrectly\n");
2142                 return IXGBE_ERR_CONFIG;
2143         }
2144
2145         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
2146                 return 0;
2147
2148         rc = hw->mac.ops.read_iosf_sb_reg(hw,
2149                                           IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2150                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
2151                                           &reg_val);
2152         if (rc)
2153                 return rc;
2154
2155         reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2156                      IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2157         if (pause)
2158                 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2159         if (asm_dir)
2160                 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2161         rc = hw->mac.ops.write_iosf_sb_reg(hw,
2162                                            IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2163                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
2164                                            reg_val);
2165
2166         /* This device does not fully support AN. */
2167         hw->fc.disable_fc_autoneg = true;
2168
2169         return rc;
2170 }
2171
2172 /** ixgbe_enter_lplu_x550em - Transition to low power states
2173  *  @hw: pointer to hardware structure
2174  *
2175  *  Configures Low Power Link Up on transition to low power states
2176  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2177  *  the X557 PHY immediately prior to entering LPLU.
2178  **/
2179 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2180 {
2181         u16 an_10g_cntl_reg, autoneg_reg, speed;
2182         s32 status;
2183         ixgbe_link_speed lcd_speed;
2184         u32 save_autoneg;
2185         bool link_up;
2186
2187         /* If blocked by MNG FW, then don't restart AN */
2188         if (ixgbe_check_reset_blocked(hw))
2189                 return 0;
2190
2191         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2192         if (status)
2193                 return status;
2194
2195         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
2196                                      &hw->eeprom.ctrl_word_3);
2197         if (status)
2198                 return status;
2199
2200         /* If link is down, LPLU disabled in NVM, WoL disabled, or
2201          * manageability disabled, then force link down by entering
2202          * low power mode.
2203          */
2204         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2205             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2206                 return ixgbe_set_copper_phy_power(hw, false);
2207
2208         /* Determine LCD */
2209         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2210         if (status)
2211                 return status;
2212
2213         /* If no valid LCD link speed, then force link down and exit. */
2214         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2215                 return ixgbe_set_copper_phy_power(hw, false);
2216
2217         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2218                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2219                                       &speed);
2220         if (status)
2221                 return status;
2222
2223         /* If no link now, speed is invalid so take link down */
2224         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2225         if (status)
2226                 return ixgbe_set_copper_phy_power(hw, false);
2227
2228         /* clear everything but the speed bits */
2229         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2230
2231         /* If current speed is already LCD, then exit. */
2232         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2233              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2234             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2235              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2236                 return status;
2237
2238         /* Clear AN completed indication */
2239         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2240                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2241                                       &autoneg_reg);
2242         if (status)
2243                 return status;
2244
2245         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2246                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2247                                       &an_10g_cntl_reg);
2248         if (status)
2249                 return status;
2250
2251         status = hw->phy.ops.read_reg(hw,
2252                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2253                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2254                                       &autoneg_reg);
2255         if (status)
2256                 return status;
2257
2258         save_autoneg = hw->phy.autoneg_advertised;
2259
2260         /* Setup link at least common link speed */
2261         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2262
2263         /* restore autoneg from before setting lplu speed */
2264         hw->phy.autoneg_advertised = save_autoneg;
2265
2266         return status;
2267 }
2268
2269 /**
2270  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2271  * @hw: pointer to hardware structure
2272  *
2273  * Read NW_MNG_IF_SEL register and save field values.
2274  */
2275 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2276 {
2277         /* Save NW management interface connected on board. This is used
2278          * to determine internal PHY mode.
2279          */
2280         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2281
2282         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2283          * PHY address. This register field was has only been used for X552.
2284          */
2285         if (!hw->phy.nw_mng_if_sel) {
2286                 if (hw->mac.type == ixgbe_mac_x550em_a) {
2287                         struct ixgbe_adapter *adapter = hw->back;
2288
2289                         e_warn(drv, "nw_mng_if_sel not set\n");
2290                 }
2291                 return;
2292         }
2293
2294         hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
2295                               IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2296                              IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2297 }
2298
2299 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2300  *  @hw: pointer to hardware structure
2301  *
2302  *  Initialize any function pointers that were not able to be
2303  *  set during init_shared_code because the PHY/SFP type was
2304  *  not known.  Perform the SFP init if necessary.
2305  **/
2306 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2307 {
2308         struct ixgbe_phy_info *phy = &hw->phy;
2309         s32 ret_val;
2310
2311         hw->mac.ops.set_lan_id(hw);
2312
2313         ixgbe_read_mng_if_sel_x550em(hw);
2314
2315         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2316                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2317                 ixgbe_setup_mux_ctl(hw);
2318         }
2319
2320         /* Identify the PHY or SFP module */
2321         ret_val = phy->ops.identify(hw);
2322
2323         /* Setup function pointers based on detected hardware */
2324         ixgbe_init_mac_link_ops_X550em(hw);
2325         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2326                 phy->ops.reset = NULL;
2327
2328         /* Set functions pointers based on phy type */
2329         switch (hw->phy.type) {
2330         case ixgbe_phy_x550em_kx4:
2331                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2332                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2333                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2334                 break;
2335         case ixgbe_phy_x550em_kr:
2336                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2337                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2338                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2339                 break;
2340         case ixgbe_phy_x550em_ext_t:
2341                 /* Save NW management interface connected on board. This is used
2342                  * to determine internal PHY mode
2343                  */
2344                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2345
2346                 /* If internal link mode is XFI, then setup iXFI internal link,
2347                  * else setup KR now.
2348                  */
2349                 phy->ops.setup_internal_link =
2350                                               ixgbe_setup_internal_phy_t_x550em;
2351
2352                 /* setup SW LPLU only for first revision */
2353                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2354                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2355                       IXGBE_FUSES0_REV_MASK))
2356                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2357
2358                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2359                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2360                 break;
2361         default:
2362                 break;
2363         }
2364
2365         return ret_val;
2366 }
2367
2368 /** ixgbe_get_media_type_X550em - Get media type
2369  *  @hw: pointer to hardware structure
2370  *
2371  *  Returns the media type (fiber, copper, backplane)
2372  *
2373  */
2374 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2375 {
2376         enum ixgbe_media_type media_type;
2377
2378         /* Detect if there is a copper PHY attached. */
2379         switch (hw->device_id) {
2380         case IXGBE_DEV_ID_X550EM_X_KR:
2381         case IXGBE_DEV_ID_X550EM_X_KX4:
2382                 media_type = ixgbe_media_type_backplane;
2383                 break;
2384         case IXGBE_DEV_ID_X550EM_X_SFP:
2385         case IXGBE_DEV_ID_X550EM_A_SFP:
2386         case IXGBE_DEV_ID_X550EM_A_SFP_N:
2387                 media_type = ixgbe_media_type_fiber;
2388                 break;
2389         case IXGBE_DEV_ID_X550EM_X_1G_T:
2390         case IXGBE_DEV_ID_X550EM_X_10G_T:
2391                 media_type = ixgbe_media_type_copper;
2392                 break;
2393         default:
2394                 media_type = ixgbe_media_type_unknown;
2395                 break;
2396         }
2397         return media_type;
2398 }
2399
2400 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2401  ** @hw: pointer to hardware structure
2402  **/
2403 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2404 {
2405         s32 status;
2406         u16 reg;
2407
2408         status = hw->phy.ops.read_reg(hw,
2409                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2410                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2411                                       &reg);
2412         if (status)
2413                 return status;
2414
2415         /* If PHY FW reset completed bit is set then this is the first
2416          * SW instance after a power on so the PHY FW must be un-stalled.
2417          */
2418         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2419                 status = hw->phy.ops.read_reg(hw,
2420                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2421                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2422                                         &reg);
2423                 if (status)
2424                         return status;
2425
2426                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2427
2428                 status = hw->phy.ops.write_reg(hw,
2429                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2430                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2431                                         reg);
2432                 if (status)
2433                         return status;
2434         }
2435
2436         return status;
2437 }
2438
2439 /**
2440  * ixgbe_set_mdio_speed - Set MDIO clock speed
2441  * @hw: pointer to hardware structure
2442  */
2443 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2444 {
2445         u32 hlreg0;
2446
2447         switch (hw->device_id) {
2448         case IXGBE_DEV_ID_X550EM_X_10G_T:
2449         case IXGBE_DEV_ID_X550EM_A_SFP:
2450                 /* Config MDIO clock speed before the first MDIO PHY access */
2451                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2452                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2453                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2454                 break;
2455         default:
2456                 break;
2457         }
2458 }
2459
2460 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2461  **  @hw: pointer to hardware structure
2462  **
2463  **  Resets the hardware by resetting the transmit and receive units, masks
2464  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2465  **  reset.
2466  **/
2467 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2468 {
2469         ixgbe_link_speed link_speed;
2470         s32 status;
2471         u32 ctrl = 0;
2472         u32 i;
2473         bool link_up = false;
2474
2475         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2476         status = hw->mac.ops.stop_adapter(hw);
2477         if (status)
2478                 return status;
2479
2480         /* flush pending Tx transactions */
2481         ixgbe_clear_tx_pending(hw);
2482
2483         /* PHY ops must be identified and initialized prior to reset */
2484
2485         /* Identify PHY and related function pointers */
2486         status = hw->phy.ops.init(hw);
2487
2488         /* start the external PHY */
2489         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2490                 status = ixgbe_init_ext_t_x550em(hw);
2491                 if (status)
2492                         return status;
2493         }
2494
2495         /* Setup SFP module if there is one present. */
2496         if (hw->phy.sfp_setup_needed) {
2497                 status = hw->mac.ops.setup_sfp(hw);
2498                 hw->phy.sfp_setup_needed = false;
2499         }
2500
2501         /* Reset PHY */
2502         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2503                 hw->phy.ops.reset(hw);
2504
2505 mac_reset_top:
2506         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2507          * If link reset is used when link is up, it might reset the PHY when
2508          * mng is using it.  If link is down or the flag to force full link
2509          * reset is set, then perform link reset.
2510          */
2511         ctrl = IXGBE_CTRL_LNK_RST;
2512
2513         if (!hw->force_full_reset) {
2514                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2515                 if (link_up)
2516                         ctrl = IXGBE_CTRL_RST;
2517         }
2518
2519         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2520         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2521         IXGBE_WRITE_FLUSH(hw);
2522         usleep_range(1000, 1200);
2523
2524         /* Poll for reset bit to self-clear meaning reset is complete */
2525         for (i = 0; i < 10; i++) {
2526                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2527                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2528                         break;
2529                 udelay(1);
2530         }
2531
2532         if (ctrl & IXGBE_CTRL_RST_MASK) {
2533                 status = IXGBE_ERR_RESET_FAILED;
2534                 hw_dbg(hw, "Reset polling failed to complete.\n");
2535         }
2536
2537         msleep(50);
2538
2539         /* Double resets are required for recovery from certain error
2540          * clear the multicast table.  Also reset num_rar_entries to 128,
2541          * since we modify this value when programming the SAN MAC address.
2542          */
2543         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2544                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2545                 goto mac_reset_top;
2546         }
2547
2548         /* Store the permanent mac address */
2549         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2550
2551         /* Store MAC address from RAR0, clear receive address registers, and
2552          * clear the multicast table.  Also reset num_rar_entries to 128,
2553          * since we modify this value when programming the SAN MAC address.
2554          */
2555         hw->mac.num_rar_entries = 128;
2556         hw->mac.ops.init_rx_addrs(hw);
2557
2558         ixgbe_set_mdio_speed(hw);
2559
2560         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2561                 ixgbe_setup_mux_ctl(hw);
2562
2563         return status;
2564 }
2565
2566 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2567  *      anti-spoofing
2568  *  @hw:  pointer to hardware structure
2569  *  @enable: enable or disable switch for Ethertype anti-spoofing
2570  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2571  **/
2572 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2573                                                    bool enable, int vf)
2574 {
2575         int vf_target_reg = vf >> 3;
2576         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2577         u32 pfvfspoof;
2578
2579         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2580         if (enable)
2581                 pfvfspoof |= (1 << vf_target_shift);
2582         else
2583                 pfvfspoof &= ~(1 << vf_target_shift);
2584
2585         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2586 }
2587
2588 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2589  *  @hw: pointer to hardware structure
2590  *  @enable: enable or disable source address pruning
2591  *  @pool: Rx pool to set source address pruning for
2592  **/
2593 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2594                                                   bool enable,
2595                                                   unsigned int pool)
2596 {
2597         u64 pfflp;
2598
2599         /* max rx pool is 63 */
2600         if (pool > 63)
2601                 return;
2602
2603         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2604         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2605
2606         if (enable)
2607                 pfflp |= (1ULL << pool);
2608         else
2609                 pfflp &= ~(1ULL << pool);
2610
2611         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2612         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2613 }
2614
2615 /**
2616  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2617  * @hw: pointer to hardware structure
2618  * @state: set mux if 1, clear if 0
2619  */
2620 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2621 {
2622         u32 esdp;
2623
2624         if (!hw->bus.lan_id)
2625                 return;
2626         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2627         if (state)
2628                 esdp |= IXGBE_ESDP_SDP1;
2629         else
2630                 esdp &= ~IXGBE_ESDP_SDP1;
2631         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2632         IXGBE_WRITE_FLUSH(hw);
2633 }
2634
2635 /**
2636  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2637  * @hw: pointer to hardware structure
2638  * @mask: Mask to specify which semaphore to acquire
2639  *
2640  * Acquires the SWFW semaphore and sets the I2C MUX
2641  */
2642 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2643 {
2644         s32 status;
2645
2646         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2647         if (status)
2648                 return status;
2649
2650         if (mask & IXGBE_GSSR_I2C_MASK)
2651                 ixgbe_set_mux(hw, 1);
2652
2653         return 0;
2654 }
2655
2656 /**
2657  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2658  * @hw: pointer to hardware structure
2659  * @mask: Mask to specify which semaphore to release
2660  *
2661  * Releases the SWFW semaphore and sets the I2C MUX
2662  */
2663 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2664 {
2665         if (mask & IXGBE_GSSR_I2C_MASK)
2666                 ixgbe_set_mux(hw, 0);
2667
2668         ixgbe_release_swfw_sync_X540(hw, mask);
2669 }
2670
2671 /**
2672  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
2673  * @hw: pointer to hardware structure
2674  * @mask: Mask to specify which semaphore to acquire
2675  *
2676  * Acquires the SWFW semaphore and get the shared PHY token as needed
2677  */
2678 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2679 {
2680         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2681         int retries = FW_PHY_TOKEN_RETRIES;
2682         s32 status;
2683
2684         while (--retries) {
2685                 status = 0;
2686                 if (hmask)
2687                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
2688                 if (status)
2689                         return status;
2690                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
2691                         return 0;
2692
2693                 status = ixgbe_get_phy_token(hw);
2694                 if (!status)
2695                         return 0;
2696                 if (hmask)
2697                         ixgbe_release_swfw_sync_X540(hw, hmask);
2698                 if (status != IXGBE_ERR_TOKEN_RETRY)
2699                         return status;
2700                 udelay(FW_PHY_TOKEN_DELAY * 1000);
2701         }
2702
2703         return status;
2704 }
2705
2706 /**
2707  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
2708  * @hw: pointer to hardware structure
2709  * @mask: Mask to specify which semaphore to release
2710  *
2711  * Release the SWFW semaphore and puts the shared PHY token as needed
2712  */
2713 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2714 {
2715         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2716
2717         if (mask & IXGBE_GSSR_TOKEN_SM)
2718                 ixgbe_put_phy_token(hw);
2719
2720         if (hmask)
2721                 ixgbe_release_swfw_sync_X540(hw, hmask);
2722 }
2723
2724 /**
2725  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
2726  * @hw: pointer to hardware structure
2727  * @reg_addr: 32 bit address of PHY register to read
2728  * @phy_data: Pointer to read data from PHY register
2729  *
2730  * Reads a value from a specified PHY register using the SWFW lock and PHY
2731  * Token. The PHY Token is needed since the MDIO is shared between to MAC
2732  * instances.
2733  */
2734 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2735                                     u32 device_type, u16 *phy_data)
2736 {
2737         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2738         s32 status;
2739
2740         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2741                 return IXGBE_ERR_SWFW_SYNC;
2742
2743         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
2744
2745         hw->mac.ops.release_swfw_sync(hw, mask);
2746
2747         return status;
2748 }
2749
2750 /**
2751  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
2752  * @hw: pointer to hardware structure
2753  * @reg_addr: 32 bit PHY register to write
2754  * @device_type: 5 bit device type
2755  * @phy_data: Data to write to the PHY register
2756  *
2757  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
2758  * The PHY Token is needed since the MDIO is shared between to MAC instances.
2759  */
2760 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2761                                      u32 device_type, u16 phy_data)
2762 {
2763         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2764         s32 status;
2765
2766         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2767                 return IXGBE_ERR_SWFW_SYNC;
2768
2769         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
2770         hw->mac.ops.release_swfw_sync(hw, mask);
2771
2772         return status;
2773 }
2774
2775 #define X550_COMMON_MAC \
2776         .init_hw                        = &ixgbe_init_hw_generic, \
2777         .start_hw                       = &ixgbe_start_hw_X540, \
2778         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2779         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2780         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2781         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2782         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2783         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2784         .read_analog_reg8               = NULL, \
2785         .write_analog_reg8              = NULL, \
2786         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2787         .check_link                     = &ixgbe_check_mac_link_generic, \
2788         .led_on                         = &ixgbe_led_on_generic, \
2789         .led_off                        = &ixgbe_led_off_generic, \
2790         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2791         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2792         .set_rar                        = &ixgbe_set_rar_generic, \
2793         .clear_rar                      = &ixgbe_clear_rar_generic, \
2794         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2795         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2796         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2797         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2798         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2799         .enable_mc                      = &ixgbe_enable_mc_generic, \
2800         .disable_mc                     = &ixgbe_disable_mc_generic, \
2801         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2802         .set_vfta                       = &ixgbe_set_vfta_generic, \
2803         .fc_enable                      = &ixgbe_fc_enable_generic, \
2804         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2805         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2806         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2807         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2808         .set_source_address_pruning     = \
2809                                 &ixgbe_set_source_address_pruning_X550, \
2810         .set_ethertype_anti_spoofing    = \
2811                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2812         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2813         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2814         .get_thermal_sensor_data        = NULL, \
2815         .init_thermal_sensor_thresh     = NULL, \
2816         .enable_rx                      = &ixgbe_enable_rx_generic, \
2817         .disable_rx                     = &ixgbe_disable_rx_x550, \
2818
2819 static const struct ixgbe_mac_operations mac_ops_X550 = {
2820         X550_COMMON_MAC
2821         .reset_hw               = &ixgbe_reset_hw_X540,
2822         .get_media_type         = &ixgbe_get_media_type_X540,
2823         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2824         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2825         .setup_link             = &ixgbe_setup_mac_link_X540,
2826         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2827         .get_bus_info           = &ixgbe_get_bus_info_generic,
2828         .setup_sfp              = NULL,
2829         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2830         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2831         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2832         .prot_autoc_read        = prot_autoc_read_generic,
2833         .prot_autoc_write       = prot_autoc_write_generic,
2834         .setup_fc               = ixgbe_setup_fc_generic,
2835 };
2836
2837 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2838         X550_COMMON_MAC
2839         .reset_hw               = &ixgbe_reset_hw_X550em,
2840         .get_media_type         = &ixgbe_get_media_type_X550em,
2841         .get_san_mac_addr       = NULL,
2842         .get_wwn_prefix         = NULL,
2843         .setup_link             = NULL, /* defined later */
2844         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2845         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2846         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2847         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2848         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2849         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2850         .setup_fc               = NULL, /* defined later */
2851         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
2852         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
2853 };
2854
2855 static struct ixgbe_mac_operations mac_ops_x550em_a = {
2856         X550_COMMON_MAC
2857         .reset_hw               = ixgbe_reset_hw_X550em,
2858         .get_media_type         = ixgbe_get_media_type_X550em,
2859         .get_san_mac_addr       = NULL,
2860         .get_wwn_prefix         = NULL,
2861         .setup_link             = NULL, /* defined later */
2862         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
2863         .get_bus_info           = ixgbe_get_bus_info_X550em,
2864         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2865         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
2866         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
2867         .setup_fc               = ixgbe_setup_fc_generic,
2868         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
2869         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
2870 };
2871
2872 #define X550_COMMON_EEP \
2873         .read                   = &ixgbe_read_ee_hostif_X550, \
2874         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2875         .write                  = &ixgbe_write_ee_hostif_X550, \
2876         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2877         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2878         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2879         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2880
2881 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2882         X550_COMMON_EEP
2883         .init_params            = &ixgbe_init_eeprom_params_X550,
2884 };
2885
2886 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2887         X550_COMMON_EEP
2888         .init_params            = &ixgbe_init_eeprom_params_X540,
2889 };
2890
2891 #define X550_COMMON_PHY \
2892         .identify_sfp           = &ixgbe_identify_module_generic, \
2893         .reset                  = NULL, \
2894         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2895         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2896         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2897         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2898         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2899         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2900         .setup_link             = &ixgbe_setup_phy_link_generic, \
2901         .set_phy_power          = NULL, \
2902         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2903         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2904
2905 static const struct ixgbe_phy_operations phy_ops_X550 = {
2906         X550_COMMON_PHY
2907         .init                   = NULL,
2908         .identify               = &ixgbe_identify_phy_generic,
2909         .read_reg               = &ixgbe_read_phy_reg_generic,
2910         .write_reg              = &ixgbe_write_phy_reg_generic,
2911 };
2912
2913 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
2914         X550_COMMON_PHY
2915         .init                   = &ixgbe_init_phy_ops_X550em,
2916         .identify               = &ixgbe_identify_phy_x550em,
2917         .read_reg               = &ixgbe_read_phy_reg_generic,
2918         .write_reg              = &ixgbe_write_phy_reg_generic,
2919         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2920         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2921         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2922         .write_i2c_combined_unlocked =
2923                                      &ixgbe_write_i2c_combined_generic_unlocked,
2924 };
2925
2926 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
2927         X550_COMMON_PHY
2928         .init                   = &ixgbe_init_phy_ops_X550em,
2929         .identify               = &ixgbe_identify_phy_x550em,
2930         .read_reg               = &ixgbe_read_phy_reg_x550a,
2931         .write_reg              = &ixgbe_write_phy_reg_x550a,
2932 };
2933
2934 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2935         IXGBE_MVALS_INIT(X550)
2936 };
2937
2938 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2939         IXGBE_MVALS_INIT(X550EM_x)
2940 };
2941
2942 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
2943         IXGBE_MVALS_INIT(X550EM_a)
2944 };
2945
2946 const struct ixgbe_info ixgbe_X550_info = {
2947         .mac                    = ixgbe_mac_X550,
2948         .get_invariants         = &ixgbe_get_invariants_X540,
2949         .mac_ops                = &mac_ops_X550,
2950         .eeprom_ops             = &eeprom_ops_X550,
2951         .phy_ops                = &phy_ops_X550,
2952         .mbx_ops                = &mbx_ops_generic,
2953         .mvals                  = ixgbe_mvals_X550,
2954 };
2955
2956 const struct ixgbe_info ixgbe_X550EM_x_info = {
2957         .mac                    = ixgbe_mac_X550EM_x,
2958         .get_invariants         = &ixgbe_get_invariants_X550_x,
2959         .mac_ops                = &mac_ops_X550EM_x,
2960         .eeprom_ops             = &eeprom_ops_X550EM_x,
2961         .phy_ops                = &phy_ops_X550EM_x,
2962         .mbx_ops                = &mbx_ops_generic,
2963         .mvals                  = ixgbe_mvals_X550EM_x,
2964 };
2965
2966 const struct ixgbe_info ixgbe_x550em_a_info = {
2967         .mac                    = ixgbe_mac_x550em_a,
2968         .get_invariants         = &ixgbe_get_invariants_X550_x,
2969         .mac_ops                = &mac_ops_x550em_a,
2970         .eeprom_ops             = &eeprom_ops_X550EM_x,
2971         .phy_ops                = &phy_ops_x550em_a,
2972         .mbx_ops                = &mbx_ops_generic,
2973         .mvals                  = ixgbe_mvals_x550em_a,
2974 };