drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2016 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  31
  32 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_mac_info *mac = &hw->mac;
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so simular */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  41                 phy->ops.set_phy_power = NULL;
  42
  43         return 0;
  44 }
  45
  46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  47  *  @hw: pointer to hardware structure
  48  **/
  49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  50 {
  51         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  52
  53         if (hw->bus.lan_id) {
  54                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  55                 esdp |= IXGBE_ESDP_SDP1_DIR;
  56         }
  57         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  58         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  59         IXGBE_WRITE_FLUSH(hw);
  60 }
  61
  62 /**
  63  * ixgbe_read_cs4227 - Read CS4227 register
  64  * @hw: pointer to hardware structure
  65  * @reg: register number to write
  66  * @value: pointer to receive value read
  67  *
  68  * Returns status code
  69  */
  70 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  71 {
  72         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  73                                                       value);
  74 }
  75
  76 /**
  77  * ixgbe_write_cs4227 - Write CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: value to write to register
  81  *
  82  * Returns status code
  83  */
  84 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  85 {
  86         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  87                                                        value);
  88 }
  89
  90 /**
  91  * ixgbe_read_pe - Read register from port expander
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to read
  94  * @value: pointer to receive read value
  95  *
  96  * Returns status code
  97  */
  98 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  99 {
 100         s32 status;
 101
 102         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 103         if (status)
 104                 hw_err(hw, "port expander access failed with %d\n", status);
 105         return status;
 106 }
 107
 108 /**
 109  * ixgbe_write_pe - Write register to port expander
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write
 113  *
 114  * Returns status code
 115  */
 116 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 117 {
 118         s32 status;
 119
 120         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 121                                                        value);
 122         if (status)
 123                 hw_err(hw, "port expander access failed with %d\n", status);
 124         return status;
 125 }
 126
 127 /**
 128  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 129  * @hw: pointer to hardware structure
 130  *
 131  * This function assumes that the caller has acquired the proper semaphore.
 132  * Returns error code
 133  */
 134 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 135 {
 136         s32 status;
 137         u32 retry;
 138         u16 value;
 139         u8 reg;
 140
 141         /* Trigger hard reset. */
 142         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 143         if (status)
 144                 return status;
 145         reg |= IXGBE_PE_BIT1;
 146         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 147         if (status)
 148                 return status;
 149
 150         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 151         if (status)
 152                 return status;
 153         reg &= ~IXGBE_PE_BIT1;
 154         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 155         if (status)
 156                 return status;
 157
 158         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 159         if (status)
 160                 return status;
 161         reg &= ~IXGBE_PE_BIT1;
 162         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 163         if (status)
 164                 return status;
 165
 166         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 167
 168         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 169         if (status)
 170                 return status;
 171         reg |= IXGBE_PE_BIT1;
 172         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 173         if (status)
 174                 return status;
 175
 176         /* Wait for the reset to complete. */
 177         msleep(IXGBE_CS4227_RESET_DELAY);
 178         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 179                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 180                                            &value);
 181                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 182                         break;
 183                 msleep(IXGBE_CS4227_CHECK_DELAY);
 184         }
 185         if (retry == IXGBE_CS4227_RETRIES) {
 186                 hw_err(hw, "CS4227 reset did not complete\n");
 187                 return IXGBE_ERR_PHY;
 188         }
 189
 190         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 191         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 192                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 193                 return IXGBE_ERR_PHY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 201  * @hw: pointer to hardware structure
 202  */
 203 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 204 {
 205         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 206         s32 status;
 207         u16 value;
 208         u8 retry;
 209
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 212                 if (status) {
 213                         hw_err(hw, "semaphore failed with %d\n", status);
 214                         msleep(IXGBE_CS4227_CHECK_DELAY);
 215                         continue;
 216                 }
 217
 218                 /* Get status of reset flow. */
 219                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 220                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 221                         goto out;
 222
 223                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 224                         break;
 225
 226                 /* Reset is pending. Wait and check again. */
 227                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 228                 msleep(IXGBE_CS4227_CHECK_DELAY);
 229         }
 230         /* If still pending, assume other instance failed. */
 231         if (retry == IXGBE_CS4227_RETRIES) {
 232                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 233                 if (status) {
 234                         hw_err(hw, "semaphore failed with %d\n", status);
 235                         return;
 236                 }
 237         }
 238
 239         /* Reset the CS4227. */
 240         status = ixgbe_reset_cs4227(hw);
 241         if (status) {
 242                 hw_err(hw, "CS4227 reset failed: %d", status);
 243                 goto out;
 244         }
 245
 246         /* Reset takes so long, temporarily release semaphore in case the
 247          * other driver instance is waiting for the reset indication.
 248          */
 249         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 250                            IXGBE_CS4227_RESET_PENDING);
 251         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 252         usleep_range(10000, 12000);
 253         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254         if (status) {
 255                 hw_err(hw, "semaphore failed with %d", status);
 256                 return;
 257         }
 258
 259         /* Record completion for next time. */
 260         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 261                                     IXGBE_CS4227_RESET_COMPLETE);
 262
 263 out:
 264         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 265         msleep(hw->eeprom.semaphore_delay);
 266 }
 267
 268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 269  *  @hw: pointer to hardware structure
 270  *
 271  *  Returns error code
 272  */
 273 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 274 {
 275         switch (hw->device_id) {
 276         case IXGBE_DEV_ID_X550EM_X_SFP:
 277                 /* set up for CS4227 usage */
 278                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 279                 ixgbe_setup_mux_ctl(hw);
 280                 ixgbe_check_cs4227(hw);
 281                 return ixgbe_identify_module_generic(hw);
 282         case IXGBE_DEV_ID_X550EM_X_KX4:
 283                 hw->phy.type = ixgbe_phy_x550em_kx4;
 284                 break;
 285         case IXGBE_DEV_ID_X550EM_X_KR:
 286                 hw->phy.type = ixgbe_phy_x550em_kr;
 287                 break;
 288         case IXGBE_DEV_ID_X550EM_X_1G_T:
 289         case IXGBE_DEV_ID_X550EM_X_10G_T:
 290                 return ixgbe_identify_phy_generic(hw);
 291         default:
 292                 break;
 293         }
 294         return 0;
 295 }
 296
 297 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 298                                      u32 device_type, u16 *phy_data)
 299 {
 300         return IXGBE_NOT_IMPLEMENTED;
 301 }
 302
 303 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 304                                       u32 device_type, u16 phy_data)
 305 {
 306         return IXGBE_NOT_IMPLEMENTED;
 307 }
 308
 309 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 310  *  @hw: pointer to hardware structure
 311  *
 312  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 313  *  ixgbe_hw struct in order to set up EEPROM access.
 314  **/
 315 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 316 {
 317         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 318         u32 eec;
 319         u16 eeprom_size;
 320
 321         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 322                 eeprom->semaphore_delay = 10;
 323                 eeprom->type = ixgbe_flash;
 324
 325                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 326                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 327                                     IXGBE_EEC_SIZE_SHIFT);
 328                 eeprom->word_size = 1 << (eeprom_size +
 329                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 330
 331                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 332                        eeprom->type, eeprom->word_size);
 333         }
 334
 335         return 0;
 336 }
 337
 338 /**
 339  * ixgbe_iosf_wait - Wait for IOSF command completion
 340  * @hw: pointer to hardware structure
 341  * @ctrl: pointer to location to receive final IOSF control value
 342  *
 343  * Return: failing status on timeout
 344  *
 345  * Note: ctrl can be NULL if the IOSF control register value is not needed
 346  */
 347 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 348 {
 349         u32 i, command;
 350
 351         /* Check every 10 usec to see if the address cycle completed.
 352          * The SB IOSF BUSY bit will clear when the operation is
 353          * complete.
 354          */
 355         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 356                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 357                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 358                         break;
 359                 udelay(10);
 360         }
 361         if (ctrl)
 362                 *ctrl = command;
 363         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 364                 hw_dbg(hw, "IOSF wait timed out\n");
 365                 return IXGBE_ERR_PHY;
 366         }
 367
 368         return 0;
 369 }
 370
 371 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 372  *  IOSF device
 373  *  @hw: pointer to hardware structure
 374  *  @reg_addr: 32 bit PHY register to write
 375  *  @device_type: 3 bit device type
 376  *  @phy_data: Pointer to read data from the register
 377  **/
 378 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 379                                        u32 device_type, u32 *data)
 380 {
 381         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 382         u32 command, error;
 383         s32 ret;
 384
 385         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 386         if (ret)
 387                 return ret;
 388
 389         ret = ixgbe_iosf_wait(hw, NULL);
 390         if (ret)
 391                 goto out;
 392
 393         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 394                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 395
 396         /* Write IOSF control register */
 397         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 398
 399         ret = ixgbe_iosf_wait(hw, &command);
 400
 401         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 402                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 403                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 404                 hw_dbg(hw, "Failed to read, error %x\n", error);
 405                 return IXGBE_ERR_PHY;
 406         }
 407
 408         if (!ret)
 409                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 410
 411 out:
 412         hw->mac.ops.release_swfw_sync(hw, gssr);
 413         return ret;
 414 }
 415
 416 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 417  *  command assuming that the semaphore is already obtained.
 418  *  @hw: pointer to hardware structure
 419  *  @offset: offset of  word in the EEPROM to read
 420  *  @data: word read from the EEPROM
 421  *
 422  *  Reads a 16 bit word from the EEPROM using the hostif.
 423  **/
 424 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 425                                           u16 *data)
 426 {
 427         s32 status;
 428         struct ixgbe_hic_read_shadow_ram buffer;
 429
 430         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 431         buffer.hdr.req.buf_lenh = 0;
 432         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 433         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 434
 435         /* convert offset from words to bytes */
 436         buffer.address = cpu_to_be32(offset * 2);
 437         /* one word */
 438         buffer.length = cpu_to_be16(sizeof(u16));
 439
 440         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 441                                               sizeof(buffer),
 442                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 443         if (status)
 444                 return status;
 445
 446         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 447                                           FW_NVM_DATA_OFFSET);
 448
 449         return 0;
 450 }
 451
 452 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 453  *  @hw: pointer to hardware structure
 454  *  @offset: offset of  word in the EEPROM to read
 455  *  @words: number of words
 456  *  @data: word(s) read from the EEPROM
 457  *
 458  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 459  **/
 460 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 461                                             u16 offset, u16 words, u16 *data)
 462 {
 463         struct ixgbe_hic_read_shadow_ram buffer;
 464         u32 current_word = 0;
 465         u16 words_to_read;
 466         s32 status;
 467         u32 i;
 468
 469         /* Take semaphore for the entire operation. */
 470         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 471         if (status) {
 472                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 473                 return status;
 474         }
 475
 476         while (words) {
 477                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 478                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 479                 else
 480                         words_to_read = words;
 481
 482                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 483                 buffer.hdr.req.buf_lenh = 0;
 484                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 485                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 486
 487                 /* convert offset from words to bytes */
 488                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 489                 buffer.length = cpu_to_be16(words_to_read * 2);
 490
 491                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 492                                                       sizeof(buffer),
 493                                                       IXGBE_HI_COMMAND_TIMEOUT,
 494                                                       false);
 495                 if (status) {
 496                         hw_dbg(hw, "Host interface command failed\n");
 497                         goto out;
 498                 }
 499
 500                 for (i = 0; i < words_to_read; i++) {
 501                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 502                                   2 * i;
 503                         u32 value = IXGBE_READ_REG(hw, reg);
 504
 505                         data[current_word] = (u16)(value & 0xffff);
 506                         current_word++;
 507                         i++;
 508                         if (i < words_to_read) {
 509                                 value >>= 16;
 510                                 data[current_word] = (u16)(value & 0xffff);
 511                                 current_word++;
 512                         }
 513                 }
 514                 words -= words_to_read;
 515         }
 516
 517 out:
 518         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 519         return status;
 520 }
 521
 522 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 523  *  @hw: pointer to hardware structure
 524  *  @ptr: pointer offset in eeprom
 525  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 526  *  @csum: address of checksum to update
 527  *
 528  *  Returns error status for any failure
 529  **/
 530 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 531                                    u16 size, u16 *csum, u16 *buffer,
 532                                    u32 buffer_size)
 533 {
 534         u16 buf[256];
 535         s32 status;
 536         u16 length, bufsz, i, start;
 537         u16 *local_buffer;
 538
 539         bufsz = sizeof(buf) / sizeof(buf[0]);
 540
 541         /* Read a chunk at the pointer location */
 542         if (!buffer) {
 543                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 544                 if (status) {
 545                         hw_dbg(hw, "Failed to read EEPROM image\n");
 546                         return status;
 547                 }
 548                 local_buffer = buf;
 549         } else {
 550                 if (buffer_size < ptr)
 551                         return  IXGBE_ERR_PARAM;
 552                 local_buffer = &buffer[ptr];
 553         }
 554
 555         if (size) {
 556                 start = 0;
 557                 length = size;
 558         } else {
 559                 start = 1;
 560                 length = local_buffer[0];
 561
 562                 /* Skip pointer section if length is invalid. */
 563                 if (length == 0xFFFF || length == 0 ||
 564                     (ptr + length) >= hw->eeprom.word_size)
 565                         return 0;
 566         }
 567
 568         if (buffer && ((u32)start + (u32)length > buffer_size))
 569                 return IXGBE_ERR_PARAM;
 570
 571         for (i = start; length; i++, length--) {
 572                 if (i == bufsz && !buffer) {
 573                         ptr += bufsz;
 574                         i = 0;
 575                         if (length < bufsz)
 576                                 bufsz = length;
 577
 578                         /* Read a chunk at the pointer location */
 579                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 580                                                                   bufsz, buf);
 581                         if (status) {
 582                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 583                                 return status;
 584                         }
 585                 }
 586                 *csum += local_buffer[i];
 587         }
 588         return 0;
 589 }
 590
 591 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 592  *  @hw: pointer to hardware structure
 593  *  @buffer: pointer to buffer containing calculated checksum
 594  *  @buffer_size: size of buffer
 595  *
 596  *  Returns a negative error code on error, or the 16-bit checksum
 597  **/
 598 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 599                                     u32 buffer_size)
 600 {
 601         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 602         u16 *local_buffer;
 603         s32 status;
 604         u16 checksum = 0;
 605         u16 pointer, i, size;
 606
 607         hw->eeprom.ops.init_params(hw);
 608
 609         if (!buffer) {
 610                 /* Read pointer area */
 611                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 612                                                 IXGBE_EEPROM_LAST_WORD + 1,
 613                                                 eeprom_ptrs);
 614                 if (status) {
 615                         hw_dbg(hw, "Failed to read EEPROM image\n");
 616                         return status;
 617                 }
 618                 local_buffer = eeprom_ptrs;
 619         } else {
 620                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 621                         return IXGBE_ERR_PARAM;
 622                 local_buffer = buffer;
 623         }
 624
 625         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 626          * checksum word itself
 627          */
 628         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 629                 if (i != IXGBE_EEPROM_CHECKSUM)
 630                         checksum += local_buffer[i];
 631
 632         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 633          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 634          */
 635         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 636                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 637                         continue;
 638
 639                 pointer = local_buffer[i];
 640
 641                 /* Skip pointer section if the pointer is invalid. */
 642                 if (pointer == 0xFFFF || pointer == 0 ||
 643                     pointer >= hw->eeprom.word_size)
 644                         continue;
 645
 646                 switch (i) {
 647                 case IXGBE_PCIE_GENERAL_PTR:
 648                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 649                         break;
 650                 case IXGBE_PCIE_CONFIG0_PTR:
 651                 case IXGBE_PCIE_CONFIG1_PTR:
 652                         size = IXGBE_PCIE_CONFIG_SIZE;
 653                         break;
 654                 default:
 655                         size = 0;
 656                         break;
 657                 }
 658
 659                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 660                                                  buffer, buffer_size);
 661                 if (status)
 662                         return status;
 663         }
 664
 665         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 666
 667         return (s32)checksum;
 668 }
 669
 670 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 671  *  @hw: pointer to hardware structure
 672  *
 673  *  Returns a negative error code on error, or the 16-bit checksum
 674  **/
 675 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 676 {
 677         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 678 }
 679
 680 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 681  *  @hw: pointer to hardware structure
 682  *  @offset: offset of  word in the EEPROM to read
 683  *  @data: word read from the EEPROM
 684  *
 685  *   Reads a 16 bit word from the EEPROM using the hostif.
 686  **/
 687 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 688 {
 689         s32 status = 0;
 690
 691         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 692                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 693                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 694         } else {
 695                 status = IXGBE_ERR_SWFW_SYNC;
 696         }
 697
 698         return status;
 699 }
 700
 701 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 702  *  @hw: pointer to hardware structure
 703  *  @checksum_val: calculated checksum
 704  *
 705  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 706  *  caller does not need checksum_val, the value can be NULL.
 707  **/
 708 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 709                                                u16 *checksum_val)
 710 {
 711         s32 status;
 712         u16 checksum;
 713         u16 read_checksum = 0;
 714
 715         /* Read the first word from the EEPROM. If this times out or fails, do
 716          * not continue or we could be in for a very long wait while every
 717          * EEPROM read fails
 718          */
 719         status = hw->eeprom.ops.read(hw, 0, &checksum);
 720         if (status) {
 721                 hw_dbg(hw, "EEPROM read failed\n");
 722                 return status;
 723         }
 724
 725         status = hw->eeprom.ops.calc_checksum(hw);
 726         if (status < 0)
 727                 return status;
 728
 729         checksum = (u16)(status & 0xffff);
 730
 731         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 732                                            &read_checksum);
 733         if (status)
 734                 return status;
 735
 736         /* Verify read checksum from EEPROM is the same as
 737          * calculated checksum
 738          */
 739         if (read_checksum != checksum) {
 740                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 741                 hw_dbg(hw, "Invalid EEPROM checksum");
 742         }
 743
 744         /* If the user cares, return the calculated checksum */
 745         if (checksum_val)
 746                 *checksum_val = checksum;
 747
 748         return status;
 749 }
 750
 751 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 752  *  @hw: pointer to hardware structure
 753  *  @offset: offset of  word in the EEPROM to write
 754  *  @data: word write to the EEPROM
 755  *
 756  *  Write a 16 bit word to the EEPROM using the hostif.
 757  **/
 758 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 759                                            u16 data)
 760 {
 761         s32 status;
 762         struct ixgbe_hic_write_shadow_ram buffer;
 763
 764         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 765         buffer.hdr.req.buf_lenh = 0;
 766         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 767         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 768
 769         /* one word */
 770         buffer.length = cpu_to_be16(sizeof(u16));
 771         buffer.data = data;
 772         buffer.address = cpu_to_be32(offset * 2);
 773
 774         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 775                                               sizeof(buffer),
 776                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 777         return status;
 778 }
 779
 780 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 781  *  @hw: pointer to hardware structure
 782  *  @offset: offset of  word in the EEPROM to write
 783  *  @data: word write to the EEPROM
 784  *
 785  *  Write a 16 bit word to the EEPROM using the hostif.
 786  **/
 787 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 788 {
 789         s32 status = 0;
 790
 791         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 792                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 793                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 794         } else {
 795                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 796                 status = IXGBE_ERR_SWFW_SYNC;
 797         }
 798
 799         return status;
 800 }
 801
 802 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 803  *  @hw: pointer to hardware structure
 804  *
 805  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 806  **/
 807 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 808 {
 809         s32 status = 0;
 810         union ixgbe_hic_hdr2 buffer;
 811
 812         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 813         buffer.req.buf_lenh = 0;
 814         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 815         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 816
 817         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 818                                               sizeof(buffer),
 819                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 820         return status;
 821 }
 822
 823 /**
 824  * ixgbe_get_bus_info_X550em - Set PCI bus info
 825  * @hw: pointer to hardware structure
 826  *
 827  * Sets bus link width and speed to unknown because X550em is
 828  * not a PCI device.
 829  **/
 830 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 831 {
 832         hw->bus.type  = ixgbe_bus_type_internal;
 833         hw->bus.width = ixgbe_bus_width_unknown;
 834         hw->bus.speed = ixgbe_bus_speed_unknown;
 835
 836         hw->mac.ops.set_lan_id(hw);
 837
 838         return 0;
 839 }
 840
 841 /** ixgbe_disable_rx_x550 - Disable RX unit
 842  *
 843  *  Enables the Rx DMA unit for x550
 844  **/
 845 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 846 {
 847         u32 rxctrl, pfdtxgswc;
 848         s32 status;
 849         struct ixgbe_hic_disable_rxen fw_cmd;
 850
 851         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 852         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 853                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 854                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 855                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 856                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 857                         hw->mac.set_lben = true;
 858                 } else {
 859                         hw->mac.set_lben = false;
 860                 }
 861
 862                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 863                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 864                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 865                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 866
 867                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 868                                         sizeof(struct ixgbe_hic_disable_rxen),
 869                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 870
 871                 /* If we fail - disable RX using register write */
 872                 if (status) {
 873                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 874                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 875                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 876                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 877                         }
 878                 }
 879         }
 880 }
 881
 882 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 883  *  @hw: pointer to hardware structure
 884  *
 885  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 886  *  checksum and updates the EEPROM and instructs the hardware to update
 887  *  the flash.
 888  **/
 889 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 890 {
 891         s32 status;
 892         u16 checksum = 0;
 893
 894         /* Read the first word from the EEPROM. If this times out or fails, do
 895          * not continue or we could be in for a very long wait while every
 896          * EEPROM read fails
 897          */
 898         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 899         if (status) {
 900                 hw_dbg(hw, "EEPROM read failed\n");
 901                 return status;
 902         }
 903
 904         status = ixgbe_calc_eeprom_checksum_X550(hw);
 905         if (status < 0)
 906                 return status;
 907
 908         checksum = (u16)(status & 0xffff);
 909
 910         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 911                                             checksum);
 912         if (status)
 913                 return status;
 914
 915         status = ixgbe_update_flash_X550(hw);
 916
 917         return status;
 918 }
 919
 920 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
 921  *  @hw: pointer to hardware structure
 922  *  @offset: offset of  word in the EEPROM to write
 923  *  @words: number of words
 924  *  @data: word(s) write to the EEPROM
 925  *
 926  *
 927  *  Write a 16 bit word(s) to the EEPROM using the hostif.
 928  **/
 929 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 930                                              u16 offset, u16 words,
 931                                              u16 *data)
 932 {
 933         s32 status = 0;
 934         u32 i = 0;
 935
 936         /* Take semaphore for the entire operation. */
 937         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 938         if (status) {
 939                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
 940                 return status;
 941         }
 942
 943         for (i = 0; i < words; i++) {
 944                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
 945                                                          data[i]);
 946                 if (status) {
 947                         hw_dbg(hw, "Eeprom buffered write failed\n");
 948                         break;
 949                 }
 950         }
 951
 952         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 953
 954         return status;
 955 }
 956
 957 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
 958  *  IOSF device
 959  *
 960  *  @hw: pointer to hardware structure
 961  *  @reg_addr: 32 bit PHY register to write
 962  *  @device_type: 3 bit device type
 963  *  @data: Data to write to the register
 964  **/
 965 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 966                                         u32 device_type, u32 data)
 967 {
 968         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 969         u32 command, error;
 970         s32 ret;
 971
 972         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 973         if (ret)
 974                 return ret;
 975
 976         ret = ixgbe_iosf_wait(hw, NULL);
 977         if (ret)
 978                 goto out;
 979
 980         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 981                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 982
 983         /* Write IOSF control register */
 984         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 985
 986         /* Write IOSF data register */
 987         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 988
 989         ret = ixgbe_iosf_wait(hw, &command);
 990
 991         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 992                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 993                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 994                 hw_dbg(hw, "Failed to write, error %x\n", error);
 995                 return IXGBE_ERR_PHY;
 996         }
 997
 998 out:
 999         hw->mac.ops.release_swfw_sync(hw, gssr);
1000         return ret;
1001 }
1002
1003 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1004  *  @hw: pointer to hardware structure
1005  *  @speed: the link speed to force
1006  *
1007  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1008  *  internal and external PHY at a specific speed, without autonegotiation.
1009  **/
1010 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1011 {
1012         s32 status;
1013         u32 reg_val;
1014
1015         /* Disable AN and force speed to 10G Serial. */
1016         status = ixgbe_read_iosf_sb_reg_x550(hw,
1017                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1018                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1019         if (status)
1020                 return status;
1021
1022         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1023         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1024
1025         /* Select forced link speed for internal PHY. */
1026         switch (*speed) {
1027         case IXGBE_LINK_SPEED_10GB_FULL:
1028                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1029                 break;
1030         case IXGBE_LINK_SPEED_1GB_FULL:
1031                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1032                 break;
1033         default:
1034                 /* Other link speeds are not supported by internal KR PHY. */
1035                 return IXGBE_ERR_LINK_SETUP;
1036         }
1037
1038         status = ixgbe_write_iosf_sb_reg_x550(hw,
1039                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1040                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1041         if (status)
1042                 return status;
1043
1044         /* Disable training protocol FSM. */
1045         status = ixgbe_read_iosf_sb_reg_x550(hw,
1046                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1047                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1048         if (status)
1049                 return status;
1050
1051         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1052         status = ixgbe_write_iosf_sb_reg_x550(hw,
1053                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1054                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1055         if (status)
1056                 return status;
1057
1058         /* Disable Flex from training TXFFE. */
1059         status = ixgbe_read_iosf_sb_reg_x550(hw,
1060                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1061                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1062         if (status)
1063                 return status;
1064
1065         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1066         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1067         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1068         status = ixgbe_write_iosf_sb_reg_x550(hw,
1069                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1070                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1071         if (status)
1072                 return status;
1073
1074         status = ixgbe_read_iosf_sb_reg_x550(hw,
1075                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1076                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1077         if (status)
1078                 return status;
1079
1080         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1081         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1082         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1083         status = ixgbe_write_iosf_sb_reg_x550(hw,
1084                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1085                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1086         if (status)
1087                 return status;
1088
1089         /* Enable override for coefficients. */
1090         status = ixgbe_read_iosf_sb_reg_x550(hw,
1091                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1092                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1093         if (status)
1094                 return status;
1095
1096         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1097         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1098         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1099         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1100         status = ixgbe_write_iosf_sb_reg_x550(hw,
1101                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1102                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1103         if (status)
1104                 return status;
1105
1106         /* Toggle port SW reset by AN reset. */
1107         status = ixgbe_read_iosf_sb_reg_x550(hw,
1108                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1109                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1110         if (status)
1111                 return status;
1112
1113         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1114         status = ixgbe_write_iosf_sb_reg_x550(hw,
1115                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1116                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1117
1118         return status;
1119 }
1120
1121 /**
1122  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1123  *  @hw: pointer to hardware structure
1124  *  @linear: true if SFP module is linear
1125  */
1126 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1127 {
1128         switch (hw->phy.sfp_type) {
1129         case ixgbe_sfp_type_not_present:
1130                 return IXGBE_ERR_SFP_NOT_PRESENT;
1131         case ixgbe_sfp_type_da_cu_core0:
1132         case ixgbe_sfp_type_da_cu_core1:
1133                 *linear = true;
1134                 break;
1135         case ixgbe_sfp_type_srlr_core0:
1136         case ixgbe_sfp_type_srlr_core1:
1137         case ixgbe_sfp_type_da_act_lmt_core0:
1138         case ixgbe_sfp_type_da_act_lmt_core1:
1139         case ixgbe_sfp_type_1g_sx_core0:
1140         case ixgbe_sfp_type_1g_sx_core1:
1141         case ixgbe_sfp_type_1g_lx_core0:
1142         case ixgbe_sfp_type_1g_lx_core1:
1143                 *linear = false;
1144                 break;
1145         case ixgbe_sfp_type_unknown:
1146         case ixgbe_sfp_type_1g_cu_core0:
1147         case ixgbe_sfp_type_1g_cu_core1:
1148         default:
1149                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1150         }
1151
1152         return 0;
1153 }
1154
1155 /**
1156  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1157  *  @hw: pointer to hardware structure
1158  *
1159  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1160  */
1161 static s32
1162 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1163                                 ixgbe_link_speed speed,
1164                                 __always_unused bool autoneg_wait_to_complete)
1165 {
1166         s32 status;
1167         u16 slice, value;
1168         bool setup_linear = false;
1169
1170         /* Check if SFP module is supported and linear */
1171         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1172
1173         /* If no SFP module present, then return success. Return success since
1174          * there is no reason to configure CS4227 and SFP not present error is
1175          * not accepted in the setup MAC link flow.
1176          */
1177         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1178                 return 0;
1179
1180         if (status)
1181                 return status;
1182
1183         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1184                 /* Configure CS4227 LINE side to 10G SR. */
1185                 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1186                 value = IXGBE_CS4227_SPEED_10G;
1187                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1188                                                           slice, value);
1189                 if (status)
1190                         goto i2c_err;
1191
1192                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1193                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1194                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1195                                                           slice, value);
1196                 if (status)
1197                         goto i2c_err;
1198
1199                 /* Configure CS4227 for HOST connection rate then type. */
1200                 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1201                 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1202                         IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1203                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1204                                                           slice, value);
1205                 if (status)
1206                         goto i2c_err;
1207
1208                 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1209                 if (setup_linear)
1210                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1211                 else
1212                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1213                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1214                                                           slice, value);
1215                 if (status)
1216                         goto i2c_err;
1217
1218                 /* Setup XFI internal link. */
1219                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1220                 if (status) {
1221                         hw_dbg(hw, "setup_ixfi failed with %d\n", status);
1222                         return status;
1223                 }
1224         } else {
1225                 /* Configure internal PHY for KR/KX. */
1226                 status = ixgbe_setup_kr_speed_x550em(hw, speed);
1227                 if (status) {
1228                         hw_dbg(hw, "setup_kr_speed failed with %d\n", status);
1229                         return status;
1230                 }
1231
1232                 /* Configure CS4227 LINE side to proper mode. */
1233                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1234                 if (setup_linear)
1235                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1236                 else
1237                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1238                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1239                                                           slice, value);
1240                 if (status)
1241                         goto i2c_err;
1242         }
1243
1244         return 0;
1245
1246 i2c_err:
1247         hw_dbg(hw, "combined i2c access failed with %d\n", status);
1248         return status;
1249 }
1250
1251 /**
1252  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1253  * @hw: pointer to hardware structure
1254  * @speed: new link speed
1255  * @autoneg_wait_to_complete: true when waiting for completion is needed
1256  *
1257  * Setup internal/external PHY link speed based on link speed, then set
1258  * external PHY auto advertised link speed.
1259  *
1260  * Returns error status for any failure
1261  **/
1262 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1263                                          ixgbe_link_speed speed,
1264                                          bool autoneg_wait)
1265 {
1266         s32 status;
1267         ixgbe_link_speed force_speed;
1268
1269         /* Setup internal/external PHY link speed to iXFI (10G), unless
1270          * only 1G is auto advertised then setup KX link.
1271          */
1272         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1273                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1274         else
1275                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1276
1277         /* If internal link mode is XFI, then setup XFI internal link. */
1278         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1279                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1280
1281                 if (status)
1282                         return status;
1283         }
1284
1285         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1286 }
1287
1288 /** ixgbe_check_link_t_X550em - Determine link and speed status
1289   * @hw: pointer to hardware structure
1290   * @speed: pointer to link speed
1291   * @link_up: true when link is up
1292   * @link_up_wait_to_complete: bool used to wait for link up or not
1293   *
1294   * Check that both the MAC and X557 external PHY have link.
1295   **/
1296 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1297                                      ixgbe_link_speed *speed,
1298                                      bool *link_up,
1299                                      bool link_up_wait_to_complete)
1300 {
1301         u32 status;
1302         u16 autoneg_status;
1303
1304         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1305                 return IXGBE_ERR_CONFIG;
1306
1307         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1308                                               link_up_wait_to_complete);
1309
1310         /* If check link fails or MAC link is not up, then return */
1311         if (status || !(*link_up))
1312                 return status;
1313
1314          /* MAC link is up, so check external PHY link.
1315           * Read this twice back to back to indicate current status.
1316           */
1317         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1318                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1319                                       &autoneg_status);
1320         if (status)
1321                 return status;
1322
1323         /* If external PHY link is not up, then indicate link not up */
1324         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1325                 *link_up = false;
1326
1327         return 0;
1328 }
1329
1330 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1331  *  @hw: pointer to hardware structure
1332  **/
1333 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1334 {
1335         struct ixgbe_mac_info *mac = &hw->mac;
1336
1337         switch (mac->ops.get_media_type(hw)) {
1338         case ixgbe_media_type_fiber:
1339                 /* CS4227 does not support autoneg, so disable the laser control
1340                  * functions for SFP+ fiber
1341                  */
1342                 mac->ops.disable_tx_laser = NULL;
1343                 mac->ops.enable_tx_laser = NULL;
1344                 mac->ops.flap_tx_laser = NULL;
1345                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1346                 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1347                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1348                 mac->ops.set_rate_select_speed =
1349                                         ixgbe_set_soft_rate_select_speed;
1350                 break;
1351         case ixgbe_media_type_copper:
1352                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1353                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1354                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1355                 break;
1356         default:
1357                 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1358                 break;
1359         }
1360 }
1361
1362 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1363  * @hw: pointer to hardware structure
1364  */
1365 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1366 {
1367         s32 status;
1368         bool linear;
1369
1370         /* Check if SFP module is supported */
1371         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1372         if (status)
1373                 return status;
1374
1375         ixgbe_init_mac_link_ops_X550em(hw);
1376         hw->phy.ops.reset = NULL;
1377
1378         return 0;
1379 }
1380
1381 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1382  * @hw: pointer to hardware structure
1383  * @speed: pointer to link speed
1384  * @autoneg: true when autoneg or autotry is enabled
1385  **/
1386 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1387                                               ixgbe_link_speed *speed,
1388                                               bool *autoneg)
1389 {
1390         /* SFP */
1391         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1392                 /* CS4227 SFP must not enable auto-negotiation */
1393                 *autoneg = false;
1394
1395                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1396                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1397                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1398                         return 0;
1399                 }
1400
1401                 /* Link capabilities are based on SFP */
1402                 if (hw->phy.multispeed_fiber)
1403                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1404                                  IXGBE_LINK_SPEED_1GB_FULL;
1405                 else
1406                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1407         } else {
1408                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1409                          IXGBE_LINK_SPEED_1GB_FULL;
1410                 *autoneg = true;
1411         }
1412         return 0;
1413 }
1414
1415 /**
1416  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1417  * @hw: pointer to hardware structure
1418  * @lsc: pointer to boolean flag which indicates whether external Base T
1419  *       PHY interrupt is lsc
1420  *
1421  * Determime if external Base T PHY interrupt cause is high temperature
1422  * failure alarm or link status change.
1423  *
1424  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1425  * failure alarm, else return PHY access status.
1426  **/
1427 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1428 {
1429         u32 status;
1430         u16 reg;
1431
1432         *lsc = false;
1433
1434         /* Vendor alarm triggered */
1435         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1436                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1437                                       &reg);
1438
1439         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1440                 return status;
1441
1442         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1443         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1444                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1445                                       &reg);
1446
1447         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1448                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1449                 return status;
1450
1451         /* Global alarm triggered */
1452         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1453                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1454                                       &reg);
1455
1456         if (status)
1457                 return status;
1458
1459         /* If high temperature failure, then return over temp error and exit */
1460         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1461                 /* power down the PHY in case the PHY FW didn't already */
1462                 ixgbe_set_copper_phy_power(hw, false);
1463                 return IXGBE_ERR_OVERTEMP;
1464         }
1465         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1466                 /*  device fault alarm triggered */
1467                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1468                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1469                                           &reg);
1470                 if (status)
1471                         return status;
1472
1473                 /* if device fault was due to high temp alarm handle and exit */
1474                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1475                         /* power down the PHY in case the PHY FW didn't */
1476                         ixgbe_set_copper_phy_power(hw, false);
1477                         return IXGBE_ERR_OVERTEMP;
1478                 }
1479         }
1480
1481         /* Vendor alarm 2 triggered */
1482         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1483                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1484
1485         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1486                 return status;
1487
1488         /* link connect/disconnect event occurred */
1489         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1490                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1491
1492         if (status)
1493                 return status;
1494
1495         /* Indicate LSC */
1496         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1497                 *lsc = true;
1498
1499         return 0;
1500 }
1501
1502 /**
1503  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1504  * @hw: pointer to hardware structure
1505  *
1506  * Enable link status change and temperature failure alarm for the external
1507  * Base T PHY
1508  *
1509  * Returns PHY access status
1510  **/
1511 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1512 {
1513         u32 status;
1514         u16 reg;
1515         bool lsc;
1516
1517         /* Clear interrupt flags */
1518         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1519
1520         /* Enable link status change alarm */
1521         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1522                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1523         if (status)
1524                 return status;
1525
1526         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1527
1528         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1529                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1530         if (status)
1531                 return status;
1532
1533         /* Enable high temperature failure and global fault alarms */
1534         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1535                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1536                                       &reg);
1537         if (status)
1538                 return status;
1539
1540         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1541                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1542
1543         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1544                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1545                                        reg);
1546         if (status)
1547                 return status;
1548
1549         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1550         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1551                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1552                                       &reg);
1553         if (status)
1554                 return status;
1555
1556         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1557                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1558
1559         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1560                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1561                                        reg);
1562         if (status)
1563                 return status;
1564
1565         /* Enable chip-wide vendor alarm */
1566         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1567                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1568                                       &reg);
1569         if (status)
1570                 return status;
1571
1572         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1573
1574         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1575                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1576                                        reg);
1577
1578         return status;
1579 }
1580
1581 /**
1582  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1583  * @hw: pointer to hardware structure
1584  *
1585  * Handle external Base T PHY interrupt. If high temperature
1586  * failure alarm then return error, else if link status change
1587  * then setup internal/external PHY link
1588  *
1589  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1590  * failure alarm, else return PHY access status.
1591  **/
1592 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1593 {
1594         struct ixgbe_phy_info *phy = &hw->phy;
1595         bool lsc;
1596         u32 status;
1597
1598         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1599         if (status)
1600                 return status;
1601
1602         if (lsc && phy->ops.setup_internal_link)
1603                 return phy->ops.setup_internal_link(hw);
1604
1605         return 0;
1606 }
1607
1608 /**
1609  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1610  * @hw: pointer to hardware structure
1611  * @speed: link speed
1612  *
1613  * Configures the integrated KR PHY.
1614  **/
1615 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1616                                        ixgbe_link_speed speed)
1617 {
1618         s32 status;
1619         u32 reg_val;
1620
1621         status = ixgbe_read_iosf_sb_reg_x550(hw,
1622                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1623                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1624         if (status)
1625                 return status;
1626
1627         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1628         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1629                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1630         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1631                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1632
1633         /* Advertise 10G support. */
1634         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1635                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1636
1637         /* Advertise 1G support. */
1638         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1639                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1640
1641         /* Restart auto-negotiation. */
1642         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1643         status = ixgbe_write_iosf_sb_reg_x550(hw,
1644                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1645                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1646
1647         return status;
1648 }
1649
1650 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1651  *  @hw: pointer to hardware structure
1652  *
1653  *   Configures the integrated KX4 PHY.
1654  **/
1655 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1656 {
1657         s32 status;
1658         u32 reg_val;
1659
1660         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1661                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1662                                              hw->bus.lan_id, &reg_val);
1663         if (status)
1664                 return status;
1665
1666         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1667                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1668
1669         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1670
1671         /* Advertise 10G support. */
1672         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1673                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1674
1675         /* Advertise 1G support. */
1676         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1677                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1678
1679         /* Restart auto-negotiation. */
1680         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1681         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1682                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1683                                               hw->bus.lan_id, reg_val);
1684
1685         return status;
1686 }
1687
1688 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1689  *   @hw: pointer to hardware structure
1690  *
1691  *   Configures the integrated KR PHY.
1692  **/
1693 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1694 {
1695         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1696 }
1697
1698 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1699  *  @hw: address of hardware structure
1700  *  @link_up: address of boolean to indicate link status
1701  *
1702  *  Returns error code if unable to get link status.
1703  **/
1704 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1705 {
1706         u32 ret;
1707         u16 autoneg_status;
1708
1709         *link_up = false;
1710
1711         /* read this twice back to back to indicate current status */
1712         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1713                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1714                                    &autoneg_status);
1715         if (ret)
1716                 return ret;
1717
1718         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1719                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1720                                    &autoneg_status);
1721         if (ret)
1722                 return ret;
1723
1724         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1725
1726         return 0;
1727 }
1728
1729 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1730  *  @hw: point to hardware structure
1731  *
1732  *  Configures the link between the integrated KR PHY and the external X557 PHY
1733  *  The driver will call this function when it gets a link status change
1734  *  interrupt from the X557 PHY. This function configures the link speed
1735  *  between the PHYs to match the link speed of the BASE-T link.
1736  *
1737  * A return of a non-zero value indicates an error, and the base driver should
1738  * not report link up.
1739  **/
1740 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1741 {
1742         ixgbe_link_speed force_speed;
1743         bool link_up;
1744         u32 status;
1745         u16 speed;
1746
1747         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1748                 return IXGBE_ERR_CONFIG;
1749
1750         if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1751                 speed = IXGBE_LINK_SPEED_10GB_FULL |
1752                         IXGBE_LINK_SPEED_1GB_FULL;
1753                 return ixgbe_setup_kr_speed_x550em(hw, speed);
1754         }
1755
1756         /* If link is not up, then there is no setup necessary so return  */
1757         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1758         if (status)
1759                 return status;
1760
1761         if (!link_up)
1762                 return 0;
1763
1764         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1765                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1766                                       &speed);
1767         if (status)
1768                 return status;
1769
1770         /* If link is not still up, then no setup is necessary so return */
1771         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1772         if (status)
1773                 return status;
1774
1775         if (!link_up)
1776                 return 0;
1777
1778         /* clear everything but the speed and duplex bits */
1779         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1780
1781         switch (speed) {
1782         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1783                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1784                 break;
1785         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1786                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1787                 break;
1788         default:
1789                 /* Internal PHY does not support anything else */
1790                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1791         }
1792
1793         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1794 }
1795
1796 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1797  *  @hw: pointer to hardware structure
1798  **/
1799 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
1800 {
1801         s32 status;
1802
1803         status = ixgbe_reset_phy_generic(hw);
1804
1805         if (status)
1806                 return status;
1807
1808         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1809         return ixgbe_enable_lasi_ext_t_x550em(hw);
1810 }
1811
1812 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
1813  *  @hw: pointer to hardware structure
1814  *  @lcd_speed: pointer to lowest common link speed
1815  *
1816  *  Determine lowest common link speed with link partner.
1817  **/
1818 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
1819                                   ixgbe_link_speed *lcd_speed)
1820 {
1821         u16 an_lp_status;
1822         s32 status;
1823         u16 word = hw->eeprom.ctrl_word_3;
1824
1825         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
1826
1827         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
1828                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1829                                       &an_lp_status);
1830         if (status)
1831                 return status;
1832
1833         /* If link partner advertised 1G, return 1G */
1834         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
1835                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
1836                 return status;
1837         }
1838
1839         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
1840         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
1841             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
1842                 return status;
1843
1844         /* Link partner not capable of lower speeds, return 10G */
1845         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
1846         return status;
1847 }
1848
1849 /**
1850  * ixgbe_setup_fc_x550em - Set up flow control
1851  * @hw: pointer to hardware structure
1852  */
1853 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
1854 {
1855         bool pause, asm_dir;
1856         u32 reg_val;
1857         s32 rc;
1858
1859         /* Validate the requested mode */
1860         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1861                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
1862                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1863         }
1864
1865         /* 10gig parts do not have a word in the EEPROM to determine the
1866          * default flow control setting, so we explicitly set it to full.
1867          */
1868         if (hw->fc.requested_mode == ixgbe_fc_default)
1869                 hw->fc.requested_mode = ixgbe_fc_full;
1870
1871         /* Determine PAUSE and ASM_DIR bits. */
1872         switch (hw->fc.requested_mode) {
1873         case ixgbe_fc_none:
1874                 pause = false;
1875                 asm_dir = false;
1876                 break;
1877         case ixgbe_fc_tx_pause:
1878                 pause = false;
1879                 asm_dir = true;
1880                 break;
1881         case ixgbe_fc_rx_pause:
1882                 /* Rx Flow control is enabled and Tx Flow control is
1883                  * disabled by software override. Since there really
1884                  * isn't a way to advertise that we are capable of RX
1885                  * Pause ONLY, we will advertise that we support both
1886                  * symmetric and asymmetric Rx PAUSE, as such we fall
1887                  * through to the fc_full statement.  Later, we will
1888                  * disable the adapter's ability to send PAUSE frames.
1889                  */
1890                 /* Fallthrough */
1891         case ixgbe_fc_full:
1892                 pause = true;
1893                 asm_dir = true;
1894                 break;
1895         default:
1896                 hw_err(hw, "Flow control param set incorrectly\n");
1897                 return IXGBE_ERR_CONFIG;
1898         }
1899
1900         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
1901                 return 0;
1902
1903         rc = ixgbe_read_iosf_sb_reg_x550(hw,
1904                                          IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
1905                                          IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1906         if (rc)
1907                 return rc;
1908
1909         reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
1910                      IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
1911         if (pause)
1912                 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
1913         if (asm_dir)
1914                 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
1915         rc = ixgbe_write_iosf_sb_reg_x550(hw,
1916                                           IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
1917                                           IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1918
1919         /* This device does not fully support AN. */
1920         hw->fc.disable_fc_autoneg = true;
1921
1922         return rc;
1923 }
1924
1925 /** ixgbe_enter_lplu_x550em - Transition to low power states
1926  *  @hw: pointer to hardware structure
1927  *
1928  *  Configures Low Power Link Up on transition to low power states
1929  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
1930  *  the X557 PHY immediately prior to entering LPLU.
1931  **/
1932 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
1933 {
1934         u16 an_10g_cntl_reg, autoneg_reg, speed;
1935         s32 status;
1936         ixgbe_link_speed lcd_speed;
1937         u32 save_autoneg;
1938         bool link_up;
1939
1940         /* If blocked by MNG FW, then don't restart AN */
1941         if (ixgbe_check_reset_blocked(hw))
1942                 return 0;
1943
1944         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1945         if (status)
1946                 return status;
1947
1948         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
1949                                      &hw->eeprom.ctrl_word_3);
1950         if (status)
1951                 return status;
1952
1953         /* If link is down, LPLU disabled in NVM, WoL disabled, or
1954          * manageability disabled, then force link down by entering
1955          * low power mode.
1956          */
1957         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
1958             !(hw->wol_enabled || ixgbe_mng_present(hw)))
1959                 return ixgbe_set_copper_phy_power(hw, false);
1960
1961         /* Determine LCD */
1962         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
1963         if (status)
1964                 return status;
1965
1966         /* If no valid LCD link speed, then force link down and exit. */
1967         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
1968                 return ixgbe_set_copper_phy_power(hw, false);
1969
1970         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1971                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1972                                       &speed);
1973         if (status)
1974                 return status;
1975
1976         /* If no link now, speed is invalid so take link down */
1977         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1978         if (status)
1979                 return ixgbe_set_copper_phy_power(hw, false);
1980
1981         /* clear everything but the speed bits */
1982         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
1983
1984         /* If current speed is already LCD, then exit. */
1985         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
1986              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
1987             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
1988              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
1989                 return status;
1990
1991         /* Clear AN completed indication */
1992         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
1993                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1994                                       &autoneg_reg);
1995         if (status)
1996                 return status;
1997
1998         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1999                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2000                                       &an_10g_cntl_reg);
2001         if (status)
2002                 return status;
2003
2004         status = hw->phy.ops.read_reg(hw,
2005                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2006                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2007                                       &autoneg_reg);
2008         if (status)
2009                 return status;
2010
2011         save_autoneg = hw->phy.autoneg_advertised;
2012
2013         /* Setup link at least common link speed */
2014         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2015
2016         /* restore autoneg from before setting lplu speed */
2017         hw->phy.autoneg_advertised = save_autoneg;
2018
2019         return status;
2020 }
2021
2022 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2023  *  @hw: pointer to hardware structure
2024  *
2025  *  Initialize any function pointers that were not able to be
2026  *  set during init_shared_code because the PHY/SFP type was
2027  *  not known.  Perform the SFP init if necessary.
2028  **/
2029 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2030 {
2031         struct ixgbe_phy_info *phy = &hw->phy;
2032         s32 ret_val;
2033
2034         hw->mac.ops.set_lan_id(hw);
2035
2036         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2037                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2038                 ixgbe_setup_mux_ctl(hw);
2039
2040                 /* Save NW management interface connected on board. This is used
2041                  * to determine internal PHY mode.
2042                  */
2043                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2044         }
2045
2046         /* Identify the PHY or SFP module */
2047         ret_val = phy->ops.identify(hw);
2048
2049         /* Setup function pointers based on detected hardware */
2050         ixgbe_init_mac_link_ops_X550em(hw);
2051         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2052                 phy->ops.reset = NULL;
2053
2054         /* Set functions pointers based on phy type */
2055         switch (hw->phy.type) {
2056         case ixgbe_phy_x550em_kx4:
2057                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2058                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2059                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2060                 break;
2061         case ixgbe_phy_x550em_kr:
2062                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2063                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2064                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2065                 break;
2066         case ixgbe_phy_x550em_ext_t:
2067                 /* Save NW management interface connected on board. This is used
2068                  * to determine internal PHY mode
2069                  */
2070                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2071
2072                 /* If internal link mode is XFI, then setup iXFI internal link,
2073                  * else setup KR now.
2074                  */
2075                 phy->ops.setup_internal_link =
2076                                               ixgbe_setup_internal_phy_t_x550em;
2077
2078                 /* setup SW LPLU only for first revision */
2079                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2080                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2081                       IXGBE_FUSES0_REV_MASK))
2082                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2083
2084                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2085                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2086                 break;
2087         default:
2088                 break;
2089         }
2090
2091         return ret_val;
2092 }
2093
2094 /** ixgbe_get_media_type_X550em - Get media type
2095  *  @hw: pointer to hardware structure
2096  *
2097  *  Returns the media type (fiber, copper, backplane)
2098  *
2099  */
2100 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2101 {
2102         enum ixgbe_media_type media_type;
2103
2104         /* Detect if there is a copper PHY attached. */
2105         switch (hw->device_id) {
2106         case IXGBE_DEV_ID_X550EM_X_KR:
2107         case IXGBE_DEV_ID_X550EM_X_KX4:
2108                 media_type = ixgbe_media_type_backplane;
2109                 break;
2110         case IXGBE_DEV_ID_X550EM_X_SFP:
2111                 media_type = ixgbe_media_type_fiber;
2112                 break;
2113         case IXGBE_DEV_ID_X550EM_X_1G_T:
2114         case IXGBE_DEV_ID_X550EM_X_10G_T:
2115                  media_type = ixgbe_media_type_copper;
2116                 break;
2117         default:
2118                 media_type = ixgbe_media_type_unknown;
2119                 break;
2120         }
2121         return media_type;
2122 }
2123
2124 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2125  ** @hw: pointer to hardware structure
2126  **/
2127 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2128 {
2129         s32 status;
2130         u16 reg;
2131
2132         status = hw->phy.ops.read_reg(hw,
2133                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2134                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2135                                       &reg);
2136         if (status)
2137                 return status;
2138
2139         /* If PHY FW reset completed bit is set then this is the first
2140          * SW instance after a power on so the PHY FW must be un-stalled.
2141          */
2142         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2143                 status = hw->phy.ops.read_reg(hw,
2144                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2145                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2146                                         &reg);
2147                 if (status)
2148                         return status;
2149
2150                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2151
2152                 status = hw->phy.ops.write_reg(hw,
2153                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2154                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155                                         reg);
2156                 if (status)
2157                         return status;
2158         }
2159
2160         return status;
2161 }
2162
2163 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2164  **  @hw: pointer to hardware structure
2165  **
2166  **  Resets the hardware by resetting the transmit and receive units, masks
2167  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2168  **  reset.
2169  **/
2170 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2171 {
2172         ixgbe_link_speed link_speed;
2173         s32 status;
2174         u32 ctrl = 0;
2175         u32 i;
2176         u32 hlreg0;
2177         bool link_up = false;
2178
2179         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2180         status = hw->mac.ops.stop_adapter(hw);
2181         if (status)
2182                 return status;
2183
2184         /* flush pending Tx transactions */
2185         ixgbe_clear_tx_pending(hw);
2186
2187         /* PHY ops must be identified and initialized prior to reset */
2188
2189         /* Identify PHY and related function pointers */
2190         status = hw->phy.ops.init(hw);
2191
2192         /* start the external PHY */
2193         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2194                 status = ixgbe_init_ext_t_x550em(hw);
2195                 if (status)
2196                         return status;
2197         }
2198
2199         /* Setup SFP module if there is one present. */
2200         if (hw->phy.sfp_setup_needed) {
2201                 status = hw->mac.ops.setup_sfp(hw);
2202                 hw->phy.sfp_setup_needed = false;
2203         }
2204
2205         /* Reset PHY */
2206         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2207                 hw->phy.ops.reset(hw);
2208
2209 mac_reset_top:
2210         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2211          * If link reset is used when link is up, it might reset the PHY when
2212          * mng is using it.  If link is down or the flag to force full link
2213          * reset is set, then perform link reset.
2214          */
2215         ctrl = IXGBE_CTRL_LNK_RST;
2216
2217         if (!hw->force_full_reset) {
2218                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2219                 if (link_up)
2220                         ctrl = IXGBE_CTRL_RST;
2221         }
2222
2223         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2224         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2225         IXGBE_WRITE_FLUSH(hw);
2226         usleep_range(1000, 1200);
2227
2228         /* Poll for reset bit to self-clear meaning reset is complete */
2229         for (i = 0; i < 10; i++) {
2230                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2231                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2232                         break;
2233                 udelay(1);
2234         }
2235
2236         if (ctrl & IXGBE_CTRL_RST_MASK) {
2237                 status = IXGBE_ERR_RESET_FAILED;
2238                 hw_dbg(hw, "Reset polling failed to complete.\n");
2239         }
2240
2241         msleep(50);
2242
2243         /* Double resets are required for recovery from certain error
2244          * clear the multicast table.  Also reset num_rar_entries to 128,
2245          * since we modify this value when programming the SAN MAC address.
2246          */
2247         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2248                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2249                 goto mac_reset_top;
2250         }
2251
2252         /* Store the permanent mac address */
2253         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2254
2255         /* Store MAC address from RAR0, clear receive address registers, and
2256          * clear the multicast table.  Also reset num_rar_entries to 128,
2257          * since we modify this value when programming the SAN MAC address.
2258          */
2259         hw->mac.num_rar_entries = 128;
2260         hw->mac.ops.init_rx_addrs(hw);
2261
2262         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
2263                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2264                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2265                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2266         }
2267
2268         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2269                 ixgbe_setup_mux_ctl(hw);
2270
2271         return status;
2272 }
2273
2274 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2275  *      anti-spoofing
2276  *  @hw:  pointer to hardware structure
2277  *  @enable: enable or disable switch for Ethertype anti-spoofing
2278  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2279  **/
2280 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2281                                                    bool enable, int vf)
2282 {
2283         int vf_target_reg = vf >> 3;
2284         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2285         u32 pfvfspoof;
2286
2287         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2288         if (enable)
2289                 pfvfspoof |= (1 << vf_target_shift);
2290         else
2291                 pfvfspoof &= ~(1 << vf_target_shift);
2292
2293         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2294 }
2295
2296 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2297  *  @hw: pointer to hardware structure
2298  *  @enable: enable or disable source address pruning
2299  *  @pool: Rx pool to set source address pruning for
2300  **/
2301 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2302                                                   bool enable,
2303                                                   unsigned int pool)
2304 {
2305         u64 pfflp;
2306
2307         /* max rx pool is 63 */
2308         if (pool > 63)
2309                 return;
2310
2311         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2312         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2313
2314         if (enable)
2315                 pfflp |= (1ULL << pool);
2316         else
2317                 pfflp &= ~(1ULL << pool);
2318
2319         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2320         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2321 }
2322
2323 /**
2324  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2325  * @hw: pointer to hardware structure
2326  * @state: set mux if 1, clear if 0
2327  */
2328 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2329 {
2330         u32 esdp;
2331
2332         if (!hw->bus.lan_id)
2333                 return;
2334         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2335         if (state)
2336                 esdp |= IXGBE_ESDP_SDP1;
2337         else
2338                 esdp &= ~IXGBE_ESDP_SDP1;
2339         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2340         IXGBE_WRITE_FLUSH(hw);
2341 }
2342
2343 /**
2344  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2345  * @hw: pointer to hardware structure
2346  * @mask: Mask to specify which semaphore to acquire
2347  *
2348  * Acquires the SWFW semaphore and sets the I2C MUX
2349  */
2350 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2351 {
2352         s32 status;
2353
2354         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2355         if (status)
2356                 return status;
2357
2358         if (mask & IXGBE_GSSR_I2C_MASK)
2359                 ixgbe_set_mux(hw, 1);
2360
2361         return 0;
2362 }
2363
2364 /**
2365  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2366  * @hw: pointer to hardware structure
2367  * @mask: Mask to specify which semaphore to release
2368  *
2369  * Releases the SWFW semaphore and sets the I2C MUX
2370  */
2371 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2372 {
2373         if (mask & IXGBE_GSSR_I2C_MASK)
2374                 ixgbe_set_mux(hw, 0);
2375
2376         ixgbe_release_swfw_sync_X540(hw, mask);
2377 }
2378
2379 #define X550_COMMON_MAC \
2380         .init_hw                        = &ixgbe_init_hw_generic, \
2381         .start_hw                       = &ixgbe_start_hw_X540, \
2382         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2383         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2384         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2385         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2386         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2387         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2388         .read_analog_reg8               = NULL, \
2389         .write_analog_reg8              = NULL, \
2390         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2391         .check_link                     = &ixgbe_check_mac_link_generic, \
2392         .led_on                         = &ixgbe_led_on_generic, \
2393         .led_off                        = &ixgbe_led_off_generic, \
2394         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2395         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2396         .set_rar                        = &ixgbe_set_rar_generic, \
2397         .clear_rar                      = &ixgbe_clear_rar_generic, \
2398         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2399         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2400         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2401         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2402         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2403         .enable_mc                      = &ixgbe_enable_mc_generic, \
2404         .disable_mc                     = &ixgbe_disable_mc_generic, \
2405         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2406         .set_vfta                       = &ixgbe_set_vfta_generic, \
2407         .fc_enable                      = &ixgbe_fc_enable_generic, \
2408         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2409         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2410         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2411         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2412         .set_source_address_pruning     = \
2413                                 &ixgbe_set_source_address_pruning_X550, \
2414         .set_ethertype_anti_spoofing    = \
2415                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2416         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2417         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2418         .get_thermal_sensor_data        = NULL, \
2419         .init_thermal_sensor_thresh     = NULL, \
2420         .enable_rx                      = &ixgbe_enable_rx_generic, \
2421         .disable_rx                     = &ixgbe_disable_rx_x550, \
2422
2423 static const struct ixgbe_mac_operations mac_ops_X550 = {
2424         X550_COMMON_MAC
2425         .reset_hw               = &ixgbe_reset_hw_X540,
2426         .get_media_type         = &ixgbe_get_media_type_X540,
2427         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2428         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2429         .setup_link             = &ixgbe_setup_mac_link_X540,
2430         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2431         .get_bus_info           = &ixgbe_get_bus_info_generic,
2432         .setup_sfp              = NULL,
2433         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2434         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2435         .prot_autoc_read        = prot_autoc_read_generic,
2436         .prot_autoc_write       = prot_autoc_write_generic,
2437         .setup_fc               = ixgbe_setup_fc_generic,
2438 };
2439
2440 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2441         X550_COMMON_MAC
2442         .reset_hw               = &ixgbe_reset_hw_X550em,
2443         .get_media_type         = &ixgbe_get_media_type_X550em,
2444         .get_san_mac_addr       = NULL,
2445         .get_wwn_prefix         = NULL,
2446         .setup_link             = NULL, /* defined later */
2447         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2448         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2449         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2450         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2451         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2452         .setup_fc               = NULL, /* defined later */
2453 };
2454
2455 #define X550_COMMON_EEP \
2456         .read                   = &ixgbe_read_ee_hostif_X550, \
2457         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2458         .write                  = &ixgbe_write_ee_hostif_X550, \
2459         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2460         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2461         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2462         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2463
2464 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2465         X550_COMMON_EEP
2466         .init_params            = &ixgbe_init_eeprom_params_X550,
2467 };
2468
2469 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2470         X550_COMMON_EEP
2471         .init_params            = &ixgbe_init_eeprom_params_X540,
2472 };
2473
2474 #define X550_COMMON_PHY \
2475         .identify_sfp           = &ixgbe_identify_module_generic, \
2476         .reset                  = NULL, \
2477         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2478         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2479         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2480         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2481         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2482         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2483         .read_reg               = &ixgbe_read_phy_reg_generic, \
2484         .write_reg              = &ixgbe_write_phy_reg_generic, \
2485         .setup_link             = &ixgbe_setup_phy_link_generic, \
2486         .set_phy_power          = NULL, \
2487         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2488         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2489
2490 static const struct ixgbe_phy_operations phy_ops_X550 = {
2491         X550_COMMON_PHY
2492         .init                   = NULL,
2493         .identify               = &ixgbe_identify_phy_generic,
2494 };
2495
2496 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
2497         X550_COMMON_PHY
2498         .init                   = &ixgbe_init_phy_ops_X550em,
2499         .identify               = &ixgbe_identify_phy_x550em,
2500         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2501         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2502         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2503         .write_i2c_combined_unlocked =
2504                                      &ixgbe_write_i2c_combined_generic_unlocked,
2505 };
2506
2507 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2508         IXGBE_MVALS_INIT(X550)
2509 };
2510
2511 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2512         IXGBE_MVALS_INIT(X550EM_x)
2513 };
2514
2515 const struct ixgbe_info ixgbe_X550_info = {
2516         .mac                    = ixgbe_mac_X550,
2517         .get_invariants         = &ixgbe_get_invariants_X540,
2518         .mac_ops                = &mac_ops_X550,
2519         .eeprom_ops             = &eeprom_ops_X550,
2520         .phy_ops                = &phy_ops_X550,
2521         .mbx_ops                = &mbx_ops_generic,
2522         .mvals                  = ixgbe_mvals_X550,
2523 };
2524
2525 const struct ixgbe_info ixgbe_X550EM_x_info = {
2526         .mac                    = ixgbe_mac_X550EM_x,
2527         .get_invariants         = &ixgbe_get_invariants_X550_x,
2528         .mac_ops                = &mac_ops_X550EM_x,
2529         .eeprom_ops             = &eeprom_ops_X550EM_x,
2530         .phy_ops                = &phy_ops_X550EM_x,
2531         .mbx_ops                = &mbx_ops_generic,
2532         .mvals                  = ixgbe_mvals_X550EM_x,
2533 };