drivers/net/ethernet/lantiq_etop.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify it
   3  *   under the terms of the GNU General Public License version 2 as published
   4  *   by the Free Software Foundation.
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, see <http://www.gnu.org/licenses/>.
  13  *
  14  *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/errno.h>
  20 #include <linux/types.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/in.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/phy.h>
  27 #include <linux/ip.h>
  28 #include <linux/tcp.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/mm.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/init.h>
  34 #include <linux/delay.h>
  35 #include <linux/io.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/module.h>
  38
  39 #include <asm/checksum.h>
  40
  41 #include <lantiq_soc.h>
  42 #include <xway_dma.h>
  43 #include <lantiq_platform.h>
  44
  45 #define LTQ_ETOP_MDIO           0x11804
  46 #define MDIO_REQUEST            0x80000000
  47 #define MDIO_READ               0x40000000
  48 #define MDIO_ADDR_MASK          0x1f
  49 #define MDIO_ADDR_OFFSET        0x15
  50 #define MDIO_REG_MASK           0x1f
  51 #define MDIO_REG_OFFSET         0x10
  52 #define MDIO_VAL_MASK           0xffff
  53
  54 #define PPE32_CGEN              0x800
  55 #define LQ_PPE32_ENET_MAC_CFG   0x1840
  56
  57 #define LTQ_ETOP_ENETS0         0x11850
  58 #define LTQ_ETOP_MAC_DA0        0x1186C
  59 #define LTQ_ETOP_MAC_DA1        0x11870
  60 #define LTQ_ETOP_CFG            0x16020
  61 #define LTQ_ETOP_IGPLEN         0x16080
  62
  63 #define MAX_DMA_CHAN            0x8
  64 #define MAX_DMA_CRC_LEN         0x4
  65 #define MAX_DMA_DATA_LEN        0x600
  66
  67 #define ETOP_FTCU               BIT(28)
  68 #define ETOP_MII_MASK           0xf
  69 #define ETOP_MII_NORMAL         0xd
  70 #define ETOP_MII_REVERSE        0xe
  71 #define ETOP_PLEN_UNDER         0x40
  72 #define ETOP_CGEN               0x800
  73
  74 /* use 2 static channels for TX/RX */
  75 #define LTQ_ETOP_TX_CHANNEL     1
  76 #define LTQ_ETOP_RX_CHANNEL     6
  77 #define IS_TX(x)                (x == LTQ_ETOP_TX_CHANNEL)
  78 #define IS_RX(x)                (x == LTQ_ETOP_RX_CHANNEL)
  79
  80 #define ltq_etop_r32(x)         ltq_r32(ltq_etop_membase + (x))
  81 #define ltq_etop_w32(x, y)      ltq_w32(x, ltq_etop_membase + (y))
  82 #define ltq_etop_w32_mask(x, y, z)      \
  83                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
  84
  85 #define DRV_VERSION     "1.0"
  86
  87 static void __iomem *ltq_etop_membase;
  88
  89 struct ltq_etop_chan {
  90         int idx;
  91         int tx_free;
  92         struct net_device *netdev;
  93         struct napi_struct napi;
  94         struct ltq_dma_channel dma;
  95         struct sk_buff *skb[LTQ_DESC_NUM];
  96 };
  97
  98 struct ltq_etop_priv {
  99         struct net_device *netdev;
 100         struct platform_device *pdev;
 101         struct ltq_eth_data *pldata;
 102         struct resource *res;
 103
 104         struct mii_bus *mii_bus;
 105
 106         struct ltq_etop_chan ch[MAX_DMA_CHAN];
 107         int tx_free[MAX_DMA_CHAN >> 1];
 108
 109         spinlock_t lock;
 110 };
 111
 112 static int
 113 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 114 {
 115         ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 116         if (!ch->skb[ch->dma.desc])
 117                 return -ENOMEM;
 118         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 119                 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
 120                 DMA_FROM_DEVICE);
 121         ch->dma.desc_base[ch->dma.desc].addr =
 122                 CPHYSADDR(ch->skb[ch->dma.desc]->data);
 123         ch->dma.desc_base[ch->dma.desc].ctl =
 124                 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
 125                 MAX_DMA_DATA_LEN;
 126         skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
 127         return 0;
 128 }
 129
 130 static void
 131 ltq_etop_hw_receive(struct ltq_etop_chan *ch)
 132 {
 133         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 134         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 135         struct sk_buff *skb = ch->skb[ch->dma.desc];
 136         int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
 137         unsigned long flags;
 138
 139         spin_lock_irqsave(&priv->lock, flags);
 140         if (ltq_etop_alloc_skb(ch)) {
 141                 netdev_err(ch->netdev,
 142                         "failed to allocate new rx buffer, stopping DMA\n");
 143                 ltq_dma_close(&ch->dma);
 144         }
 145         ch->dma.desc++;
 146         ch->dma.desc %= LTQ_DESC_NUM;
 147         spin_unlock_irqrestore(&priv->lock, flags);
 148
 149         skb_put(skb, len);
 150         skb->protocol = eth_type_trans(skb, ch->netdev);
 151         netif_receive_skb(skb);
 152 }
 153
 154 static int
 155 ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 156 {
 157         struct ltq_etop_chan *ch = container_of(napi,
 158                                 struct ltq_etop_chan, napi);
 159         int rx = 0;
 160         int complete = 0;
 161
 162         while ((rx < budget) && !complete) {
 163                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 164
 165                 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 166                         ltq_etop_hw_receive(ch);
 167                         rx++;
 168                 } else {
 169                         complete = 1;
 170                 }
 171         }
 172         if (complete || !rx) {
 173                 napi_complete(&ch->napi);
 174                 ltq_dma_ack_irq(&ch->dma);
 175         }
 176         return rx;
 177 }
 178
 179 static int
 180 ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 181 {
 182         struct ltq_etop_chan *ch =
 183                 container_of(napi, struct ltq_etop_chan, napi);
 184         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 185         struct netdev_queue *txq =
 186                 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 187         unsigned long flags;
 188
 189         spin_lock_irqsave(&priv->lock, flags);
 190         while ((ch->dma.desc_base[ch->tx_free].ctl &
 191                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 192                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 193                 ch->skb[ch->tx_free] = NULL;
 194                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 195                         sizeof(struct ltq_dma_desc));
 196                 ch->tx_free++;
 197                 ch->tx_free %= LTQ_DESC_NUM;
 198         }
 199         spin_unlock_irqrestore(&priv->lock, flags);
 200
 201         if (netif_tx_queue_stopped(txq))
 202                 netif_tx_start_queue(txq);
 203         napi_complete(&ch->napi);
 204         ltq_dma_ack_irq(&ch->dma);
 205         return 1;
 206 }
 207
 208 static irqreturn_t
 209 ltq_etop_dma_irq(int irq, void *_priv)
 210 {
 211         struct ltq_etop_priv *priv = _priv;
 212         int ch = irq - LTQ_DMA_CH0_INT;
 213
 214         napi_schedule(&priv->ch[ch].napi);
 215         return IRQ_HANDLED;
 216 }
 217
 218 static void
 219 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 220 {
 221         struct ltq_etop_priv *priv = netdev_priv(dev);
 222
 223         ltq_dma_free(&ch->dma);
 224         if (ch->dma.irq)
 225                 free_irq(ch->dma.irq, priv);
 226         if (IS_RX(ch->idx)) {
 227                 int desc;
 228                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 229                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 230         }
 231 }
 232
 233 static void
 234 ltq_etop_hw_exit(struct net_device *dev)
 235 {
 236         struct ltq_etop_priv *priv = netdev_priv(dev);
 237         int i;
 238
 239         ltq_pmu_disable(PMU_PPE);
 240         for (i = 0; i < MAX_DMA_CHAN; i++)
 241                 if (IS_TX(i) || IS_RX(i))
 242                         ltq_etop_free_channel(dev, &priv->ch[i]);
 243 }
 244
 245 static int
 246 ltq_etop_hw_init(struct net_device *dev)
 247 {
 248         struct ltq_etop_priv *priv = netdev_priv(dev);
 249         int i;
 250
 251         ltq_pmu_enable(PMU_PPE);
 252
 253         switch (priv->pldata->mii_mode) {
 254         case PHY_INTERFACE_MODE_RMII:
 255                 ltq_etop_w32_mask(ETOP_MII_MASK,
 256                         ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 257                 break;
 258
 259         case PHY_INTERFACE_MODE_MII:
 260                 ltq_etop_w32_mask(ETOP_MII_MASK,
 261                         ETOP_MII_NORMAL, LTQ_ETOP_CFG);
 262                 break;
 263
 264         default:
 265                 netdev_err(dev, "unknown mii mode %d\n",
 266                         priv->pldata->mii_mode);
 267                 return -ENOTSUPP;
 268         }
 269
 270         /* enable crc generation */
 271         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 272
 273         ltq_dma_init_port(DMA_PORT_ETOP);
 274
 275         for (i = 0; i < MAX_DMA_CHAN; i++) {
 276                 int irq = LTQ_DMA_CH0_INT + i;
 277                 struct ltq_etop_chan *ch = &priv->ch[i];
 278
 279                 ch->idx = ch->dma.nr = i;
 280
 281                 if (IS_TX(i)) {
 282                         ltq_dma_alloc_tx(&ch->dma);
 283                         request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 284                 } else if (IS_RX(i)) {
 285                         ltq_dma_alloc_rx(&ch->dma);
 286                         for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 287                                         ch->dma.desc++)
 288                                 if (ltq_etop_alloc_skb(ch))
 289                                         return -ENOMEM;
 290                         ch->dma.desc = 0;
 291                         request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 292                 }
 293                 ch->dma.irq = irq;
 294         }
 295         return 0;
 296 }
 297
 298 static void
 299 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 300 {
 301         strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
 302         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
 303         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 304 }
 305
 306 static int
 307 ltq_etop_nway_reset(struct net_device *dev)
 308 {
 309         return phy_start_aneg(dev->phydev);
 310 }
 311
 312 static const struct ethtool_ops ltq_etop_ethtool_ops = {
 313         .get_drvinfo = ltq_etop_get_drvinfo,
 314         .nway_reset = ltq_etop_nway_reset,
 315         .get_link_ksettings = phy_ethtool_get_link_ksettings,
 316         .set_link_ksettings = phy_ethtool_set_link_ksettings,
 317 };
 318
 319 static int
 320 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 321 {
 322         u32 val = MDIO_REQUEST |
 323                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 324                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 325                 phy_data;
 326
 327         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 328                 ;
 329         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 330         return 0;
 331 }
 332
 333 static int
 334 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
 335 {
 336         u32 val = MDIO_REQUEST | MDIO_READ |
 337                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 338                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 339
 340         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 341                 ;
 342         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 343         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 344                 ;
 345         val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 346         return val;
 347 }
 348
 349 static void
 350 ltq_etop_mdio_link(struct net_device *dev)
 351 {
 352         /* nothing to do  */
 353 }
 354
 355 static int
 356 ltq_etop_mdio_probe(struct net_device *dev)
 357 {
 358         struct ltq_etop_priv *priv = netdev_priv(dev);
 359         struct phy_device *phydev;
 360
 361         phydev = phy_find_first(priv->mii_bus);
 362
 363         if (!phydev) {
 364                 netdev_err(dev, "no PHY found\n");
 365                 return -ENODEV;
 366         }
 367
 368         phydev = phy_connect(dev, phydev_name(phydev),
 369                              &ltq_etop_mdio_link, priv->pldata->mii_mode);
 370
 371         if (IS_ERR(phydev)) {
 372                 netdev_err(dev, "Could not attach to PHY\n");
 373                 return PTR_ERR(phydev);
 374         }
 375
 376         phydev->supported &= (SUPPORTED_10baseT_Half
 377                               | SUPPORTED_10baseT_Full
 378                               | SUPPORTED_100baseT_Half
 379                               | SUPPORTED_100baseT_Full
 380                               | SUPPORTED_Autoneg
 381                               | SUPPORTED_MII
 382                               | SUPPORTED_TP);
 383
 384         phydev->advertising = phydev->supported;
 385         phy_attached_info(phydev);
 386
 387         return 0;
 388 }
 389
 390 static int
 391 ltq_etop_mdio_init(struct net_device *dev)
 392 {
 393         struct ltq_etop_priv *priv = netdev_priv(dev);
 394         int err;
 395
 396         priv->mii_bus = mdiobus_alloc();
 397         if (!priv->mii_bus) {
 398                 netdev_err(dev, "failed to allocate mii bus\n");
 399                 err = -ENOMEM;
 400                 goto err_out;
 401         }
 402
 403         priv->mii_bus->priv = dev;
 404         priv->mii_bus->read = ltq_etop_mdio_rd;
 405         priv->mii_bus->write = ltq_etop_mdio_wr;
 406         priv->mii_bus->name = "ltq_mii";
 407         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 408                 priv->pdev->name, priv->pdev->id);
 409         if (mdiobus_register(priv->mii_bus)) {
 410                 err = -ENXIO;
 411                 goto err_out_free_mdiobus;
 412         }
 413
 414         if (ltq_etop_mdio_probe(dev)) {
 415                 err = -ENXIO;
 416                 goto err_out_unregister_bus;
 417         }
 418         return 0;
 419
 420 err_out_unregister_bus:
 421         mdiobus_unregister(priv->mii_bus);
 422 err_out_free_mdiobus:
 423         mdiobus_free(priv->mii_bus);
 424 err_out:
 425         return err;
 426 }
 427
 428 static void
 429 ltq_etop_mdio_cleanup(struct net_device *dev)
 430 {
 431         struct ltq_etop_priv *priv = netdev_priv(dev);
 432
 433         phy_disconnect(dev->phydev);
 434         mdiobus_unregister(priv->mii_bus);
 435         mdiobus_free(priv->mii_bus);
 436 }
 437
 438 static int
 439 ltq_etop_open(struct net_device *dev)
 440 {
 441         struct ltq_etop_priv *priv = netdev_priv(dev);
 442         int i;
 443
 444         for (i = 0; i < MAX_DMA_CHAN; i++) {
 445                 struct ltq_etop_chan *ch = &priv->ch[i];
 446
 447                 if (!IS_TX(i) && (!IS_RX(i)))
 448                         continue;
 449                 ltq_dma_open(&ch->dma);
 450                 napi_enable(&ch->napi);
 451         }
 452         phy_start(dev->phydev);
 453         netif_tx_start_all_queues(dev);
 454         return 0;
 455 }
 456
 457 static int
 458 ltq_etop_stop(struct net_device *dev)
 459 {
 460         struct ltq_etop_priv *priv = netdev_priv(dev);
 461         int i;
 462
 463         netif_tx_stop_all_queues(dev);
 464         phy_stop(dev->phydev);
 465         for (i = 0; i < MAX_DMA_CHAN; i++) {
 466                 struct ltq_etop_chan *ch = &priv->ch[i];
 467
 468                 if (!IS_RX(i) && !IS_TX(i))
 469                         continue;
 470                 napi_disable(&ch->napi);
 471                 ltq_dma_close(&ch->dma);
 472         }
 473         return 0;
 474 }
 475
 476 static int
 477 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 478 {
 479         int queue = skb_get_queue_mapping(skb);
 480         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 481         struct ltq_etop_priv *priv = netdev_priv(dev);
 482         struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 483         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 484         int len;
 485         unsigned long flags;
 486         u32 byte_offset;
 487
 488         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 489
 490         if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 491                 dev_kfree_skb_any(skb);
 492                 netdev_err(dev, "tx ring full\n");
 493                 netif_tx_stop_queue(txq);
 494                 return NETDEV_TX_BUSY;
 495         }
 496
 497         /* dma needs to start on a 16 byte aligned address */
 498         byte_offset = CPHYSADDR(skb->data) % 16;
 499         ch->skb[ch->dma.desc] = skb;
 500
 501         netif_trans_update(dev);
 502
 503         spin_lock_irqsave(&priv->lock, flags);
 504         desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
 505                                                 DMA_TO_DEVICE)) - byte_offset;
 506         wmb();
 507         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 508                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 509         ch->dma.desc++;
 510         ch->dma.desc %= LTQ_DESC_NUM;
 511         spin_unlock_irqrestore(&priv->lock, flags);
 512
 513         if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 514                 netif_tx_stop_queue(txq);
 515
 516         return NETDEV_TX_OK;
 517 }
 518
 519 static int
 520 ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
 521 {
 522         int ret = eth_change_mtu(dev, new_mtu);
 523
 524         if (!ret) {
 525                 struct ltq_etop_priv *priv = netdev_priv(dev);
 526                 unsigned long flags;
 527
 528                 spin_lock_irqsave(&priv->lock, flags);
 529                 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
 530                         LTQ_ETOP_IGPLEN);
 531                 spin_unlock_irqrestore(&priv->lock, flags);
 532         }
 533         return ret;
 534 }
 535
 536 static int
 537 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 538 {
 539         /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
 540         return phy_mii_ioctl(dev->phydev, rq, cmd);
 541 }
 542
 543 static int
 544 ltq_etop_set_mac_address(struct net_device *dev, void *p)
 545 {
 546         int ret = eth_mac_addr(dev, p);
 547
 548         if (!ret) {
 549                 struct ltq_etop_priv *priv = netdev_priv(dev);
 550                 unsigned long flags;
 551
 552                 /* store the mac for the unicast filter */
 553                 spin_lock_irqsave(&priv->lock, flags);
 554                 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
 555                 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
 556                         LTQ_ETOP_MAC_DA1);
 557                 spin_unlock_irqrestore(&priv->lock, flags);
 558         }
 559         return ret;
 560 }
 561
 562 static void
 563 ltq_etop_set_multicast_list(struct net_device *dev)
 564 {
 565         struct ltq_etop_priv *priv = netdev_priv(dev);
 566         unsigned long flags;
 567
 568         /* ensure that the unicast filter is not enabled in promiscious mode */
 569         spin_lock_irqsave(&priv->lock, flags);
 570         if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
 571                 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
 572         else
 573                 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
 574         spin_unlock_irqrestore(&priv->lock, flags);
 575 }
 576
 577 static u16
 578 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb,
 579                       void *accel_priv, select_queue_fallback_t fallback)
 580 {
 581         /* we are currently only using the first queue */
 582         return 0;
 583 }
 584
 585 static int
 586 ltq_etop_init(struct net_device *dev)
 587 {
 588         struct ltq_etop_priv *priv = netdev_priv(dev);
 589         struct sockaddr mac;
 590         int err;
 591         bool random_mac = false;
 592
 593         dev->watchdog_timeo = 10 * HZ;
 594         err = ltq_etop_hw_init(dev);
 595         if (err)
 596                 goto err_hw;
 597         ltq_etop_change_mtu(dev, 1500);
 598
 599         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 600         if (!is_valid_ether_addr(mac.sa_data)) {
 601                 pr_warn("etop: invalid MAC, using random\n");
 602                 eth_random_addr(mac.sa_data);
 603                 random_mac = true;
 604         }
 605
 606         err = ltq_etop_set_mac_address(dev, &mac);
 607         if (err)
 608                 goto err_netdev;
 609
 610         /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
 611         if (random_mac)
 612                 dev->addr_assign_type = NET_ADDR_RANDOM;
 613
 614         ltq_etop_set_multicast_list(dev);
 615         err = ltq_etop_mdio_init(dev);
 616         if (err)
 617                 goto err_netdev;
 618         return 0;
 619
 620 err_netdev:
 621         unregister_netdev(dev);
 622         free_netdev(dev);
 623 err_hw:
 624         ltq_etop_hw_exit(dev);
 625         return err;
 626 }
 627
 628 static void
 629 ltq_etop_tx_timeout(struct net_device *dev)
 630 {
 631         int err;
 632
 633         ltq_etop_hw_exit(dev);
 634         err = ltq_etop_hw_init(dev);
 635         if (err)
 636                 goto err_hw;
 637         netif_trans_update(dev);
 638         netif_wake_queue(dev);
 639         return;
 640
 641 err_hw:
 642         ltq_etop_hw_exit(dev);
 643         netdev_err(dev, "failed to restart etop after TX timeout\n");
 644 }
 645
 646 static const struct net_device_ops ltq_eth_netdev_ops = {
 647         .ndo_open = ltq_etop_open,
 648         .ndo_stop = ltq_etop_stop,
 649         .ndo_start_xmit = ltq_etop_tx,
 650         .ndo_change_mtu = ltq_etop_change_mtu,
 651         .ndo_do_ioctl = ltq_etop_ioctl,
 652         .ndo_set_mac_address = ltq_etop_set_mac_address,
 653         .ndo_validate_addr = eth_validate_addr,
 654         .ndo_set_rx_mode = ltq_etop_set_multicast_list,
 655         .ndo_select_queue = ltq_etop_select_queue,
 656         .ndo_init = ltq_etop_init,
 657         .ndo_tx_timeout = ltq_etop_tx_timeout,
 658 };
 659
 660 static int __init
 661 ltq_etop_probe(struct platform_device *pdev)
 662 {
 663         struct net_device *dev;
 664         struct ltq_etop_priv *priv;
 665         struct resource *res;
 666         int err;
 667         int i;
 668
 669         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 670         if (!res) {
 671                 dev_err(&pdev->dev, "failed to get etop resource\n");
 672                 err = -ENOENT;
 673                 goto err_out;
 674         }
 675
 676         res = devm_request_mem_region(&pdev->dev, res->start,
 677                 resource_size(res), dev_name(&pdev->dev));
 678         if (!res) {
 679                 dev_err(&pdev->dev, "failed to request etop resource\n");
 680                 err = -EBUSY;
 681                 goto err_out;
 682         }
 683
 684         ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
 685                 res->start, resource_size(res));
 686         if (!ltq_etop_membase) {
 687                 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
 688                         pdev->id);
 689                 err = -ENOMEM;
 690                 goto err_out;
 691         }
 692
 693         dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 694         if (!dev) {
 695                 err = -ENOMEM;
 696                 goto err_out;
 697         }
 698         strcpy(dev->name, "eth%d");
 699         dev->netdev_ops = &ltq_eth_netdev_ops;
 700         dev->ethtool_ops = &ltq_etop_ethtool_ops;
 701         priv = netdev_priv(dev);
 702         priv->res = res;
 703         priv->pdev = pdev;
 704         priv->pldata = dev_get_platdata(&pdev->dev);
 705         priv->netdev = dev;
 706         spin_lock_init(&priv->lock);
 707
 708         for (i = 0; i < MAX_DMA_CHAN; i++) {
 709                 if (IS_TX(i))
 710                         netif_napi_add(dev, &priv->ch[i].napi,
 711                                 ltq_etop_poll_tx, 8);
 712                 else if (IS_RX(i))
 713                         netif_napi_add(dev, &priv->ch[i].napi,
 714                                 ltq_etop_poll_rx, 32);
 715                 priv->ch[i].netdev = dev;
 716         }
 717
 718         err = register_netdev(dev);
 719         if (err)
 720                 goto err_free;
 721
 722         platform_set_drvdata(pdev, dev);
 723         return 0;
 724
 725 err_free:
 726         free_netdev(dev);
 727 err_out:
 728         return err;
 729 }
 730
 731 static int
 732 ltq_etop_remove(struct platform_device *pdev)
 733 {
 734         struct net_device *dev = platform_get_drvdata(pdev);
 735
 736         if (dev) {
 737                 netif_tx_stop_all_queues(dev);
 738                 ltq_etop_hw_exit(dev);
 739                 ltq_etop_mdio_cleanup(dev);
 740                 unregister_netdev(dev);
 741         }
 742         return 0;
 743 }
 744
 745 static struct platform_driver ltq_mii_driver = {
 746         .remove = ltq_etop_remove,
 747         .driver = {
 748                 .name = "ltq_etop",
 749         },
 750 };
 751
 752 int __init
 753 init_ltq_etop(void)
 754 {
 755         int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 756
 757         if (ret)
 758                 pr_err("ltq_etop: Error registering platform driver!");
 759         return ret;
 760 }
 761
 762 static void __exit
 763 exit_ltq_etop(void)
 764 {
 765         platform_driver_unregister(&ltq_mii_driver);
 766 }
 767
 768 module_init(init_ltq_etop);
 769 module_exit(exit_ltq_etop);
 770
 771 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 772 MODULE_DESCRIPTION("Lantiq SoC ETOP");
 773 MODULE_LICENSE("GPL");