1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
26 #include "mtk_eth_soc.h"
28 static int mtk_msg_level = -1;
29 module_param_named(msg_level, mtk_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32 #define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
35 /* strings used by ethtool */
36 static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
39 } mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54 static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2"
58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
60 __raw_writel(val, eth->base + reg);
63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
65 return __raw_readl(eth->base + reg);
68 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
70 unsigned long t_start = jiffies;
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
87 if (mtk_mdio_busy_wait(eth))
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
97 if (mtk_mdio_busy_wait(eth))
103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 if (mtk_mdio_busy_wait(eth))
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
115 if (mtk_mdio_busy_wait(eth))
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
126 struct mtk_eth *eth = bus->priv;
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
133 struct mtk_eth *eth = bus->priv;
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
138 static void mtk_phy_link_adjust(struct net_device *dev)
140 struct mtk_mac *mac = netdev_priv(dev);
141 u16 lcl_adv = 0, rmt_adv = 0;
143 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
144 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
145 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
148 switch (mac->phy_dev->speed) {
150 mcr |= MAC_MCR_SPEED_1000;
153 mcr |= MAC_MCR_SPEED_100;
157 if (mac->phy_dev->link)
158 mcr |= MAC_MCR_FORCE_LINK;
160 if (mac->phy_dev->duplex) {
161 mcr |= MAC_MCR_FORCE_DPX;
163 if (mac->phy_dev->pause)
164 rmt_adv = LPA_PAUSE_CAP;
165 if (mac->phy_dev->asym_pause)
166 rmt_adv |= LPA_PAUSE_ASYM;
168 if (mac->phy_dev->advertising & ADVERTISED_Pause)
169 lcl_adv |= ADVERTISE_PAUSE_CAP;
170 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
171 lcl_adv |= ADVERTISE_PAUSE_ASYM;
173 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
175 if (flowctrl & FLOW_CTRL_TX)
176 mcr |= MAC_MCR_FORCE_TX_FC;
177 if (flowctrl & FLOW_CTRL_RX)
178 mcr |= MAC_MCR_FORCE_RX_FC;
180 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
181 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
182 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
185 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
187 if (mac->phy_dev->link)
188 netif_carrier_on(dev);
190 netif_carrier_off(dev);
193 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
194 struct device_node *phy_node)
196 const __be32 *_addr = NULL;
197 struct phy_device *phydev;
200 _addr = of_get_property(phy_node, "reg", NULL);
202 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
203 pr_err("%s: invalid phy address\n", phy_node->name);
206 addr = be32_to_cpu(*_addr);
207 phy_mode = of_get_phy_mode(phy_node);
209 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
213 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
214 mtk_phy_link_adjust, 0, phy_mode);
216 dev_err(eth->dev, "could not connect to PHY\n");
221 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
222 mac->id, phydev_name(phydev), phydev->phy_id,
225 mac->phy_dev = phydev;
230 static int mtk_phy_connect(struct mtk_mac *mac)
232 struct mtk_eth *eth = mac->hw;
233 struct device_node *np;
236 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
237 if (!np && of_phy_is_fixed_link(mac->of_node))
238 if (!of_phy_register_fixed_link(mac->of_node))
239 np = of_node_get(mac->of_node);
243 switch (of_get_phy_mode(np)) {
244 case PHY_INTERFACE_MODE_RGMII_TXID:
245 case PHY_INTERFACE_MODE_RGMII_RXID:
246 case PHY_INTERFACE_MODE_RGMII_ID:
247 case PHY_INTERFACE_MODE_RGMII:
250 case PHY_INTERFACE_MODE_MII:
253 case PHY_INTERFACE_MODE_REVMII:
256 case PHY_INTERFACE_MODE_RMII:
265 /* put the gmac into the right mode */
266 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
267 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
268 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
269 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
271 mtk_phy_connect_node(eth, mac, np);
272 mac->phy_dev->autoneg = AUTONEG_ENABLE;
273 mac->phy_dev->speed = 0;
274 mac->phy_dev->duplex = 0;
276 if (of_phy_is_fixed_link(mac->of_node))
277 mac->phy_dev->supported |=
278 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
280 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
281 SUPPORTED_Asym_Pause;
282 mac->phy_dev->advertising = mac->phy_dev->supported |
284 phy_start_aneg(mac->phy_dev);
292 dev_err(eth->dev, "invalid phy_mode\n");
296 static int mtk_mdio_init(struct mtk_eth *eth)
298 struct device_node *mii_np;
301 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
303 dev_err(eth->dev, "no %s child node found", "mdio-bus");
307 if (!of_device_is_available(mii_np)) {
312 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
318 eth->mii_bus->name = "mdio";
319 eth->mii_bus->read = mtk_mdio_read;
320 eth->mii_bus->write = mtk_mdio_write;
321 eth->mii_bus->priv = eth;
322 eth->mii_bus->parent = eth->dev;
324 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
325 ret = of_mdiobus_register(eth->mii_bus, mii_np);
332 static void mtk_mdio_cleanup(struct mtk_eth *eth)
337 mdiobus_unregister(eth->mii_bus);
340 static inline void mtk_irq_disable(struct mtk_eth *eth,
341 unsigned reg, u32 mask)
346 spin_lock_irqsave(ð->irq_lock, flags);
347 val = mtk_r32(eth, reg);
348 mtk_w32(eth, val & ~mask, reg);
349 spin_unlock_irqrestore(ð->irq_lock, flags);
352 static inline void mtk_irq_enable(struct mtk_eth *eth,
353 unsigned reg, u32 mask)
358 spin_lock_irqsave(ð->irq_lock, flags);
359 val = mtk_r32(eth, reg);
360 mtk_w32(eth, val | mask, reg);
361 spin_unlock_irqrestore(ð->irq_lock, flags);
364 static int mtk_set_mac_address(struct net_device *dev, void *p)
366 int ret = eth_mac_addr(dev, p);
367 struct mtk_mac *mac = netdev_priv(dev);
368 const char *macaddr = dev->dev_addr;
373 spin_lock_bh(&mac->hw->page_lock);
374 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
375 MTK_GDMA_MAC_ADRH(mac->id));
376 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
377 (macaddr[4] << 8) | macaddr[5],
378 MTK_GDMA_MAC_ADRL(mac->id));
379 spin_unlock_bh(&mac->hw->page_lock);
384 void mtk_stats_update_mac(struct mtk_mac *mac)
386 struct mtk_hw_stats *hw_stats = mac->hw_stats;
387 unsigned int base = MTK_GDM1_TX_GBCNT;
390 base += hw_stats->reg_offset;
392 u64_stats_update_begin(&hw_stats->syncp);
394 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
395 stats = mtk_r32(mac->hw, base + 0x04);
397 hw_stats->rx_bytes += (stats << 32);
398 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
399 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
400 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
401 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
402 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
403 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
404 hw_stats->rx_flow_control_packets +=
405 mtk_r32(mac->hw, base + 0x24);
406 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
407 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
408 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
409 stats = mtk_r32(mac->hw, base + 0x34);
411 hw_stats->tx_bytes += (stats << 32);
412 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
413 u64_stats_update_end(&hw_stats->syncp);
416 static void mtk_stats_update(struct mtk_eth *eth)
420 for (i = 0; i < MTK_MAC_COUNT; i++) {
421 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
423 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
424 mtk_stats_update_mac(eth->mac[i]);
425 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
430 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
431 struct rtnl_link_stats64 *storage)
433 struct mtk_mac *mac = netdev_priv(dev);
434 struct mtk_hw_stats *hw_stats = mac->hw_stats;
437 if (netif_running(dev) && netif_device_present(dev)) {
438 if (spin_trylock(&hw_stats->stats_lock)) {
439 mtk_stats_update_mac(mac);
440 spin_unlock(&hw_stats->stats_lock);
445 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
446 storage->rx_packets = hw_stats->rx_packets;
447 storage->tx_packets = hw_stats->tx_packets;
448 storage->rx_bytes = hw_stats->rx_bytes;
449 storage->tx_bytes = hw_stats->tx_bytes;
450 storage->collisions = hw_stats->tx_collisions;
451 storage->rx_length_errors = hw_stats->rx_short_errors +
452 hw_stats->rx_long_errors;
453 storage->rx_over_errors = hw_stats->rx_overflow;
454 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
455 storage->rx_errors = hw_stats->rx_checksum_errors;
456 storage->tx_aborted_errors = hw_stats->tx_skip;
457 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
459 storage->tx_errors = dev->stats.tx_errors;
460 storage->rx_dropped = dev->stats.rx_dropped;
461 storage->tx_dropped = dev->stats.tx_dropped;
466 static inline int mtk_max_frag_size(int mtu)
468 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
469 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
470 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
472 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
473 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
476 static inline int mtk_max_buf_size(int frag_size)
478 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
479 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
481 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
486 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
487 struct mtk_rx_dma *dma_rxd)
489 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
490 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
491 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
492 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
495 /* the qdma core needs scratch memory to be setup */
496 static int mtk_init_fq_dma(struct mtk_eth *eth)
498 dma_addr_t phy_ring_tail;
499 int cnt = MTK_DMA_SIZE;
503 eth->scratch_ring = dma_alloc_coherent(eth->dev,
504 cnt * sizeof(struct mtk_tx_dma),
505 ð->phy_scratch_ring,
506 GFP_ATOMIC | __GFP_ZERO);
507 if (unlikely(!eth->scratch_ring))
510 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
512 if (unlikely(!eth->scratch_head))
515 dma_addr = dma_map_single(eth->dev,
516 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
518 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
521 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
522 phy_ring_tail = eth->phy_scratch_ring +
523 (sizeof(struct mtk_tx_dma) * (cnt - 1));
525 for (i = 0; i < cnt; i++) {
526 eth->scratch_ring[i].txd1 =
527 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
529 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
530 ((i + 1) * sizeof(struct mtk_tx_dma)));
531 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
534 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
535 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
536 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
537 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
542 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
544 void *ret = ring->dma;
546 return ret + (desc - ring->phys);
549 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
550 struct mtk_tx_dma *txd)
552 int idx = txd - ring->dma;
554 return &ring->buf[idx];
557 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
559 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
560 dma_unmap_single(eth->dev,
561 dma_unmap_addr(tx_buf, dma_addr0),
562 dma_unmap_len(tx_buf, dma_len0),
564 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
565 dma_unmap_page(eth->dev,
566 dma_unmap_addr(tx_buf, dma_addr0),
567 dma_unmap_len(tx_buf, dma_len0),
572 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
573 dev_kfree_skb_any(tx_buf->skb);
577 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
578 int tx_num, struct mtk_tx_ring *ring, bool gso)
580 struct mtk_mac *mac = netdev_priv(dev);
581 struct mtk_eth *eth = mac->hw;
582 struct mtk_tx_dma *itxd, *txd;
583 struct mtk_tx_buf *tx_buf;
584 dma_addr_t mapped_addr;
585 unsigned int nr_frags;
589 itxd = ring->next_free;
590 if (itxd == ring->last_free)
593 /* set the forward port */
594 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
597 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
598 memset(tx_buf, 0, sizeof(*tx_buf));
603 /* TX Checksum offload */
604 if (skb->ip_summed == CHECKSUM_PARTIAL)
605 txd4 |= TX_DMA_CHKSUM;
607 /* VLAN header offload */
608 if (skb_vlan_tag_present(skb))
609 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
611 mapped_addr = dma_map_single(eth->dev, skb->data,
612 skb_headlen(skb), DMA_TO_DEVICE);
613 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
616 WRITE_ONCE(itxd->txd1, mapped_addr);
617 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
618 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
619 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
623 nr_frags = skb_shinfo(skb)->nr_frags;
624 for (i = 0; i < nr_frags; i++) {
625 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
626 unsigned int offset = 0;
627 int frag_size = skb_frag_size(frag);
630 bool last_frag = false;
631 unsigned int frag_map_size;
633 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
634 if (txd == ring->last_free)
638 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
639 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
642 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
645 if (i == nr_frags - 1 &&
646 (frag_size - frag_map_size) == 0)
649 WRITE_ONCE(txd->txd1, mapped_addr);
650 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
651 TX_DMA_PLEN0(frag_map_size) |
652 last_frag * TX_DMA_LS0));
653 WRITE_ONCE(txd->txd4, fport);
655 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
656 tx_buf = mtk_desc_to_tx_buf(ring, txd);
657 memset(tx_buf, 0, sizeof(*tx_buf));
659 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
660 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
661 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
662 frag_size -= frag_map_size;
663 offset += frag_map_size;
667 /* store skb to cleanup */
670 WRITE_ONCE(itxd->txd4, txd4);
671 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
672 (!nr_frags * TX_DMA_LS0)));
674 netdev_sent_queue(dev, skb->len);
675 skb_tx_timestamp(skb);
677 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
678 atomic_sub(n_desc, &ring->free_count);
680 /* make sure that all changes to the dma ring are flushed before we
685 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
686 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
692 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
695 mtk_tx_unmap(eth, tx_buf);
697 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
698 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
699 } while (itxd != txd);
704 static inline int mtk_cal_txd_req(struct sk_buff *skb)
707 struct skb_frag_struct *frag;
710 if (skb_is_gso(skb)) {
711 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
712 frag = &skb_shinfo(skb)->frags[i];
713 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
716 nfrags += skb_shinfo(skb)->nr_frags;
722 static int mtk_queue_stopped(struct mtk_eth *eth)
726 for (i = 0; i < MTK_MAC_COUNT; i++) {
729 if (netif_queue_stopped(eth->netdev[i]))
736 static void mtk_wake_queue(struct mtk_eth *eth)
740 for (i = 0; i < MTK_MAC_COUNT; i++) {
743 netif_wake_queue(eth->netdev[i]);
747 static void mtk_stop_queue(struct mtk_eth *eth)
751 for (i = 0; i < MTK_MAC_COUNT; i++) {
754 netif_stop_queue(eth->netdev[i]);
758 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
760 struct mtk_mac *mac = netdev_priv(dev);
761 struct mtk_eth *eth = mac->hw;
762 struct mtk_tx_ring *ring = ð->tx_ring;
763 struct net_device_stats *stats = &dev->stats;
767 /* normally we can rely on the stack not calling this more than once,
768 * however we have 2 queues running on the same ring so we need to lock
771 spin_lock(ð->page_lock);
773 tx_num = mtk_cal_txd_req(skb);
774 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
776 netif_err(eth, tx_queued, dev,
777 "Tx Ring full when queue awake!\n");
778 spin_unlock(ð->page_lock);
779 return NETDEV_TX_BUSY;
782 /* TSO: fill MSS info in tcp checksum field */
783 if (skb_is_gso(skb)) {
784 if (skb_cow_head(skb, 0)) {
785 netif_warn(eth, tx_err, dev,
786 "GSO expand head fail.\n");
790 if (skb_shinfo(skb)->gso_type &
791 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
793 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
797 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
800 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
803 spin_unlock(ð->page_lock);
808 spin_unlock(ð->page_lock);
814 static int mtk_poll_rx(struct napi_struct *napi, int budget,
817 struct mtk_rx_ring *ring = ð->rx_ring;
818 int idx = ring->calc_idx;
821 struct mtk_rx_dma *rxd, trxd;
824 while (done < budget) {
825 struct net_device *netdev;
830 idx = NEXT_RX_DESP_IDX(idx);
831 rxd = &ring->dma[idx];
832 data = ring->data[idx];
834 mtk_rx_get_desc(&trxd, rxd);
835 if (!(trxd.rxd2 & RX_DMA_DONE))
838 /* find out which mac the packet come from. values start at 1 */
839 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
843 netdev = eth->netdev[mac];
845 /* alloc new buffer */
846 new_data = napi_alloc_frag(ring->frag_size);
847 if (unlikely(!new_data)) {
848 netdev->stats.rx_dropped++;
851 dma_addr = dma_map_single(eth->dev,
852 new_data + NET_SKB_PAD,
855 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
856 skb_free_frag(new_data);
857 netdev->stats.rx_dropped++;
862 skb = build_skb(data, ring->frag_size);
863 if (unlikely(!skb)) {
864 skb_free_frag(new_data);
865 netdev->stats.rx_dropped++;
868 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
870 dma_unmap_single(eth->dev, trxd.rxd1,
871 ring->buf_size, DMA_FROM_DEVICE);
872 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
874 skb_put(skb, pktlen);
875 if (trxd.rxd4 & RX_DMA_L4_VALID)
876 skb->ip_summed = CHECKSUM_UNNECESSARY;
878 skb_checksum_none_assert(skb);
879 skb->protocol = eth_type_trans(skb, netdev);
881 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
882 RX_DMA_VID(trxd.rxd3))
883 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
884 RX_DMA_VID(trxd.rxd3));
885 napi_gro_receive(napi, skb);
887 ring->data[idx] = new_data;
888 rxd->rxd1 = (unsigned int)dma_addr;
891 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
893 ring->calc_idx = idx;
899 /* make sure that all changes to the dma ring are flushed before
903 mtk_w32(eth, ring->calc_idx, MTK_PRX_CRX_IDX0);
909 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
911 struct mtk_tx_ring *ring = ð->tx_ring;
912 struct mtk_tx_dma *desc;
914 struct mtk_tx_buf *tx_buf;
915 unsigned int done[MTK_MAX_DEVS];
916 unsigned int bytes[MTK_MAX_DEVS];
918 static int condition;
921 memset(done, 0, sizeof(done));
922 memset(bytes, 0, sizeof(bytes));
924 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
925 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
927 desc = mtk_qdma_phys_to_virt(ring, cpu);
929 while ((cpu != dma) && budget) {
930 u32 next_cpu = desc->txd2;
933 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
934 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
937 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
941 tx_buf = mtk_desc_to_tx_buf(ring, desc);
948 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
949 bytes[mac] += skb->len;
953 mtk_tx_unmap(eth, tx_buf);
955 ring->last_free = desc;
956 atomic_inc(&ring->free_count);
961 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
963 for (i = 0; i < MTK_MAC_COUNT; i++) {
964 if (!eth->netdev[i] || !done[i])
966 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
970 if (mtk_queue_stopped(eth) &&
971 (atomic_read(&ring->free_count) > ring->thresh))
977 static void mtk_handle_status_irq(struct mtk_eth *eth)
979 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
981 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
982 mtk_stats_update(eth);
983 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
988 static int mtk_napi_tx(struct napi_struct *napi, int budget)
990 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
994 mtk_handle_status_irq(eth);
995 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
996 tx_done = mtk_poll_tx(eth, budget);
998 if (unlikely(netif_msg_intr(eth))) {
999 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1000 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1002 "done tx %d, intr 0x%08x/0x%x\n",
1003 tx_done, status, mask);
1006 if (tx_done == budget)
1009 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1010 if (status & MTK_TX_DONE_INT)
1013 napi_complete(napi);
1014 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1019 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1021 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1024 int remain_budget = budget;
1026 mtk_handle_status_irq(eth);
1029 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1030 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1032 if (unlikely(netif_msg_intr(eth))) {
1033 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1034 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1036 "done rx %d, intr 0x%08x/0x%x\n",
1037 rx_done, status, mask);
1039 if (rx_done == remain_budget)
1042 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1043 if (status & MTK_RX_DONE_INT) {
1044 remain_budget -= rx_done;
1047 napi_complete(napi);
1048 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1050 return rx_done + budget - remain_budget;
1053 static int mtk_tx_alloc(struct mtk_eth *eth)
1055 struct mtk_tx_ring *ring = ð->tx_ring;
1056 int i, sz = sizeof(*ring->dma);
1058 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1063 ring->dma = dma_alloc_coherent(eth->dev,
1066 GFP_ATOMIC | __GFP_ZERO);
1070 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1071 for (i = 0; i < MTK_DMA_SIZE; i++) {
1072 int next = (i + 1) % MTK_DMA_SIZE;
1073 u32 next_ptr = ring->phys + next * sz;
1075 ring->dma[i].txd2 = next_ptr;
1076 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1079 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1080 ring->next_free = &ring->dma[0];
1081 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1082 ring->thresh = MAX_SKB_FRAGS;
1084 /* make sure that all changes to the dma ring are flushed before we
1089 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1090 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1092 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1095 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1097 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1105 static void mtk_tx_clean(struct mtk_eth *eth)
1107 struct mtk_tx_ring *ring = ð->tx_ring;
1111 for (i = 0; i < MTK_DMA_SIZE; i++)
1112 mtk_tx_unmap(eth, &ring->buf[i]);
1118 dma_free_coherent(eth->dev,
1119 MTK_DMA_SIZE * sizeof(*ring->dma),
1126 static int mtk_rx_alloc(struct mtk_eth *eth)
1128 struct mtk_rx_ring *ring = ð->rx_ring;
1131 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1132 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1133 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1138 for (i = 0; i < MTK_DMA_SIZE; i++) {
1139 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1144 ring->dma = dma_alloc_coherent(eth->dev,
1145 MTK_DMA_SIZE * sizeof(*ring->dma),
1147 GFP_ATOMIC | __GFP_ZERO);
1151 for (i = 0; i < MTK_DMA_SIZE; i++) {
1152 dma_addr_t dma_addr = dma_map_single(eth->dev,
1153 ring->data[i] + NET_SKB_PAD,
1156 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1158 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1160 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1162 ring->calc_idx = MTK_DMA_SIZE - 1;
1163 /* make sure that all changes to the dma ring are flushed before we
1168 mtk_w32(eth, eth->rx_ring.phys, MTK_PRX_BASE_PTR0);
1169 mtk_w32(eth, MTK_DMA_SIZE, MTK_PRX_MAX_CNT0);
1170 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_PRX_CRX_IDX0);
1171 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_PDMA_RST_IDX);
1176 static void mtk_rx_clean(struct mtk_eth *eth)
1178 struct mtk_rx_ring *ring = ð->rx_ring;
1181 if (ring->data && ring->dma) {
1182 for (i = 0; i < MTK_DMA_SIZE; i++) {
1185 if (!ring->dma[i].rxd1)
1187 dma_unmap_single(eth->dev,
1191 skb_free_frag(ring->data[i]);
1198 dma_free_coherent(eth->dev,
1199 MTK_DMA_SIZE * sizeof(*ring->dma),
1206 /* wait for DMA to finish whatever it is doing before we start using it again */
1207 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1209 unsigned long t_start = jiffies;
1212 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1213 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1215 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1219 dev_err(eth->dev, "DMA init timeout\n");
1223 static int mtk_dma_init(struct mtk_eth *eth)
1227 if (mtk_dma_busy_wait(eth))
1230 /* QDMA needs scratch memory for internal reordering of the
1233 err = mtk_init_fq_dma(eth);
1237 err = mtk_tx_alloc(eth);
1241 err = mtk_rx_alloc(eth);
1245 /* Enable random early drop and set drop threshold automatically */
1246 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1248 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1253 static void mtk_dma_free(struct mtk_eth *eth)
1257 for (i = 0; i < MTK_MAC_COUNT; i++)
1259 netdev_reset_queue(eth->netdev[i]);
1260 if (eth->scratch_ring) {
1261 dma_free_coherent(eth->dev,
1262 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1264 eth->phy_scratch_ring);
1265 eth->scratch_ring = NULL;
1266 eth->phy_scratch_ring = 0;
1270 kfree(eth->scratch_head);
1273 static void mtk_tx_timeout(struct net_device *dev)
1275 struct mtk_mac *mac = netdev_priv(dev);
1276 struct mtk_eth *eth = mac->hw;
1278 eth->netdev[mac->id]->stats.tx_errors++;
1279 netif_err(eth, tx_err, dev,
1280 "transmit timed out\n");
1281 schedule_work(ð->pending_work);
1284 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1286 struct mtk_eth *eth = _eth;
1288 if (likely(napi_schedule_prep(ð->rx_napi))) {
1289 __napi_schedule(ð->rx_napi);
1290 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1296 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1298 struct mtk_eth *eth = _eth;
1300 if (likely(napi_schedule_prep(ð->tx_napi))) {
1301 __napi_schedule(ð->tx_napi);
1302 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1308 #ifdef CONFIG_NET_POLL_CONTROLLER
1309 static void mtk_poll_controller(struct net_device *dev)
1311 struct mtk_mac *mac = netdev_priv(dev);
1312 struct mtk_eth *eth = mac->hw;
1314 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1315 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1316 mtk_handle_irq_rx(eth->irq[2], dev);
1317 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1318 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1322 static int mtk_start_dma(struct mtk_eth *eth)
1326 err = mtk_dma_init(eth);
1333 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1334 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
1338 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1339 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1345 static int mtk_open(struct net_device *dev)
1347 struct mtk_mac *mac = netdev_priv(dev);
1348 struct mtk_eth *eth = mac->hw;
1350 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1351 if (!atomic_read(ð->dma_refcnt)) {
1352 int err = mtk_start_dma(eth);
1357 napi_enable(ð->tx_napi);
1358 napi_enable(ð->rx_napi);
1359 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1360 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1362 atomic_inc(ð->dma_refcnt);
1364 phy_start(mac->phy_dev);
1365 netif_start_queue(dev);
1370 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1375 /* stop the dma engine */
1376 spin_lock_bh(ð->page_lock);
1377 val = mtk_r32(eth, glo_cfg);
1378 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1380 spin_unlock_bh(ð->page_lock);
1382 /* wait for dma stop */
1383 for (i = 0; i < 10; i++) {
1384 val = mtk_r32(eth, glo_cfg);
1385 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1393 static int mtk_stop(struct net_device *dev)
1395 struct mtk_mac *mac = netdev_priv(dev);
1396 struct mtk_eth *eth = mac->hw;
1398 netif_tx_disable(dev);
1399 phy_stop(mac->phy_dev);
1401 /* only shutdown DMA if this is the last user */
1402 if (!atomic_dec_and_test(ð->dma_refcnt))
1405 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1406 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1407 napi_disable(ð->tx_napi);
1408 napi_disable(ð->rx_napi);
1410 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1417 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1419 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1423 usleep_range(1000, 1100);
1424 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1430 static int mtk_hw_init(struct mtk_eth *eth)
1434 if (test_and_set_bit(MTK_HW_INIT, ð->state))
1437 pm_runtime_enable(eth->dev);
1438 pm_runtime_get_sync(eth->dev);
1440 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1441 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1442 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1443 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
1444 ethsys_reset(eth, RSTCTRL_FE);
1445 ethsys_reset(eth, RSTCTRL_PPE);
1447 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1448 for (i = 0; i < MTK_MAC_COUNT; i++) {
1451 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1452 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1454 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1456 /* Set GE2 driving and slew rate */
1457 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1460 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1463 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1465 /* GE1, Force 1000M/FD, FC ON */
1466 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1468 /* GE2, Force 1000M/FD, FC ON */
1469 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1471 /* Enable RX VLan Offloading */
1472 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1474 /* disable delay and normal interrupt */
1475 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1476 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1477 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1478 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1479 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1480 mtk_w32(eth, 0, MTK_RST_GL);
1482 /* FE int grouping */
1483 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1484 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1485 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1486 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1487 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1489 for (i = 0; i < 2; i++) {
1490 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1492 /* setup the forward port to send frame to PDMA */
1495 /* Enable RX checksum */
1496 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1498 /* setup the mac dma */
1499 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1505 static int mtk_hw_deinit(struct mtk_eth *eth)
1507 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
1510 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1511 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1512 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1513 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1515 pm_runtime_put_sync(eth->dev);
1516 pm_runtime_disable(eth->dev);
1521 static int __init mtk_init(struct net_device *dev)
1523 struct mtk_mac *mac = netdev_priv(dev);
1524 struct mtk_eth *eth = mac->hw;
1525 const char *mac_addr;
1527 mac_addr = of_get_mac_address(mac->of_node);
1529 ether_addr_copy(dev->dev_addr, mac_addr);
1531 /* If the mac address is invalid, use random mac address */
1532 if (!is_valid_ether_addr(dev->dev_addr)) {
1533 random_ether_addr(dev->dev_addr);
1534 dev_err(eth->dev, "generated random MAC address %pM\n",
1536 dev->addr_assign_type = NET_ADDR_RANDOM;
1539 return mtk_phy_connect(mac);
1542 static void mtk_uninit(struct net_device *dev)
1544 struct mtk_mac *mac = netdev_priv(dev);
1545 struct mtk_eth *eth = mac->hw;
1547 phy_disconnect(mac->phy_dev);
1548 mtk_mdio_cleanup(eth);
1549 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1550 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1551 free_irq(eth->irq[1], dev);
1552 free_irq(eth->irq[2], dev);
1555 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1557 struct mtk_mac *mac = netdev_priv(dev);
1563 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1571 static void mtk_pending_work(struct work_struct *work)
1573 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1575 unsigned long restart = 0;
1579 /* stop all devices to make sure that dma is properly shut down */
1580 for (i = 0; i < MTK_MAC_COUNT; i++) {
1581 if (!eth->netdev[i])
1583 mtk_stop(eth->netdev[i]);
1584 __set_bit(i, &restart);
1587 /* restart underlying hardware such as power, clock, pin mux
1588 * and the connected phy
1593 pinctrl_select_state(eth->dev->pins->p,
1594 eth->dev->pins->default_state);
1597 for (i = 0; i < MTK_MAC_COUNT; i++) {
1599 of_phy_is_fixed_link(eth->mac[i]->of_node))
1601 err = phy_init_hw(eth->mac[i]->phy_dev);
1603 dev_err(eth->dev, "%s: PHY init failed.\n",
1604 eth->netdev[i]->name);
1607 /* restart DMA and enable IRQs */
1608 for (i = 0; i < MTK_MAC_COUNT; i++) {
1609 if (!test_bit(i, &restart))
1611 err = mtk_open(eth->netdev[i]);
1613 netif_alert(eth, ifup, eth->netdev[i],
1614 "Driver up/down cycle failed, closing device.\n");
1615 dev_close(eth->netdev[i]);
1621 static int mtk_free_dev(struct mtk_eth *eth)
1625 for (i = 0; i < MTK_MAC_COUNT; i++) {
1626 if (!eth->netdev[i])
1628 free_netdev(eth->netdev[i]);
1634 static int mtk_unreg_dev(struct mtk_eth *eth)
1638 for (i = 0; i < MTK_MAC_COUNT; i++) {
1639 if (!eth->netdev[i])
1641 unregister_netdev(eth->netdev[i]);
1647 static int mtk_cleanup(struct mtk_eth *eth)
1651 cancel_work_sync(ð->pending_work);
1656 static int mtk_get_settings(struct net_device *dev,
1657 struct ethtool_cmd *cmd)
1659 struct mtk_mac *mac = netdev_priv(dev);
1662 err = phy_read_status(mac->phy_dev);
1666 return phy_ethtool_gset(mac->phy_dev, cmd);
1669 static int mtk_set_settings(struct net_device *dev,
1670 struct ethtool_cmd *cmd)
1672 struct mtk_mac *mac = netdev_priv(dev);
1674 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1675 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1681 return phy_ethtool_sset(mac->phy_dev, cmd);
1684 static void mtk_get_drvinfo(struct net_device *dev,
1685 struct ethtool_drvinfo *info)
1687 struct mtk_mac *mac = netdev_priv(dev);
1689 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1690 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1691 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1694 static u32 mtk_get_msglevel(struct net_device *dev)
1696 struct mtk_mac *mac = netdev_priv(dev);
1698 return mac->hw->msg_enable;
1701 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1703 struct mtk_mac *mac = netdev_priv(dev);
1705 mac->hw->msg_enable = value;
1708 static int mtk_nway_reset(struct net_device *dev)
1710 struct mtk_mac *mac = netdev_priv(dev);
1712 return genphy_restart_aneg(mac->phy_dev);
1715 static u32 mtk_get_link(struct net_device *dev)
1717 struct mtk_mac *mac = netdev_priv(dev);
1720 err = genphy_update_link(mac->phy_dev);
1722 return ethtool_op_get_link(dev);
1724 return mac->phy_dev->link;
1727 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1731 switch (stringset) {
1733 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1734 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1735 data += ETH_GSTRING_LEN;
1741 static int mtk_get_sset_count(struct net_device *dev, int sset)
1745 return ARRAY_SIZE(mtk_ethtool_stats);
1751 static void mtk_get_ethtool_stats(struct net_device *dev,
1752 struct ethtool_stats *stats, u64 *data)
1754 struct mtk_mac *mac = netdev_priv(dev);
1755 struct mtk_hw_stats *hwstats = mac->hw_stats;
1756 u64 *data_src, *data_dst;
1760 if (netif_running(dev) && netif_device_present(dev)) {
1761 if (spin_trylock(&hwstats->stats_lock)) {
1762 mtk_stats_update_mac(mac);
1763 spin_unlock(&hwstats->stats_lock);
1768 data_src = (u64 *)hwstats;
1770 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1772 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1773 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1774 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1777 static const struct ethtool_ops mtk_ethtool_ops = {
1778 .get_settings = mtk_get_settings,
1779 .set_settings = mtk_set_settings,
1780 .get_drvinfo = mtk_get_drvinfo,
1781 .get_msglevel = mtk_get_msglevel,
1782 .set_msglevel = mtk_set_msglevel,
1783 .nway_reset = mtk_nway_reset,
1784 .get_link = mtk_get_link,
1785 .get_strings = mtk_get_strings,
1786 .get_sset_count = mtk_get_sset_count,
1787 .get_ethtool_stats = mtk_get_ethtool_stats,
1790 static const struct net_device_ops mtk_netdev_ops = {
1791 .ndo_init = mtk_init,
1792 .ndo_uninit = mtk_uninit,
1793 .ndo_open = mtk_open,
1794 .ndo_stop = mtk_stop,
1795 .ndo_start_xmit = mtk_start_xmit,
1796 .ndo_set_mac_address = mtk_set_mac_address,
1797 .ndo_validate_addr = eth_validate_addr,
1798 .ndo_do_ioctl = mtk_do_ioctl,
1799 .ndo_change_mtu = eth_change_mtu,
1800 .ndo_tx_timeout = mtk_tx_timeout,
1801 .ndo_get_stats64 = mtk_get_stats64,
1802 #ifdef CONFIG_NET_POLL_CONTROLLER
1803 .ndo_poll_controller = mtk_poll_controller,
1807 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1809 struct mtk_mac *mac;
1810 const __be32 *_id = of_get_property(np, "reg", NULL);
1814 dev_err(eth->dev, "missing mac id\n");
1818 id = be32_to_cpup(_id);
1819 if (id >= MTK_MAC_COUNT) {
1820 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1824 if (eth->netdev[id]) {
1825 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1829 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1830 if (!eth->netdev[id]) {
1831 dev_err(eth->dev, "alloc_etherdev failed\n");
1834 mac = netdev_priv(eth->netdev[id]);
1840 mac->hw_stats = devm_kzalloc(eth->dev,
1841 sizeof(*mac->hw_stats),
1843 if (!mac->hw_stats) {
1844 dev_err(eth->dev, "failed to allocate counter memory\n");
1848 spin_lock_init(&mac->hw_stats->stats_lock);
1849 u64_stats_init(&mac->hw_stats->syncp);
1850 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1852 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1853 eth->netdev[id]->watchdog_timeo = 5 * HZ;
1854 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1855 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1856 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1857 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1858 eth->netdev[id]->features |= MTK_HW_FEATURES;
1859 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1861 eth->netdev[id]->irq = eth->irq[0];
1865 free_netdev(eth->netdev[id]);
1869 static int mtk_probe(struct platform_device *pdev)
1871 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1872 struct device_node *mac_np;
1873 const struct of_device_id *match;
1874 struct mtk_soc_data *soc;
1875 struct mtk_eth *eth;
1879 match = of_match_device(of_mtk_match, &pdev->dev);
1880 soc = (struct mtk_soc_data *)match->data;
1882 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1886 eth->dev = &pdev->dev;
1887 eth->base = devm_ioremap_resource(&pdev->dev, res);
1888 if (IS_ERR(eth->base))
1889 return PTR_ERR(eth->base);
1891 spin_lock_init(ð->page_lock);
1892 spin_lock_init(ð->irq_lock);
1894 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1896 if (IS_ERR(eth->ethsys)) {
1897 dev_err(&pdev->dev, "no ethsys regmap found\n");
1898 return PTR_ERR(eth->ethsys);
1901 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1903 if (IS_ERR(eth->pctl)) {
1904 dev_err(&pdev->dev, "no pctl regmap found\n");
1905 return PTR_ERR(eth->pctl);
1908 for (i = 0; i < 3; i++) {
1909 eth->irq[i] = platform_get_irq(pdev, i);
1910 if (eth->irq[i] < 0) {
1911 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1915 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
1916 eth->clks[i] = devm_clk_get(eth->dev,
1917 mtk_clks_source_name[i]);
1918 if (IS_ERR(eth->clks[i])) {
1919 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
1920 return -EPROBE_DEFER;
1925 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1926 INIT_WORK(ð->pending_work, mtk_pending_work);
1928 err = mtk_hw_init(eth);
1932 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1933 if (!of_device_is_compatible(mac_np,
1934 "mediatek,eth-mac"))
1937 if (!of_device_is_available(mac_np))
1940 err = mtk_add_mac(eth, mac_np);
1945 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1946 dev_name(eth->dev), eth);
1950 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
1951 dev_name(eth->dev), eth);
1955 err = mtk_mdio_init(eth);
1959 for (i = 0; i < MTK_MAX_DEVS; i++) {
1960 if (!eth->netdev[i])
1963 err = register_netdev(eth->netdev[i]);
1965 dev_err(eth->dev, "error bringing up device\n");
1966 goto err_deinit_mdio;
1968 netif_info(eth, probe, eth->netdev[i],
1969 "mediatek frame engine at 0x%08lx, irq %d\n",
1970 eth->netdev[i]->base_addr, eth->irq[0]);
1973 /* we run 2 devices on the same DMA ring so we need a dummy device
1976 init_dummy_netdev(ð->dummy_dev);
1977 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
1979 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
1982 platform_set_drvdata(pdev, eth);
1987 mtk_mdio_cleanup(eth);
1996 static int mtk_remove(struct platform_device *pdev)
1998 struct mtk_eth *eth = platform_get_drvdata(pdev);
2001 /* stop all devices to make sure that dma is properly shut down */
2002 for (i = 0; i < MTK_MAC_COUNT; i++) {
2003 if (!eth->netdev[i])
2005 mtk_stop(eth->netdev[i]);
2010 netif_napi_del(ð->tx_napi);
2011 netif_napi_del(ð->rx_napi);
2017 const struct of_device_id of_mtk_match[] = {
2018 { .compatible = "mediatek,mt7623-eth" },
2022 static struct platform_driver mtk_driver = {
2024 .remove = mtk_remove,
2026 .name = "mtk_soc_eth",
2027 .of_match_table = of_mtk_match,
2031 module_platform_driver(mtk_driver);
2033 MODULE_LICENSE("GPL");
2034 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2035 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");