drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45 #include <linux/delay.h>
  46
  47 #include <asm/io.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "fw_qos.h"
  52
  53 #define CMD_POLL_TOKEN 0xffff
  54 #define INBOX_MASK      0xffffffffffffff00ULL
  55
  56 #define CMD_CHAN_VER 1
  57 #define CMD_CHAN_IF_REV 1
  58
  59 enum {
  60         /* command completed successfully: */
  61         CMD_STAT_OK             = 0x00,
  62         /* Internal error (such as a bus error) occurred while processing command: */
  63         CMD_STAT_INTERNAL_ERR   = 0x01,
  64         /* Operation/command not supported or opcode modifier not supported: */
  65         CMD_STAT_BAD_OP         = 0x02,
  66         /* Parameter not supported or parameter out of range: */
  67         CMD_STAT_BAD_PARAM      = 0x03,
  68         /* System not enabled or bad system state: */
  69         CMD_STAT_BAD_SYS_STATE  = 0x04,
  70         /* Attempt to access reserved or unallocaterd resource: */
  71         CMD_STAT_BAD_RESOURCE   = 0x05,
  72         /* Requested resource is currently executing a command, or is otherwise busy: */
  73         CMD_STAT_RESOURCE_BUSY  = 0x06,
  74         /* Required capability exceeds device limits: */
  75         CMD_STAT_EXCEED_LIM     = 0x08,
  76         /* Resource is not in the appropriate state or ownership: */
  77         CMD_STAT_BAD_RES_STATE  = 0x09,
  78         /* Index out of range: */
  79         CMD_STAT_BAD_INDEX      = 0x0a,
  80         /* FW image corrupted: */
  81         CMD_STAT_BAD_NVMEM      = 0x0b,
  82         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  83         CMD_STAT_ICM_ERROR      = 0x0c,
  84         /* Attempt to modify a QP/EE which is not in the presumed state: */
  85         CMD_STAT_BAD_QP_STATE   = 0x10,
  86         /* Bad segment parameters (Address/Size): */
  87         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  88         /* Memory Region has Memory Windows bound to: */
  89         CMD_STAT_REG_BOUND      = 0x21,
  90         /* HCA local attached memory not present: */
  91         CMD_STAT_LAM_NOT_PRE    = 0x22,
  92         /* Bad management packet (silently discarded): */
  93         CMD_STAT_BAD_PKT        = 0x30,
  94         /* More outstanding CQEs in CQ than new CQ size: */
  95         CMD_STAT_BAD_SIZE       = 0x40,
  96         /* Multi Function device support required: */
  97         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  98 };
  99
 100 enum {
 101         HCR_IN_PARAM_OFFSET     = 0x00,
 102         HCR_IN_MODIFIER_OFFSET  = 0x08,
 103         HCR_OUT_PARAM_OFFSET    = 0x0c,
 104         HCR_TOKEN_OFFSET        = 0x14,
 105         HCR_STATUS_OFFSET       = 0x18,
 106
 107         HCR_OPMOD_SHIFT         = 12,
 108         HCR_T_BIT               = 21,
 109         HCR_E_BIT               = 22,
 110         HCR_GO_BIT              = 23
 111 };
 112
 113 enum {
 114         GO_BIT_TIMEOUT_MSECS    = 10000
 115 };
 116
 117 enum mlx4_vlan_transition {
 118         MLX4_VLAN_TRANSITION_VST_VST = 0,
 119         MLX4_VLAN_TRANSITION_VST_VGT = 1,
 120         MLX4_VLAN_TRANSITION_VGT_VST = 2,
 121         MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 122 };
 123
 124
 125 struct mlx4_cmd_context {
 126         struct completion       done;
 127         int                     result;
 128         int                     next;
 129         u64                     out_param;
 130         u16                     token;
 131         u8                      fw_status;
 132 };
 133
 134 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 135                                     struct mlx4_vhcr_cmd *in_vhcr);
 136
 137 static int mlx4_status_to_errno(u8 status)
 138 {
 139         static const int trans_table[] = {
 140                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 141                 [CMD_STAT_BAD_OP]         = -EPERM,
 142                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 143                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 144                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 145                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 146                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 147                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 148                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 149                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 150                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 151                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 152                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 153                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 154                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 155                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 156                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 157                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 158         };
 159
 160         if (status >= ARRAY_SIZE(trans_table) ||
 161             (status != CMD_STAT_OK && trans_table[status] == 0))
 162                 return -EIO;
 163
 164         return trans_table[status];
 165 }
 166
 167 static u8 mlx4_errno_to_status(int errno)
 168 {
 169         switch (errno) {
 170         case -EPERM:
 171                 return CMD_STAT_BAD_OP;
 172         case -EINVAL:
 173                 return CMD_STAT_BAD_PARAM;
 174         case -ENXIO:
 175                 return CMD_STAT_BAD_SYS_STATE;
 176         case -EBUSY:
 177                 return CMD_STAT_RESOURCE_BUSY;
 178         case -ENOMEM:
 179                 return CMD_STAT_EXCEED_LIM;
 180         case -ENFILE:
 181                 return CMD_STAT_ICM_ERROR;
 182         default:
 183                 return CMD_STAT_INTERNAL_ERR;
 184         }
 185 }
 186
 187 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
 188                                        u8 op_modifier)
 189 {
 190         switch (op) {
 191         case MLX4_CMD_UNMAP_ICM:
 192         case MLX4_CMD_UNMAP_ICM_AUX:
 193         case MLX4_CMD_UNMAP_FA:
 194         case MLX4_CMD_2RST_QP:
 195         case MLX4_CMD_HW2SW_EQ:
 196         case MLX4_CMD_HW2SW_CQ:
 197         case MLX4_CMD_HW2SW_SRQ:
 198         case MLX4_CMD_HW2SW_MPT:
 199         case MLX4_CMD_CLOSE_HCA:
 200         case MLX4_QP_FLOW_STEERING_DETACH:
 201         case MLX4_CMD_FREE_RES:
 202         case MLX4_CMD_CLOSE_PORT:
 203                 return CMD_STAT_OK;
 204
 205         case MLX4_CMD_QP_ATTACH:
 206                 /* On Detach case return success */
 207                 if (op_modifier == 0)
 208                         return CMD_STAT_OK;
 209                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 210
 211         default:
 212                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 213         }
 214 }
 215
 216 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
 217 {
 218         /* Any error during the closing commands below is considered fatal */
 219         if (op == MLX4_CMD_CLOSE_HCA ||
 220             op == MLX4_CMD_HW2SW_EQ ||
 221             op == MLX4_CMD_HW2SW_CQ ||
 222             op == MLX4_CMD_2RST_QP ||
 223             op == MLX4_CMD_HW2SW_SRQ ||
 224             op == MLX4_CMD_SYNC_TPT ||
 225             op == MLX4_CMD_UNMAP_ICM ||
 226             op == MLX4_CMD_UNMAP_ICM_AUX ||
 227             op == MLX4_CMD_UNMAP_FA)
 228                 return 1;
 229         /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
 230           * CMD_STAT_REG_BOUND.
 231           * This status indicates that memory region has memory windows bound to it
 232           * which may result from invalid user space usage and is not fatal.
 233           */
 234         if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
 235                 return 1;
 236         return 0;
 237 }
 238
 239 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
 240                                int err)
 241 {
 242         /* Only if reset flow is really active return code is based on
 243           * command, otherwise current error code is returned.
 244           */
 245         if (mlx4_internal_err_reset) {
 246                 mlx4_enter_error_state(dev->persist);
 247                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 248         }
 249
 250         return err;
 251 }
 252
 253 static int comm_pending(struct mlx4_dev *dev)
 254 {
 255         struct mlx4_priv *priv = mlx4_priv(dev);
 256         u32 status = readl(&priv->mfunc.comm->slave_read);
 257
 258         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 259 }
 260
 261 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 262 {
 263         struct mlx4_priv *priv = mlx4_priv(dev);
 264         u32 val;
 265
 266         /* To avoid writing to unknown addresses after the device state was
 267          * changed to internal error and the function was rest,
 268          * check the INTERNAL_ERROR flag which is updated under
 269          * device_state_mutex lock.
 270          */
 271         mutex_lock(&dev->persist->device_state_mutex);
 272
 273         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 274                 mutex_unlock(&dev->persist->device_state_mutex);
 275                 return -EIO;
 276         }
 277
 278         priv->cmd.comm_toggle ^= 1;
 279         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 280         __raw_writel((__force u32) cpu_to_be32(val),
 281                      &priv->mfunc.comm->slave_write);
 282         mmiowb();
 283         mutex_unlock(&dev->persist->device_state_mutex);
 284         return 0;
 285 }
 286
 287 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 288                        unsigned long timeout)
 289 {
 290         struct mlx4_priv *priv = mlx4_priv(dev);
 291         unsigned long end;
 292         int err = 0;
 293         int ret_from_pending = 0;
 294
 295         /* First, verify that the master reports correct status */
 296         if (comm_pending(dev)) {
 297                 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
 298                           priv->cmd.comm_toggle, cmd);
 299                 return -EAGAIN;
 300         }
 301
 302         /* Write command */
 303         down(&priv->cmd.poll_sem);
 304         if (mlx4_comm_cmd_post(dev, cmd, param)) {
 305                 /* Only in case the device state is INTERNAL_ERROR,
 306                  * mlx4_comm_cmd_post returns with an error
 307                  */
 308                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 309                 goto out;
 310         }
 311
 312         end = msecs_to_jiffies(timeout) + jiffies;
 313         while (comm_pending(dev) && time_before(jiffies, end))
 314                 cond_resched();
 315         ret_from_pending = comm_pending(dev);
 316         if (ret_from_pending) {
 317                 /* check if the slave is trying to boot in the middle of
 318                  * FLR process. The only non-zero result in the RESET command
 319                  * is MLX4_DELAY_RESET_SLAVE*/
 320                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 321                         err = MLX4_DELAY_RESET_SLAVE;
 322                         goto out;
 323                 } else {
 324                         mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
 325                                   cmd);
 326                         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 327                 }
 328         }
 329
 330         if (err)
 331                 mlx4_enter_error_state(dev->persist);
 332 out:
 333         up(&priv->cmd.poll_sem);
 334         return err;
 335 }
 336
 337 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
 338                               u16 param, u16 op, unsigned long timeout)
 339 {
 340         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 341         struct mlx4_cmd_context *context;
 342         unsigned long end;
 343         int err = 0;
 344
 345         down(&cmd->event_sem);
 346
 347         spin_lock(&cmd->context_lock);
 348         BUG_ON(cmd->free_head < 0);
 349         context = &cmd->context[cmd->free_head];
 350         context->token += cmd->token_mask + 1;
 351         cmd->free_head = context->next;
 352         spin_unlock(&cmd->context_lock);
 353
 354         reinit_completion(&context->done);
 355
 356         if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
 357                 /* Only in case the device state is INTERNAL_ERROR,
 358                  * mlx4_comm_cmd_post returns with an error
 359                  */
 360                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 361                 goto out;
 362         }
 363
 364         if (!wait_for_completion_timeout(&context->done,
 365                                          msecs_to_jiffies(timeout))) {
 366                 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
 367                           vhcr_cmd, op);
 368                 goto out_reset;
 369         }
 370
 371         err = context->result;
 372         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 373                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 374                          vhcr_cmd, context->fw_status);
 375                 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 376                         goto out_reset;
 377         }
 378
 379         /* wait for comm channel ready
 380          * this is necessary for prevention the race
 381          * when switching between event to polling mode
 382          * Skipping this section in case the device is in FATAL_ERROR state,
 383          * In this state, no commands are sent via the comm channel until
 384          * the device has returned from reset.
 385          */
 386         if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 387                 end = msecs_to_jiffies(timeout) + jiffies;
 388                 while (comm_pending(dev) && time_before(jiffies, end))
 389                         cond_resched();
 390         }
 391         goto out;
 392
 393 out_reset:
 394         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 395         mlx4_enter_error_state(dev->persist);
 396 out:
 397         spin_lock(&cmd->context_lock);
 398         context->next = cmd->free_head;
 399         cmd->free_head = context - cmd->context;
 400         spin_unlock(&cmd->context_lock);
 401
 402         up(&cmd->event_sem);
 403         return err;
 404 }
 405
 406 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 407                   u16 op, unsigned long timeout)
 408 {
 409         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 410                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 411
 412         if (mlx4_priv(dev)->cmd.use_events)
 413                 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
 414         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 415 }
 416
 417 static int cmd_pending(struct mlx4_dev *dev)
 418 {
 419         u32 status;
 420
 421         if (pci_channel_offline(dev->persist->pdev))
 422                 return -EIO;
 423
 424         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 425
 426         return (status & swab32(1 << HCR_GO_BIT)) ||
 427                 (mlx4_priv(dev)->cmd.toggle ==
 428                  !!(status & swab32(1 << HCR_T_BIT)));
 429 }
 430
 431 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 432                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 433                          int event)
 434 {
 435         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 436         u32 __iomem *hcr = cmd->hcr;
 437         int ret = -EIO;
 438         unsigned long end;
 439
 440         mutex_lock(&dev->persist->device_state_mutex);
 441         /* To avoid writing to unknown addresses after the device state was
 442           * changed to internal error and the chip was reset,
 443           * check the INTERNAL_ERROR flag which is updated under
 444           * device_state_mutex lock.
 445           */
 446         if (pci_channel_offline(dev->persist->pdev) ||
 447             (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 448                 /*
 449                  * Device is going through error recovery
 450                  * and cannot accept commands.
 451                  */
 452                 goto out;
 453         }
 454
 455         end = jiffies;
 456         if (event)
 457                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 458
 459         while (cmd_pending(dev)) {
 460                 if (pci_channel_offline(dev->persist->pdev)) {
 461                         /*
 462                          * Device is going through error recovery
 463                          * and cannot accept commands.
 464                          */
 465                         goto out;
 466                 }
 467
 468                 if (time_after_eq(jiffies, end)) {
 469                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 470                         goto out;
 471                 }
 472                 cond_resched();
 473         }
 474
 475         /*
 476          * We use writel (instead of something like memcpy_toio)
 477          * because writes of less than 32 bits to the HCR don't work
 478          * (and some architectures such as ia64 implement memcpy_toio
 479          * in terms of writeb).
 480          */
 481         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 482         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 483         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 484         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 485         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 486         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 487
 488         /* __raw_writel may not order writes. */
 489         wmb();
 490
 491         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 492                                                (cmd->toggle << HCR_T_BIT)       |
 493                                                (event ? (1 << HCR_E_BIT) : 0)   |
 494                                                (op_modifier << HCR_OPMOD_SHIFT) |
 495                                                op), hcr + 6);
 496
 497         /*
 498          * Make sure that our HCR writes don't get mixed in with
 499          * writes from another CPU starting a FW command.
 500          */
 501         mmiowb();
 502
 503         cmd->toggle = cmd->toggle ^ 1;
 504
 505         ret = 0;
 506
 507 out:
 508         if (ret)
 509                 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
 510                           op, ret, in_param, in_modifier, op_modifier);
 511         mutex_unlock(&dev->persist->device_state_mutex);
 512
 513         return ret;
 514 }
 515
 516 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 517                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 518                           u16 op, unsigned long timeout)
 519 {
 520         struct mlx4_priv *priv = mlx4_priv(dev);
 521         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 522         int ret;
 523
 524         mutex_lock(&priv->cmd.slave_cmd_mutex);
 525
 526         vhcr->in_param = cpu_to_be64(in_param);
 527         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 528         vhcr->in_modifier = cpu_to_be32(in_modifier);
 529         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 530         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 531         vhcr->status = 0;
 532         vhcr->flags = !!(priv->cmd.use_events) << 6;
 533
 534         if (mlx4_is_master(dev)) {
 535                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 536                 if (!ret) {
 537                         if (out_is_imm) {
 538                                 if (out_param)
 539                                         *out_param =
 540                                                 be64_to_cpu(vhcr->out_param);
 541                                 else {
 542                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 543                                                  op);
 544                                         vhcr->status = CMD_STAT_BAD_PARAM;
 545                                 }
 546                         }
 547                         ret = mlx4_status_to_errno(vhcr->status);
 548                 }
 549                 if (ret &&
 550                     dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 551                         ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
 552         } else {
 553                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
 554                                     MLX4_COMM_TIME + timeout);
 555                 if (!ret) {
 556                         if (out_is_imm) {
 557                                 if (out_param)
 558                                         *out_param =
 559                                                 be64_to_cpu(vhcr->out_param);
 560                                 else {
 561                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 562                                                  op);
 563                                         vhcr->status = CMD_STAT_BAD_PARAM;
 564                                 }
 565                         }
 566                         ret = mlx4_status_to_errno(vhcr->status);
 567                 } else {
 568                         if (dev->persist->state &
 569                             MLX4_DEVICE_STATE_INTERNAL_ERROR)
 570                                 ret = mlx4_internal_err_ret_value(dev, op,
 571                                                                   op_modifier);
 572                         else
 573                                 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
 574                 }
 575         }
 576
 577         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 578         return ret;
 579 }
 580
 581 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 582                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 583                          u16 op, unsigned long timeout)
 584 {
 585         struct mlx4_priv *priv = mlx4_priv(dev);
 586         void __iomem *hcr = priv->cmd.hcr;
 587         int err = 0;
 588         unsigned long end;
 589         u32 stat;
 590
 591         down(&priv->cmd.poll_sem);
 592
 593         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 594                 /*
 595                  * Device is going through error recovery
 596                  * and cannot accept commands.
 597                  */
 598                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 599                 goto out;
 600         }
 601
 602         if (out_is_imm && !out_param) {
 603                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 604                          op);
 605                 err = -EINVAL;
 606                 goto out;
 607         }
 608
 609         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 610                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 611         if (err)
 612                 goto out_reset;
 613
 614         end = msecs_to_jiffies(timeout) + jiffies;
 615         while (cmd_pending(dev) && time_before(jiffies, end)) {
 616                 if (pci_channel_offline(dev->persist->pdev)) {
 617                         /*
 618                          * Device is going through error recovery
 619                          * and cannot accept commands.
 620                          */
 621                         err = -EIO;
 622                         goto out_reset;
 623                 }
 624
 625                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 626                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 627                         goto out;
 628                 }
 629
 630                 cond_resched();
 631         }
 632
 633         if (cmd_pending(dev)) {
 634                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 635                           op);
 636                 err = -EIO;
 637                 goto out_reset;
 638         }
 639
 640         if (out_is_imm)
 641                 *out_param =
 642                         (u64) be32_to_cpu((__force __be32)
 643                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 644                         (u64) be32_to_cpu((__force __be32)
 645                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 646         stat = be32_to_cpu((__force __be32)
 647                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 648         err = mlx4_status_to_errno(stat);
 649         if (err) {
 650                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 651                          op, stat);
 652                 if (mlx4_closing_cmd_fatal_error(op, stat))
 653                         goto out_reset;
 654                 goto out;
 655         }
 656
 657 out_reset:
 658         if (err)
 659                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 660 out:
 661         up(&priv->cmd.poll_sem);
 662         return err;
 663 }
 664
 665 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 666 {
 667         struct mlx4_priv *priv = mlx4_priv(dev);
 668         struct mlx4_cmd_context *context =
 669                 &priv->cmd.context[token & priv->cmd.token_mask];
 670
 671         /* previously timed out command completing at long last */
 672         if (token != context->token)
 673                 return;
 674
 675         context->fw_status = status;
 676         context->result    = mlx4_status_to_errno(status);
 677         context->out_param = out_param;
 678
 679         complete(&context->done);
 680 }
 681
 682 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 683                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 684                          u16 op, unsigned long timeout)
 685 {
 686         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 687         struct mlx4_cmd_context *context;
 688         int err = 0;
 689
 690         down(&cmd->event_sem);
 691
 692         spin_lock(&cmd->context_lock);
 693         BUG_ON(cmd->free_head < 0);
 694         context = &cmd->context[cmd->free_head];
 695         context->token += cmd->token_mask + 1;
 696         cmd->free_head = context->next;
 697         spin_unlock(&cmd->context_lock);
 698
 699         if (out_is_imm && !out_param) {
 700                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 701                          op);
 702                 err = -EINVAL;
 703                 goto out;
 704         }
 705
 706         reinit_completion(&context->done);
 707
 708         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 709                             in_modifier, op_modifier, op, context->token, 1);
 710         if (err)
 711                 goto out_reset;
 712
 713         if (!wait_for_completion_timeout(&context->done,
 714                                          msecs_to_jiffies(timeout))) {
 715                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 716                           op);
 717                 err = -EIO;
 718                 goto out_reset;
 719         }
 720
 721         err = context->result;
 722         if (err) {
 723                 /* Since we do not want to have this error message always
 724                  * displayed at driver start when there are ConnectX2 HCAs
 725                  * on the host, we deprecate the error message for this
 726                  * specific command/input_mod/opcode_mod/fw-status to be debug.
 727                  */
 728                 if (op == MLX4_CMD_SET_PORT && in_modifier == 1 &&
 729                     op_modifier == 0 && context->fw_status == CMD_STAT_BAD_SIZE)
 730                         mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
 731                                  op, context->fw_status);
 732                 else
 733                         mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 734                                  op, context->fw_status);
 735                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 736                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 737                 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 738                         goto out_reset;
 739
 740                 goto out;
 741         }
 742
 743         if (out_is_imm)
 744                 *out_param = context->out_param;
 745
 746 out_reset:
 747         if (err)
 748                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 749 out:
 750         spin_lock(&cmd->context_lock);
 751         context->next = cmd->free_head;
 752         cmd->free_head = context - cmd->context;
 753         spin_unlock(&cmd->context_lock);
 754
 755         up(&cmd->event_sem);
 756         return err;
 757 }
 758
 759 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 760                int out_is_imm, u32 in_modifier, u8 op_modifier,
 761                u16 op, unsigned long timeout, int native)
 762 {
 763         if (pci_channel_offline(dev->persist->pdev))
 764                 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
 765
 766         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 767                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 768                         return mlx4_internal_err_ret_value(dev, op,
 769                                                           op_modifier);
 770                 if (mlx4_priv(dev)->cmd.use_events)
 771                         return mlx4_cmd_wait(dev, in_param, out_param,
 772                                              out_is_imm, in_modifier,
 773                                              op_modifier, op, timeout);
 774                 else
 775                         return mlx4_cmd_poll(dev, in_param, out_param,
 776                                              out_is_imm, in_modifier,
 777                                              op_modifier, op, timeout);
 778         }
 779         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 780                               in_modifier, op_modifier, op, timeout);
 781 }
 782 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 783
 784
 785 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 786 {
 787         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 788                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 789 }
 790
 791 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 792                            int slave, u64 slave_addr,
 793                            int size, int is_read)
 794 {
 795         u64 in_param;
 796         u64 out_param;
 797
 798         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 799             (slave & ~0x7f) | (size & 0xff)) {
 800                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
 801                          slave_addr, master_addr, slave, size);
 802                 return -EINVAL;
 803         }
 804
 805         if (is_read) {
 806                 in_param = (u64) slave | slave_addr;
 807                 out_param = (u64) dev->caps.function | master_addr;
 808         } else {
 809                 in_param = (u64) dev->caps.function | master_addr;
 810                 out_param = (u64) slave | slave_addr;
 811         }
 812
 813         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 814                             MLX4_CMD_ACCESS_MEM,
 815                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 816 }
 817
 818 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 819                                struct mlx4_cmd_mailbox *inbox,
 820                                struct mlx4_cmd_mailbox *outbox)
 821 {
 822         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 823         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 824         int err;
 825         int i;
 826
 827         if (index & 0x1f)
 828                 return -EINVAL;
 829
 830         in_mad->attr_mod = cpu_to_be32(index / 32);
 831
 832         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 833                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 834                            MLX4_CMD_NATIVE);
 835         if (err)
 836                 return err;
 837
 838         for (i = 0; i < 32; ++i)
 839                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 840
 841         return err;
 842 }
 843
 844 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 845                                struct mlx4_cmd_mailbox *inbox,
 846                                struct mlx4_cmd_mailbox *outbox)
 847 {
 848         int i;
 849         int err;
 850
 851         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 852                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 853                 if (err)
 854                         return err;
 855         }
 856
 857         return 0;
 858 }
 859 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 860 #define PORT_STATE_OFFSET 32
 861
 862 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 863 {
 864         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 865                 return IB_PORT_ACTIVE;
 866         else
 867                 return IB_PORT_DOWN;
 868 }
 869
 870 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 871                                 struct mlx4_vhcr *vhcr,
 872                                 struct mlx4_cmd_mailbox *inbox,
 873                                 struct mlx4_cmd_mailbox *outbox,
 874                                 struct mlx4_cmd_info *cmd)
 875 {
 876         struct ib_smp *smp = inbox->buf;
 877         u32 index;
 878         u8 port;
 879         u8 opcode_modifier;
 880         u16 *table;
 881         int err;
 882         int vidx, pidx;
 883         int network_view;
 884         struct mlx4_priv *priv = mlx4_priv(dev);
 885         struct ib_smp *outsmp = outbox->buf;
 886         __be16 *outtab = (__be16 *)(outsmp->data);
 887         __be32 slave_cap_mask;
 888         __be64 slave_node_guid;
 889
 890         port = vhcr->in_modifier;
 891
 892         /* network-view bit is for driver use only, and should not be passed to FW */
 893         opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
 894         network_view = !!(vhcr->op_modifier & 0x8);
 895
 896         if (smp->base_version == 1 &&
 897             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 898             smp->class_version == 1) {
 899                 /* host view is paravirtualized */
 900                 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
 901                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 902                                 index = be32_to_cpu(smp->attr_mod);
 903                                 if (port < 1 || port > dev->caps.num_ports)
 904                                         return -EINVAL;
 905                                 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
 906                                                 sizeof(*table) * 32, GFP_KERNEL);
 907
 908                                 if (!table)
 909                                         return -ENOMEM;
 910                                 /* need to get the full pkey table because the paravirtualized
 911                                  * pkeys may be scattered among several pkey blocks.
 912                                  */
 913                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 914                                 if (!err) {
 915                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 916                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 917                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 918                                         }
 919                                 }
 920                                 kfree(table);
 921                                 return err;
 922                         }
 923                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 924                                 /*get the slave specific caps:*/
 925                                 /*do the command */
 926                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 927                                             vhcr->in_modifier, opcode_modifier,
 928                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 929                                 /* modify the response for slaves */
 930                                 if (!err && slave != mlx4_master_func_num(dev)) {
 931                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 932
 933                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 934                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 935                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 936                                 }
 937                                 return err;
 938                         }
 939                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 940                                 /* compute slave's gid block */
 941                                 smp->attr_mod = cpu_to_be32(slave / 8);
 942                                 /* execute cmd */
 943                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 944                                              vhcr->in_modifier, opcode_modifier,
 945                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 946                                 if (!err) {
 947                                         /* if needed, move slave gid to index 0 */
 948                                         if (slave % 8)
 949                                                 memcpy(outsmp->data,
 950                                                        outsmp->data + (slave % 8) * 8, 8);
 951                                         /* delete all other gids */
 952                                         memset(outsmp->data + 8, 0, 56);
 953                                 }
 954                                 return err;
 955                         }
 956                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 957                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 958                                              vhcr->in_modifier, opcode_modifier,
 959                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 960                                 if (!err) {
 961                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 962                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 963                                 }
 964                                 return err;
 965                         }
 966                 }
 967         }
 968
 969         /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
 970          * These are the MADs used by ib verbs (such as ib_query_gids).
 971          */
 972         if (slave != mlx4_master_func_num(dev) &&
 973             !mlx4_vf_smi_enabled(dev, slave, port)) {
 974                 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 975                       smp->method == IB_MGMT_METHOD_GET) || network_view) {
 976                         mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
 977                                  slave, smp->method, smp->mgmt_class,
 978                                  network_view ? "Network" : "Host",
 979                                  be16_to_cpu(smp->attr_id));
 980                         return -EPERM;
 981                 }
 982         }
 983
 984         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 985                                     vhcr->in_modifier, opcode_modifier,
 986                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 987 }
 988
 989 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
 990                      struct mlx4_vhcr *vhcr,
 991                      struct mlx4_cmd_mailbox *inbox,
 992                      struct mlx4_cmd_mailbox *outbox,
 993                      struct mlx4_cmd_info *cmd)
 994 {
 995         return -EPERM;
 996 }
 997
 998 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 999                      struct mlx4_vhcr *vhcr,
1000                      struct mlx4_cmd_mailbox *inbox,
1001                      struct mlx4_cmd_mailbox *outbox,
1002                      struct mlx4_cmd_info *cmd)
1003 {
1004         u64 in_param;
1005         u64 out_param;
1006         int err;
1007
1008         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1009         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1010         if (cmd->encode_slave_id) {
1011                 in_param &= 0xffffffffffffff00ll;
1012                 in_param |= slave;
1013         }
1014
1015         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1016                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1017                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1018
1019         if (cmd->out_is_imm)
1020                 vhcr->out_param = out_param;
1021
1022         return err;
1023 }
1024
1025 static struct mlx4_cmd_info cmd_info[] = {
1026         {
1027                 .opcode = MLX4_CMD_QUERY_FW,
1028                 .has_inbox = false,
1029                 .has_outbox = true,
1030                 .out_is_imm = false,
1031                 .encode_slave_id = false,
1032                 .verify = NULL,
1033                 .wrapper = mlx4_QUERY_FW_wrapper
1034         },
1035         {
1036                 .opcode = MLX4_CMD_QUERY_HCA,
1037                 .has_inbox = false,
1038                 .has_outbox = true,
1039                 .out_is_imm = false,
1040                 .encode_slave_id = false,
1041                 .verify = NULL,
1042                 .wrapper = NULL
1043         },
1044         {
1045                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1046                 .has_inbox = false,
1047                 .has_outbox = true,
1048                 .out_is_imm = false,
1049                 .encode_slave_id = false,
1050                 .verify = NULL,
1051                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1052         },
1053         {
1054                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1055                 .has_inbox = false,
1056                 .has_outbox = true,
1057                 .out_is_imm = false,
1058                 .encode_slave_id = false,
1059                 .verify = NULL,
1060                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1061         },
1062         {
1063                 .opcode = MLX4_CMD_QUERY_ADAPTER,
1064                 .has_inbox = false,
1065                 .has_outbox = true,
1066                 .out_is_imm = false,
1067                 .encode_slave_id = false,
1068                 .verify = NULL,
1069                 .wrapper = NULL
1070         },
1071         {
1072                 .opcode = MLX4_CMD_INIT_PORT,
1073                 .has_inbox = false,
1074                 .has_outbox = false,
1075                 .out_is_imm = false,
1076                 .encode_slave_id = false,
1077                 .verify = NULL,
1078                 .wrapper = mlx4_INIT_PORT_wrapper
1079         },
1080         {
1081                 .opcode = MLX4_CMD_CLOSE_PORT,
1082                 .has_inbox = false,
1083                 .has_outbox = false,
1084                 .out_is_imm  = false,
1085                 .encode_slave_id = false,
1086                 .verify = NULL,
1087                 .wrapper = mlx4_CLOSE_PORT_wrapper
1088         },
1089         {
1090                 .opcode = MLX4_CMD_QUERY_PORT,
1091                 .has_inbox = false,
1092                 .has_outbox = true,
1093                 .out_is_imm = false,
1094                 .encode_slave_id = false,
1095                 .verify = NULL,
1096                 .wrapper = mlx4_QUERY_PORT_wrapper
1097         },
1098         {
1099                 .opcode = MLX4_CMD_SET_PORT,
1100                 .has_inbox = true,
1101                 .has_outbox = false,
1102                 .out_is_imm = false,
1103                 .encode_slave_id = false,
1104                 .verify = NULL,
1105                 .wrapper = mlx4_SET_PORT_wrapper
1106         },
1107         {
1108                 .opcode = MLX4_CMD_MAP_EQ,
1109                 .has_inbox = false,
1110                 .has_outbox = false,
1111                 .out_is_imm = false,
1112                 .encode_slave_id = false,
1113                 .verify = NULL,
1114                 .wrapper = mlx4_MAP_EQ_wrapper
1115         },
1116         {
1117                 .opcode = MLX4_CMD_SW2HW_EQ,
1118                 .has_inbox = true,
1119                 .has_outbox = false,
1120                 .out_is_imm = false,
1121                 .encode_slave_id = true,
1122                 .verify = NULL,
1123                 .wrapper = mlx4_SW2HW_EQ_wrapper
1124         },
1125         {
1126                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1127                 .has_inbox = false,
1128                 .has_outbox = false,
1129                 .out_is_imm = false,
1130                 .encode_slave_id = false,
1131                 .verify = NULL,
1132                 .wrapper = NULL
1133         },
1134         {
1135                 .opcode = MLX4_CMD_NOP,
1136                 .has_inbox = false,
1137                 .has_outbox = false,
1138                 .out_is_imm = false,
1139                 .encode_slave_id = false,
1140                 .verify = NULL,
1141                 .wrapper = NULL
1142         },
1143         {
1144                 .opcode = MLX4_CMD_CONFIG_DEV,
1145                 .has_inbox = false,
1146                 .has_outbox = true,
1147                 .out_is_imm = false,
1148                 .encode_slave_id = false,
1149                 .verify = NULL,
1150                 .wrapper = mlx4_CONFIG_DEV_wrapper
1151         },
1152         {
1153                 .opcode = MLX4_CMD_ALLOC_RES,
1154                 .has_inbox = false,
1155                 .has_outbox = false,
1156                 .out_is_imm = true,
1157                 .encode_slave_id = false,
1158                 .verify = NULL,
1159                 .wrapper = mlx4_ALLOC_RES_wrapper
1160         },
1161         {
1162                 .opcode = MLX4_CMD_FREE_RES,
1163                 .has_inbox = false,
1164                 .has_outbox = false,
1165                 .out_is_imm = false,
1166                 .encode_slave_id = false,
1167                 .verify = NULL,
1168                 .wrapper = mlx4_FREE_RES_wrapper
1169         },
1170         {
1171                 .opcode = MLX4_CMD_SW2HW_MPT,
1172                 .has_inbox = true,
1173                 .has_outbox = false,
1174                 .out_is_imm = false,
1175                 .encode_slave_id = true,
1176                 .verify = NULL,
1177                 .wrapper = mlx4_SW2HW_MPT_wrapper
1178         },
1179         {
1180                 .opcode = MLX4_CMD_QUERY_MPT,
1181                 .has_inbox = false,
1182                 .has_outbox = true,
1183                 .out_is_imm = false,
1184                 .encode_slave_id = false,
1185                 .verify = NULL,
1186                 .wrapper = mlx4_QUERY_MPT_wrapper
1187         },
1188         {
1189                 .opcode = MLX4_CMD_HW2SW_MPT,
1190                 .has_inbox = false,
1191                 .has_outbox = false,
1192                 .out_is_imm = false,
1193                 .encode_slave_id = false,
1194                 .verify = NULL,
1195                 .wrapper = mlx4_HW2SW_MPT_wrapper
1196         },
1197         {
1198                 .opcode = MLX4_CMD_READ_MTT,
1199                 .has_inbox = false,
1200                 .has_outbox = true,
1201                 .out_is_imm = false,
1202                 .encode_slave_id = false,
1203                 .verify = NULL,
1204                 .wrapper = NULL
1205         },
1206         {
1207                 .opcode = MLX4_CMD_WRITE_MTT,
1208                 .has_inbox = true,
1209                 .has_outbox = false,
1210                 .out_is_imm = false,
1211                 .encode_slave_id = false,
1212                 .verify = NULL,
1213                 .wrapper = mlx4_WRITE_MTT_wrapper
1214         },
1215         {
1216                 .opcode = MLX4_CMD_SYNC_TPT,
1217                 .has_inbox = true,
1218                 .has_outbox = false,
1219                 .out_is_imm = false,
1220                 .encode_slave_id = false,
1221                 .verify = NULL,
1222                 .wrapper = NULL
1223         },
1224         {
1225                 .opcode = MLX4_CMD_HW2SW_EQ,
1226                 .has_inbox = false,
1227                 .has_outbox = false,
1228                 .out_is_imm = false,
1229                 .encode_slave_id = true,
1230                 .verify = NULL,
1231                 .wrapper = mlx4_HW2SW_EQ_wrapper
1232         },
1233         {
1234                 .opcode = MLX4_CMD_QUERY_EQ,
1235                 .has_inbox = false,
1236                 .has_outbox = true,
1237                 .out_is_imm = false,
1238                 .encode_slave_id = true,
1239                 .verify = NULL,
1240                 .wrapper = mlx4_QUERY_EQ_wrapper
1241         },
1242         {
1243                 .opcode = MLX4_CMD_SW2HW_CQ,
1244                 .has_inbox = true,
1245                 .has_outbox = false,
1246                 .out_is_imm = false,
1247                 .encode_slave_id = true,
1248                 .verify = NULL,
1249                 .wrapper = mlx4_SW2HW_CQ_wrapper
1250         },
1251         {
1252                 .opcode = MLX4_CMD_HW2SW_CQ,
1253                 .has_inbox = false,
1254                 .has_outbox = false,
1255                 .out_is_imm = false,
1256                 .encode_slave_id = false,
1257                 .verify = NULL,
1258                 .wrapper = mlx4_HW2SW_CQ_wrapper
1259         },
1260         {
1261                 .opcode = MLX4_CMD_QUERY_CQ,
1262                 .has_inbox = false,
1263                 .has_outbox = true,
1264                 .out_is_imm = false,
1265                 .encode_slave_id = false,
1266                 .verify = NULL,
1267                 .wrapper = mlx4_QUERY_CQ_wrapper
1268         },
1269         {
1270                 .opcode = MLX4_CMD_MODIFY_CQ,
1271                 .has_inbox = true,
1272                 .has_outbox = false,
1273                 .out_is_imm = true,
1274                 .encode_slave_id = false,
1275                 .verify = NULL,
1276                 .wrapper = mlx4_MODIFY_CQ_wrapper
1277         },
1278         {
1279                 .opcode = MLX4_CMD_SW2HW_SRQ,
1280                 .has_inbox = true,
1281                 .has_outbox = false,
1282                 .out_is_imm = false,
1283                 .encode_slave_id = true,
1284                 .verify = NULL,
1285                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1286         },
1287         {
1288                 .opcode = MLX4_CMD_HW2SW_SRQ,
1289                 .has_inbox = false,
1290                 .has_outbox = false,
1291                 .out_is_imm = false,
1292                 .encode_slave_id = false,
1293                 .verify = NULL,
1294                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1295         },
1296         {
1297                 .opcode = MLX4_CMD_QUERY_SRQ,
1298                 .has_inbox = false,
1299                 .has_outbox = true,
1300                 .out_is_imm = false,
1301                 .encode_slave_id = false,
1302                 .verify = NULL,
1303                 .wrapper = mlx4_QUERY_SRQ_wrapper
1304         },
1305         {
1306                 .opcode = MLX4_CMD_ARM_SRQ,
1307                 .has_inbox = false,
1308                 .has_outbox = false,
1309                 .out_is_imm = false,
1310                 .encode_slave_id = false,
1311                 .verify = NULL,
1312                 .wrapper = mlx4_ARM_SRQ_wrapper
1313         },
1314         {
1315                 .opcode = MLX4_CMD_RST2INIT_QP,
1316                 .has_inbox = true,
1317                 .has_outbox = false,
1318                 .out_is_imm = false,
1319                 .encode_slave_id = true,
1320                 .verify = NULL,
1321                 .wrapper = mlx4_RST2INIT_QP_wrapper
1322         },
1323         {
1324                 .opcode = MLX4_CMD_INIT2INIT_QP,
1325                 .has_inbox = true,
1326                 .has_outbox = false,
1327                 .out_is_imm = false,
1328                 .encode_slave_id = false,
1329                 .verify = NULL,
1330                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1331         },
1332         {
1333                 .opcode = MLX4_CMD_INIT2RTR_QP,
1334                 .has_inbox = true,
1335                 .has_outbox = false,
1336                 .out_is_imm = false,
1337                 .encode_slave_id = false,
1338                 .verify = NULL,
1339                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1340         },
1341         {
1342                 .opcode = MLX4_CMD_RTR2RTS_QP,
1343                 .has_inbox = true,
1344                 .has_outbox = false,
1345                 .out_is_imm = false,
1346                 .encode_slave_id = false,
1347                 .verify = NULL,
1348                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1349         },
1350         {
1351                 .opcode = MLX4_CMD_RTS2RTS_QP,
1352                 .has_inbox = true,
1353                 .has_outbox = false,
1354                 .out_is_imm = false,
1355                 .encode_slave_id = false,
1356                 .verify = NULL,
1357                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1358         },
1359         {
1360                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1361                 .has_inbox = true,
1362                 .has_outbox = false,
1363                 .out_is_imm = false,
1364                 .encode_slave_id = false,
1365                 .verify = NULL,
1366                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1367         },
1368         {
1369                 .opcode = MLX4_CMD_2ERR_QP,
1370                 .has_inbox = false,
1371                 .has_outbox = false,
1372                 .out_is_imm = false,
1373                 .encode_slave_id = false,
1374                 .verify = NULL,
1375                 .wrapper = mlx4_GEN_QP_wrapper
1376         },
1377         {
1378                 .opcode = MLX4_CMD_RTS2SQD_QP,
1379                 .has_inbox = false,
1380                 .has_outbox = false,
1381                 .out_is_imm = false,
1382                 .encode_slave_id = false,
1383                 .verify = NULL,
1384                 .wrapper = mlx4_GEN_QP_wrapper
1385         },
1386         {
1387                 .opcode = MLX4_CMD_SQD2SQD_QP,
1388                 .has_inbox = true,
1389                 .has_outbox = false,
1390                 .out_is_imm = false,
1391                 .encode_slave_id = false,
1392                 .verify = NULL,
1393                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1394         },
1395         {
1396                 .opcode = MLX4_CMD_SQD2RTS_QP,
1397                 .has_inbox = true,
1398                 .has_outbox = false,
1399                 .out_is_imm = false,
1400                 .encode_slave_id = false,
1401                 .verify = NULL,
1402                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1403         },
1404         {
1405                 .opcode = MLX4_CMD_2RST_QP,
1406                 .has_inbox = false,
1407                 .has_outbox = false,
1408                 .out_is_imm = false,
1409                 .encode_slave_id = false,
1410                 .verify = NULL,
1411                 .wrapper = mlx4_2RST_QP_wrapper
1412         },
1413         {
1414                 .opcode = MLX4_CMD_QUERY_QP,
1415                 .has_inbox = false,
1416                 .has_outbox = true,
1417                 .out_is_imm = false,
1418                 .encode_slave_id = false,
1419                 .verify = NULL,
1420                 .wrapper = mlx4_GEN_QP_wrapper
1421         },
1422         {
1423                 .opcode = MLX4_CMD_SUSPEND_QP,
1424                 .has_inbox = false,
1425                 .has_outbox = false,
1426                 .out_is_imm = false,
1427                 .encode_slave_id = false,
1428                 .verify = NULL,
1429                 .wrapper = mlx4_GEN_QP_wrapper
1430         },
1431         {
1432                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1433                 .has_inbox = false,
1434                 .has_outbox = false,
1435                 .out_is_imm = false,
1436                 .encode_slave_id = false,
1437                 .verify = NULL,
1438                 .wrapper = mlx4_GEN_QP_wrapper
1439         },
1440         {
1441                 .opcode = MLX4_CMD_UPDATE_QP,
1442                 .has_inbox = true,
1443                 .has_outbox = false,
1444                 .out_is_imm = false,
1445                 .encode_slave_id = false,
1446                 .verify = NULL,
1447                 .wrapper = mlx4_UPDATE_QP_wrapper
1448         },
1449         {
1450                 .opcode = MLX4_CMD_GET_OP_REQ,
1451                 .has_inbox = false,
1452                 .has_outbox = false,
1453                 .out_is_imm = false,
1454                 .encode_slave_id = false,
1455                 .verify = NULL,
1456                 .wrapper = mlx4_CMD_EPERM_wrapper,
1457         },
1458         {
1459                 .opcode = MLX4_CMD_ALLOCATE_VPP,
1460                 .has_inbox = false,
1461                 .has_outbox = true,
1462                 .out_is_imm = false,
1463                 .encode_slave_id = false,
1464                 .verify = NULL,
1465                 .wrapper = mlx4_CMD_EPERM_wrapper,
1466         },
1467         {
1468                 .opcode = MLX4_CMD_SET_VPORT_QOS,
1469                 .has_inbox = false,
1470                 .has_outbox = true,
1471                 .out_is_imm = false,
1472                 .encode_slave_id = false,
1473                 .verify = NULL,
1474                 .wrapper = mlx4_CMD_EPERM_wrapper,
1475         },
1476         {
1477                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1478                 .has_inbox = false,
1479                 .has_outbox = false,
1480                 .out_is_imm = false,
1481                 .encode_slave_id = false,
1482                 .verify = NULL, /* XXX verify: only demux can do this */
1483                 .wrapper = NULL
1484         },
1485         {
1486                 .opcode = MLX4_CMD_MAD_IFC,
1487                 .has_inbox = true,
1488                 .has_outbox = true,
1489                 .out_is_imm = false,
1490                 .encode_slave_id = false,
1491                 .verify = NULL,
1492                 .wrapper = mlx4_MAD_IFC_wrapper
1493         },
1494         {
1495                 .opcode = MLX4_CMD_MAD_DEMUX,
1496                 .has_inbox = false,
1497                 .has_outbox = false,
1498                 .out_is_imm = false,
1499                 .encode_slave_id = false,
1500                 .verify = NULL,
1501                 .wrapper = mlx4_CMD_EPERM_wrapper
1502         },
1503         {
1504                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1505                 .has_inbox = false,
1506                 .has_outbox = true,
1507                 .out_is_imm = false,
1508                 .encode_slave_id = false,
1509                 .verify = NULL,
1510                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1511         },
1512         {
1513                 .opcode = MLX4_CMD_ACCESS_REG,
1514                 .has_inbox = true,
1515                 .has_outbox = true,
1516                 .out_is_imm = false,
1517                 .encode_slave_id = false,
1518                 .verify = NULL,
1519                 .wrapper = mlx4_ACCESS_REG_wrapper,
1520         },
1521         {
1522                 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1523                 .has_inbox = false,
1524                 .has_outbox = false,
1525                 .out_is_imm = false,
1526                 .encode_slave_id = false,
1527                 .verify = NULL,
1528                 .wrapper = mlx4_CMD_EPERM_wrapper,
1529         },
1530         /* Native multicast commands are not available for guests */
1531         {
1532                 .opcode = MLX4_CMD_QP_ATTACH,
1533                 .has_inbox = true,
1534                 .has_outbox = false,
1535                 .out_is_imm = false,
1536                 .encode_slave_id = false,
1537                 .verify = NULL,
1538                 .wrapper = mlx4_QP_ATTACH_wrapper
1539         },
1540         {
1541                 .opcode = MLX4_CMD_PROMISC,
1542                 .has_inbox = false,
1543                 .has_outbox = false,
1544                 .out_is_imm = false,
1545                 .encode_slave_id = false,
1546                 .verify = NULL,
1547                 .wrapper = mlx4_PROMISC_wrapper
1548         },
1549         /* Ethernet specific commands */
1550         {
1551                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1552                 .has_inbox = true,
1553                 .has_outbox = false,
1554                 .out_is_imm = false,
1555                 .encode_slave_id = false,
1556                 .verify = NULL,
1557                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1558         },
1559         {
1560                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1561                 .has_inbox = false,
1562                 .has_outbox = false,
1563                 .out_is_imm = false,
1564                 .encode_slave_id = false,
1565                 .verify = NULL,
1566                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1567         },
1568         {
1569                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1570                 .has_inbox = false,
1571                 .has_outbox = true,
1572                 .out_is_imm = false,
1573                 .encode_slave_id = false,
1574                 .verify = NULL,
1575                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1576         },
1577         {
1578                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1579                 .has_inbox = false,
1580                 .has_outbox = false,
1581                 .out_is_imm = false,
1582                 .encode_slave_id = false,
1583                 .verify = NULL,
1584                 .wrapper = NULL
1585         },
1586         /* flow steering commands */
1587         {
1588                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1589                 .has_inbox = true,
1590                 .has_outbox = false,
1591                 .out_is_imm = true,
1592                 .encode_slave_id = false,
1593                 .verify = NULL,
1594                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1595         },
1596         {
1597                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1598                 .has_inbox = false,
1599                 .has_outbox = false,
1600                 .out_is_imm = false,
1601                 .encode_slave_id = false,
1602                 .verify = NULL,
1603                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1604         },
1605         {
1606                 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1607                 .has_inbox = false,
1608                 .has_outbox = false,
1609                 .out_is_imm = false,
1610                 .encode_slave_id = false,
1611                 .verify = NULL,
1612                 .wrapper = mlx4_CMD_EPERM_wrapper
1613         },
1614         {
1615                 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1616                 .has_inbox = false,
1617                 .has_outbox = false,
1618                 .out_is_imm = false,
1619                 .encode_slave_id = false,
1620                 .verify = NULL,
1621                 .wrapper = mlx4_CMD_EPERM_wrapper
1622         },
1623 };
1624
1625 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1626                                     struct mlx4_vhcr_cmd *in_vhcr)
1627 {
1628         struct mlx4_priv *priv = mlx4_priv(dev);
1629         struct mlx4_cmd_info *cmd = NULL;
1630         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1631         struct mlx4_vhcr *vhcr;
1632         struct mlx4_cmd_mailbox *inbox = NULL;
1633         struct mlx4_cmd_mailbox *outbox = NULL;
1634         u64 in_param;
1635         u64 out_param;
1636         int ret = 0;
1637         int i;
1638         int err = 0;
1639
1640         /* Create sw representation of Virtual HCR */
1641         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1642         if (!vhcr)
1643                 return -ENOMEM;
1644
1645         /* DMA in the vHCR */
1646         if (!in_vhcr) {
1647                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1648                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1649                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1650                                             MLX4_ACCESS_MEM_ALIGN), 1);
1651                 if (ret) {
1652                         if (!(dev->persist->state &
1653                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1654                                 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1655                                          __func__, ret);
1656                         kfree(vhcr);
1657                         return ret;
1658                 }
1659         }
1660
1661         /* Fill SW VHCR fields */
1662         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1663         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1664         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1665         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1666         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1667         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1668         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1669
1670         /* Lookup command */
1671         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1672                 if (vhcr->op == cmd_info[i].opcode) {
1673                         cmd = &cmd_info[i];
1674                         break;
1675                 }
1676         }
1677         if (!cmd) {
1678                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1679                          vhcr->op, slave);
1680                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1681                 goto out_status;
1682         }
1683
1684         /* Read inbox */
1685         if (cmd->has_inbox) {
1686                 vhcr->in_param &= INBOX_MASK;
1687                 inbox = mlx4_alloc_cmd_mailbox(dev);
1688                 if (IS_ERR(inbox)) {
1689                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1690                         inbox = NULL;
1691                         goto out_status;
1692                 }
1693
1694                 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1695                                       vhcr->in_param,
1696                                       MLX4_MAILBOX_SIZE, 1);
1697                 if (ret) {
1698                         if (!(dev->persist->state &
1699                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1700                                 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1701                                          __func__, cmd->opcode);
1702                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1703                         goto out_status;
1704                 }
1705         }
1706
1707         /* Apply permission and bound checks if applicable */
1708         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1709                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1710                           vhcr->op, slave, vhcr->in_modifier);
1711                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1712                 goto out_status;
1713         }
1714
1715         /* Allocate outbox */
1716         if (cmd->has_outbox) {
1717                 outbox = mlx4_alloc_cmd_mailbox(dev);
1718                 if (IS_ERR(outbox)) {
1719                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1720                         outbox = NULL;
1721                         goto out_status;
1722                 }
1723         }
1724
1725         /* Execute the command! */
1726         if (cmd->wrapper) {
1727                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1728                                    cmd);
1729                 if (cmd->out_is_imm)
1730                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1731         } else {
1732                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1733                         vhcr->in_param;
1734                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1735                         vhcr->out_param;
1736                 err = __mlx4_cmd(dev, in_param, &out_param,
1737                                  cmd->out_is_imm, vhcr->in_modifier,
1738                                  vhcr->op_modifier, vhcr->op,
1739                                  MLX4_CMD_TIME_CLASS_A,
1740                                  MLX4_CMD_NATIVE);
1741
1742                 if (cmd->out_is_imm) {
1743                         vhcr->out_param = out_param;
1744                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1745                 }
1746         }
1747
1748         if (err) {
1749                 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1750                         mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1751                                   vhcr->op, slave, vhcr->errno, err);
1752                 vhcr_cmd->status = mlx4_errno_to_status(err);
1753                 goto out_status;
1754         }
1755
1756
1757         /* Write outbox if command completed successfully */
1758         if (cmd->has_outbox && !vhcr_cmd->status) {
1759                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1760                                       vhcr->out_param,
1761                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1762                 if (ret) {
1763                         /* If we failed to write back the outbox after the
1764                          *command was successfully executed, we must fail this
1765                          * slave, as it is now in undefined state */
1766                         if (!(dev->persist->state &
1767                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1768                                 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1769                         goto out;
1770                 }
1771         }
1772
1773 out_status:
1774         /* DMA back vhcr result */
1775         if (!in_vhcr) {
1776                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1777                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1778                                       ALIGN(sizeof(struct mlx4_vhcr),
1779                                             MLX4_ACCESS_MEM_ALIGN),
1780                                       MLX4_CMD_WRAPPED);
1781                 if (ret)
1782                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1783                                  __func__);
1784                 else if (vhcr->e_bit &&
1785                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1786                                 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1787                                           slave);
1788         }
1789
1790 out:
1791         kfree(vhcr);
1792         mlx4_free_cmd_mailbox(dev, inbox);
1793         mlx4_free_cmd_mailbox(dev, outbox);
1794         return ret;
1795 }
1796
1797 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1798                                             int slave, int port)
1799 {
1800         struct mlx4_vport_oper_state *vp_oper;
1801         struct mlx4_vport_state *vp_admin;
1802         struct mlx4_vf_immed_vlan_work *work;
1803         struct mlx4_dev *dev = &(priv->dev);
1804         int err;
1805         int admin_vlan_ix = NO_INDX;
1806
1807         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1808         vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1809
1810         if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1811             vp_oper->state.default_qos == vp_admin->default_qos &&
1812             vp_oper->state.link_state == vp_admin->link_state &&
1813             vp_oper->state.qos_vport == vp_admin->qos_vport)
1814                 return 0;
1815
1816         if (!(priv->mfunc.master.slave_state[slave].active &&
1817               dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1818                 /* even if the UPDATE_QP command isn't supported, we still want
1819                  * to set this VF link according to the admin directive
1820                  */
1821                 vp_oper->state.link_state = vp_admin->link_state;
1822                 return -1;
1823         }
1824
1825         mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1826                  slave, port);
1827         mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1828                  vp_admin->default_vlan, vp_admin->default_qos,
1829                  vp_admin->link_state);
1830
1831         work = kzalloc(sizeof(*work), GFP_KERNEL);
1832         if (!work)
1833                 return -ENOMEM;
1834
1835         if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1836                 if (MLX4_VGT != vp_admin->default_vlan) {
1837                         err = __mlx4_register_vlan(&priv->dev, port,
1838                                                    vp_admin->default_vlan,
1839                                                    &admin_vlan_ix);
1840                         if (err) {
1841                                 kfree(work);
1842                                 mlx4_warn(&priv->dev,
1843                                           "No vlan resources slave %d, port %d\n",
1844                                           slave, port);
1845                                 return err;
1846                         }
1847                 } else {
1848                         admin_vlan_ix = NO_INDX;
1849                 }
1850                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1851                 mlx4_dbg(&priv->dev,
1852                          "alloc vlan %d idx  %d slave %d port %d\n",
1853                          (int)(vp_admin->default_vlan),
1854                          admin_vlan_ix, slave, port);
1855         }
1856
1857         /* save original vlan ix and vlan id */
1858         work->orig_vlan_id = vp_oper->state.default_vlan;
1859         work->orig_vlan_ix = vp_oper->vlan_idx;
1860
1861         /* handle new qos */
1862         if (vp_oper->state.default_qos != vp_admin->default_qos)
1863                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1864
1865         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1866                 vp_oper->vlan_idx = admin_vlan_ix;
1867
1868         vp_oper->state.default_vlan = vp_admin->default_vlan;
1869         vp_oper->state.default_qos = vp_admin->default_qos;
1870         vp_oper->state.link_state = vp_admin->link_state;
1871         vp_oper->state.qos_vport = vp_admin->qos_vport;
1872
1873         if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1874                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1875
1876         /* iterate over QPs owned by this slave, using UPDATE_QP */
1877         work->port = port;
1878         work->slave = slave;
1879         work->qos = vp_oper->state.default_qos;
1880         work->qos_vport = vp_oper->state.qos_vport;
1881         work->vlan_id = vp_oper->state.default_vlan;
1882         work->vlan_ix = vp_oper->vlan_idx;
1883         work->priv = priv;
1884         INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1885         queue_work(priv->mfunc.master.comm_wq, &work->work);
1886
1887         return 0;
1888 }
1889
1890 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1891 {
1892         struct mlx4_qos_manager *port_qos_ctl;
1893         struct mlx4_priv *priv = mlx4_priv(dev);
1894
1895         port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1896         bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1897
1898         /* Enable only default prio at PF init routine */
1899         set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1900 }
1901
1902 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1903 {
1904         int i;
1905         int err;
1906         int num_vfs;
1907         u16 availible_vpp;
1908         u8 vpp_param[MLX4_NUM_UP];
1909         struct mlx4_qos_manager *port_qos;
1910         struct mlx4_priv *priv = mlx4_priv(dev);
1911
1912         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1913         if (err) {
1914                 mlx4_info(dev, "Failed query availible VPPs\n");
1915                 return;
1916         }
1917
1918         port_qos = &priv->mfunc.master.qos_ctl[port];
1919         num_vfs = (availible_vpp /
1920                    bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1921
1922         for (i = 0; i < MLX4_NUM_UP; i++) {
1923                 if (test_bit(i, port_qos->priority_bm))
1924                         vpp_param[i] = num_vfs;
1925         }
1926
1927         err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1928         if (err) {
1929                 mlx4_info(dev, "Failed allocating VPPs\n");
1930                 return;
1931         }
1932
1933         /* Query actual allocated VPP, just to make sure */
1934         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1935         if (err) {
1936                 mlx4_info(dev, "Failed query availible VPPs\n");
1937                 return;
1938         }
1939
1940         port_qos->num_of_qos_vfs = num_vfs;
1941         mlx4_dbg(dev, "Port %d Availible VPPs %d\n", port, availible_vpp);
1942
1943         for (i = 0; i < MLX4_NUM_UP; i++)
1944                 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1945                          vpp_param[i]);
1946 }
1947
1948 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1949 {
1950         int port, err;
1951         struct mlx4_vport_state *vp_admin;
1952         struct mlx4_vport_oper_state *vp_oper;
1953         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1954                         &priv->dev, slave);
1955         int min_port = find_first_bit(actv_ports.ports,
1956                                       priv->dev.caps.num_ports) + 1;
1957         int max_port = min_port - 1 +
1958                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1959
1960         for (port = min_port; port <= max_port; port++) {
1961                 if (!test_bit(port - 1, actv_ports.ports))
1962                         continue;
1963                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1964                         priv->mfunc.master.vf_admin[slave].enable_smi[port];
1965                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1966                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1967                 vp_oper->state = *vp_admin;
1968                 if (MLX4_VGT != vp_admin->default_vlan) {
1969                         err = __mlx4_register_vlan(&priv->dev, port,
1970                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1971                         if (err) {
1972                                 vp_oper->vlan_idx = NO_INDX;
1973                                 mlx4_warn(&priv->dev,
1974                                           "No vlan resources slave %d, port %d\n",
1975                                           slave, port);
1976                                 return err;
1977                         }
1978                         mlx4_dbg(&priv->dev, "alloc vlan %d idx  %d slave %d port %d\n",
1979                                  (int)(vp_oper->state.default_vlan),
1980                                  vp_oper->vlan_idx, slave, port);
1981                 }
1982                 if (vp_admin->spoofchk) {
1983                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1984                                                                port,
1985                                                                vp_admin->mac);
1986                         if (0 > vp_oper->mac_idx) {
1987                                 err = vp_oper->mac_idx;
1988                                 vp_oper->mac_idx = NO_INDX;
1989                                 mlx4_warn(&priv->dev,
1990                                           "No mac resources slave %d, port %d\n",
1991                                           slave, port);
1992                                 return err;
1993                         }
1994                         mlx4_dbg(&priv->dev, "alloc mac %llx idx  %d slave %d port %d\n",
1995                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1996                 }
1997         }
1998         return 0;
1999 }
2000
2001 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2002 {
2003         int port;
2004         struct mlx4_vport_oper_state *vp_oper;
2005         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2006                         &priv->dev, slave);
2007         int min_port = find_first_bit(actv_ports.ports,
2008                                       priv->dev.caps.num_ports) + 1;
2009         int max_port = min_port - 1 +
2010                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2011
2012
2013         for (port = min_port; port <= max_port; port++) {
2014                 if (!test_bit(port - 1, actv_ports.ports))
2015                         continue;
2016                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2017                         MLX4_VF_SMI_DISABLED;
2018                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2019                 if (NO_INDX != vp_oper->vlan_idx) {
2020                         __mlx4_unregister_vlan(&priv->dev,
2021                                                port, vp_oper->state.default_vlan);
2022                         vp_oper->vlan_idx = NO_INDX;
2023                 }
2024                 if (NO_INDX != vp_oper->mac_idx) {
2025                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2026                         vp_oper->mac_idx = NO_INDX;
2027                 }
2028         }
2029         return;
2030 }
2031
2032 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2033                                u16 param, u8 toggle)
2034 {
2035         struct mlx4_priv *priv = mlx4_priv(dev);
2036         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2037         u32 reply;
2038         u8 is_going_down = 0;
2039         int i;
2040         unsigned long flags;
2041
2042         slave_state[slave].comm_toggle ^= 1;
2043         reply = (u32) slave_state[slave].comm_toggle << 31;
2044         if (toggle != slave_state[slave].comm_toggle) {
2045                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2046                           toggle, slave);
2047                 goto reset_slave;
2048         }
2049         if (cmd == MLX4_COMM_CMD_RESET) {
2050                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2051                 slave_state[slave].active = false;
2052                 slave_state[slave].old_vlan_api = false;
2053                 mlx4_master_deactivate_admin_state(priv, slave);
2054                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2055                                 slave_state[slave].event_eq[i].eqn = -1;
2056                                 slave_state[slave].event_eq[i].token = 0;
2057                 }
2058                 /*check if we are in the middle of FLR process,
2059                 if so return "retry" status to the slave*/
2060                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2061                         goto inform_slave_state;
2062
2063                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2064
2065                 /* write the version in the event field */
2066                 reply |= mlx4_comm_get_version();
2067
2068                 goto reset_slave;
2069         }
2070         /*command from slave in the middle of FLR*/
2071         if (cmd != MLX4_COMM_CMD_RESET &&
2072             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2073                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2074                           slave, cmd);
2075                 return;
2076         }
2077
2078         switch (cmd) {
2079         case MLX4_COMM_CMD_VHCR0:
2080                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2081                         goto reset_slave;
2082                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2083                 priv->mfunc.master.slave_state[slave].cookie = 0;
2084                 break;
2085         case MLX4_COMM_CMD_VHCR1:
2086                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2087                         goto reset_slave;
2088                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2089                 break;
2090         case MLX4_COMM_CMD_VHCR2:
2091                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2092                         goto reset_slave;
2093                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2094                 break;
2095         case MLX4_COMM_CMD_VHCR_EN:
2096                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2097                         goto reset_slave;
2098                 slave_state[slave].vhcr_dma |= param;
2099                 if (mlx4_master_activate_admin_state(priv, slave))
2100                                 goto reset_slave;
2101                 slave_state[slave].active = true;
2102                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2103                 break;
2104         case MLX4_COMM_CMD_VHCR_POST:
2105                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2106                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2107                         mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2108                                   slave, cmd, slave_state[slave].last_cmd);
2109                         goto reset_slave;
2110                 }
2111
2112                 mutex_lock(&priv->cmd.slave_cmd_mutex);
2113                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2114                         mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2115                                  slave);
2116                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2117                         goto reset_slave;
2118                 }
2119                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2120                 break;
2121         default:
2122                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2123                 goto reset_slave;
2124         }
2125         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2126         if (!slave_state[slave].is_slave_going_down)
2127                 slave_state[slave].last_cmd = cmd;
2128         else
2129                 is_going_down = 1;
2130         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2131         if (is_going_down) {
2132                 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2133                           cmd, slave);
2134                 return;
2135         }
2136         __raw_writel((__force u32) cpu_to_be32(reply),
2137                      &priv->mfunc.comm[slave].slave_read);
2138         mmiowb();
2139
2140         return;
2141
2142 reset_slave:
2143         /* cleanup any slave resources */
2144         if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2145                 mlx4_delete_all_resources_for_slave(dev, slave);
2146
2147         if (cmd != MLX4_COMM_CMD_RESET) {
2148                 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2149                           slave, cmd);
2150                 /* Turn on internal error letting slave reset itself immeditaly,
2151                  * otherwise it might take till timeout on command is passed
2152                  */
2153                 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2154         }
2155
2156         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2157         if (!slave_state[slave].is_slave_going_down)
2158                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2159         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2160         /*with slave in the middle of flr, no need to clean resources again.*/
2161 inform_slave_state:
2162         memset(&slave_state[slave].event_eq, 0,
2163                sizeof(struct mlx4_slave_event_eq_info));
2164         __raw_writel((__force u32) cpu_to_be32(reply),
2165                      &priv->mfunc.comm[slave].slave_read);
2166         wmb();
2167 }
2168
2169 /* master command processing */
2170 void mlx4_master_comm_channel(struct work_struct *work)
2171 {
2172         struct mlx4_mfunc_master_ctx *master =
2173                 container_of(work,
2174                              struct mlx4_mfunc_master_ctx,
2175                              comm_work);
2176         struct mlx4_mfunc *mfunc =
2177                 container_of(master, struct mlx4_mfunc, master);
2178         struct mlx4_priv *priv =
2179                 container_of(mfunc, struct mlx4_priv, mfunc);
2180         struct mlx4_dev *dev = &priv->dev;
2181         __be32 *bit_vec;
2182         u32 comm_cmd;
2183         u32 vec;
2184         int i, j, slave;
2185         int toggle;
2186         int served = 0;
2187         int reported = 0;
2188         u32 slt;
2189
2190         bit_vec = master->comm_arm_bit_vector;
2191         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2192                 vec = be32_to_cpu(bit_vec[i]);
2193                 for (j = 0; j < 32; j++) {
2194                         if (!(vec & (1 << j)))
2195                                 continue;
2196                         ++reported;
2197                         slave = (i * 32) + j;
2198                         comm_cmd = swab32(readl(
2199                                           &mfunc->comm[slave].slave_write));
2200                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
2201                                      >> 31;
2202                         toggle = comm_cmd >> 31;
2203                         if (toggle != slt) {
2204                                 if (master->slave_state[slave].comm_toggle
2205                                     != slt) {
2206                                         pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2207                                                 slave, slt,
2208                                                 master->slave_state[slave].comm_toggle);
2209                                         master->slave_state[slave].comm_toggle =
2210                                                 slt;
2211                                 }
2212                                 mlx4_master_do_cmd(dev, slave,
2213                                                    comm_cmd >> 16 & 0xff,
2214                                                    comm_cmd & 0xffff, toggle);
2215                                 ++served;
2216                         }
2217                 }
2218         }
2219
2220         if (reported && reported != served)
2221                 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2222                           reported, served);
2223
2224         if (mlx4_ARM_COMM_CHANNEL(dev))
2225                 mlx4_warn(dev, "Failed to arm comm channel events\n");
2226 }
2227
2228 static int sync_toggles(struct mlx4_dev *dev)
2229 {
2230         struct mlx4_priv *priv = mlx4_priv(dev);
2231         u32 wr_toggle;
2232         u32 rd_toggle;
2233         unsigned long end;
2234
2235         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2236         if (wr_toggle == 0xffffffff)
2237                 end = jiffies + msecs_to_jiffies(30000);
2238         else
2239                 end = jiffies + msecs_to_jiffies(5000);
2240
2241         while (time_before(jiffies, end)) {
2242                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2243                 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2244                         /* PCI might be offline */
2245                         msleep(100);
2246                         wr_toggle = swab32(readl(&priv->mfunc.comm->
2247                                            slave_write));
2248                         continue;
2249                 }
2250
2251                 if (rd_toggle >> 31 == wr_toggle >> 31) {
2252                         priv->cmd.comm_toggle = rd_toggle >> 31;
2253                         return 0;
2254                 }
2255
2256                 cond_resched();
2257         }
2258
2259         /*
2260          * we could reach here if for example the previous VM using this
2261          * function misbehaved and left the channel with unsynced state. We
2262          * should fix this here and give this VM a chance to use a properly
2263          * synced channel
2264          */
2265         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2266         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2267         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2268         priv->cmd.comm_toggle = 0;
2269
2270         return 0;
2271 }
2272
2273 int mlx4_multi_func_init(struct mlx4_dev *dev)
2274 {
2275         struct mlx4_priv *priv = mlx4_priv(dev);
2276         struct mlx4_slave_state *s_state;
2277         int i, j, err, port;
2278
2279         if (mlx4_is_master(dev))
2280                 priv->mfunc.comm =
2281                 ioremap(pci_resource_start(dev->persist->pdev,
2282                                            priv->fw.comm_bar) +
2283                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2284         else
2285                 priv->mfunc.comm =
2286                 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2287                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2288         if (!priv->mfunc.comm) {
2289                 mlx4_err(dev, "Couldn't map communication vector\n");
2290                 goto err_vhcr;
2291         }
2292
2293         if (mlx4_is_master(dev)) {
2294                 struct mlx4_vf_oper_state *vf_oper;
2295                 struct mlx4_vf_admin_state *vf_admin;
2296
2297                 priv->mfunc.master.slave_state =
2298                         kzalloc(dev->num_slaves *
2299                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2300                 if (!priv->mfunc.master.slave_state)
2301                         goto err_comm;
2302
2303                 priv->mfunc.master.vf_admin =
2304                         kzalloc(dev->num_slaves *
2305                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2306                 if (!priv->mfunc.master.vf_admin)
2307                         goto err_comm_admin;
2308
2309                 priv->mfunc.master.vf_oper =
2310                         kzalloc(dev->num_slaves *
2311                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2312                 if (!priv->mfunc.master.vf_oper)
2313                         goto err_comm_oper;
2314
2315                 for (i = 0; i < dev->num_slaves; ++i) {
2316                         vf_admin = &priv->mfunc.master.vf_admin[i];
2317                         vf_oper = &priv->mfunc.master.vf_oper[i];
2318                         s_state = &priv->mfunc.master.slave_state[i];
2319                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
2320                         mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2321                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2322                                 s_state->event_eq[j].eqn = -1;
2323                         __raw_writel((__force u32) 0,
2324                                      &priv->mfunc.comm[i].slave_write);
2325                         __raw_writel((__force u32) 0,
2326                                      &priv->mfunc.comm[i].slave_read);
2327                         mmiowb();
2328                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2329                                 struct mlx4_vport_state *admin_vport;
2330                                 struct mlx4_vport_state *oper_vport;
2331
2332                                 s_state->vlan_filter[port] =
2333                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
2334                                                 GFP_KERNEL);
2335                                 if (!s_state->vlan_filter[port]) {
2336                                         if (--port)
2337                                                 kfree(s_state->vlan_filter[port]);
2338                                         goto err_slaves;
2339                                 }
2340
2341                                 admin_vport = &vf_admin->vport[port];
2342                                 oper_vport = &vf_oper->vport[port].state;
2343                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2344                                 admin_vport->default_vlan = MLX4_VGT;
2345                                 oper_vport->default_vlan = MLX4_VGT;
2346                                 admin_vport->qos_vport =
2347                                                 MLX4_VPP_DEFAULT_VPORT;
2348                                 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2349                                 vf_oper->vport[port].vlan_idx = NO_INDX;
2350                                 vf_oper->vport[port].mac_idx = NO_INDX;
2351                         }
2352                         spin_lock_init(&s_state->lock);
2353                 }
2354
2355                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2356                         for (port = 1; port <= dev->caps.num_ports; port++) {
2357                                 if (mlx4_is_eth(dev, port)) {
2358                                         mlx4_set_default_port_qos(dev, port);
2359                                         mlx4_allocate_port_vpps(dev, port);
2360                                 }
2361                         }
2362                 }
2363
2364                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2365                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2366                 INIT_WORK(&priv->mfunc.master.comm_work,
2367                           mlx4_master_comm_channel);
2368                 INIT_WORK(&priv->mfunc.master.slave_event_work,
2369                           mlx4_gen_slave_eqe);
2370                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2371                           mlx4_master_handle_slave_flr);
2372                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2373                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2374                 priv->mfunc.master.comm_wq =
2375                         create_singlethread_workqueue("mlx4_comm");
2376                 if (!priv->mfunc.master.comm_wq)
2377                         goto err_slaves;
2378
2379                 if (mlx4_init_resource_tracker(dev))
2380                         goto err_thread;
2381
2382         } else {
2383                 err = sync_toggles(dev);
2384                 if (err) {
2385                         mlx4_err(dev, "Couldn't sync toggles\n");
2386                         goto err_comm;
2387                 }
2388         }
2389         return 0;
2390
2391 err_thread:
2392         flush_workqueue(priv->mfunc.master.comm_wq);
2393         destroy_workqueue(priv->mfunc.master.comm_wq);
2394 err_slaves:
2395         while (--i) {
2396                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2397                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2398         }
2399         kfree(priv->mfunc.master.vf_oper);
2400 err_comm_oper:
2401         kfree(priv->mfunc.master.vf_admin);
2402 err_comm_admin:
2403         kfree(priv->mfunc.master.slave_state);
2404 err_comm:
2405         iounmap(priv->mfunc.comm);
2406 err_vhcr:
2407         dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2408                           priv->mfunc.vhcr,
2409                           priv->mfunc.vhcr_dma);
2410         priv->mfunc.vhcr = NULL;
2411         return -ENOMEM;
2412 }
2413
2414 int mlx4_cmd_init(struct mlx4_dev *dev)
2415 {
2416         struct mlx4_priv *priv = mlx4_priv(dev);
2417         int flags = 0;
2418
2419         if (!priv->cmd.initialized) {
2420                 mutex_init(&priv->cmd.slave_cmd_mutex);
2421                 sema_init(&priv->cmd.poll_sem, 1);
2422                 priv->cmd.use_events = 0;
2423                 priv->cmd.toggle     = 1;
2424                 priv->cmd.initialized = 1;
2425                 flags |= MLX4_CMD_CLEANUP_STRUCT;
2426         }
2427
2428         if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2429                 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2430                                         0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2431                 if (!priv->cmd.hcr) {
2432                         mlx4_err(dev, "Couldn't map command register\n");
2433                         goto err;
2434                 }
2435                 flags |= MLX4_CMD_CLEANUP_HCR;
2436         }
2437
2438         if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2439                 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2440                                                       PAGE_SIZE,
2441                                                       &priv->mfunc.vhcr_dma,
2442                                                       GFP_KERNEL);
2443                 if (!priv->mfunc.vhcr)
2444                         goto err;
2445
2446                 flags |= MLX4_CMD_CLEANUP_VHCR;
2447         }
2448
2449         if (!priv->cmd.pool) {
2450                 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2451                                                  dev->persist->pdev,
2452                                                  MLX4_MAILBOX_SIZE,
2453                                                  MLX4_MAILBOX_SIZE, 0);
2454                 if (!priv->cmd.pool)
2455                         goto err;
2456
2457                 flags |= MLX4_CMD_CLEANUP_POOL;
2458         }
2459
2460         return 0;
2461
2462 err:
2463         mlx4_cmd_cleanup(dev, flags);
2464         return -ENOMEM;
2465 }
2466
2467 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2468 {
2469         struct mlx4_priv *priv = mlx4_priv(dev);
2470         int slave;
2471         u32 slave_read;
2472
2473         /* Report an internal error event to all
2474          * communication channels.
2475          */
2476         for (slave = 0; slave < dev->num_slaves; slave++) {
2477                 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2478                 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2479                 __raw_writel((__force u32)cpu_to_be32(slave_read),
2480                              &priv->mfunc.comm[slave].slave_read);
2481                 /* Make sure that our comm channel write doesn't
2482                  * get mixed in with writes from another CPU.
2483                  */
2484                 mmiowb();
2485         }
2486 }
2487
2488 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2489 {
2490         struct mlx4_priv *priv = mlx4_priv(dev);
2491         int i, port;
2492
2493         if (mlx4_is_master(dev)) {
2494                 flush_workqueue(priv->mfunc.master.comm_wq);
2495                 destroy_workqueue(priv->mfunc.master.comm_wq);
2496                 for (i = 0; i < dev->num_slaves; i++) {
2497                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
2498                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2499                 }
2500                 kfree(priv->mfunc.master.slave_state);
2501                 kfree(priv->mfunc.master.vf_admin);
2502                 kfree(priv->mfunc.master.vf_oper);
2503                 dev->num_slaves = 0;
2504         }
2505
2506         iounmap(priv->mfunc.comm);
2507 }
2508
2509 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2510 {
2511         struct mlx4_priv *priv = mlx4_priv(dev);
2512
2513         if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2514                 pci_pool_destroy(priv->cmd.pool);
2515                 priv->cmd.pool = NULL;
2516         }
2517
2518         if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2519             (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2520                 iounmap(priv->cmd.hcr);
2521                 priv->cmd.hcr = NULL;
2522         }
2523         if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2524             (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2525                 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2526                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2527                 priv->mfunc.vhcr = NULL;
2528         }
2529         if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2530                 priv->cmd.initialized = 0;
2531 }
2532
2533 /*
2534  * Switch to using events to issue FW commands (can only be called
2535  * after event queue for command events has been initialized).
2536  */
2537 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2538 {
2539         struct mlx4_priv *priv = mlx4_priv(dev);
2540         int i;
2541         int err = 0;
2542
2543         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2544                                    sizeof (struct mlx4_cmd_context),
2545                                    GFP_KERNEL);
2546         if (!priv->cmd.context)
2547                 return -ENOMEM;
2548
2549         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2550                 priv->cmd.context[i].token = i;
2551                 priv->cmd.context[i].next  = i + 1;
2552                 /* To support fatal error flow, initialize all
2553                  * cmd contexts to allow simulating completions
2554                  * with complete() at any time.
2555                  */
2556                 init_completion(&priv->cmd.context[i].done);
2557         }
2558
2559         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2560         priv->cmd.free_head = 0;
2561
2562         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2563         spin_lock_init(&priv->cmd.context_lock);
2564
2565         for (priv->cmd.token_mask = 1;
2566              priv->cmd.token_mask < priv->cmd.max_cmds;
2567              priv->cmd.token_mask <<= 1)
2568                 ; /* nothing */
2569         --priv->cmd.token_mask;
2570
2571         down(&priv->cmd.poll_sem);
2572         priv->cmd.use_events = 1;
2573
2574         return err;
2575 }
2576
2577 /*
2578  * Switch back to polling (used when shutting down the device)
2579  */
2580 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2581 {
2582         struct mlx4_priv *priv = mlx4_priv(dev);
2583         int i;
2584
2585         priv->cmd.use_events = 0;
2586
2587         for (i = 0; i < priv->cmd.max_cmds; ++i)
2588                 down(&priv->cmd.event_sem);
2589
2590         kfree(priv->cmd.context);
2591
2592         up(&priv->cmd.poll_sem);
2593 }
2594
2595 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2596 {
2597         struct mlx4_cmd_mailbox *mailbox;
2598
2599         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2600         if (!mailbox)
2601                 return ERR_PTR(-ENOMEM);
2602
2603         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2604                                       &mailbox->dma);
2605         if (!mailbox->buf) {
2606                 kfree(mailbox);
2607                 return ERR_PTR(-ENOMEM);
2608         }
2609
2610         memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2611
2612         return mailbox;
2613 }
2614 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2615
2616 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2617                            struct mlx4_cmd_mailbox *mailbox)
2618 {
2619         if (!mailbox)
2620                 return;
2621
2622         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2623         kfree(mailbox);
2624 }
2625 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2626
2627 u32 mlx4_comm_get_version(void)
2628 {
2629          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2630 }
2631
2632 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2633 {
2634         if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2635                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2636                          vf, dev->persist->num_vfs);
2637                 return -EINVAL;
2638         }
2639
2640         return vf+1;
2641 }
2642
2643 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2644 {
2645         if (slave < 1 || slave > dev->persist->num_vfs) {
2646                 mlx4_err(dev,
2647                          "Bad slave number:%d (number of activated slaves: %lu)\n",
2648                          slave, dev->num_slaves);
2649                 return -EINVAL;
2650         }
2651         return slave - 1;
2652 }
2653
2654 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2655 {
2656         struct mlx4_priv *priv = mlx4_priv(dev);
2657         struct mlx4_cmd_context *context;
2658         int i;
2659
2660         spin_lock(&priv->cmd.context_lock);
2661         if (priv->cmd.context) {
2662                 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2663                         context = &priv->cmd.context[i];
2664                         context->fw_status = CMD_STAT_INTERNAL_ERR;
2665                         context->result    =
2666                                 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2667                         complete(&context->done);
2668                 }
2669         }
2670         spin_unlock(&priv->cmd.context_lock);
2671 }
2672
2673 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2674 {
2675         struct mlx4_active_ports actv_ports;
2676         int vf;
2677
2678         bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2679
2680         if (slave == 0) {
2681                 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2682                 return actv_ports;
2683         }
2684
2685         vf = mlx4_get_vf_indx(dev, slave);
2686         if (vf < 0)
2687                 return actv_ports;
2688
2689         bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2690                    min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2691                    dev->caps.num_ports));
2692
2693         return actv_ports;
2694 }
2695 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2696
2697 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2698 {
2699         unsigned n;
2700         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2701         unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2702
2703         if (port <= 0 || port > m)
2704                 return -EINVAL;
2705
2706         n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2707         if (port <= n)
2708                 port = n + 1;
2709
2710         return port;
2711 }
2712 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2713
2714 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2715 {
2716         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2717         if (test_bit(port - 1, actv_ports.ports))
2718                 return port -
2719                         find_first_bit(actv_ports.ports, dev->caps.num_ports);
2720
2721         return -1;
2722 }
2723 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2724
2725 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2726                                                    int port)
2727 {
2728         unsigned i;
2729         struct mlx4_slaves_pport slaves_pport;
2730
2731         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2732
2733         if (port <= 0 || port > dev->caps.num_ports)
2734                 return slaves_pport;
2735
2736         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2737                 struct mlx4_active_ports actv_ports =
2738                         mlx4_get_active_ports(dev, i);
2739                 if (test_bit(port - 1, actv_ports.ports))
2740                         set_bit(i, slaves_pport.slaves);
2741         }
2742
2743         return slaves_pport;
2744 }
2745 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2746
2747 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2748                 struct mlx4_dev *dev,
2749                 const struct mlx4_active_ports *crit_ports)
2750 {
2751         unsigned i;
2752         struct mlx4_slaves_pport slaves_pport;
2753
2754         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2755
2756         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2757                 struct mlx4_active_ports actv_ports =
2758                         mlx4_get_active_ports(dev, i);
2759                 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2760                                  dev->caps.num_ports))
2761                         set_bit(i, slaves_pport.slaves);
2762         }
2763
2764         return slaves_pport;
2765 }
2766 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2767
2768 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2769 {
2770         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2771         int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2772                         + 1;
2773         int max_port = min_port +
2774                 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2775
2776         if (port < min_port)
2777                 port = min_port;
2778         else if (port >= max_port)
2779                 port = max_port - 1;
2780
2781         return port;
2782 }
2783
2784 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2785                               int max_tx_rate)
2786 {
2787         int i;
2788         int err;
2789         struct mlx4_qos_manager *port_qos;
2790         struct mlx4_dev *dev = &priv->dev;
2791         struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2792
2793         port_qos = &priv->mfunc.master.qos_ctl[port];
2794         memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2795
2796         if (slave > port_qos->num_of_qos_vfs) {
2797                 mlx4_info(dev, "No availible VPP resources for this VF\n");
2798                 return -EINVAL;
2799         }
2800
2801         /* Query for default QoS values from Vport 0 is needed */
2802         err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2803         if (err) {
2804                 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2805                 return err;
2806         }
2807
2808         for (i = 0; i < MLX4_NUM_UP; i++) {
2809                 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2810                         vpp_qos[i].max_avg_bw = max_tx_rate;
2811                         vpp_qos[i].enable = 1;
2812                 } else {
2813                         /* if user supplied tx_rate == 0, meaning no rate limit
2814                          * configuration is required. so we are leaving the
2815                          * value of max_avg_bw as queried from Vport 0.
2816                          */
2817                         vpp_qos[i].enable = 0;
2818                 }
2819         }
2820
2821         err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2822         if (err) {
2823                 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2824                 return err;
2825         }
2826
2827         return 0;
2828 }
2829
2830 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2831                                         struct mlx4_vport_state *vf_admin)
2832 {
2833         struct mlx4_qos_manager *info;
2834         struct mlx4_priv *priv = mlx4_priv(dev);
2835
2836         if (!mlx4_is_master(dev) ||
2837             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2838                 return false;
2839
2840         info = &priv->mfunc.master.qos_ctl[port];
2841
2842         if (vf_admin->default_vlan != MLX4_VGT &&
2843             test_bit(vf_admin->default_qos, info->priority_bm))
2844                 return true;
2845
2846         return false;
2847 }
2848
2849 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2850                                        struct mlx4_vport_state *vf_admin,
2851                                        int vlan, int qos)
2852 {
2853         struct mlx4_vport_state dummy_admin = {0};
2854
2855         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2856             !vf_admin->tx_rate)
2857                 return true;
2858
2859         dummy_admin.default_qos = qos;
2860         dummy_admin.default_vlan = vlan;
2861
2862         /* VF wants to move to other VST state which is valid with current
2863          * rate limit. Either differnt default vlan in VST or other
2864          * supported QoS priority. Otherwise we don't allow this change when
2865          * the TX rate is still configured.
2866          */
2867         if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2868                 return true;
2869
2870         mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2871                   (vlan == MLX4_VGT) ? "VGT" : "VST");
2872
2873         if (vlan != MLX4_VGT)
2874                 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2875
2876         mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2877
2878         return false;
2879 }
2880
2881 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2882 {
2883         struct mlx4_priv *priv = mlx4_priv(dev);
2884         struct mlx4_vport_state *s_info;
2885         int slave;
2886
2887         if (!mlx4_is_master(dev))
2888                 return -EPROTONOSUPPORT;
2889
2890         slave = mlx4_get_slave_indx(dev, vf);
2891         if (slave < 0)
2892                 return -EINVAL;
2893
2894         port = mlx4_slaves_closest_port(dev, slave, port);
2895         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2896         s_info->mac = mac;
2897         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2898                   vf, port, s_info->mac);
2899         return 0;
2900 }
2901 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2902
2903
2904 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2905 {
2906         struct mlx4_priv *priv = mlx4_priv(dev);
2907         struct mlx4_vport_state *vf_admin;
2908         int slave;
2909
2910         if ((!mlx4_is_master(dev)) ||
2911             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2912                 return -EPROTONOSUPPORT;
2913
2914         if ((vlan > 4095) || (qos > 7))
2915                 return -EINVAL;
2916
2917         slave = mlx4_get_slave_indx(dev, vf);
2918         if (slave < 0)
2919                 return -EINVAL;
2920
2921         port = mlx4_slaves_closest_port(dev, slave, port);
2922         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2923
2924         if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
2925                 return -EPERM;
2926
2927         if ((0 == vlan) && (0 == qos))
2928                 vf_admin->default_vlan = MLX4_VGT;
2929         else
2930                 vf_admin->default_vlan = vlan;
2931         vf_admin->default_qos = qos;
2932
2933         /* If rate was configured prior to VST, we saved the configured rate
2934          * in vf_admin->rate and now, if priority supported we enforce the QoS
2935          */
2936         if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
2937             vf_admin->tx_rate)
2938                 vf_admin->qos_vport = slave;
2939
2940         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2941                 mlx4_info(dev,
2942                           "updating vf %d port %d config will take effect on next VF restart\n",
2943                           vf, port);
2944         return 0;
2945 }
2946 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2947
2948 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
2949                      int max_tx_rate)
2950 {
2951         int err;
2952         int slave;
2953         struct mlx4_vport_state *vf_admin;
2954         struct mlx4_priv *priv = mlx4_priv(dev);
2955
2956         if (!mlx4_is_master(dev) ||
2957             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2958                 return -EPROTONOSUPPORT;
2959
2960         if (min_tx_rate) {
2961                 mlx4_info(dev, "Minimum BW share not supported\n");
2962                 return -EPROTONOSUPPORT;
2963         }
2964
2965         slave = mlx4_get_slave_indx(dev, vf);
2966         if (slave < 0)
2967                 return -EINVAL;
2968
2969         port = mlx4_slaves_closest_port(dev, slave, port);
2970         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2971
2972         err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
2973         if (err) {
2974                 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
2975                           max_tx_rate);
2976                 return err;
2977         }
2978
2979         vf_admin->tx_rate = max_tx_rate;
2980         /* if VF is not in supported mode (VST with supported prio),
2981          * we do not change vport configuration for its QPs, but save
2982          * the rate, so it will be enforced when it moves to supported
2983          * mode next time.
2984          */
2985         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
2986                 mlx4_info(dev,
2987                           "rate set for VF %d when not in valid state\n", vf);
2988
2989                 if (vf_admin->default_vlan != MLX4_VGT)
2990                         mlx4_info(dev, "VST priority not supported by QoS\n");
2991                 else
2992                         mlx4_info(dev, "VF in VGT mode (needed VST)\n");
2993
2994                 mlx4_info(dev,
2995                           "rate %d take affect when VF moves to valid state\n",
2996                           max_tx_rate);
2997                 return 0;
2998         }
2999
3000         /* If user sets rate 0 assigning default vport for its QPs */
3001         vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3002
3003         if (priv->mfunc.master.slave_state[slave].active &&
3004             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3005                 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3006
3007         return 0;
3008 }
3009 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3010
3011  /* mlx4_get_slave_default_vlan -
3012  * return true if VST ( default vlan)
3013  * if VST, will return vlan & qos (if not NULL)
3014  */
3015 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3016                                  u16 *vlan, u8 *qos)
3017 {
3018         struct mlx4_vport_oper_state *vp_oper;
3019         struct mlx4_priv *priv;
3020
3021         priv = mlx4_priv(dev);
3022         port = mlx4_slaves_closest_port(dev, slave, port);
3023         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3024
3025         if (MLX4_VGT != vp_oper->state.default_vlan) {
3026                 if (vlan)
3027                         *vlan = vp_oper->state.default_vlan;
3028                 if (qos)
3029                         *qos = vp_oper->state.default_qos;
3030                 return true;
3031         }
3032         return false;
3033 }
3034 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3035
3036 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3037 {
3038         struct mlx4_priv *priv = mlx4_priv(dev);
3039         struct mlx4_vport_state *s_info;
3040         int slave;
3041
3042         if ((!mlx4_is_master(dev)) ||
3043             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3044                 return -EPROTONOSUPPORT;
3045
3046         slave = mlx4_get_slave_indx(dev, vf);
3047         if (slave < 0)
3048                 return -EINVAL;
3049
3050         port = mlx4_slaves_closest_port(dev, slave, port);
3051         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3052         s_info->spoofchk = setting;
3053
3054         return 0;
3055 }
3056 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3057
3058 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3059 {
3060         struct mlx4_priv *priv = mlx4_priv(dev);
3061         struct mlx4_vport_state *s_info;
3062         int slave;
3063
3064         if (!mlx4_is_master(dev))
3065                 return -EPROTONOSUPPORT;
3066
3067         slave = mlx4_get_slave_indx(dev, vf);
3068         if (slave < 0)
3069                 return -EINVAL;
3070
3071         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3072         ivf->vf = vf;
3073
3074         /* need to convert it to a func */
3075         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3076         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3077         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3078         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3079         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3080         ivf->mac[5] = ((s_info->mac)  & 0xff);
3081
3082         ivf->vlan               = s_info->default_vlan;
3083         ivf->qos                = s_info->default_qos;
3084
3085         if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3086                 ivf->max_tx_rate = s_info->tx_rate;
3087         else
3088                 ivf->max_tx_rate = 0;
3089
3090         ivf->min_tx_rate        = 0;
3091         ivf->spoofchk           = s_info->spoofchk;
3092         ivf->linkstate          = s_info->link_state;
3093
3094         return 0;
3095 }
3096 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3097
3098 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3099 {
3100         struct mlx4_priv *priv = mlx4_priv(dev);
3101         struct mlx4_vport_state *s_info;
3102         int slave;
3103         u8 link_stat_event;
3104
3105         slave = mlx4_get_slave_indx(dev, vf);
3106         if (slave < 0)
3107                 return -EINVAL;
3108
3109         port = mlx4_slaves_closest_port(dev, slave, port);
3110         switch (link_state) {
3111         case IFLA_VF_LINK_STATE_AUTO:
3112                 /* get current link state */
3113                 if (!priv->sense.do_sense_port[port])
3114                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3115                 else
3116                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3117             break;
3118
3119         case IFLA_VF_LINK_STATE_ENABLE:
3120                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3121             break;
3122
3123         case IFLA_VF_LINK_STATE_DISABLE:
3124                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3125             break;
3126
3127         default:
3128                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3129                           link_state, slave, port);
3130                 return -EINVAL;
3131         };
3132         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3133         s_info->link_state = link_state;
3134
3135         /* send event */
3136         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3137
3138         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3139                 mlx4_dbg(dev,
3140                          "updating vf %d port %d no link state HW enforcment\n",
3141                          vf, port);
3142         return 0;
3143 }
3144 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3145
3146 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3147 {
3148         struct mlx4_priv *priv = mlx4_priv(dev);
3149
3150         if (slave < 1 || slave >= dev->num_slaves ||
3151             port < 1 || port > MLX4_MAX_PORTS)
3152                 return 0;
3153
3154         return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3155                 MLX4_VF_SMI_ENABLED;
3156 }
3157 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3158
3159 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3160 {
3161         struct mlx4_priv *priv = mlx4_priv(dev);
3162
3163         if (slave == mlx4_master_func_num(dev))
3164                 return 1;
3165
3166         if (slave < 1 || slave >= dev->num_slaves ||
3167             port < 1 || port > MLX4_MAX_PORTS)
3168                 return 0;
3169
3170         return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3171                 MLX4_VF_SMI_ENABLED;
3172 }
3173 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3174
3175 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3176                                  int enabled)
3177 {
3178         struct mlx4_priv *priv = mlx4_priv(dev);
3179
3180         if (slave == mlx4_master_func_num(dev))
3181                 return 0;
3182
3183         if (slave < 1 || slave >= dev->num_slaves ||
3184             port < 1 || port > MLX4_MAX_PORTS ||
3185             enabled < 0 || enabled > 1)
3186                 return -EINVAL;
3187
3188         priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3189         return 0;
3190 }
3191 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);