2 * Copyright (c) 2011 Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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34 #include <linux/dcbnl.h>
38 static int mlx4_en_dcbnl_ieee_getets(struct net_device *dev,
41 struct mlx4_en_priv *priv = netdev_priv(dev);
42 struct ieee_ets *my_ets = &priv->ets;
44 /* No IEEE PFC settings available */
48 ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
49 ets->cbs = my_ets->cbs;
50 memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw));
51 memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa));
52 memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc));
57 static int mlx4_en_ets_validate(struct mlx4_en_priv *priv, struct ieee_ets *ets)
63 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
64 if (ets->prio_tc[i] > MLX4_EN_NUM_UP) {
65 en_err(priv, "Bad priority in UP <=> TC mapping. TC: %d, UP: %d\n",
70 switch (ets->tc_tsa[i]) {
71 case IEEE_8021QAZ_TSA_STRICT:
73 case IEEE_8021QAZ_TSA_ETS:
75 total_ets_bw += ets->tc_tx_bw[i];
78 en_err(priv, "TC[%d]: Not supported TSA: %d\n",
84 if (has_ets_tc && total_ets_bw != MLX4_EN_BW_MAX) {
85 en_err(priv, "Bad ETS BW sum: %d. Should be exactly 100%%\n",
93 static int mlx4_en_config_port_scheduler(struct mlx4_en_priv *priv,
94 struct ieee_ets *ets, u16 *ratelimit)
96 struct mlx4_en_dev *mdev = priv->mdev;
99 __u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS] = { 0 };
100 __u8 pg[IEEE_8021QAZ_MAX_TCS] = { 0 };
102 ets = ets ?: &priv->ets;
104 /* higher TC means higher priority => lower pg */
105 for (i = IEEE_8021QAZ_MAX_TCS - 1; i >= 0; i--) {
106 switch (ets->tc_tsa[i]) {
107 case IEEE_8021QAZ_TSA_STRICT:
108 pg[i] = num_strict++;
109 tc_tx_bw[i] = MLX4_EN_BW_MAX;
111 case IEEE_8021QAZ_TSA_ETS:
112 pg[i] = MLX4_EN_TC_ETS;
113 tc_tx_bw[i] = ets->tc_tx_bw[i] ?: MLX4_EN_BW_MIN;
118 return mlx4_SET_PORT_SCHEDULER(mdev->dev, priv->port, tc_tx_bw, pg,
123 mlx4_en_dcbnl_ieee_setets(struct net_device *dev, struct ieee_ets *ets)
125 struct mlx4_en_priv *priv = netdev_priv(dev);
126 struct mlx4_en_dev *mdev = priv->mdev;
129 err = mlx4_en_ets_validate(priv, ets);
133 err = mlx4_SET_PORT_PRIO2TC(mdev->dev, priv->port, ets->prio_tc);
137 err = mlx4_en_config_port_scheduler(priv, ets, NULL);
141 memcpy(&priv->ets, ets, sizeof(priv->ets));
146 static int mlx4_en_dcbnl_ieee_getpfc(struct net_device *dev,
147 struct ieee_pfc *pfc)
149 struct mlx4_en_priv *priv = netdev_priv(dev);
151 pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
152 pfc->pfc_en = priv->prof->tx_ppp;
157 static int mlx4_en_dcbnl_ieee_setpfc(struct net_device *dev,
158 struct ieee_pfc *pfc)
160 struct mlx4_en_priv *priv = netdev_priv(dev);
161 struct mlx4_en_dev *mdev = priv->mdev;
164 en_dbg(DRV, priv, "cap: 0x%x en: 0x%x mbc: 0x%x delay: %d\n",
170 priv->prof->rx_pause = priv->prof->tx_pause = !!pfc->pfc_en;
171 priv->prof->rx_ppp = priv->prof->tx_ppp = pfc->pfc_en;
173 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
174 priv->rx_skb_size + ETH_FCS_LEN,
175 priv->prof->tx_pause,
177 priv->prof->rx_pause,
180 en_err(priv, "Failed setting pause params\n");
185 static u8 mlx4_en_dcbnl_getdcbx(struct net_device *dev)
187 return DCB_CAP_DCBX_VER_IEEE;
190 static u8 mlx4_en_dcbnl_setdcbx(struct net_device *dev, u8 mode)
192 if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
193 (mode & DCB_CAP_DCBX_VER_CEE) ||
194 !(mode & DCB_CAP_DCBX_VER_IEEE) ||
195 !(mode & DCB_CAP_DCBX_HOST))
201 const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops = {
202 .ieee_getets = mlx4_en_dcbnl_ieee_getets,
203 .ieee_setets = mlx4_en_dcbnl_ieee_setets,
204 .ieee_getpfc = mlx4_en_dcbnl_ieee_getpfc,
205 .ieee_setpfc = mlx4_en_dcbnl_ieee_setpfc,
207 .getdcbx = mlx4_en_dcbnl_getdcbx,
208 .setdcbx = mlx4_en_dcbnl_setdcbx,