drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/irq.h>
  44
  45 #if IS_ENABLED(CONFIG_IPV6)
  46 #include <net/ip6_checksum.h>
  47 #endif
  48
  49 #include "mlx4_en.h"
  50
  51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  52                             struct mlx4_en_rx_alloc *page_alloc,
  53                             const struct mlx4_en_frag_info *frag_info,
  54                             gfp_t _gfp)
  55 {
  56         int order;
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  61                 gfp_t gfp = _gfp;
  62
  63                 if (order)
  64                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  65                 page = alloc_pages(gfp, order);
  66                 if (likely(page))
  67                         break;
  68                 if (--order < 0 ||
  69                     ((PAGE_SIZE << order) < frag_info->frag_size))
  70                         return -ENOMEM;
  71         }
  72         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  73                            PCI_DMA_FROMDEVICE);
  74         if (dma_mapping_error(priv->ddev, dma)) {
  75                 put_page(page);
  76                 return -ENOMEM;
  77         }
  78         page_alloc->page_size = PAGE_SIZE << order;
  79         page_alloc->page = page;
  80         page_alloc->dma = dma;
  81         page_alloc->page_offset = 0;
  82         /* Not doing get_page() for each frag is a big win
  83          * on asymetric workloads. Note we can not use atomic_set().
  84          */
  85         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  86         return 0;
  87 }
  88
  89 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  90                                struct mlx4_en_rx_desc *rx_desc,
  91                                struct mlx4_en_rx_alloc *frags,
  92                                struct mlx4_en_rx_alloc *ring_alloc,
  93                                gfp_t gfp)
  94 {
  95         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  96         const struct mlx4_en_frag_info *frag_info;
  97         struct page *page;
  98         dma_addr_t dma;
  99         int i;
 100
 101         for (i = 0; i < priv->num_frags; i++) {
 102                 frag_info = &priv->frag_info[i];
 103                 page_alloc[i] = ring_alloc[i];
 104                 page_alloc[i].page_offset += frag_info->frag_stride;
 105
 106                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 107                     ring_alloc[i].page_size)
 108                         continue;
 109
 110                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
 111                         goto out;
 112         }
 113
 114         for (i = 0; i < priv->num_frags; i++) {
 115                 frags[i] = ring_alloc[i];
 116                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 117                 ring_alloc[i] = page_alloc[i];
 118                 rx_desc->data[i].addr = cpu_to_be64(dma);
 119         }
 120
 121         return 0;
 122
 123 out:
 124         while (i--) {
 125                 if (page_alloc[i].page != ring_alloc[i].page) {
 126                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 127                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
 128                         page = page_alloc[i].page;
 129                         /* Revert changes done by mlx4_alloc_pages */
 130                         page_ref_sub(page, page_alloc[i].page_size /
 131                                            priv->frag_info[i].frag_stride - 1);
 132                         put_page(page);
 133                 }
 134         }
 135         return -ENOMEM;
 136 }
 137
 138 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 139                               struct mlx4_en_rx_alloc *frags,
 140                               int i)
 141 {
 142         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 143         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 144
 145
 146         if (next_frag_end > frags[i].page_size)
 147                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 148                                PCI_DMA_FROMDEVICE);
 149
 150         if (frags[i].page)
 151                 put_page(frags[i].page);
 152 }
 153
 154 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 155                                   struct mlx4_en_rx_ring *ring)
 156 {
 157         int i;
 158         struct mlx4_en_rx_alloc *page_alloc;
 159
 160         for (i = 0; i < priv->num_frags; i++) {
 161                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 162
 163                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 164                                      frag_info, GFP_KERNEL | __GFP_COLD))
 165                         goto out;
 166
 167                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 168                        i, ring->page_alloc[i].page_size,
 169                        page_ref_count(ring->page_alloc[i].page));
 170         }
 171         return 0;
 172
 173 out:
 174         while (i--) {
 175                 struct page *page;
 176
 177                 page_alloc = &ring->page_alloc[i];
 178                 dma_unmap_page(priv->ddev, page_alloc->dma,
 179                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
 180                 page = page_alloc->page;
 181                 /* Revert changes done by mlx4_alloc_pages */
 182                 page_ref_sub(page, page_alloc->page_size /
 183                                    priv->frag_info[i].frag_stride - 1);
 184                 put_page(page);
 185                 page_alloc->page = NULL;
 186         }
 187         return -ENOMEM;
 188 }
 189
 190 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 191                                       struct mlx4_en_rx_ring *ring)
 192 {
 193         struct mlx4_en_rx_alloc *page_alloc;
 194         int i;
 195
 196         for (i = 0; i < priv->num_frags; i++) {
 197                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 198
 199                 page_alloc = &ring->page_alloc[i];
 200                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 201                        i, page_count(page_alloc->page));
 202
 203                 dma_unmap_page(priv->ddev, page_alloc->dma,
 204                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
 205                 while (page_alloc->page_offset + frag_info->frag_stride <
 206                        page_alloc->page_size) {
 207                         put_page(page_alloc->page);
 208                         page_alloc->page_offset += frag_info->frag_stride;
 209                 }
 210                 page_alloc->page = NULL;
 211         }
 212 }
 213
 214 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 215                                  struct mlx4_en_rx_ring *ring, int index)
 216 {
 217         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 218         int possible_frags;
 219         int i;
 220
 221         /* Set size and memtype fields */
 222         for (i = 0; i < priv->num_frags; i++) {
 223                 rx_desc->data[i].byte_count =
 224                         cpu_to_be32(priv->frag_info[i].frag_size);
 225                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 226         }
 227
 228         /* If the number of used fragments does not fill up the ring stride,
 229          * remaining (unused) fragments must be padded with null address/size
 230          * and a special memory key */
 231         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 232         for (i = priv->num_frags; i < possible_frags; i++) {
 233                 rx_desc->data[i].byte_count = 0;
 234                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 235                 rx_desc->data[i].addr = 0;
 236         }
 237 }
 238
 239 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 240                                    struct mlx4_en_rx_ring *ring, int index,
 241                                    gfp_t gfp)
 242 {
 243         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 244         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 245                                         (index << priv->log_rx_info);
 246
 247         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 248 }
 249
 250 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 251 {
 252         return ring->prod == ring->cons;
 253 }
 254
 255 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 256 {
 257         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 258 }
 259
 260 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 261                                  struct mlx4_en_rx_ring *ring,
 262                                  int index)
 263 {
 264         struct mlx4_en_rx_alloc *frags;
 265         int nr;
 266
 267         frags = ring->rx_info + (index << priv->log_rx_info);
 268         for (nr = 0; nr < priv->num_frags; nr++) {
 269                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 270                 mlx4_en_free_frag(priv, frags, nr);
 271         }
 272 }
 273
 274 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 275 {
 276         struct mlx4_en_rx_ring *ring;
 277         int ring_ind;
 278         int buf_ind;
 279         int new_size;
 280
 281         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 282                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 283                         ring = priv->rx_ring[ring_ind];
 284
 285                         if (mlx4_en_prepare_rx_desc(priv, ring,
 286                                                     ring->actual_size,
 287                                                     GFP_KERNEL | __GFP_COLD)) {
 288                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 289                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 290                                         return -ENOMEM;
 291                                 } else {
 292                                         new_size = rounddown_pow_of_two(ring->actual_size);
 293                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 294                                                 ring->actual_size, new_size);
 295                                         goto reduce_rings;
 296                                 }
 297                         }
 298                         ring->actual_size++;
 299                         ring->prod++;
 300                 }
 301         }
 302         return 0;
 303
 304 reduce_rings:
 305         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 306                 ring = priv->rx_ring[ring_ind];
 307                 while (ring->actual_size > new_size) {
 308                         ring->actual_size--;
 309                         ring->prod--;
 310                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 311                 }
 312         }
 313
 314         return 0;
 315 }
 316
 317 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 318                                 struct mlx4_en_rx_ring *ring)
 319 {
 320         int index;
 321
 322         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 323                ring->cons, ring->prod);
 324
 325         /* Unmap and free Rx buffers */
 326         while (!mlx4_en_is_ring_empty(ring)) {
 327                 index = ring->cons & ring->size_mask;
 328                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 329                 mlx4_en_free_rx_desc(priv, ring, index);
 330                 ++ring->cons;
 331         }
 332 }
 333
 334 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 335 {
 336         int i;
 337         int num_of_eqs;
 338         int num_rx_rings;
 339         struct mlx4_dev *dev = mdev->dev;
 340
 341         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 342                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 343                                    min_t(int,
 344                                          mlx4_get_eqs_per_port(mdev->dev, i),
 345                                          DEF_RX_RINGS));
 346
 347                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 348                         min_t(int, num_of_eqs,
 349                               netif_get_num_default_rss_queues());
 350                 mdev->profile.prof[i].rx_ring_num =
 351                         rounddown_pow_of_two(num_rx_rings);
 352         }
 353 }
 354
 355 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 356                            struct mlx4_en_rx_ring **pring,
 357                            u32 size, u16 stride, int node)
 358 {
 359         struct mlx4_en_dev *mdev = priv->mdev;
 360         struct mlx4_en_rx_ring *ring;
 361         int err = -ENOMEM;
 362         int tmp;
 363
 364         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 365         if (!ring) {
 366                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 367                 if (!ring) {
 368                         en_err(priv, "Failed to allocate RX ring structure\n");
 369                         return -ENOMEM;
 370                 }
 371         }
 372
 373         ring->prod = 0;
 374         ring->cons = 0;
 375         ring->size = size;
 376         ring->size_mask = size - 1;
 377         ring->stride = stride;
 378         ring->log_stride = ffs(ring->stride) - 1;
 379         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 380
 381         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 382                                         sizeof(struct mlx4_en_rx_alloc));
 383         ring->rx_info = vmalloc_node(tmp, node);
 384         if (!ring->rx_info) {
 385                 ring->rx_info = vmalloc(tmp);
 386                 if (!ring->rx_info) {
 387                         err = -ENOMEM;
 388                         goto err_ring;
 389                 }
 390         }
 391
 392         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 393                  ring->rx_info, tmp);
 394
 395         /* Allocate HW buffers on provided NUMA node */
 396         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 397         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 398         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 399         if (err)
 400                 goto err_info;
 401
 402         ring->buf = ring->wqres.buf.direct.buf;
 403
 404         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 405
 406         *pring = ring;
 407         return 0;
 408
 409 err_info:
 410         vfree(ring->rx_info);
 411         ring->rx_info = NULL;
 412 err_ring:
 413         kfree(ring);
 414         *pring = NULL;
 415
 416         return err;
 417 }
 418
 419 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 420 {
 421         struct mlx4_en_rx_ring *ring;
 422         int i;
 423         int ring_ind;
 424         int err;
 425         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 426                                         DS_SIZE * priv->num_frags);
 427
 428         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 429                 ring = priv->rx_ring[ring_ind];
 430
 431                 ring->prod = 0;
 432                 ring->cons = 0;
 433                 ring->actual_size = 0;
 434                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 435
 436                 ring->stride = stride;
 437                 if (ring->stride <= TXBB_SIZE)
 438                         ring->buf += TXBB_SIZE;
 439
 440                 ring->log_stride = ffs(ring->stride) - 1;
 441                 ring->buf_size = ring->size * ring->stride;
 442
 443                 memset(ring->buf, 0, ring->buf_size);
 444                 mlx4_en_update_rx_prod_db(ring);
 445
 446                 /* Initialize all descriptors */
 447                 for (i = 0; i < ring->size; i++)
 448                         mlx4_en_init_rx_desc(priv, ring, i);
 449
 450                 /* Initialize page allocators */
 451                 err = mlx4_en_init_allocator(priv, ring);
 452                 if (err) {
 453                         en_err(priv, "Failed initializing ring allocator\n");
 454                         if (ring->stride <= TXBB_SIZE)
 455                                 ring->buf -= TXBB_SIZE;
 456                         ring_ind--;
 457                         goto err_allocator;
 458                 }
 459         }
 460         err = mlx4_en_fill_rx_buffers(priv);
 461         if (err)
 462                 goto err_buffers;
 463
 464         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 465                 ring = priv->rx_ring[ring_ind];
 466
 467                 ring->size_mask = ring->actual_size - 1;
 468                 mlx4_en_update_rx_prod_db(ring);
 469         }
 470
 471         return 0;
 472
 473 err_buffers:
 474         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 475                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 476
 477         ring_ind = priv->rx_ring_num - 1;
 478 err_allocator:
 479         while (ring_ind >= 0) {
 480                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 481                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 482                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 483                 ring_ind--;
 484         }
 485         return err;
 486 }
 487
 488 /* We recover from out of memory by scheduling our napi poll
 489  * function (mlx4_en_process_cq), which tries to allocate
 490  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 491  */
 492 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 493 {
 494         int ring;
 495
 496         if (!priv->port_up)
 497                 return;
 498
 499         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 500                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 501                         napi_reschedule(&priv->rx_cq[ring]->napi);
 502         }
 503 }
 504
 505 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 506                              struct mlx4_en_rx_ring **pring,
 507                              u32 size, u16 stride)
 508 {
 509         struct mlx4_en_dev *mdev = priv->mdev;
 510         struct mlx4_en_rx_ring *ring = *pring;
 511
 512         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 513         vfree(ring->rx_info);
 514         ring->rx_info = NULL;
 515         kfree(ring);
 516         *pring = NULL;
 517 #ifdef CONFIG_RFS_ACCEL
 518         mlx4_en_cleanup_filters(priv);
 519 #endif
 520 }
 521
 522 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 523                                 struct mlx4_en_rx_ring *ring)
 524 {
 525         mlx4_en_free_rx_buf(priv, ring);
 526         if (ring->stride <= TXBB_SIZE)
 527                 ring->buf -= TXBB_SIZE;
 528         mlx4_en_destroy_allocator(priv, ring);
 529 }
 530
 531
 532 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 533                                     struct mlx4_en_rx_desc *rx_desc,
 534                                     struct mlx4_en_rx_alloc *frags,
 535                                     struct sk_buff *skb,
 536                                     int length)
 537 {
 538         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 539         struct mlx4_en_frag_info *frag_info;
 540         int nr;
 541         dma_addr_t dma;
 542
 543         /* Collect used fragments while replacing them in the HW descriptors */
 544         for (nr = 0; nr < priv->num_frags; nr++) {
 545                 frag_info = &priv->frag_info[nr];
 546                 if (length <= frag_info->frag_prefix_size)
 547                         break;
 548                 if (!frags[nr].page)
 549                         goto fail;
 550
 551                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 552                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 553                                         DMA_FROM_DEVICE);
 554
 555                 /* Save page reference in skb */
 556                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 557                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 558                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 559                 skb->truesize += frag_info->frag_stride;
 560                 frags[nr].page = NULL;
 561         }
 562         /* Adjust size of last fragment to match actual length */
 563         if (nr > 0)
 564                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 565                         length - priv->frag_info[nr - 1].frag_prefix_size);
 566         return nr;
 567
 568 fail:
 569         while (nr > 0) {
 570                 nr--;
 571                 __skb_frag_unref(&skb_frags_rx[nr]);
 572         }
 573         return 0;
 574 }
 575
 576
 577 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 578                                       struct mlx4_en_rx_desc *rx_desc,
 579                                       struct mlx4_en_rx_alloc *frags,
 580                                       unsigned int length)
 581 {
 582         struct sk_buff *skb;
 583         void *va;
 584         int used_frags;
 585         dma_addr_t dma;
 586
 587         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 588         if (!skb) {
 589                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 590                 return NULL;
 591         }
 592         skb_reserve(skb, NET_IP_ALIGN);
 593         skb->len = length;
 594
 595         /* Get pointer to first fragment so we could copy the headers into the
 596          * (linear part of the) skb */
 597         va = page_address(frags[0].page) + frags[0].page_offset;
 598
 599         if (length <= SMALL_PACKET_SIZE) {
 600                 /* We are copying all relevant data to the skb - temporarily
 601                  * sync buffers for the copy */
 602                 dma = be64_to_cpu(rx_desc->data[0].addr);
 603                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 604                                         DMA_FROM_DEVICE);
 605                 skb_copy_to_linear_data(skb, va, length);
 606                 skb->tail += length;
 607         } else {
 608                 unsigned int pull_len;
 609
 610                 /* Move relevant fragments to skb */
 611                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 612                                                         skb, length);
 613                 if (unlikely(!used_frags)) {
 614                         kfree_skb(skb);
 615                         return NULL;
 616                 }
 617                 skb_shinfo(skb)->nr_frags = used_frags;
 618
 619                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 620                 /* Copy headers into the skb linear buffer */
 621                 memcpy(skb->data, va, pull_len);
 622                 skb->tail += pull_len;
 623
 624                 /* Skip headers in first fragment */
 625                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 626
 627                 /* Adjust size of first fragment */
 628                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 629                 skb->data_len = length - pull_len;
 630         }
 631         return skb;
 632 }
 633
 634 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 635 {
 636         int i;
 637         int offset = ETH_HLEN;
 638
 639         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 640                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 641                         goto out_loopback;
 642         }
 643         /* Loopback found */
 644         priv->loopback_ok = 1;
 645
 646 out_loopback:
 647         dev_kfree_skb_any(skb);
 648 }
 649
 650 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 651                                      struct mlx4_en_rx_ring *ring)
 652 {
 653         int index = ring->prod & ring->size_mask;
 654
 655         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 656                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
 657                                             GFP_ATOMIC | __GFP_COLD))
 658                         break;
 659                 ring->prod++;
 660                 index = ring->prod & ring->size_mask;
 661         }
 662 }
 663
 664 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 665  * over it and add it to the hardware's checksum calculation
 666  */
 667 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 668                                          struct vlan_hdr *vlanh)
 669 {
 670         return csum_add(hw_checksum, *(__wsum *)vlanh);
 671 }
 672
 673 /* Although the stack expects checksum which doesn't include the pseudo
 674  * header, the HW adds it. To address that, we are subtracting the pseudo
 675  * header checksum from the checksum value provided by the HW.
 676  */
 677 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 678                                 struct iphdr *iph)
 679 {
 680         __u16 length_for_csum = 0;
 681         __wsum csum_pseudo_header = 0;
 682
 683         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 684         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 685                                                 length_for_csum, iph->protocol, 0);
 686         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 687 }
 688
 689 #if IS_ENABLED(CONFIG_IPV6)
 690 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 691  * we also compute/add the IP header checksum which
 692  * is not added by the HW.
 693  */
 694 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 695                                struct ipv6hdr *ipv6h)
 696 {
 697         __wsum csum_pseudo_hdr = 0;
 698
 699         if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
 700                 return -1;
 701         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 702
 703         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 704                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 705         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 706         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 707
 708         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 709         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 710         return 0;
 711 }
 712 #endif
 713 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 714                       netdev_features_t dev_features)
 715 {
 716         __wsum hw_checksum = 0;
 717
 718         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 719
 720         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 721
 722         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 723             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 724                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 725                 hdr += sizeof(struct vlan_hdr);
 726         }
 727
 728         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 729                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 730 #if IS_ENABLED(CONFIG_IPV6)
 731         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 732                 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
 733                         return -1;
 734 #endif
 735         return 0;
 736 }
 737
 738 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 739 {
 740         struct mlx4_en_priv *priv = netdev_priv(dev);
 741         struct mlx4_en_dev *mdev = priv->mdev;
 742         struct mlx4_cqe *cqe;
 743         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 744         struct mlx4_en_rx_alloc *frags;
 745         struct mlx4_en_rx_desc *rx_desc;
 746         struct sk_buff *skb;
 747         int index;
 748         int nr;
 749         unsigned int length;
 750         int polled = 0;
 751         int ip_summed;
 752         int factor = priv->cqe_factor;
 753         u64 timestamp;
 754         bool l2_tunnel;
 755
 756         if (!priv->port_up)
 757                 return 0;
 758
 759         if (budget <= 0)
 760                 return polled;
 761
 762         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 763          * descriptor offset can be deduced from the CQE index instead of
 764          * reading 'cqe->index' */
 765         index = cq->mcq.cons_index & ring->size_mask;
 766         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 767
 768         /* Process all completed CQEs */
 769         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 770                     cq->mcq.cons_index & cq->size)) {
 771
 772                 frags = ring->rx_info + (index << priv->log_rx_info);
 773                 rx_desc = ring->buf + (index << ring->log_stride);
 774
 775                 /*
 776                  * make sure we read the CQE after we read the ownership bit
 777                  */
 778                 dma_rmb();
 779
 780                 /* Drop packet on bad receive or bad checksum */
 781                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 782                                                 MLX4_CQE_OPCODE_ERROR)) {
 783                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 784                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 785                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 786                         goto next;
 787                 }
 788                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 789                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 790                         goto next;
 791                 }
 792
 793                 /* Check if we need to drop the packet if SRIOV is not enabled
 794                  * and not performing the selftest or flb disabled
 795                  */
 796                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 797                         struct ethhdr *ethh;
 798                         dma_addr_t dma;
 799                         /* Get pointer to first fragment since we haven't
 800                          * skb yet and cast it to ethhdr struct
 801                          */
 802                         dma = be64_to_cpu(rx_desc->data[0].addr);
 803                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 804                                                 DMA_FROM_DEVICE);
 805                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 806                                                  frags[0].page_offset);
 807
 808                         if (is_multicast_ether_addr(ethh->h_dest)) {
 809                                 struct mlx4_mac_entry *entry;
 810                                 struct hlist_head *bucket;
 811                                 unsigned int mac_hash;
 812
 813                                 /* Drop the packet, since HW loopback-ed it */
 814                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 815                                 bucket = &priv->mac_hash[mac_hash];
 816                                 rcu_read_lock();
 817                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 818                                         if (ether_addr_equal_64bits(entry->mac,
 819                                                                     ethh->h_source)) {
 820                                                 rcu_read_unlock();
 821                                                 goto next;
 822                                         }
 823                                 }
 824                                 rcu_read_unlock();
 825                         }
 826                 }
 827
 828                 /*
 829                  * Packet is OK - process it.
 830                  */
 831                 length = be32_to_cpu(cqe->byte_cnt);
 832                 length -= ring->fcs_del;
 833                 ring->bytes += length;
 834                 ring->packets++;
 835                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 836                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 837
 838                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 839                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 840                                                       MLX4_CQE_STATUS_UDP)) {
 841                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 842                                     cqe->checksum == cpu_to_be16(0xffff)) {
 843                                         ip_summed = CHECKSUM_UNNECESSARY;
 844                                         ring->csum_ok++;
 845                                 } else {
 846                                         ip_summed = CHECKSUM_NONE;
 847                                         ring->csum_none++;
 848                                 }
 849                         } else {
 850                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 851                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 852                                                                MLX4_CQE_STATUS_IPV6))) {
 853                                         ip_summed = CHECKSUM_COMPLETE;
 854                                         ring->csum_complete++;
 855                                 } else {
 856                                         ip_summed = CHECKSUM_NONE;
 857                                         ring->csum_none++;
 858                                 }
 859                         }
 860                 } else {
 861                         ip_summed = CHECKSUM_NONE;
 862                         ring->csum_none++;
 863                 }
 864
 865                 /* This packet is eligible for GRO if it is:
 866                  * - DIX Ethernet (type interpretation)
 867                  * - TCP/IP (v4)
 868                  * - without IP options
 869                  * - not an IP fragment
 870                  */
 871                 if (dev->features & NETIF_F_GRO) {
 872                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 873                         if (!gro_skb)
 874                                 goto next;
 875
 876                         nr = mlx4_en_complete_rx_desc(priv,
 877                                 rx_desc, frags, gro_skb,
 878                                 length);
 879                         if (!nr)
 880                                 goto next;
 881
 882                         if (ip_summed == CHECKSUM_COMPLETE) {
 883                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 884                                 if (check_csum(cqe, gro_skb, va,
 885                                                dev->features)) {
 886                                         ip_summed = CHECKSUM_NONE;
 887                                         ring->csum_none++;
 888                                         ring->csum_complete--;
 889                                 }
 890                         }
 891
 892                         skb_shinfo(gro_skb)->nr_frags = nr;
 893                         gro_skb->len = length;
 894                         gro_skb->data_len = length;
 895                         gro_skb->ip_summed = ip_summed;
 896
 897                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 898                                 gro_skb->csum_level = 1;
 899
 900                         if ((cqe->vlan_my_qpn &
 901                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 902                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 903                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 904
 905                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 906                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 907                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
 908                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
 909                                 __vlan_hwaccel_put_tag(gro_skb,
 910                                                        htons(ETH_P_8021AD),
 911                                                        be16_to_cpu(cqe->sl_vid));
 912                         }
 913
 914                         if (dev->features & NETIF_F_RXHASH)
 915                                 skb_set_hash(gro_skb,
 916                                              be32_to_cpu(cqe->immed_rss_invalid),
 917                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
 918                                                 PKT_HASH_TYPE_L4 :
 919                                                 PKT_HASH_TYPE_L3);
 920
 921                         skb_record_rx_queue(gro_skb, cq->ring);
 922
 923                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 924                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 925                                 mlx4_en_fill_hwtstamps(mdev,
 926                                                        skb_hwtstamps(gro_skb),
 927                                                        timestamp);
 928                         }
 929
 930                         napi_gro_frags(&cq->napi);
 931                         goto next;
 932                 }
 933
 934                 /* GRO not possible, complete processing here */
 935                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 936                 if (!skb) {
 937                         ring->dropped++;
 938                         goto next;
 939                 }
 940
 941                 if (unlikely(priv->validate_loopback)) {
 942                         validate_loopback(priv, skb);
 943                         goto next;
 944                 }
 945
 946                 if (ip_summed == CHECKSUM_COMPLETE) {
 947                         if (check_csum(cqe, skb, skb->data, dev->features)) {
 948                                 ip_summed = CHECKSUM_NONE;
 949                                 ring->csum_complete--;
 950                                 ring->csum_none++;
 951                         }
 952                 }
 953
 954                 skb->ip_summed = ip_summed;
 955                 skb->protocol = eth_type_trans(skb, dev);
 956                 skb_record_rx_queue(skb, cq->ring);
 957
 958                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 959                         skb->csum_level = 1;
 960
 961                 if (dev->features & NETIF_F_RXHASH)
 962                         skb_set_hash(skb,
 963                                      be32_to_cpu(cqe->immed_rss_invalid),
 964                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
 965                                         PKT_HASH_TYPE_L4 :
 966                                         PKT_HASH_TYPE_L3);
 967
 968                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 969                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
 970                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 971                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 972                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 973                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
 974                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
 975                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
 976                                                be16_to_cpu(cqe->sl_vid));
 977
 978                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 979                         timestamp = mlx4_en_get_cqe_ts(cqe);
 980                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 981                                                timestamp);
 982                 }
 983
 984                 napi_gro_receive(&cq->napi, skb);
 985 next:
 986                 for (nr = 0; nr < priv->num_frags; nr++)
 987                         mlx4_en_free_frag(priv, frags, nr);
 988
 989                 ++cq->mcq.cons_index;
 990                 index = (cq->mcq.cons_index) & ring->size_mask;
 991                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 992                 if (++polled == budget)
 993                         goto out;
 994         }
 995
 996 out:
 997         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 998         mlx4_cq_set_ci(&cq->mcq);
 999         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1000         ring->cons = cq->mcq.cons_index;
1001         mlx4_en_refill_rx_buffers(priv, ring);
1002         mlx4_en_update_rx_prod_db(ring);
1003         return polled;
1004 }
1005
1006
1007 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1008 {
1009         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1010         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1011
1012         if (likely(priv->port_up))
1013                 napi_schedule_irqoff(&cq->napi);
1014         else
1015                 mlx4_en_arm_cq(priv, cq);
1016 }
1017
1018 /* Rx CQ polling - called by NAPI */
1019 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1020 {
1021         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1022         struct net_device *dev = cq->dev;
1023         struct mlx4_en_priv *priv = netdev_priv(dev);
1024         int done;
1025
1026         done = mlx4_en_process_rx_cq(dev, cq, budget);
1027
1028         /* If we used up all the quota - we're probably not done yet... */
1029         if (done == budget) {
1030                 const struct cpumask *aff;
1031                 struct irq_data *idata;
1032                 int cpu_curr;
1033
1034                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1035
1036                 cpu_curr = smp_processor_id();
1037                 idata = irq_desc_get_irq_data(cq->irq_desc);
1038                 aff = irq_data_get_affinity_mask(idata);
1039
1040                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1041                         return budget;
1042
1043                 /* Current cpu is not according to smp_irq_affinity -
1044                  * probably affinity changed. need to stop this NAPI
1045                  * poll, and restart it on the right CPU
1046                  */
1047                 done = 0;
1048         }
1049         /* Done for now */
1050         napi_complete_done(napi, done);
1051         mlx4_en_arm_cq(priv, cq);
1052         return done;
1053 }
1054
1055 static const int frag_sizes[] = {
1056         FRAG_SZ0,
1057         FRAG_SZ1,
1058         FRAG_SZ2,
1059         FRAG_SZ3
1060 };
1061
1062 void mlx4_en_calc_rx_buf(struct net_device *dev)
1063 {
1064         struct mlx4_en_priv *priv = netdev_priv(dev);
1065         /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1066          * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1067          */
1068         int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1069         int buf_size = 0;
1070         int i = 0;
1071
1072         while (buf_size < eff_mtu) {
1073                 priv->frag_info[i].frag_size =
1074                         (eff_mtu > buf_size + frag_sizes[i]) ?
1075                                 frag_sizes[i] : eff_mtu - buf_size;
1076                 priv->frag_info[i].frag_prefix_size = buf_size;
1077                 priv->frag_info[i].frag_stride =
1078                                 ALIGN(priv->frag_info[i].frag_size,
1079                                       SMP_CACHE_BYTES);
1080                 buf_size += priv->frag_info[i].frag_size;
1081                 i++;
1082         }
1083
1084         priv->num_frags = i;
1085         priv->rx_skb_size = eff_mtu;
1086         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1087
1088         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1089                eff_mtu, priv->num_frags);
1090         for (i = 0; i < priv->num_frags; i++) {
1091                 en_err(priv,
1092                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1093                        i,
1094                        priv->frag_info[i].frag_size,
1095                        priv->frag_info[i].frag_prefix_size,
1096                        priv->frag_info[i].frag_stride);
1097         }
1098 }
1099
1100 /* RSS related functions */
1101
1102 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1103                                  struct mlx4_en_rx_ring *ring,
1104                                  enum mlx4_qp_state *state,
1105                                  struct mlx4_qp *qp)
1106 {
1107         struct mlx4_en_dev *mdev = priv->mdev;
1108         struct mlx4_qp_context *context;
1109         int err = 0;
1110
1111         context = kmalloc(sizeof(*context), GFP_KERNEL);
1112         if (!context)
1113                 return -ENOMEM;
1114
1115         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1116         if (err) {
1117                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1118                 goto out;
1119         }
1120         qp->event = mlx4_en_sqp_event;
1121
1122         memset(context, 0, sizeof *context);
1123         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1124                                 qpn, ring->cqn, -1, context);
1125         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1126
1127         /* Cancel FCS removal if FW allows */
1128         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1129                 context->param3 |= cpu_to_be32(1 << 29);
1130                 if (priv->dev->features & NETIF_F_RXFCS)
1131                         ring->fcs_del = 0;
1132                 else
1133                         ring->fcs_del = ETH_FCS_LEN;
1134         } else
1135                 ring->fcs_del = 0;
1136
1137         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1138         if (err) {
1139                 mlx4_qp_remove(mdev->dev, qp);
1140                 mlx4_qp_free(mdev->dev, qp);
1141         }
1142         mlx4_en_update_rx_prod_db(ring);
1143 out:
1144         kfree(context);
1145         return err;
1146 }
1147
1148 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1149 {
1150         int err;
1151         u32 qpn;
1152
1153         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1154                                     MLX4_RESERVE_A0_QP);
1155         if (err) {
1156                 en_err(priv, "Failed reserving drop qpn\n");
1157                 return err;
1158         }
1159         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1160         if (err) {
1161                 en_err(priv, "Failed allocating drop qp\n");
1162                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1163                 return err;
1164         }
1165
1166         return 0;
1167 }
1168
1169 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1170 {
1171         u32 qpn;
1172
1173         qpn = priv->drop_qp.qpn;
1174         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1175         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1176         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1177 }
1178
1179 /* Allocate rx qp's and configure them according to rss map */
1180 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1181 {
1182         struct mlx4_en_dev *mdev = priv->mdev;
1183         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1184         struct mlx4_qp_context context;
1185         struct mlx4_rss_context *rss_context;
1186         int rss_rings;
1187         void *ptr;
1188         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1189                         MLX4_RSS_TCP_IPV6);
1190         int i, qpn;
1191         int err = 0;
1192         int good_qps = 0;
1193
1194         en_dbg(DRV, priv, "Configuring rss steering\n");
1195         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1196                                     priv->rx_ring_num,
1197                                     &rss_map->base_qpn, 0);
1198         if (err) {
1199                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1200                 return err;
1201         }
1202
1203         for (i = 0; i < priv->rx_ring_num; i++) {
1204                 qpn = rss_map->base_qpn + i;
1205                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1206                                             &rss_map->state[i],
1207                                             &rss_map->qps[i]);
1208                 if (err)
1209                         goto rss_err;
1210
1211                 ++good_qps;
1212         }
1213
1214         /* Configure RSS indirection qp */
1215         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1216         if (err) {
1217                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1218                 goto rss_err;
1219         }
1220         rss_map->indir_qp.event = mlx4_en_sqp_event;
1221         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1222                                 priv->rx_ring[0]->cqn, -1, &context);
1223
1224         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1225                 rss_rings = priv->rx_ring_num;
1226         else
1227                 rss_rings = priv->prof->rss_rings;
1228
1229         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1230                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1231         rss_context = ptr;
1232         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1233                                             (rss_map->base_qpn));
1234         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1235         if (priv->mdev->profile.udp_rss) {
1236                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1237                 rss_context->base_qpn_udp = rss_context->default_qpn;
1238         }
1239
1240         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1241                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1242                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1243         }
1244
1245         rss_context->flags = rss_mask;
1246         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1247         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1248                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1249         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1250                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1251                 memcpy(rss_context->rss_key, priv->rss_key,
1252                        MLX4_EN_RSS_KEY_SIZE);
1253         } else {
1254                 en_err(priv, "Unknown RSS hash function requested\n");
1255                 err = -EINVAL;
1256                 goto indir_err;
1257         }
1258         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1259                                &rss_map->indir_qp, &rss_map->indir_state);
1260         if (err)
1261                 goto indir_err;
1262
1263         return 0;
1264
1265 indir_err:
1266         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1267                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1268         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1269         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1270 rss_err:
1271         for (i = 0; i < good_qps; i++) {
1272                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1273                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1274                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1275                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1276         }
1277         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1278         return err;
1279 }
1280
1281 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1282 {
1283         struct mlx4_en_dev *mdev = priv->mdev;
1284         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1285         int i;
1286
1287         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1288                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1289         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1290         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1291
1292         for (i = 0; i < priv->rx_ring_num; i++) {
1293                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1294                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1295                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1296                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1297         }
1298         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1299 }