drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/irq.h>
  44
  45 #if IS_ENABLED(CONFIG_IPV6)
  46 #include <net/ip6_checksum.h>
  47 #endif
  48
  49 #include "mlx4_en.h"
  50
  51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  52                             struct mlx4_en_rx_alloc *page_alloc,
  53                             const struct mlx4_en_frag_info *frag_info,
  54                             gfp_t _gfp)
  55 {
  56         int order;
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  61                 gfp_t gfp = _gfp;
  62
  63                 if (order)
  64                         gfp |= __GFP_COMP | __GFP_NOWARN;
  65                 page = alloc_pages(gfp, order);
  66                 if (likely(page))
  67                         break;
  68                 if (--order < 0 ||
  69                     ((PAGE_SIZE << order) < frag_info->frag_size))
  70                         return -ENOMEM;
  71         }
  72         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  73                            PCI_DMA_FROMDEVICE);
  74         if (dma_mapping_error(priv->ddev, dma)) {
  75                 put_page(page);
  76                 return -ENOMEM;
  77         }
  78         page_alloc->page_size = PAGE_SIZE << order;
  79         page_alloc->page = page;
  80         page_alloc->dma = dma;
  81         page_alloc->page_offset = 0;
  82         /* Not doing get_page() for each frag is a big win
  83          * on asymetric workloads. Note we can not use atomic_set().
  84          */
  85         atomic_add(page_alloc->page_size / frag_info->frag_stride - 1,
  86                    &page->_count);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         dma_addr_t dma;
 100         int i;
 101
 102         for (i = 0; i < priv->num_frags; i++) {
 103                 frag_info = &priv->frag_info[i];
 104                 page_alloc[i] = ring_alloc[i];
 105                 page_alloc[i].page_offset += frag_info->frag_stride;
 106
 107                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 108                     ring_alloc[i].page_size)
 109                         continue;
 110
 111                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
 112                         goto out;
 113         }
 114
 115         for (i = 0; i < priv->num_frags; i++) {
 116                 frags[i] = ring_alloc[i];
 117                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 118                 ring_alloc[i] = page_alloc[i];
 119                 rx_desc->data[i].addr = cpu_to_be64(dma);
 120         }
 121
 122         return 0;
 123
 124 out:
 125         while (i--) {
 126                 if (page_alloc[i].page != ring_alloc[i].page) {
 127                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 128                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
 129                         page = page_alloc[i].page;
 130                         atomic_set(&page->_count, 1);
 131                         put_page(page);
 132                 }
 133         }
 134         return -ENOMEM;
 135 }
 136
 137 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 138                               struct mlx4_en_rx_alloc *frags,
 139                               int i)
 140 {
 141         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 142         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 143
 144
 145         if (next_frag_end > frags[i].page_size)
 146                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 147                                PCI_DMA_FROMDEVICE);
 148
 149         if (frags[i].page)
 150                 put_page(frags[i].page);
 151 }
 152
 153 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 154                                   struct mlx4_en_rx_ring *ring)
 155 {
 156         int i;
 157         struct mlx4_en_rx_alloc *page_alloc;
 158
 159         for (i = 0; i < priv->num_frags; i++) {
 160                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 161
 162                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 163                                      frag_info, GFP_KERNEL | __GFP_COLD))
 164                         goto out;
 165         }
 166         return 0;
 167
 168 out:
 169         while (i--) {
 170                 struct page *page;
 171
 172                 page_alloc = &ring->page_alloc[i];
 173                 dma_unmap_page(priv->ddev, page_alloc->dma,
 174                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
 175                 page = page_alloc->page;
 176                 atomic_set(&page->_count, 1);
 177                 put_page(page);
 178                 page_alloc->page = NULL;
 179         }
 180         return -ENOMEM;
 181 }
 182
 183 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 184                                       struct mlx4_en_rx_ring *ring)
 185 {
 186         struct mlx4_en_rx_alloc *page_alloc;
 187         int i;
 188
 189         for (i = 0; i < priv->num_frags; i++) {
 190                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 191
 192                 page_alloc = &ring->page_alloc[i];
 193                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 194                        i, page_count(page_alloc->page));
 195
 196                 dma_unmap_page(priv->ddev, page_alloc->dma,
 197                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
 198                 while (page_alloc->page_offset + frag_info->frag_stride <
 199                        page_alloc->page_size) {
 200                         put_page(page_alloc->page);
 201                         page_alloc->page_offset += frag_info->frag_stride;
 202                 }
 203                 page_alloc->page = NULL;
 204         }
 205 }
 206
 207 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 208                                  struct mlx4_en_rx_ring *ring, int index)
 209 {
 210         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 211         int possible_frags;
 212         int i;
 213
 214         /* Set size and memtype fields */
 215         for (i = 0; i < priv->num_frags; i++) {
 216                 rx_desc->data[i].byte_count =
 217                         cpu_to_be32(priv->frag_info[i].frag_size);
 218                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 219         }
 220
 221         /* If the number of used fragments does not fill up the ring stride,
 222          * remaining (unused) fragments must be padded with null address/size
 223          * and a special memory key */
 224         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 225         for (i = priv->num_frags; i < possible_frags; i++) {
 226                 rx_desc->data[i].byte_count = 0;
 227                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 228                 rx_desc->data[i].addr = 0;
 229         }
 230 }
 231
 232 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 233                                    struct mlx4_en_rx_ring *ring, int index,
 234                                    gfp_t gfp)
 235 {
 236         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 237         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 238                                         (index << priv->log_rx_info);
 239
 240         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 241 }
 242
 243 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 244 {
 245         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 246 }
 247
 248 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 249                                  struct mlx4_en_rx_ring *ring,
 250                                  int index)
 251 {
 252         struct mlx4_en_rx_alloc *frags;
 253         int nr;
 254
 255         frags = ring->rx_info + (index << priv->log_rx_info);
 256         for (nr = 0; nr < priv->num_frags; nr++) {
 257                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 258                 mlx4_en_free_frag(priv, frags, nr);
 259         }
 260 }
 261
 262 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 263 {
 264         struct mlx4_en_rx_ring *ring;
 265         int ring_ind;
 266         int buf_ind;
 267         int new_size;
 268
 269         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 270                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 271                         ring = priv->rx_ring[ring_ind];
 272
 273                         if (mlx4_en_prepare_rx_desc(priv, ring,
 274                                                     ring->actual_size,
 275                                                     GFP_KERNEL | __GFP_COLD)) {
 276                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 277                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 278                                         return -ENOMEM;
 279                                 } else {
 280                                         new_size = rounddown_pow_of_two(ring->actual_size);
 281                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 282                                                 ring->actual_size, new_size);
 283                                         goto reduce_rings;
 284                                 }
 285                         }
 286                         ring->actual_size++;
 287                         ring->prod++;
 288                 }
 289         }
 290         return 0;
 291
 292 reduce_rings:
 293         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 294                 ring = priv->rx_ring[ring_ind];
 295                 while (ring->actual_size > new_size) {
 296                         ring->actual_size--;
 297                         ring->prod--;
 298                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304
 305 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 306                                 struct mlx4_en_rx_ring *ring)
 307 {
 308         int index;
 309
 310         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 311                ring->cons, ring->prod);
 312
 313         /* Unmap and free Rx buffers */
 314         BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
 315         while (ring->cons != ring->prod) {
 316                 index = ring->cons & ring->size_mask;
 317                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 318                 mlx4_en_free_rx_desc(priv, ring, index);
 319                 ++ring->cons;
 320         }
 321 }
 322
 323 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 324 {
 325         int i;
 326         int num_of_eqs;
 327         int num_rx_rings;
 328         struct mlx4_dev *dev = mdev->dev;
 329
 330         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 331                 if (!dev->caps.comp_pool)
 332                         num_of_eqs = max_t(int, MIN_RX_RINGS,
 333                                            min_t(int,
 334                                                  dev->caps.num_comp_vectors,
 335                                                  DEF_RX_RINGS));
 336                 else
 337                         num_of_eqs = min_t(int, MAX_MSIX_P_PORT,
 338                                            dev->caps.comp_pool/
 339                                            dev->caps.num_ports) - 1;
 340
 341                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 342                         min_t(int, num_of_eqs,
 343                               netif_get_num_default_rss_queues());
 344                 mdev->profile.prof[i].rx_ring_num =
 345                         rounddown_pow_of_two(num_rx_rings);
 346         }
 347 }
 348
 349 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 350                            struct mlx4_en_rx_ring **pring,
 351                            u32 size, u16 stride, int node)
 352 {
 353         struct mlx4_en_dev *mdev = priv->mdev;
 354         struct mlx4_en_rx_ring *ring;
 355         int err = -ENOMEM;
 356         int tmp;
 357
 358         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 359         if (!ring) {
 360                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 361                 if (!ring) {
 362                         en_err(priv, "Failed to allocate RX ring structure\n");
 363                         return -ENOMEM;
 364                 }
 365         }
 366
 367         ring->prod = 0;
 368         ring->cons = 0;
 369         ring->size = size;
 370         ring->size_mask = size - 1;
 371         ring->stride = stride;
 372         ring->log_stride = ffs(ring->stride) - 1;
 373         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 374
 375         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 376                                         sizeof(struct mlx4_en_rx_alloc));
 377         ring->rx_info = vmalloc_node(tmp, node);
 378         if (!ring->rx_info) {
 379                 ring->rx_info = vmalloc(tmp);
 380                 if (!ring->rx_info) {
 381                         err = -ENOMEM;
 382                         goto err_ring;
 383                 }
 384         }
 385
 386         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 387                  ring->rx_info, tmp);
 388
 389         /* Allocate HW buffers on provided NUMA node */
 390         set_dev_node(&mdev->dev->pdev->dev, node);
 391         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 392                                  ring->buf_size, 2 * PAGE_SIZE);
 393         set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
 394         if (err)
 395                 goto err_info;
 396
 397         err = mlx4_en_map_buffer(&ring->wqres.buf);
 398         if (err) {
 399                 en_err(priv, "Failed to map RX buffer\n");
 400                 goto err_hwq;
 401         }
 402         ring->buf = ring->wqres.buf.direct.buf;
 403
 404         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 405
 406         *pring = ring;
 407         return 0;
 408
 409 err_hwq:
 410         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 411 err_info:
 412         vfree(ring->rx_info);
 413         ring->rx_info = NULL;
 414 err_ring:
 415         kfree(ring);
 416         *pring = NULL;
 417
 418         return err;
 419 }
 420
 421 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 422 {
 423         struct mlx4_en_rx_ring *ring;
 424         int i;
 425         int ring_ind;
 426         int err;
 427         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 428                                         DS_SIZE * priv->num_frags);
 429
 430         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 431                 ring = priv->rx_ring[ring_ind];
 432
 433                 ring->prod = 0;
 434                 ring->cons = 0;
 435                 ring->actual_size = 0;
 436                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 437
 438                 ring->stride = stride;
 439                 if (ring->stride <= TXBB_SIZE)
 440                         ring->buf += TXBB_SIZE;
 441
 442                 ring->log_stride = ffs(ring->stride) - 1;
 443                 ring->buf_size = ring->size * ring->stride;
 444
 445                 memset(ring->buf, 0, ring->buf_size);
 446                 mlx4_en_update_rx_prod_db(ring);
 447
 448                 /* Initialize all descriptors */
 449                 for (i = 0; i < ring->size; i++)
 450                         mlx4_en_init_rx_desc(priv, ring, i);
 451
 452                 /* Initialize page allocators */
 453                 err = mlx4_en_init_allocator(priv, ring);
 454                 if (err) {
 455                         en_err(priv, "Failed initializing ring allocator\n");
 456                         if (ring->stride <= TXBB_SIZE)
 457                                 ring->buf -= TXBB_SIZE;
 458                         ring_ind--;
 459                         goto err_allocator;
 460                 }
 461         }
 462         err = mlx4_en_fill_rx_buffers(priv);
 463         if (err)
 464                 goto err_buffers;
 465
 466         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 467                 ring = priv->rx_ring[ring_ind];
 468
 469                 ring->size_mask = ring->actual_size - 1;
 470                 mlx4_en_update_rx_prod_db(ring);
 471         }
 472
 473         return 0;
 474
 475 err_buffers:
 476         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 477                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 478
 479         ring_ind = priv->rx_ring_num - 1;
 480 err_allocator:
 481         while (ring_ind >= 0) {
 482                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 483                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 484                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 485                 ring_ind--;
 486         }
 487         return err;
 488 }
 489
 490 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 491                              struct mlx4_en_rx_ring **pring,
 492                              u32 size, u16 stride)
 493 {
 494         struct mlx4_en_dev *mdev = priv->mdev;
 495         struct mlx4_en_rx_ring *ring = *pring;
 496
 497         mlx4_en_unmap_buffer(&ring->wqres.buf);
 498         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 499         vfree(ring->rx_info);
 500         ring->rx_info = NULL;
 501         kfree(ring);
 502         *pring = NULL;
 503 #ifdef CONFIG_RFS_ACCEL
 504         mlx4_en_cleanup_filters(priv);
 505 #endif
 506 }
 507
 508 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 509                                 struct mlx4_en_rx_ring *ring)
 510 {
 511         mlx4_en_free_rx_buf(priv, ring);
 512         if (ring->stride <= TXBB_SIZE)
 513                 ring->buf -= TXBB_SIZE;
 514         mlx4_en_destroy_allocator(priv, ring);
 515 }
 516
 517
 518 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 519                                     struct mlx4_en_rx_desc *rx_desc,
 520                                     struct mlx4_en_rx_alloc *frags,
 521                                     struct sk_buff *skb,
 522                                     int length)
 523 {
 524         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 525         struct mlx4_en_frag_info *frag_info;
 526         int nr;
 527         dma_addr_t dma;
 528
 529         /* Collect used fragments while replacing them in the HW descriptors */
 530         for (nr = 0; nr < priv->num_frags; nr++) {
 531                 frag_info = &priv->frag_info[nr];
 532                 if (length <= frag_info->frag_prefix_size)
 533                         break;
 534                 if (!frags[nr].page)
 535                         goto fail;
 536
 537                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 538                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 539                                         DMA_FROM_DEVICE);
 540
 541                 /* Save page reference in skb */
 542                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 543                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 544                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 545                 skb->truesize += frag_info->frag_stride;
 546                 frags[nr].page = NULL;
 547         }
 548         /* Adjust size of last fragment to match actual length */
 549         if (nr > 0)
 550                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 551                         length - priv->frag_info[nr - 1].frag_prefix_size);
 552         return nr;
 553
 554 fail:
 555         while (nr > 0) {
 556                 nr--;
 557                 __skb_frag_unref(&skb_frags_rx[nr]);
 558         }
 559         return 0;
 560 }
 561
 562
 563 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 564                                       struct mlx4_en_rx_desc *rx_desc,
 565                                       struct mlx4_en_rx_alloc *frags,
 566                                       unsigned int length)
 567 {
 568         struct sk_buff *skb;
 569         void *va;
 570         int used_frags;
 571         dma_addr_t dma;
 572
 573         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 574         if (!skb) {
 575                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 576                 return NULL;
 577         }
 578         skb_reserve(skb, NET_IP_ALIGN);
 579         skb->len = length;
 580
 581         /* Get pointer to first fragment so we could copy the headers into the
 582          * (linear part of the) skb */
 583         va = page_address(frags[0].page) + frags[0].page_offset;
 584
 585         if (length <= SMALL_PACKET_SIZE) {
 586                 /* We are copying all relevant data to the skb - temporarily
 587                  * sync buffers for the copy */
 588                 dma = be64_to_cpu(rx_desc->data[0].addr);
 589                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 590                                         DMA_FROM_DEVICE);
 591                 skb_copy_to_linear_data(skb, va, length);
 592                 skb->tail += length;
 593         } else {
 594                 unsigned int pull_len;
 595
 596                 /* Move relevant fragments to skb */
 597                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 598                                                         skb, length);
 599                 if (unlikely(!used_frags)) {
 600                         kfree_skb(skb);
 601                         return NULL;
 602                 }
 603                 skb_shinfo(skb)->nr_frags = used_frags;
 604
 605                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 606                 /* Copy headers into the skb linear buffer */
 607                 memcpy(skb->data, va, pull_len);
 608                 skb->tail += pull_len;
 609
 610                 /* Skip headers in first fragment */
 611                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 612
 613                 /* Adjust size of first fragment */
 614                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 615                 skb->data_len = length - pull_len;
 616         }
 617         return skb;
 618 }
 619
 620 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 621 {
 622         int i;
 623         int offset = ETH_HLEN;
 624
 625         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 626                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 627                         goto out_loopback;
 628         }
 629         /* Loopback found */
 630         priv->loopback_ok = 1;
 631
 632 out_loopback:
 633         dev_kfree_skb_any(skb);
 634 }
 635
 636 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 637                                      struct mlx4_en_rx_ring *ring)
 638 {
 639         int index = ring->prod & ring->size_mask;
 640
 641         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 642                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
 643                                             GFP_ATOMIC | __GFP_COLD))
 644                         break;
 645                 ring->prod++;
 646                 index = ring->prod & ring->size_mask;
 647         }
 648 }
 649
 650 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 651  * over it and add it to the hardware's checksum calculation
 652  */
 653 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 654                                          struct vlan_hdr *vlanh)
 655 {
 656         return csum_add(hw_checksum, *(__wsum *)vlanh);
 657 }
 658
 659 /* Although the stack expects checksum which doesn't include the pseudo
 660  * header, the HW adds it. To address that, we are subtracting the pseudo
 661  * header checksum from the checksum value provided by the HW.
 662  */
 663 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 664                                 struct iphdr *iph)
 665 {
 666         __u16 length_for_csum = 0;
 667         __wsum csum_pseudo_header = 0;
 668
 669         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 670         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 671                                                 length_for_csum, iph->protocol, 0);
 672         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 673 }
 674
 675 #if IS_ENABLED(CONFIG_IPV6)
 676 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 677  * we also compute/add the IP header checksum which
 678  * is not added by the HW.
 679  */
 680 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 681                                struct ipv6hdr *ipv6h)
 682 {
 683         __wsum csum_pseudo_hdr = 0;
 684
 685         if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
 686                 return -1;
 687         hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8));
 688
 689         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 690                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 691         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 692         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 693
 694         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 695         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 696         return 0;
 697 }
 698 #endif
 699 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 700                       int hwtstamp_rx_filter)
 701 {
 702         __wsum hw_checksum = 0;
 703
 704         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 705
 706         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 707
 708         if (((struct ethhdr *)va)->h_proto == htons(ETH_P_8021Q) &&
 709             hwtstamp_rx_filter != HWTSTAMP_FILTER_NONE) {
 710                 /* next protocol non IPv4 or IPv6 */
 711                 if (((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto
 712                     != htons(ETH_P_IP) &&
 713                     ((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto
 714                     != htons(ETH_P_IPV6))
 715                         return -1;
 716                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 717                 hdr += sizeof(struct vlan_hdr);
 718         }
 719
 720         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 721                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 722 #if IS_ENABLED(CONFIG_IPV6)
 723         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 724                 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
 725                         return -1;
 726 #endif
 727         return 0;
 728 }
 729
 730 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 731 {
 732         struct mlx4_en_priv *priv = netdev_priv(dev);
 733         struct mlx4_en_dev *mdev = priv->mdev;
 734         struct mlx4_cqe *cqe;
 735         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 736         struct mlx4_en_rx_alloc *frags;
 737         struct mlx4_en_rx_desc *rx_desc;
 738         struct sk_buff *skb;
 739         int index;
 740         int nr;
 741         unsigned int length;
 742         int polled = 0;
 743         int ip_summed;
 744         int factor = priv->cqe_factor;
 745         u64 timestamp;
 746         bool l2_tunnel;
 747
 748         if (!priv->port_up)
 749                 return 0;
 750
 751         if (budget <= 0)
 752                 return polled;
 753
 754         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 755          * descriptor offset can be deduced from the CQE index instead of
 756          * reading 'cqe->index' */
 757         index = cq->mcq.cons_index & ring->size_mask;
 758         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 759
 760         /* Process all completed CQEs */
 761         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 762                     cq->mcq.cons_index & cq->size)) {
 763
 764                 frags = ring->rx_info + (index << priv->log_rx_info);
 765                 rx_desc = ring->buf + (index << ring->log_stride);
 766
 767                 /*
 768                  * make sure we read the CQE after we read the ownership bit
 769                  */
 770                 rmb();
 771
 772                 /* Drop packet on bad receive or bad checksum */
 773                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 774                                                 MLX4_CQE_OPCODE_ERROR)) {
 775                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 776                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 777                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 778                         goto next;
 779                 }
 780                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 781                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 782                         goto next;
 783                 }
 784
 785                 /* Check if we need to drop the packet if SRIOV is not enabled
 786                  * and not performing the selftest or flb disabled
 787                  */
 788                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 789                         struct ethhdr *ethh;
 790                         dma_addr_t dma;
 791                         /* Get pointer to first fragment since we haven't
 792                          * skb yet and cast it to ethhdr struct
 793                          */
 794                         dma = be64_to_cpu(rx_desc->data[0].addr);
 795                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 796                                                 DMA_FROM_DEVICE);
 797                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 798                                                  frags[0].page_offset);
 799
 800                         if (is_multicast_ether_addr(ethh->h_dest)) {
 801                                 struct mlx4_mac_entry *entry;
 802                                 struct hlist_head *bucket;
 803                                 unsigned int mac_hash;
 804
 805                                 /* Drop the packet, since HW loopback-ed it */
 806                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 807                                 bucket = &priv->mac_hash[mac_hash];
 808                                 rcu_read_lock();
 809                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 810                                         if (ether_addr_equal_64bits(entry->mac,
 811                                                                     ethh->h_source)) {
 812                                                 rcu_read_unlock();
 813                                                 goto next;
 814                                         }
 815                                 }
 816                                 rcu_read_unlock();
 817                         }
 818                 }
 819
 820                 /*
 821                  * Packet is OK - process it.
 822                  */
 823                 length = be32_to_cpu(cqe->byte_cnt);
 824                 length -= ring->fcs_del;
 825                 ring->bytes += length;
 826                 ring->packets++;
 827                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 828                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 829
 830                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 831                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 832                                                       MLX4_CQE_STATUS_UDP)) {
 833                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 834                                     cqe->checksum == cpu_to_be16(0xffff)) {
 835                                         ip_summed = CHECKSUM_UNNECESSARY;
 836                                         ring->csum_ok++;
 837                                 } else {
 838                                         ip_summed = CHECKSUM_NONE;
 839                                         ring->csum_none++;
 840                                 }
 841                         } else {
 842                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 843                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 844                                                                MLX4_CQE_STATUS_IPV6))) {
 845                                         ip_summed = CHECKSUM_COMPLETE;
 846                                         ring->csum_complete++;
 847                                 } else {
 848                                         ip_summed = CHECKSUM_NONE;
 849                                         ring->csum_none++;
 850                                 }
 851                         }
 852                 } else {
 853                         ip_summed = CHECKSUM_NONE;
 854                         ring->csum_none++;
 855                 }
 856
 857                 /* This packet is eligible for GRO if it is:
 858                  * - DIX Ethernet (type interpretation)
 859                  * - TCP/IP (v4)
 860                  * - without IP options
 861                  * - not an IP fragment
 862                  * - no LLS polling in progress
 863                  */
 864                 if (!mlx4_en_cq_busy_polling(cq) &&
 865                     (dev->features & NETIF_F_GRO)) {
 866                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 867                         if (!gro_skb)
 868                                 goto next;
 869
 870                         nr = mlx4_en_complete_rx_desc(priv,
 871                                 rx_desc, frags, gro_skb,
 872                                 length);
 873                         if (!nr)
 874                                 goto next;
 875
 876                         if (ip_summed == CHECKSUM_COMPLETE) {
 877                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 878                                 if (check_csum(cqe, gro_skb, va, ring->hwtstamp_rx_filter)) {
 879                                         ip_summed = CHECKSUM_NONE;
 880                                         ring->csum_none++;
 881                                         ring->csum_complete--;
 882                                 }
 883                         }
 884
 885                         skb_shinfo(gro_skb)->nr_frags = nr;
 886                         gro_skb->len = length;
 887                         gro_skb->data_len = length;
 888                         gro_skb->ip_summed = ip_summed;
 889
 890                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 891                                 gro_skb->encapsulation = 1;
 892                         if ((cqe->vlan_my_qpn &
 893                             cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
 894                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 895                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 896
 897                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 898                         }
 899
 900                         if (dev->features & NETIF_F_RXHASH)
 901                                 skb_set_hash(gro_skb,
 902                                              be32_to_cpu(cqe->immed_rss_invalid),
 903                                              PKT_HASH_TYPE_L3);
 904
 905                         skb_record_rx_queue(gro_skb, cq->ring);
 906                         skb_mark_napi_id(gro_skb, &cq->napi);
 907
 908                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 909                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 910                                 mlx4_en_fill_hwtstamps(mdev,
 911                                                        skb_hwtstamps(gro_skb),
 912                                                        timestamp);
 913                         }
 914
 915                         napi_gro_frags(&cq->napi);
 916                         goto next;
 917                 }
 918
 919                 /* GRO not possible, complete processing here */
 920                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 921                 if (!skb) {
 922                         priv->stats.rx_dropped++;
 923                         goto next;
 924                 }
 925
 926                 if (unlikely(priv->validate_loopback)) {
 927                         validate_loopback(priv, skb);
 928                         goto next;
 929                 }
 930
 931                 if (ip_summed == CHECKSUM_COMPLETE) {
 932                         if (check_csum(cqe, skb, skb->data, ring->hwtstamp_rx_filter)) {
 933                                 ip_summed = CHECKSUM_NONE;
 934                                 ring->csum_complete--;
 935                                 ring->csum_none++;
 936                         }
 937                 }
 938
 939                 skb->ip_summed = ip_summed;
 940                 skb->protocol = eth_type_trans(skb, dev);
 941                 skb_record_rx_queue(skb, cq->ring);
 942
 943                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 944                         skb->csum_level = 1;
 945
 946                 if (dev->features & NETIF_F_RXHASH)
 947                         skb_set_hash(skb,
 948                                      be32_to_cpu(cqe->immed_rss_invalid),
 949                                      PKT_HASH_TYPE_L3);
 950
 951                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 952                     MLX4_CQE_VLAN_PRESENT_MASK) &&
 953                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 954                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 955
 956                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 957                         timestamp = mlx4_en_get_cqe_ts(cqe);
 958                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 959                                                timestamp);
 960                 }
 961
 962                 skb_mark_napi_id(skb, &cq->napi);
 963
 964                 if (!mlx4_en_cq_busy_polling(cq))
 965                         napi_gro_receive(&cq->napi, skb);
 966                 else
 967                         netif_receive_skb(skb);
 968
 969 next:
 970                 for (nr = 0; nr < priv->num_frags; nr++)
 971                         mlx4_en_free_frag(priv, frags, nr);
 972
 973                 ++cq->mcq.cons_index;
 974                 index = (cq->mcq.cons_index) & ring->size_mask;
 975                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 976                 if (++polled == budget)
 977                         goto out;
 978         }
 979
 980 out:
 981         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 982         mlx4_cq_set_ci(&cq->mcq);
 983         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 984         ring->cons = cq->mcq.cons_index;
 985         mlx4_en_refill_rx_buffers(priv, ring);
 986         mlx4_en_update_rx_prod_db(ring);
 987         return polled;
 988 }
 989
 990
 991 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 992 {
 993         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 994         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 995
 996         if (likely(priv->port_up))
 997                 napi_schedule_irqoff(&cq->napi);
 998         else
 999                 mlx4_en_arm_cq(priv, cq);
1000 }
1001
1002 /* Rx CQ polling - called by NAPI */
1003 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1004 {
1005         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1006         struct net_device *dev = cq->dev;
1007         struct mlx4_en_priv *priv = netdev_priv(dev);
1008         int done;
1009
1010         if (!mlx4_en_cq_lock_napi(cq))
1011                 return budget;
1012
1013         done = mlx4_en_process_rx_cq(dev, cq, budget);
1014
1015         mlx4_en_cq_unlock_napi(cq);
1016
1017         /* If we used up all the quota - we're probably not done yet... */
1018         if (done == budget) {
1019                 int cpu_curr;
1020                 const struct cpumask *aff;
1021
1022                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1023
1024                 cpu_curr = smp_processor_id();
1025                 aff = irq_desc_get_irq_data(cq->irq_desc)->affinity;
1026
1027                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1028                         return budget;
1029
1030                 /* Current cpu is not according to smp_irq_affinity -
1031                  * probably affinity changed. need to stop this NAPI
1032                  * poll, and restart it on the right CPU
1033                  */
1034                 done = 0;
1035         }
1036         /* Done for now */
1037         napi_complete_done(napi, done);
1038         mlx4_en_arm_cq(priv, cq);
1039         return done;
1040 }
1041
1042 static const int frag_sizes[] = {
1043         FRAG_SZ0,
1044         FRAG_SZ1,
1045         FRAG_SZ2,
1046         FRAG_SZ3
1047 };
1048
1049 void mlx4_en_calc_rx_buf(struct net_device *dev)
1050 {
1051         struct mlx4_en_priv *priv = netdev_priv(dev);
1052         int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN;
1053         int buf_size = 0;
1054         int i = 0;
1055
1056         while (buf_size < eff_mtu) {
1057                 priv->frag_info[i].frag_size =
1058                         (eff_mtu > buf_size + frag_sizes[i]) ?
1059                                 frag_sizes[i] : eff_mtu - buf_size;
1060                 priv->frag_info[i].frag_prefix_size = buf_size;
1061                 priv->frag_info[i].frag_stride = ALIGN(frag_sizes[i],
1062                                                        SMP_CACHE_BYTES);
1063                 buf_size += priv->frag_info[i].frag_size;
1064                 i++;
1065         }
1066
1067         priv->num_frags = i;
1068         priv->rx_skb_size = eff_mtu;
1069         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1070
1071         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1072                eff_mtu, priv->num_frags);
1073         for (i = 0; i < priv->num_frags; i++) {
1074                 en_err(priv,
1075                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1076                        i,
1077                        priv->frag_info[i].frag_size,
1078                        priv->frag_info[i].frag_prefix_size,
1079                        priv->frag_info[i].frag_stride);
1080         }
1081 }
1082
1083 /* RSS related functions */
1084
1085 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1086                                  struct mlx4_en_rx_ring *ring,
1087                                  enum mlx4_qp_state *state,
1088                                  struct mlx4_qp *qp)
1089 {
1090         struct mlx4_en_dev *mdev = priv->mdev;
1091         struct mlx4_qp_context *context;
1092         int err = 0;
1093
1094         context = kmalloc(sizeof(*context), GFP_KERNEL);
1095         if (!context)
1096                 return -ENOMEM;
1097
1098         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1099         if (err) {
1100                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1101                 goto out;
1102         }
1103         qp->event = mlx4_en_sqp_event;
1104
1105         memset(context, 0, sizeof *context);
1106         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1107                                 qpn, ring->cqn, -1, context);
1108         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1109
1110         /* Cancel FCS removal if FW allows */
1111         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1112                 context->param3 |= cpu_to_be32(1 << 29);
1113                 ring->fcs_del = ETH_FCS_LEN;
1114         } else
1115                 ring->fcs_del = 0;
1116
1117         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1118         if (err) {
1119                 mlx4_qp_remove(mdev->dev, qp);
1120                 mlx4_qp_free(mdev->dev, qp);
1121         }
1122         mlx4_en_update_rx_prod_db(ring);
1123 out:
1124         kfree(context);
1125         return err;
1126 }
1127
1128 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1129 {
1130         int err;
1131         u32 qpn;
1132
1133         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
1134         if (err) {
1135                 en_err(priv, "Failed reserving drop qpn\n");
1136                 return err;
1137         }
1138         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1139         if (err) {
1140                 en_err(priv, "Failed allocating drop qp\n");
1141                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1142                 return err;
1143         }
1144
1145         return 0;
1146 }
1147
1148 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1149 {
1150         u32 qpn;
1151
1152         qpn = priv->drop_qp.qpn;
1153         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1154         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1155         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1156 }
1157
1158 /* Allocate rx qp's and configure them according to rss map */
1159 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1160 {
1161         struct mlx4_en_dev *mdev = priv->mdev;
1162         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1163         struct mlx4_qp_context context;
1164         struct mlx4_rss_context *rss_context;
1165         int rss_rings;
1166         void *ptr;
1167         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1168                         MLX4_RSS_TCP_IPV6);
1169         int i, qpn;
1170         int err = 0;
1171         int good_qps = 0;
1172         static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
1173                                 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
1174                                 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
1175
1176         en_dbg(DRV, priv, "Configuring rss steering\n");
1177         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1178                                     priv->rx_ring_num,
1179                                     &rss_map->base_qpn);
1180         if (err) {
1181                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1182                 return err;
1183         }
1184
1185         for (i = 0; i < priv->rx_ring_num; i++) {
1186                 qpn = rss_map->base_qpn + i;
1187                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1188                                             &rss_map->state[i],
1189                                             &rss_map->qps[i]);
1190                 if (err)
1191                         goto rss_err;
1192
1193                 ++good_qps;
1194         }
1195
1196         /* Configure RSS indirection qp */
1197         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1198         if (err) {
1199                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1200                 goto rss_err;
1201         }
1202         rss_map->indir_qp.event = mlx4_en_sqp_event;
1203         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1204                                 priv->rx_ring[0]->cqn, -1, &context);
1205
1206         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1207                 rss_rings = priv->rx_ring_num;
1208         else
1209                 rss_rings = priv->prof->rss_rings;
1210
1211         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1212                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1213         rss_context = ptr;
1214         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1215                                             (rss_map->base_qpn));
1216         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1217         if (priv->mdev->profile.udp_rss) {
1218                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1219                 rss_context->base_qpn_udp = rss_context->default_qpn;
1220         }
1221
1222         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1223                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1224                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1225         }
1226
1227         rss_context->flags = rss_mask;
1228         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1229         for (i = 0; i < 10; i++)
1230                 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
1231
1232         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1233                                &rss_map->indir_qp, &rss_map->indir_state);
1234         if (err)
1235                 goto indir_err;
1236
1237         return 0;
1238
1239 indir_err:
1240         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1241                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1242         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1243         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1244 rss_err:
1245         for (i = 0; i < good_qps; i++) {
1246                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1247                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1248                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1249                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1250         }
1251         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1252         return err;
1253 }
1254
1255 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1256 {
1257         struct mlx4_en_dev *mdev = priv->mdev;
1258         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1259         int i;
1260
1261         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1262                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1263         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1264         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1265
1266         for (i = 0; i < priv->rx_ring_num; i++) {
1267                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1268                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1269                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1270                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1271         }
1272         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1273 }