drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/irq.h>
  44
  45 #include "mlx4_en.h"
  46
  47 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  48                             struct mlx4_en_rx_alloc *page_alloc,
  49                             const struct mlx4_en_frag_info *frag_info,
  50                             gfp_t _gfp)
  51 {
  52         int order;
  53         struct page *page;
  54         dma_addr_t dma;
  55
  56         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  57                 gfp_t gfp = _gfp;
  58
  59                 if (order)
  60                         gfp |= __GFP_COMP | __GFP_NOWARN;
  61                 page = alloc_pages(gfp, order);
  62                 if (likely(page))
  63                         break;
  64                 if (--order < 0 ||
  65                     ((PAGE_SIZE << order) < frag_info->frag_size))
  66                         return -ENOMEM;
  67         }
  68         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  69                            PCI_DMA_FROMDEVICE);
  70         if (dma_mapping_error(priv->ddev, dma)) {
  71                 put_page(page);
  72                 return -ENOMEM;
  73         }
  74         page_alloc->page_size = PAGE_SIZE << order;
  75         page_alloc->page = page;
  76         page_alloc->dma = dma;
  77         page_alloc->page_offset = frag_info->frag_align;
  78         /* Not doing get_page() for each frag is a big win
  79          * on asymetric workloads. Note we can not use atomic_set().
  80          */
  81         atomic_add(page_alloc->page_size / frag_info->frag_stride - 1,
  82                    &page->_count);
  83         return 0;
  84 }
  85
  86 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  87                                struct mlx4_en_rx_desc *rx_desc,
  88                                struct mlx4_en_rx_alloc *frags,
  89                                struct mlx4_en_rx_alloc *ring_alloc,
  90                                gfp_t gfp)
  91 {
  92         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  93         const struct mlx4_en_frag_info *frag_info;
  94         struct page *page;
  95         dma_addr_t dma;
  96         int i;
  97
  98         for (i = 0; i < priv->num_frags; i++) {
  99                 frag_info = &priv->frag_info[i];
 100                 page_alloc[i] = ring_alloc[i];
 101                 page_alloc[i].page_offset += frag_info->frag_stride;
 102
 103                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 104                     ring_alloc[i].page_size)
 105                         continue;
 106
 107                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
 108                         goto out;
 109         }
 110
 111         for (i = 0; i < priv->num_frags; i++) {
 112                 frags[i] = ring_alloc[i];
 113                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 114                 ring_alloc[i] = page_alloc[i];
 115                 rx_desc->data[i].addr = cpu_to_be64(dma);
 116         }
 117
 118         return 0;
 119
 120 out:
 121         while (i--) {
 122                 if (page_alloc[i].page != ring_alloc[i].page) {
 123                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 124                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
 125                         page = page_alloc[i].page;
 126                         atomic_set(&page->_count, 1);
 127                         put_page(page);
 128                 }
 129         }
 130         return -ENOMEM;
 131 }
 132
 133 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 134                               struct mlx4_en_rx_alloc *frags,
 135                               int i)
 136 {
 137         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 138         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 139
 140
 141         if (next_frag_end > frags[i].page_size)
 142                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 143                                PCI_DMA_FROMDEVICE);
 144
 145         if (frags[i].page)
 146                 put_page(frags[i].page);
 147 }
 148
 149 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 150                                   struct mlx4_en_rx_ring *ring)
 151 {
 152         int i;
 153         struct mlx4_en_rx_alloc *page_alloc;
 154
 155         for (i = 0; i < priv->num_frags; i++) {
 156                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 157
 158                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 159                                      frag_info, GFP_KERNEL))
 160                         goto out;
 161         }
 162         return 0;
 163
 164 out:
 165         while (i--) {
 166                 struct page *page;
 167
 168                 page_alloc = &ring->page_alloc[i];
 169                 dma_unmap_page(priv->ddev, page_alloc->dma,
 170                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
 171                 page = page_alloc->page;
 172                 atomic_set(&page->_count, 1);
 173                 put_page(page);
 174                 page_alloc->page = NULL;
 175         }
 176         return -ENOMEM;
 177 }
 178
 179 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 180                                       struct mlx4_en_rx_ring *ring)
 181 {
 182         struct mlx4_en_rx_alloc *page_alloc;
 183         int i;
 184
 185         for (i = 0; i < priv->num_frags; i++) {
 186                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 187
 188                 page_alloc = &ring->page_alloc[i];
 189                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 190                        i, page_count(page_alloc->page));
 191
 192                 dma_unmap_page(priv->ddev, page_alloc->dma,
 193                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
 194                 while (page_alloc->page_offset + frag_info->frag_stride <
 195                        page_alloc->page_size) {
 196                         put_page(page_alloc->page);
 197                         page_alloc->page_offset += frag_info->frag_stride;
 198                 }
 199                 page_alloc->page = NULL;
 200         }
 201 }
 202
 203 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 204                                  struct mlx4_en_rx_ring *ring, int index)
 205 {
 206         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 207         int possible_frags;
 208         int i;
 209
 210         /* Set size and memtype fields */
 211         for (i = 0; i < priv->num_frags; i++) {
 212                 rx_desc->data[i].byte_count =
 213                         cpu_to_be32(priv->frag_info[i].frag_size);
 214                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 215         }
 216
 217         /* If the number of used fragments does not fill up the ring stride,
 218          * remaining (unused) fragments must be padded with null address/size
 219          * and a special memory key */
 220         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 221         for (i = priv->num_frags; i < possible_frags; i++) {
 222                 rx_desc->data[i].byte_count = 0;
 223                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 224                 rx_desc->data[i].addr = 0;
 225         }
 226 }
 227
 228 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 229                                    struct mlx4_en_rx_ring *ring, int index,
 230                                    gfp_t gfp)
 231 {
 232         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 233         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 234                                         (index << priv->log_rx_info);
 235
 236         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 237 }
 238
 239 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 240 {
 241         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 242 }
 243
 244 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 245                                  struct mlx4_en_rx_ring *ring,
 246                                  int index)
 247 {
 248         struct mlx4_en_rx_alloc *frags;
 249         int nr;
 250
 251         frags = ring->rx_info + (index << priv->log_rx_info);
 252         for (nr = 0; nr < priv->num_frags; nr++) {
 253                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 254                 mlx4_en_free_frag(priv, frags, nr);
 255         }
 256 }
 257
 258 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 259 {
 260         struct mlx4_en_rx_ring *ring;
 261         int ring_ind;
 262         int buf_ind;
 263         int new_size;
 264
 265         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 266                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 267                         ring = priv->rx_ring[ring_ind];
 268
 269                         if (mlx4_en_prepare_rx_desc(priv, ring,
 270                                                     ring->actual_size,
 271                                                     GFP_KERNEL)) {
 272                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 273                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 274                                         return -ENOMEM;
 275                                 } else {
 276                                         new_size = rounddown_pow_of_two(ring->actual_size);
 277                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 278                                                 ring->actual_size, new_size);
 279                                         goto reduce_rings;
 280                                 }
 281                         }
 282                         ring->actual_size++;
 283                         ring->prod++;
 284                 }
 285         }
 286         return 0;
 287
 288 reduce_rings:
 289         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 290                 ring = priv->rx_ring[ring_ind];
 291                 while (ring->actual_size > new_size) {
 292                         ring->actual_size--;
 293                         ring->prod--;
 294                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 295                 }
 296         }
 297
 298         return 0;
 299 }
 300
 301 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 302                                 struct mlx4_en_rx_ring *ring)
 303 {
 304         int index;
 305
 306         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 307                ring->cons, ring->prod);
 308
 309         /* Unmap and free Rx buffers */
 310         BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
 311         while (ring->cons != ring->prod) {
 312                 index = ring->cons & ring->size_mask;
 313                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 314                 mlx4_en_free_rx_desc(priv, ring, index);
 315                 ++ring->cons;
 316         }
 317 }
 318
 319 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 320 {
 321         int i;
 322         int num_of_eqs;
 323         int num_rx_rings;
 324         struct mlx4_dev *dev = mdev->dev;
 325
 326         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 327                 if (!dev->caps.comp_pool)
 328                         num_of_eqs = max_t(int, MIN_RX_RINGS,
 329                                            min_t(int,
 330                                                  dev->caps.num_comp_vectors,
 331                                                  DEF_RX_RINGS));
 332                 else
 333                         num_of_eqs = min_t(int, MAX_MSIX_P_PORT,
 334                                            dev->caps.comp_pool/
 335                                            dev->caps.num_ports) - 1;
 336
 337                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 338                         min_t(int, num_of_eqs,
 339                               netif_get_num_default_rss_queues());
 340                 mdev->profile.prof[i].rx_ring_num =
 341                         rounddown_pow_of_two(num_rx_rings);
 342         }
 343 }
 344
 345 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 346                            struct mlx4_en_rx_ring **pring,
 347                            u32 size, u16 stride, int node)
 348 {
 349         struct mlx4_en_dev *mdev = priv->mdev;
 350         struct mlx4_en_rx_ring *ring;
 351         int err = -ENOMEM;
 352         int tmp;
 353
 354         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 355         if (!ring) {
 356                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 357                 if (!ring) {
 358                         en_err(priv, "Failed to allocate RX ring structure\n");
 359                         return -ENOMEM;
 360                 }
 361         }
 362
 363         ring->prod = 0;
 364         ring->cons = 0;
 365         ring->size = size;
 366         ring->size_mask = size - 1;
 367         ring->stride = stride;
 368         ring->log_stride = ffs(ring->stride) - 1;
 369         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 370
 371         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 372                                         sizeof(struct mlx4_en_rx_alloc));
 373         ring->rx_info = vmalloc_node(tmp, node);
 374         if (!ring->rx_info) {
 375                 ring->rx_info = vmalloc(tmp);
 376                 if (!ring->rx_info) {
 377                         err = -ENOMEM;
 378                         goto err_ring;
 379                 }
 380         }
 381
 382         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 383                  ring->rx_info, tmp);
 384
 385         /* Allocate HW buffers on provided NUMA node */
 386         set_dev_node(&mdev->dev->pdev->dev, node);
 387         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 388                                  ring->buf_size, 2 * PAGE_SIZE);
 389         set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
 390         if (err)
 391                 goto err_info;
 392
 393         err = mlx4_en_map_buffer(&ring->wqres.buf);
 394         if (err) {
 395                 en_err(priv, "Failed to map RX buffer\n");
 396                 goto err_hwq;
 397         }
 398         ring->buf = ring->wqres.buf.direct.buf;
 399
 400         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 401
 402         *pring = ring;
 403         return 0;
 404
 405 err_hwq:
 406         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 407 err_info:
 408         vfree(ring->rx_info);
 409         ring->rx_info = NULL;
 410 err_ring:
 411         kfree(ring);
 412         *pring = NULL;
 413
 414         return err;
 415 }
 416
 417 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 418 {
 419         struct mlx4_en_rx_ring *ring;
 420         int i;
 421         int ring_ind;
 422         int err;
 423         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 424                                         DS_SIZE * priv->num_frags);
 425
 426         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 427                 ring = priv->rx_ring[ring_ind];
 428
 429                 ring->prod = 0;
 430                 ring->cons = 0;
 431                 ring->actual_size = 0;
 432                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 433
 434                 ring->stride = stride;
 435                 if (ring->stride <= TXBB_SIZE)
 436                         ring->buf += TXBB_SIZE;
 437
 438                 ring->log_stride = ffs(ring->stride) - 1;
 439                 ring->buf_size = ring->size * ring->stride;
 440
 441                 memset(ring->buf, 0, ring->buf_size);
 442                 mlx4_en_update_rx_prod_db(ring);
 443
 444                 /* Initialize all descriptors */
 445                 for (i = 0; i < ring->size; i++)
 446                         mlx4_en_init_rx_desc(priv, ring, i);
 447
 448                 /* Initialize page allocators */
 449                 err = mlx4_en_init_allocator(priv, ring);
 450                 if (err) {
 451                         en_err(priv, "Failed initializing ring allocator\n");
 452                         if (ring->stride <= TXBB_SIZE)
 453                                 ring->buf -= TXBB_SIZE;
 454                         ring_ind--;
 455                         goto err_allocator;
 456                 }
 457         }
 458         err = mlx4_en_fill_rx_buffers(priv);
 459         if (err)
 460                 goto err_buffers;
 461
 462         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 463                 ring = priv->rx_ring[ring_ind];
 464
 465                 ring->size_mask = ring->actual_size - 1;
 466                 mlx4_en_update_rx_prod_db(ring);
 467         }
 468
 469         return 0;
 470
 471 err_buffers:
 472         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 473                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 474
 475         ring_ind = priv->rx_ring_num - 1;
 476 err_allocator:
 477         while (ring_ind >= 0) {
 478                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 479                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 480                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 481                 ring_ind--;
 482         }
 483         return err;
 484 }
 485
 486 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 487                              struct mlx4_en_rx_ring **pring,
 488                              u32 size, u16 stride)
 489 {
 490         struct mlx4_en_dev *mdev = priv->mdev;
 491         struct mlx4_en_rx_ring *ring = *pring;
 492
 493         mlx4_en_unmap_buffer(&ring->wqres.buf);
 494         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 495         vfree(ring->rx_info);
 496         ring->rx_info = NULL;
 497         kfree(ring);
 498         *pring = NULL;
 499 #ifdef CONFIG_RFS_ACCEL
 500         mlx4_en_cleanup_filters(priv);
 501 #endif
 502 }
 503
 504 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 505                                 struct mlx4_en_rx_ring *ring)
 506 {
 507         mlx4_en_free_rx_buf(priv, ring);
 508         if (ring->stride <= TXBB_SIZE)
 509                 ring->buf -= TXBB_SIZE;
 510         mlx4_en_destroy_allocator(priv, ring);
 511 }
 512
 513
 514 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 515                                     struct mlx4_en_rx_desc *rx_desc,
 516                                     struct mlx4_en_rx_alloc *frags,
 517                                     struct sk_buff *skb,
 518                                     int length)
 519 {
 520         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 521         struct mlx4_en_frag_info *frag_info;
 522         int nr;
 523         dma_addr_t dma;
 524
 525         /* Collect used fragments while replacing them in the HW descriptors */
 526         for (nr = 0; nr < priv->num_frags; nr++) {
 527                 frag_info = &priv->frag_info[nr];
 528                 if (length <= frag_info->frag_prefix_size)
 529                         break;
 530                 if (!frags[nr].page)
 531                         goto fail;
 532
 533                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 534                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 535                                         DMA_FROM_DEVICE);
 536
 537                 /* Save page reference in skb */
 538                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 539                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 540                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 541                 skb->truesize += frag_info->frag_stride;
 542                 frags[nr].page = NULL;
 543         }
 544         /* Adjust size of last fragment to match actual length */
 545         if (nr > 0)
 546                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 547                         length - priv->frag_info[nr - 1].frag_prefix_size);
 548         return nr;
 549
 550 fail:
 551         while (nr > 0) {
 552                 nr--;
 553                 __skb_frag_unref(&skb_frags_rx[nr]);
 554         }
 555         return 0;
 556 }
 557
 558
 559 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 560                                       struct mlx4_en_rx_desc *rx_desc,
 561                                       struct mlx4_en_rx_alloc *frags,
 562                                       unsigned int length)
 563 {
 564         struct sk_buff *skb;
 565         void *va;
 566         int used_frags;
 567         dma_addr_t dma;
 568
 569         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 570         if (!skb) {
 571                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 572                 return NULL;
 573         }
 574         skb_reserve(skb, NET_IP_ALIGN);
 575         skb->len = length;
 576
 577         /* Get pointer to first fragment so we could copy the headers into the
 578          * (linear part of the) skb */
 579         va = page_address(frags[0].page) + frags[0].page_offset;
 580
 581         if (length <= SMALL_PACKET_SIZE) {
 582                 /* We are copying all relevant data to the skb - temporarily
 583                  * sync buffers for the copy */
 584                 dma = be64_to_cpu(rx_desc->data[0].addr);
 585                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 586                                         DMA_FROM_DEVICE);
 587                 skb_copy_to_linear_data(skb, va, length);
 588                 skb->tail += length;
 589         } else {
 590                 unsigned int pull_len;
 591
 592                 /* Move relevant fragments to skb */
 593                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 594                                                         skb, length);
 595                 if (unlikely(!used_frags)) {
 596                         kfree_skb(skb);
 597                         return NULL;
 598                 }
 599                 skb_shinfo(skb)->nr_frags = used_frags;
 600
 601                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 602                 /* Copy headers into the skb linear buffer */
 603                 memcpy(skb->data, va, pull_len);
 604                 skb->tail += pull_len;
 605
 606                 /* Skip headers in first fragment */
 607                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 608
 609                 /* Adjust size of first fragment */
 610                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 611                 skb->data_len = length - pull_len;
 612         }
 613         return skb;
 614 }
 615
 616 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 617 {
 618         int i;
 619         int offset = ETH_HLEN;
 620
 621         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 622                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 623                         goto out_loopback;
 624         }
 625         /* Loopback found */
 626         priv->loopback_ok = 1;
 627
 628 out_loopback:
 629         dev_kfree_skb_any(skb);
 630 }
 631
 632 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 633                                      struct mlx4_en_rx_ring *ring)
 634 {
 635         int index = ring->prod & ring->size_mask;
 636
 637         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 638                 if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC))
 639                         break;
 640                 ring->prod++;
 641                 index = ring->prod & ring->size_mask;
 642         }
 643 }
 644
 645 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 646 {
 647         struct mlx4_en_priv *priv = netdev_priv(dev);
 648         struct mlx4_en_dev *mdev = priv->mdev;
 649         struct mlx4_cqe *cqe;
 650         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 651         struct mlx4_en_rx_alloc *frags;
 652         struct mlx4_en_rx_desc *rx_desc;
 653         struct sk_buff *skb;
 654         int index;
 655         int nr;
 656         unsigned int length;
 657         int polled = 0;
 658         int ip_summed;
 659         int factor = priv->cqe_factor;
 660         u64 timestamp;
 661         bool l2_tunnel;
 662
 663         if (!priv->port_up)
 664                 return 0;
 665
 666         if (budget <= 0)
 667                 return polled;
 668
 669         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 670          * descriptor offset can be deduced from the CQE index instead of
 671          * reading 'cqe->index' */
 672         index = cq->mcq.cons_index & ring->size_mask;
 673         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 674
 675         /* Process all completed CQEs */
 676         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 677                     cq->mcq.cons_index & cq->size)) {
 678
 679                 frags = ring->rx_info + (index << priv->log_rx_info);
 680                 rx_desc = ring->buf + (index << ring->log_stride);
 681
 682                 /*
 683                  * make sure we read the CQE after we read the ownership bit
 684                  */
 685                 rmb();
 686
 687                 /* Drop packet on bad receive or bad checksum */
 688                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 689                                                 MLX4_CQE_OPCODE_ERROR)) {
 690                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 691                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 692                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 693                         goto next;
 694                 }
 695                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 696                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 697                         goto next;
 698                 }
 699
 700                 /* Check if we need to drop the packet if SRIOV is not enabled
 701                  * and not performing the selftest or flb disabled
 702                  */
 703                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 704                         struct ethhdr *ethh;
 705                         dma_addr_t dma;
 706                         /* Get pointer to first fragment since we haven't
 707                          * skb yet and cast it to ethhdr struct
 708                          */
 709                         dma = be64_to_cpu(rx_desc->data[0].addr);
 710                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 711                                                 DMA_FROM_DEVICE);
 712                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 713                                                  frags[0].page_offset);
 714
 715                         if (is_multicast_ether_addr(ethh->h_dest)) {
 716                                 struct mlx4_mac_entry *entry;
 717                                 struct hlist_head *bucket;
 718                                 unsigned int mac_hash;
 719
 720                                 /* Drop the packet, since HW loopback-ed it */
 721                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 722                                 bucket = &priv->mac_hash[mac_hash];
 723                                 rcu_read_lock();
 724                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 725                                         if (ether_addr_equal_64bits(entry->mac,
 726                                                                     ethh->h_source)) {
 727                                                 rcu_read_unlock();
 728                                                 goto next;
 729                                         }
 730                                 }
 731                                 rcu_read_unlock();
 732                         }
 733                 }
 734
 735                 /*
 736                  * Packet is OK - process it.
 737                  */
 738                 length = be32_to_cpu(cqe->byte_cnt);
 739                 length -= ring->fcs_del;
 740                 ring->bytes += length;
 741                 ring->packets++;
 742                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 743                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 744
 745                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 746                         if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 747                             (cqe->checksum == cpu_to_be16(0xffff))) {
 748                                 ring->csum_ok++;
 749                                 /* This packet is eligible for GRO if it is:
 750                                  * - DIX Ethernet (type interpretation)
 751                                  * - TCP/IP (v4)
 752                                  * - without IP options
 753                                  * - not an IP fragment
 754                                  * - no LLS polling in progress
 755                                  */
 756                                 if (!mlx4_en_cq_busy_polling(cq) &&
 757                                     (dev->features & NETIF_F_GRO)) {
 758                                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 759                                         if (!gro_skb)
 760                                                 goto next;
 761
 762                                         nr = mlx4_en_complete_rx_desc(priv,
 763                                                 rx_desc, frags, gro_skb,
 764                                                 length);
 765                                         if (!nr)
 766                                                 goto next;
 767
 768                                         skb_shinfo(gro_skb)->nr_frags = nr;
 769                                         gro_skb->len = length;
 770                                         gro_skb->data_len = length;
 771                                         gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
 772
 773                                         if (l2_tunnel)
 774                                                 gro_skb->csum_level = 1;
 775                                         if ((cqe->vlan_my_qpn &
 776                                             cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
 777                                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 778                                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 779
 780                                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 781                                         }
 782
 783                                         if (dev->features & NETIF_F_RXHASH)
 784                                                 skb_set_hash(gro_skb,
 785                                                              be32_to_cpu(cqe->immed_rss_invalid),
 786                                                              PKT_HASH_TYPE_L3);
 787
 788                                         skb_record_rx_queue(gro_skb, cq->ring);
 789                                         skb_mark_napi_id(gro_skb, &cq->napi);
 790
 791                                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 792                                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 793                                                 mlx4_en_fill_hwtstamps(mdev,
 794                                                                        skb_hwtstamps(gro_skb),
 795                                                                        timestamp);
 796                                         }
 797
 798                                         napi_gro_frags(&cq->napi);
 799                                         goto next;
 800                                 }
 801
 802                                 /* GRO not possible, complete processing here */
 803                                 ip_summed = CHECKSUM_UNNECESSARY;
 804                         } else {
 805                                 ip_summed = CHECKSUM_NONE;
 806                                 ring->csum_none++;
 807                         }
 808                 } else {
 809                         ip_summed = CHECKSUM_NONE;
 810                         ring->csum_none++;
 811                 }
 812
 813                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 814                 if (!skb) {
 815                         priv->stats.rx_dropped++;
 816                         goto next;
 817                 }
 818
 819                 if (unlikely(priv->validate_loopback)) {
 820                         validate_loopback(priv, skb);
 821                         goto next;
 822                 }
 823
 824                 skb->ip_summed = ip_summed;
 825                 skb->protocol = eth_type_trans(skb, dev);
 826                 skb_record_rx_queue(skb, cq->ring);
 827
 828                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 829                         skb->csum_level = 1;
 830
 831                 if (dev->features & NETIF_F_RXHASH)
 832                         skb_set_hash(skb,
 833                                      be32_to_cpu(cqe->immed_rss_invalid),
 834                                      PKT_HASH_TYPE_L3);
 835
 836                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 837                     MLX4_CQE_VLAN_PRESENT_MASK) &&
 838                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 839                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 840
 841                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 842                         timestamp = mlx4_en_get_cqe_ts(cqe);
 843                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 844                                                timestamp);
 845                 }
 846
 847                 skb_mark_napi_id(skb, &cq->napi);
 848
 849                 if (!mlx4_en_cq_busy_polling(cq))
 850                         napi_gro_receive(&cq->napi, skb);
 851                 else
 852                         netif_receive_skb(skb);
 853
 854 next:
 855                 for (nr = 0; nr < priv->num_frags; nr++)
 856                         mlx4_en_free_frag(priv, frags, nr);
 857
 858                 ++cq->mcq.cons_index;
 859                 index = (cq->mcq.cons_index) & ring->size_mask;
 860                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 861                 if (++polled == budget)
 862                         goto out;
 863         }
 864
 865 out:
 866         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 867         mlx4_cq_set_ci(&cq->mcq);
 868         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 869         ring->cons = cq->mcq.cons_index;
 870         mlx4_en_refill_rx_buffers(priv, ring);
 871         mlx4_en_update_rx_prod_db(ring);
 872         return polled;
 873 }
 874
 875
 876 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 877 {
 878         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 879         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 880
 881         if (priv->port_up)
 882                 napi_schedule(&cq->napi);
 883         else
 884                 mlx4_en_arm_cq(priv, cq);
 885 }
 886
 887 /* Rx CQ polling - called by NAPI */
 888 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
 889 {
 890         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 891         struct net_device *dev = cq->dev;
 892         struct mlx4_en_priv *priv = netdev_priv(dev);
 893         int done;
 894
 895         if (!mlx4_en_cq_lock_napi(cq))
 896                 return budget;
 897
 898         done = mlx4_en_process_rx_cq(dev, cq, budget);
 899
 900         mlx4_en_cq_unlock_napi(cq);
 901
 902         /* If we used up all the quota - we're probably not done yet... */
 903         if (done == budget) {
 904                 int cpu_curr;
 905                 const struct cpumask *aff;
 906
 907                 INC_PERF_COUNTER(priv->pstats.napi_quota);
 908
 909                 cpu_curr = smp_processor_id();
 910                 aff = irq_desc_get_irq_data(cq->irq_desc)->affinity;
 911
 912                 if (unlikely(!cpumask_test_cpu(cpu_curr, aff))) {
 913                         /* Current cpu is not according to smp_irq_affinity -
 914                          * probably affinity changed. need to stop this NAPI
 915                          * poll, and restart it on the right CPU
 916                          */
 917                         napi_complete(napi);
 918                         mlx4_en_arm_cq(priv, cq);
 919                         return 0;
 920                 }
 921         } else {
 922                 /* Done for now */
 923                 napi_complete(napi);
 924                 mlx4_en_arm_cq(priv, cq);
 925         }
 926         return done;
 927 }
 928
 929 static const int frag_sizes[] = {
 930         FRAG_SZ0,
 931         FRAG_SZ1,
 932         FRAG_SZ2,
 933         FRAG_SZ3
 934 };
 935
 936 void mlx4_en_calc_rx_buf(struct net_device *dev)
 937 {
 938         struct mlx4_en_priv *priv = netdev_priv(dev);
 939         int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN;
 940         int buf_size = 0;
 941         int i = 0;
 942
 943         while (buf_size < eff_mtu) {
 944                 priv->frag_info[i].frag_size =
 945                         (eff_mtu > buf_size + frag_sizes[i]) ?
 946                                 frag_sizes[i] : eff_mtu - buf_size;
 947                 priv->frag_info[i].frag_prefix_size = buf_size;
 948                 if (!i) {
 949                         priv->frag_info[i].frag_align = NET_IP_ALIGN;
 950                         priv->frag_info[i].frag_stride =
 951                                 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
 952                 } else {
 953                         priv->frag_info[i].frag_align = 0;
 954                         priv->frag_info[i].frag_stride =
 955                                 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
 956                 }
 957                 buf_size += priv->frag_info[i].frag_size;
 958                 i++;
 959         }
 960
 961         priv->num_frags = i;
 962         priv->rx_skb_size = eff_mtu;
 963         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
 964
 965         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
 966                eff_mtu, priv->num_frags);
 967         for (i = 0; i < priv->num_frags; i++) {
 968                 en_err(priv,
 969                        "  frag:%d - size:%d prefix:%d align:%d stride:%d\n",
 970                        i,
 971                        priv->frag_info[i].frag_size,
 972                        priv->frag_info[i].frag_prefix_size,
 973                        priv->frag_info[i].frag_align,
 974                        priv->frag_info[i].frag_stride);
 975         }
 976 }
 977
 978 /* RSS related functions */
 979
 980 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
 981                                  struct mlx4_en_rx_ring *ring,
 982                                  enum mlx4_qp_state *state,
 983                                  struct mlx4_qp *qp)
 984 {
 985         struct mlx4_en_dev *mdev = priv->mdev;
 986         struct mlx4_qp_context *context;
 987         int err = 0;
 988
 989         context = kmalloc(sizeof(*context), GFP_KERNEL);
 990         if (!context)
 991                 return -ENOMEM;
 992
 993         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
 994         if (err) {
 995                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
 996                 goto out;
 997         }
 998         qp->event = mlx4_en_sqp_event;
 999
1000         memset(context, 0, sizeof *context);
1001         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1002                                 qpn, ring->cqn, -1, context);
1003         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1004
1005         /* Cancel FCS removal if FW allows */
1006         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1007                 context->param3 |= cpu_to_be32(1 << 29);
1008                 ring->fcs_del = ETH_FCS_LEN;
1009         } else
1010                 ring->fcs_del = 0;
1011
1012         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1013         if (err) {
1014                 mlx4_qp_remove(mdev->dev, qp);
1015                 mlx4_qp_free(mdev->dev, qp);
1016         }
1017         mlx4_en_update_rx_prod_db(ring);
1018 out:
1019         kfree(context);
1020         return err;
1021 }
1022
1023 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1024 {
1025         int err;
1026         u32 qpn;
1027
1028         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
1029         if (err) {
1030                 en_err(priv, "Failed reserving drop qpn\n");
1031                 return err;
1032         }
1033         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1034         if (err) {
1035                 en_err(priv, "Failed allocating drop qp\n");
1036                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1037                 return err;
1038         }
1039
1040         return 0;
1041 }
1042
1043 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1044 {
1045         u32 qpn;
1046
1047         qpn = priv->drop_qp.qpn;
1048         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1049         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1050         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1051 }
1052
1053 /* Allocate rx qp's and configure them according to rss map */
1054 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1055 {
1056         struct mlx4_en_dev *mdev = priv->mdev;
1057         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1058         struct mlx4_qp_context context;
1059         struct mlx4_rss_context *rss_context;
1060         int rss_rings;
1061         void *ptr;
1062         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1063                         MLX4_RSS_TCP_IPV6);
1064         int i, qpn;
1065         int err = 0;
1066         int good_qps = 0;
1067         static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
1068                                 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
1069                                 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
1070
1071         en_dbg(DRV, priv, "Configuring rss steering\n");
1072         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1073                                     priv->rx_ring_num,
1074                                     &rss_map->base_qpn);
1075         if (err) {
1076                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1077                 return err;
1078         }
1079
1080         for (i = 0; i < priv->rx_ring_num; i++) {
1081                 qpn = rss_map->base_qpn + i;
1082                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1083                                             &rss_map->state[i],
1084                                             &rss_map->qps[i]);
1085                 if (err)
1086                         goto rss_err;
1087
1088                 ++good_qps;
1089         }
1090
1091         /* Configure RSS indirection qp */
1092         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1093         if (err) {
1094                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1095                 goto rss_err;
1096         }
1097         rss_map->indir_qp.event = mlx4_en_sqp_event;
1098         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1099                                 priv->rx_ring[0]->cqn, -1, &context);
1100
1101         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1102                 rss_rings = priv->rx_ring_num;
1103         else
1104                 rss_rings = priv->prof->rss_rings;
1105
1106         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1107                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1108         rss_context = ptr;
1109         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1110                                             (rss_map->base_qpn));
1111         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1112         if (priv->mdev->profile.udp_rss) {
1113                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1114                 rss_context->base_qpn_udp = rss_context->default_qpn;
1115         }
1116
1117         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1118                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1119                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1120         }
1121
1122         rss_context->flags = rss_mask;
1123         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1124         for (i = 0; i < 10; i++)
1125                 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
1126
1127         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1128                                &rss_map->indir_qp, &rss_map->indir_state);
1129         if (err)
1130                 goto indir_err;
1131
1132         return 0;
1133
1134 indir_err:
1135         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1136                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1137         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1138         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1139 rss_err:
1140         for (i = 0; i < good_qps; i++) {
1141                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1142                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1143                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1144                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1145         }
1146         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1147         return err;
1148 }
1149
1150 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1151 {
1152         struct mlx4_en_dev *mdev = priv->mdev;
1153         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1154         int i;
1155
1156         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1157                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1158         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1159         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1160
1161         for (i = 0; i < priv->rx_ring_num; i++) {
1162                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1163                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1164                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1165                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1166         }
1167         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1168 }