drivers/net/ethernet/mellanox/mlx4/mcg.c

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/string.h>
  35 #include <linux/etherdevice.h>
  36
  37 #include <linux/mlx4/cmd.h>
  38 #include <linux/export.h>
  39
  40 #include "mlx4.h"
  41
  42 #define MGM_QPN_MASK       0x00FFFFFF
  43 #define MGM_BLCK_LB_BIT    30
  44
  45 static const u8 zero_gid[16];   /* automatically initialized to 0 */
  46
  47 struct mlx4_mgm {
  48         __be32                  next_gid_index;
  49         __be32                  members_count;
  50         u32                     reserved[2];
  51         u8                      gid[16];
  52         __be32                  qp[MLX4_MAX_QP_PER_MGM];
  53 };
  54
  55 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
  56 {
  57         return 1 << dev->oper_log_mgm_entry_size;
  58 }
  59
  60 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
  61 {
  62         return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
  63 }
  64
  65 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
  66                                         struct mlx4_cmd_mailbox *mailbox,
  67                                         u32 size,
  68                                         u64 *reg_id)
  69 {
  70         u64 imm;
  71         int err = 0;
  72
  73         err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
  74                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  75                            MLX4_CMD_NATIVE);
  76         if (err)
  77                 return err;
  78         *reg_id = imm;
  79
  80         return err;
  81 }
  82
  83 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
  84 {
  85         int err = 0;
  86
  87         err = mlx4_cmd(dev, regid, 0, 0,
  88                        MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  89                        MLX4_CMD_NATIVE);
  90
  91         return err;
  92 }
  93
  94 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
  95                            struct mlx4_cmd_mailbox *mailbox)
  96 {
  97         return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
  98                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  99 }
 100
 101 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
 102                             struct mlx4_cmd_mailbox *mailbox)
 103 {
 104         return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
 105                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 106 }
 107
 108 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
 109                               struct mlx4_cmd_mailbox *mailbox)
 110 {
 111         u32 in_mod;
 112
 113         in_mod = (u32) port << 16 | steer << 1;
 114         return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
 115                         MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
 116                         MLX4_CMD_NATIVE);
 117 }
 118
 119 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 120                          u16 *hash, u8 op_mod)
 121 {
 122         u64 imm;
 123         int err;
 124
 125         err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
 126                            MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
 127                            MLX4_CMD_NATIVE);
 128
 129         if (!err)
 130                 *hash = imm;
 131
 132         return err;
 133 }
 134
 135 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
 136                                               enum mlx4_steer_type steer,
 137                                               u32 qpn)
 138 {
 139         struct mlx4_steer *s_steer = &mlx4_priv(dev)->steer[port - 1];
 140         struct mlx4_promisc_qp *pqp;
 141
 142         list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
 143                 if (pqp->qpn == qpn)
 144                         return pqp;
 145         }
 146         /* not found */
 147         return NULL;
 148 }
 149
 150 /*
 151  * Add new entry to steering data structure.
 152  * All promisc QPs should be added as well
 153  */
 154 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
 155                               enum mlx4_steer_type steer,
 156                               unsigned int index, u32 qpn)
 157 {
 158         struct mlx4_steer *s_steer;
 159         struct mlx4_cmd_mailbox *mailbox;
 160         struct mlx4_mgm *mgm;
 161         u32 members_count;
 162         struct mlx4_steer_index *new_entry;
 163         struct mlx4_promisc_qp *pqp;
 164         struct mlx4_promisc_qp *dqp = NULL;
 165         u32 prot;
 166         int err;
 167
 168         s_steer = &mlx4_priv(dev)->steer[port - 1];
 169         new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
 170         if (!new_entry)
 171                 return -ENOMEM;
 172
 173         INIT_LIST_HEAD(&new_entry->duplicates);
 174         new_entry->index = index;
 175         list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
 176
 177         /* If the given qpn is also a promisc qp,
 178          * it should be inserted to duplicates list
 179          */
 180         pqp = get_promisc_qp(dev, port, steer, qpn);
 181         if (pqp) {
 182                 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 183                 if (!dqp) {
 184                         err = -ENOMEM;
 185                         goto out_alloc;
 186                 }
 187                 dqp->qpn = qpn;
 188                 list_add_tail(&dqp->list, &new_entry->duplicates);
 189         }
 190
 191         /* if no promisc qps for this vep, we are done */
 192         if (list_empty(&s_steer->promisc_qps[steer]))
 193                 return 0;
 194
 195         /* now need to add all the promisc qps to the new
 196          * steering entry, as they should also receive the packets
 197          * destined to this address */
 198         mailbox = mlx4_alloc_cmd_mailbox(dev);
 199         if (IS_ERR(mailbox)) {
 200                 err = -ENOMEM;
 201                 goto out_alloc;
 202         }
 203         mgm = mailbox->buf;
 204
 205         err = mlx4_READ_ENTRY(dev, index, mailbox);
 206         if (err)
 207                 goto out_mailbox;
 208
 209         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 210         prot = be32_to_cpu(mgm->members_count) >> 30;
 211         list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
 212                 /* don't add already existing qpn */
 213                 if (pqp->qpn == qpn)
 214                         continue;
 215                 if (members_count == dev->caps.num_qp_per_mgm) {
 216                         /* out of space */
 217                         err = -ENOMEM;
 218                         goto out_mailbox;
 219                 }
 220
 221                 /* add the qpn */
 222                 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
 223         }
 224         /* update the qps count and update the entry with all the promisc qps*/
 225         mgm->members_count = cpu_to_be32(members_count | (prot << 30));
 226         err = mlx4_WRITE_ENTRY(dev, index, mailbox);
 227
 228 out_mailbox:
 229         mlx4_free_cmd_mailbox(dev, mailbox);
 230         if (!err)
 231                 return 0;
 232 out_alloc:
 233         if (dqp) {
 234                 list_del(&dqp->list);
 235                 kfree(dqp);
 236         }
 237         list_del(&new_entry->list);
 238         kfree(new_entry);
 239         return err;
 240 }
 241
 242 /* update the data structures with existing steering entry */
 243 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
 244                                    enum mlx4_steer_type steer,
 245                                    unsigned int index, u32 qpn)
 246 {
 247         struct mlx4_steer *s_steer;
 248         struct mlx4_steer_index *tmp_entry, *entry = NULL;
 249         struct mlx4_promisc_qp *pqp;
 250         struct mlx4_promisc_qp *dqp;
 251
 252         s_steer = &mlx4_priv(dev)->steer[port - 1];
 253
 254         pqp = get_promisc_qp(dev, port, steer, qpn);
 255         if (!pqp)
 256                 return 0; /* nothing to do */
 257
 258         list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
 259                 if (tmp_entry->index == index) {
 260                         entry = tmp_entry;
 261                         break;
 262                 }
 263         }
 264         if (unlikely(!entry)) {
 265                 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
 266                 return -EINVAL;
 267         }
 268
 269         /* the given qpn is listed as a promisc qpn
 270          * we need to add it as a duplicate to this entry
 271          * for future references */
 272         list_for_each_entry(dqp, &entry->duplicates, list) {
 273                 if (qpn == pqp->qpn)
 274                         return 0; /* qp is already duplicated */
 275         }
 276
 277         /* add the qp as a duplicate on this index */
 278         dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 279         if (!dqp)
 280                 return -ENOMEM;
 281         dqp->qpn = qpn;
 282         list_add_tail(&dqp->list, &entry->duplicates);
 283
 284         return 0;
 285 }
 286
 287 /* Check whether a qpn is a duplicate on steering entry
 288  * If so, it should not be removed from mgm */
 289 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
 290                                   enum mlx4_steer_type steer,
 291                                   unsigned int index, u32 qpn)
 292 {
 293         struct mlx4_steer *s_steer;
 294         struct mlx4_steer_index *tmp_entry, *entry = NULL;
 295         struct mlx4_promisc_qp *dqp, *tmp_dqp;
 296
 297         s_steer = &mlx4_priv(dev)->steer[port - 1];
 298
 299         /* if qp is not promisc, it cannot be duplicated */
 300         if (!get_promisc_qp(dev, port, steer, qpn))
 301                 return false;
 302
 303         /* The qp is promisc qp so it is a duplicate on this index
 304          * Find the index entry, and remove the duplicate */
 305         list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
 306                 if (tmp_entry->index == index) {
 307                         entry = tmp_entry;
 308                         break;
 309                 }
 310         }
 311         if (unlikely(!entry)) {
 312                 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
 313                 return false;
 314         }
 315         list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
 316                 if (dqp->qpn == qpn) {
 317                         list_del(&dqp->list);
 318                         kfree(dqp);
 319                 }
 320         }
 321         return true;
 322 }
 323
 324 /* I a steering entry contains only promisc QPs, it can be removed. */
 325 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
 326                                       enum mlx4_steer_type steer,
 327                                       unsigned int index, u32 tqpn)
 328 {
 329         struct mlx4_steer *s_steer;
 330         struct mlx4_cmd_mailbox *mailbox;
 331         struct mlx4_mgm *mgm;
 332         struct mlx4_steer_index *entry = NULL, *tmp_entry;
 333         u32 qpn;
 334         u32 members_count;
 335         bool ret = false;
 336         int i;
 337
 338         s_steer = &mlx4_priv(dev)->steer[port - 1];
 339
 340         mailbox = mlx4_alloc_cmd_mailbox(dev);
 341         if (IS_ERR(mailbox))
 342                 return false;
 343         mgm = mailbox->buf;
 344
 345         if (mlx4_READ_ENTRY(dev, index, mailbox))
 346                 goto out;
 347         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 348         for (i = 0;  i < members_count; i++) {
 349                 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
 350                 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
 351                         /* the qp is not promisc, the entry can't be removed */
 352                         goto out;
 353                 }
 354         }
 355          /* All the qps currently registered for this entry are promiscuous,
 356           * Checking for duplicates */
 357         ret = true;
 358         list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
 359                 if (entry->index == index) {
 360                         if (list_empty(&entry->duplicates)) {
 361                                 list_del(&entry->list);
 362                                 kfree(entry);
 363                         } else {
 364                                 /* This entry contains duplicates so it shouldn't be removed */
 365                                 ret = false;
 366                                 goto out;
 367                         }
 368                 }
 369         }
 370
 371 out:
 372         mlx4_free_cmd_mailbox(dev, mailbox);
 373         return ret;
 374 }
 375
 376 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
 377                           enum mlx4_steer_type steer, u32 qpn)
 378 {
 379         struct mlx4_steer *s_steer;
 380         struct mlx4_cmd_mailbox *mailbox;
 381         struct mlx4_mgm *mgm;
 382         struct mlx4_steer_index *entry;
 383         struct mlx4_promisc_qp *pqp;
 384         struct mlx4_promisc_qp *dqp;
 385         u32 members_count;
 386         u32 prot;
 387         int i;
 388         bool found;
 389         int err;
 390         struct mlx4_priv *priv = mlx4_priv(dev);
 391
 392         s_steer = &mlx4_priv(dev)->steer[port - 1];
 393
 394         mutex_lock(&priv->mcg_table.mutex);
 395
 396         if (get_promisc_qp(dev, port, steer, qpn)) {
 397                 err = 0;  /* Noting to do, already exists */
 398                 goto out_mutex;
 399         }
 400
 401         pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
 402         if (!pqp) {
 403                 err = -ENOMEM;
 404                 goto out_mutex;
 405         }
 406         pqp->qpn = qpn;
 407
 408         mailbox = mlx4_alloc_cmd_mailbox(dev);
 409         if (IS_ERR(mailbox)) {
 410                 err = -ENOMEM;
 411                 goto out_alloc;
 412         }
 413         mgm = mailbox->buf;
 414
 415         /* the promisc qp needs to be added for each one of the steering
 416          * entries, if it already exists, needs to be added as a duplicate
 417          * for this entry */
 418         list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
 419                 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
 420                 if (err)
 421                         goto out_mailbox;
 422
 423                 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 424                 prot = be32_to_cpu(mgm->members_count) >> 30;
 425                 found = false;
 426                 for (i = 0; i < members_count; i++) {
 427                         if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) {
 428                                 /* Entry already exists, add to duplicates */
 429                                 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 430                                 if (!dqp) {
 431                                         err = -ENOMEM;
 432                                         goto out_mailbox;
 433                                 }
 434                                 dqp->qpn = qpn;
 435                                 list_add_tail(&dqp->list, &entry->duplicates);
 436                                 found = true;
 437                         }
 438                 }
 439                 if (!found) {
 440                         /* Need to add the qpn to mgm */
 441                         if (members_count == dev->caps.num_qp_per_mgm) {
 442                                 /* entry is full */
 443                                 err = -ENOMEM;
 444                                 goto out_mailbox;
 445                         }
 446                         mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK);
 447                         mgm->members_count = cpu_to_be32(members_count | (prot << 30));
 448                         err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
 449                         if (err)
 450                                 goto out_mailbox;
 451                 }
 452         }
 453
 454         /* add the new qpn to list of promisc qps */
 455         list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
 456         /* now need to add all the promisc qps to default entry */
 457         memset(mgm, 0, sizeof *mgm);
 458         members_count = 0;
 459         list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
 460                 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
 461         mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
 462
 463         err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
 464         if (err)
 465                 goto out_list;
 466
 467         mlx4_free_cmd_mailbox(dev, mailbox);
 468         mutex_unlock(&priv->mcg_table.mutex);
 469         return 0;
 470
 471 out_list:
 472         list_del(&pqp->list);
 473 out_mailbox:
 474         mlx4_free_cmd_mailbox(dev, mailbox);
 475 out_alloc:
 476         kfree(pqp);
 477 out_mutex:
 478         mutex_unlock(&priv->mcg_table.mutex);
 479         return err;
 480 }
 481
 482 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
 483                              enum mlx4_steer_type steer, u32 qpn)
 484 {
 485         struct mlx4_priv *priv = mlx4_priv(dev);
 486         struct mlx4_steer *s_steer;
 487         struct mlx4_cmd_mailbox *mailbox;
 488         struct mlx4_mgm *mgm;
 489         struct mlx4_steer_index *entry;
 490         struct mlx4_promisc_qp *pqp;
 491         struct mlx4_promisc_qp *dqp;
 492         u32 members_count;
 493         bool found;
 494         bool back_to_list = false;
 495         int loc, i;
 496         int err;
 497
 498         s_steer = &mlx4_priv(dev)->steer[port - 1];
 499         mutex_lock(&priv->mcg_table.mutex);
 500
 501         pqp = get_promisc_qp(dev, port, steer, qpn);
 502         if (unlikely(!pqp)) {
 503                 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
 504                 /* nothing to do */
 505                 err = 0;
 506                 goto out_mutex;
 507         }
 508
 509         /*remove from list of promisc qps */
 510         list_del(&pqp->list);
 511
 512         /* set the default entry not to include the removed one */
 513         mailbox = mlx4_alloc_cmd_mailbox(dev);
 514         if (IS_ERR(mailbox)) {
 515                 err = -ENOMEM;
 516                 back_to_list = true;
 517                 goto out_list;
 518         }
 519         mgm = mailbox->buf;
 520         memset(mgm, 0, sizeof *mgm);
 521         members_count = 0;
 522         list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
 523                 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
 524         mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
 525
 526         err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
 527         if (err)
 528                 goto out_mailbox;
 529
 530         /* remove the qp from all the steering entries*/
 531         list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
 532                 found = false;
 533                 list_for_each_entry(dqp, &entry->duplicates, list) {
 534                         if (dqp->qpn == qpn) {
 535                                 found = true;
 536                                 break;
 537                         }
 538                 }
 539                 if (found) {
 540                         /* a duplicate, no need to change the mgm,
 541                          * only update the duplicates list */
 542                         list_del(&dqp->list);
 543                         kfree(dqp);
 544                 } else {
 545                         err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
 546                                 if (err)
 547                                         goto out_mailbox;
 548                         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 549                         for (loc = -1, i = 0; i < members_count; ++i)
 550                                 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn)
 551                                         loc = i;
 552
 553                         mgm->members_count = cpu_to_be32(--members_count |
 554                                                          (MLX4_PROT_ETH << 30));
 555                         mgm->qp[loc] = mgm->qp[i - 1];
 556                         mgm->qp[i - 1] = 0;
 557
 558                         err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
 559                                 if (err)
 560                                         goto out_mailbox;
 561                 }
 562
 563         }
 564
 565 out_mailbox:
 566         mlx4_free_cmd_mailbox(dev, mailbox);
 567 out_list:
 568         if (back_to_list)
 569                 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
 570         else
 571                 kfree(pqp);
 572 out_mutex:
 573         mutex_unlock(&priv->mcg_table.mutex);
 574         return err;
 575 }
 576
 577 /*
 578  * Caller must hold MCG table semaphore.  gid and mgm parameters must
 579  * be properly aligned for command interface.
 580  *
 581  *  Returns 0 unless a firmware command error occurs.
 582  *
 583  * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
 584  * and *mgm holds MGM entry.
 585  *
 586  * if GID is found in AMGM, *index = index in AMGM, *prev = index of
 587  * previous entry in hash chain and *mgm holds AMGM entry.
 588  *
 589  * If no AMGM exists for given gid, *index = -1, *prev = index of last
 590  * entry in hash chain and *mgm holds end of hash chain.
 591  */
 592 static int find_entry(struct mlx4_dev *dev, u8 port,
 593                       u8 *gid, enum mlx4_protocol prot,
 594                       struct mlx4_cmd_mailbox *mgm_mailbox,
 595                       int *prev, int *index)
 596 {
 597         struct mlx4_cmd_mailbox *mailbox;
 598         struct mlx4_mgm *mgm = mgm_mailbox->buf;
 599         u8 *mgid;
 600         int err;
 601         u16 hash;
 602         u8 op_mod = (prot == MLX4_PROT_ETH) ?
 603                 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
 604
 605         mailbox = mlx4_alloc_cmd_mailbox(dev);
 606         if (IS_ERR(mailbox))
 607                 return -ENOMEM;
 608         mgid = mailbox->buf;
 609
 610         memcpy(mgid, gid, 16);
 611
 612         err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
 613         mlx4_free_cmd_mailbox(dev, mailbox);
 614         if (err)
 615                 return err;
 616
 617         if (0)
 618                 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
 619
 620         *index = hash;
 621         *prev  = -1;
 622
 623         do {
 624                 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
 625                 if (err)
 626                         return err;
 627
 628                 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
 629                         if (*index != hash) {
 630                                 mlx4_err(dev, "Found zero MGID in AMGM.\n");
 631                                 err = -EINVAL;
 632                         }
 633                         return err;
 634                 }
 635
 636                 if (!memcmp(mgm->gid, gid, 16) &&
 637                     be32_to_cpu(mgm->members_count) >> 30 == prot)
 638                         return err;
 639
 640                 *prev = *index;
 641                 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
 642         } while (*index);
 643
 644         *index = -1;
 645         return err;
 646 }
 647
 648 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
 649                                   struct mlx4_net_trans_rule_hw_ctrl *hw)
 650 {
 651         static const u8 __promisc_mode[] = {
 652                 [MLX4_FS_REGULAR]       = 0x0,
 653                 [MLX4_FS_ALL_DEFAULT]   = 0x1,
 654                 [MLX4_FS_MC_DEFAULT]    = 0x3,
 655                 [MLX4_FS_UC_SNIFFER]    = 0x4,
 656                 [MLX4_FS_MC_SNIFFER]    = 0x5,
 657         };
 658
 659         u32 dw = 0;
 660
 661         dw = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
 662         dw |= ctrl->exclusive ? (1 << 2) : 0;
 663         dw |= ctrl->allow_loopback ? (1 << 3) : 0;
 664         dw |= __promisc_mode[ctrl->promisc_mode] << 8;
 665         dw |= ctrl->priority << 16;
 666
 667         hw->ctrl = cpu_to_be32(dw);
 668         hw->port = ctrl->port;
 669         hw->qpn = cpu_to_be32(ctrl->qpn);
 670 }
 671
 672 const u16 __sw_id_hw[] = {
 673         [MLX4_NET_TRANS_RULE_ID_ETH]     = 0xE001,
 674         [MLX4_NET_TRANS_RULE_ID_IB]      = 0xE005,
 675         [MLX4_NET_TRANS_RULE_ID_IPV6]    = 0xE003,
 676         [MLX4_NET_TRANS_RULE_ID_IPV4]    = 0xE002,
 677         [MLX4_NET_TRANS_RULE_ID_TCP]     = 0xE004,
 678         [MLX4_NET_TRANS_RULE_ID_UDP]     = 0xE006
 679 };
 680
 681 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
 682                             struct _rule_hw *rule_hw)
 683 {
 684         static const size_t __rule_hw_sz[] = {
 685                 [MLX4_NET_TRANS_RULE_ID_ETH] =
 686                         sizeof(struct mlx4_net_trans_rule_hw_eth),
 687                 [MLX4_NET_TRANS_RULE_ID_IB] =
 688                         sizeof(struct mlx4_net_trans_rule_hw_ib),
 689                 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
 690                 [MLX4_NET_TRANS_RULE_ID_IPV4] =
 691                         sizeof(struct mlx4_net_trans_rule_hw_ipv4),
 692                 [MLX4_NET_TRANS_RULE_ID_TCP] =
 693                         sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
 694                 [MLX4_NET_TRANS_RULE_ID_UDP] =
 695                         sizeof(struct mlx4_net_trans_rule_hw_tcp_udp)
 696         };
 697         if (spec->id >= MLX4_NET_TRANS_RULE_NUM) {
 698                 mlx4_err(dev, "Invalid network rule id. id = %d\n", spec->id);
 699                 return -EINVAL;
 700         }
 701         memset(rule_hw, 0, __rule_hw_sz[spec->id]);
 702         rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
 703         rule_hw->size = __rule_hw_sz[spec->id] >> 2;
 704
 705         switch (spec->id) {
 706         case MLX4_NET_TRANS_RULE_ID_ETH:
 707                 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
 708                 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
 709                        ETH_ALEN);
 710                 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
 711                 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
 712                        ETH_ALEN);
 713                 if (spec->eth.ether_type_enable) {
 714                         rule_hw->eth.ether_type_enable = 1;
 715                         rule_hw->eth.ether_type = spec->eth.ether_type;
 716                 }
 717                 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
 718                 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
 719                 break;
 720
 721         case MLX4_NET_TRANS_RULE_ID_IB:
 722                 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
 723                 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
 724                 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
 725                 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
 726                 break;
 727
 728         case MLX4_NET_TRANS_RULE_ID_IPV6:
 729                 return -EOPNOTSUPP;
 730
 731         case MLX4_NET_TRANS_RULE_ID_IPV4:
 732                 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
 733                 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
 734                 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
 735                 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
 736                 break;
 737
 738         case MLX4_NET_TRANS_RULE_ID_TCP:
 739         case MLX4_NET_TRANS_RULE_ID_UDP:
 740                 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
 741                 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
 742                 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
 743                 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
 744                 break;
 745
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         return __rule_hw_sz[spec->id];
 751 }
 752
 753 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
 754                           struct mlx4_net_trans_rule *rule)
 755 {
 756 #define BUF_SIZE 256
 757         struct mlx4_spec_list *cur;
 758         char buf[BUF_SIZE];
 759         int len = 0;
 760
 761         mlx4_err(dev, "%s", str);
 762         len += snprintf(buf + len, BUF_SIZE - len,
 763                         "port = %d prio = 0x%x qp = 0x%x ",
 764                         rule->port, rule->priority, rule->qpn);
 765
 766         list_for_each_entry(cur, &rule->list, list) {
 767                 switch (cur->id) {
 768                 case MLX4_NET_TRANS_RULE_ID_ETH:
 769                         len += snprintf(buf + len, BUF_SIZE - len,
 770                                         "dmac = %pM ", &cur->eth.dst_mac);
 771                         if (cur->eth.ether_type)
 772                                 len += snprintf(buf + len, BUF_SIZE - len,
 773                                                 "ethertype = 0x%x ",
 774                                                 be16_to_cpu(cur->eth.ether_type));
 775                         if (cur->eth.vlan_id)
 776                                 len += snprintf(buf + len, BUF_SIZE - len,
 777                                                 "vlan-id = %d ",
 778                                                 be16_to_cpu(cur->eth.vlan_id));
 779                         break;
 780
 781                 case MLX4_NET_TRANS_RULE_ID_IPV4:
 782                         if (cur->ipv4.src_ip)
 783                                 len += snprintf(buf + len, BUF_SIZE - len,
 784                                                 "src-ip = %pI4 ",
 785                                                 &cur->ipv4.src_ip);
 786                         if (cur->ipv4.dst_ip)
 787                                 len += snprintf(buf + len, BUF_SIZE - len,
 788                                                 "dst-ip = %pI4 ",
 789                                                 &cur->ipv4.dst_ip);
 790                         break;
 791
 792                 case MLX4_NET_TRANS_RULE_ID_TCP:
 793                 case MLX4_NET_TRANS_RULE_ID_UDP:
 794                         if (cur->tcp_udp.src_port)
 795                                 len += snprintf(buf + len, BUF_SIZE - len,
 796                                                 "src-port = %d ",
 797                                                 be16_to_cpu(cur->tcp_udp.src_port));
 798                         if (cur->tcp_udp.dst_port)
 799                                 len += snprintf(buf + len, BUF_SIZE - len,
 800                                                 "dst-port = %d ",
 801                                                 be16_to_cpu(cur->tcp_udp.dst_port));
 802                         break;
 803
 804                 case MLX4_NET_TRANS_RULE_ID_IB:
 805                         len += snprintf(buf + len, BUF_SIZE - len,
 806                                         "dst-gid = %pI6\n", cur->ib.dst_gid);
 807                         len += snprintf(buf + len, BUF_SIZE - len,
 808                                         "dst-gid-mask = %pI6\n",
 809                                         cur->ib.dst_gid_msk);
 810                         break;
 811
 812                 case MLX4_NET_TRANS_RULE_ID_IPV6:
 813                         break;
 814
 815                 default:
 816                         break;
 817                 }
 818         }
 819         len += snprintf(buf + len, BUF_SIZE - len, "\n");
 820         mlx4_err(dev, "%s", buf);
 821
 822         if (len >= BUF_SIZE)
 823                 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small.\n");
 824 }
 825
 826 int mlx4_flow_attach(struct mlx4_dev *dev,
 827                      struct mlx4_net_trans_rule *rule, u64 *reg_id)
 828 {
 829         struct mlx4_cmd_mailbox *mailbox;
 830         struct mlx4_spec_list *cur;
 831         u32 size = 0;
 832         int ret;
 833
 834         mailbox = mlx4_alloc_cmd_mailbox(dev);
 835         if (IS_ERR(mailbox))
 836                 return PTR_ERR(mailbox);
 837
 838         memset(mailbox->buf, 0, sizeof(struct mlx4_net_trans_rule_hw_ctrl));
 839         trans_rule_ctrl_to_hw(rule, mailbox->buf);
 840
 841         size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
 842
 843         list_for_each_entry(cur, &rule->list, list) {
 844                 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
 845                 if (ret < 0) {
 846                         mlx4_free_cmd_mailbox(dev, mailbox);
 847                         return -EINVAL;
 848                 }
 849                 size += ret;
 850         }
 851
 852         ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
 853         if (ret == -ENOMEM)
 854                 mlx4_err_rule(dev,
 855                               "mcg table is full. Fail to register network rule.\n",
 856                               rule);
 857         else if (ret)
 858                 mlx4_err_rule(dev, "Fail to register network rule.\n", rule);
 859
 860         mlx4_free_cmd_mailbox(dev, mailbox);
 861
 862         return ret;
 863 }
 864 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
 865
 866 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
 867 {
 868         int err;
 869
 870         err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
 871         if (err)
 872                 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
 873                          reg_id);
 874         return err;
 875 }
 876 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
 877
 878 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 879                           int block_mcast_loopback, enum mlx4_protocol prot,
 880                           enum mlx4_steer_type steer)
 881 {
 882         struct mlx4_priv *priv = mlx4_priv(dev);
 883         struct mlx4_cmd_mailbox *mailbox;
 884         struct mlx4_mgm *mgm;
 885         u32 members_count;
 886         int index, prev;
 887         int link = 0;
 888         int i;
 889         int err;
 890         u8 port = gid[5];
 891         u8 new_entry = 0;
 892
 893         mailbox = mlx4_alloc_cmd_mailbox(dev);
 894         if (IS_ERR(mailbox))
 895                 return PTR_ERR(mailbox);
 896         mgm = mailbox->buf;
 897
 898         mutex_lock(&priv->mcg_table.mutex);
 899         err = find_entry(dev, port, gid, prot,
 900                          mailbox, &prev, &index);
 901         if (err)
 902                 goto out;
 903
 904         if (index != -1) {
 905                 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
 906                         new_entry = 1;
 907                         memcpy(mgm->gid, gid, 16);
 908                 }
 909         } else {
 910                 link = 1;
 911
 912                 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
 913                 if (index == -1) {
 914                         mlx4_err(dev, "No AMGM entries left\n");
 915                         err = -ENOMEM;
 916                         goto out;
 917                 }
 918                 index += dev->caps.num_mgms;
 919
 920                 new_entry = 1;
 921                 memset(mgm, 0, sizeof *mgm);
 922                 memcpy(mgm->gid, gid, 16);
 923         }
 924
 925         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 926         if (members_count == dev->caps.num_qp_per_mgm) {
 927                 mlx4_err(dev, "MGM at index %x is full.\n", index);
 928                 err = -ENOMEM;
 929                 goto out;
 930         }
 931
 932         for (i = 0; i < members_count; ++i)
 933                 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
 934                         mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
 935                         err = 0;
 936                         goto out;
 937                 }
 938
 939         if (block_mcast_loopback)
 940                 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
 941                                                        (1U << MGM_BLCK_LB_BIT));
 942         else
 943                 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
 944
 945         mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
 946
 947         err = mlx4_WRITE_ENTRY(dev, index, mailbox);
 948         if (err)
 949                 goto out;
 950
 951         if (!link)
 952                 goto out;
 953
 954         err = mlx4_READ_ENTRY(dev, prev, mailbox);
 955         if (err)
 956                 goto out;
 957
 958         mgm->next_gid_index = cpu_to_be32(index << 6);
 959
 960         err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
 961         if (err)
 962                 goto out;
 963
 964 out:
 965         if (prot == MLX4_PROT_ETH) {
 966                 /* manage the steering entry for promisc mode */
 967                 if (new_entry)
 968                         new_steering_entry(dev, port, steer, index, qp->qpn);
 969                 else
 970                         existing_steering_entry(dev, port, steer,
 971                                                 index, qp->qpn);
 972         }
 973         if (err && link && index != -1) {
 974                 if (index < dev->caps.num_mgms)
 975                         mlx4_warn(dev, "Got AMGM index %d < %d",
 976                                   index, dev->caps.num_mgms);
 977                 else
 978                         mlx4_bitmap_free(&priv->mcg_table.bitmap,
 979                                          index - dev->caps.num_mgms);
 980         }
 981         mutex_unlock(&priv->mcg_table.mutex);
 982
 983         mlx4_free_cmd_mailbox(dev, mailbox);
 984         return err;
 985 }
 986
 987 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 988                           enum mlx4_protocol prot, enum mlx4_steer_type steer)
 989 {
 990         struct mlx4_priv *priv = mlx4_priv(dev);
 991         struct mlx4_cmd_mailbox *mailbox;
 992         struct mlx4_mgm *mgm;
 993         u32 members_count;
 994         int prev, index;
 995         int i, loc;
 996         int err;
 997         u8 port = gid[5];
 998         bool removed_entry = false;
 999
1000         mailbox = mlx4_alloc_cmd_mailbox(dev);
1001         if (IS_ERR(mailbox))
1002                 return PTR_ERR(mailbox);
1003         mgm = mailbox->buf;
1004
1005         mutex_lock(&priv->mcg_table.mutex);
1006
1007         err = find_entry(dev, port, gid, prot,
1008                          mailbox, &prev, &index);
1009         if (err)
1010                 goto out;
1011
1012         if (index == -1) {
1013                 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1014                 err = -EINVAL;
1015                 goto out;
1016         }
1017
1018         /* if this pq is also a promisc qp, it shouldn't be removed */
1019         if (prot == MLX4_PROT_ETH &&
1020             check_duplicate_entry(dev, port, steer, index, qp->qpn))
1021                 goto out;
1022
1023         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1024         for (loc = -1, i = 0; i < members_count; ++i)
1025                 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn)
1026                         loc = i;
1027
1028         if (loc == -1) {
1029                 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1030                 err = -EINVAL;
1031                 goto out;
1032         }
1033
1034
1035         mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1036         mgm->qp[loc]       = mgm->qp[i - 1];
1037         mgm->qp[i - 1]     = 0;
1038
1039         if (prot == MLX4_PROT_ETH)
1040                 removed_entry = can_remove_steering_entry(dev, port, steer,
1041                                                                 index, qp->qpn);
1042         if (i != 1 && (prot != MLX4_PROT_ETH || !removed_entry)) {
1043                 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1044                 goto out;
1045         }
1046
1047         /* We are going to delete the entry, members count should be 0 */
1048         mgm->members_count = cpu_to_be32((u32) prot << 30);
1049
1050         if (prev == -1) {
1051                 /* Remove entry from MGM */
1052                 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1053                 if (amgm_index) {
1054                         err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1055                         if (err)
1056                                 goto out;
1057                 } else
1058                         memset(mgm->gid, 0, 16);
1059
1060                 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1061                 if (err)
1062                         goto out;
1063
1064                 if (amgm_index) {
1065                         if (amgm_index < dev->caps.num_mgms)
1066                                 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d",
1067                                           index, amgm_index, dev->caps.num_mgms);
1068                         else
1069                                 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1070                                                  amgm_index - dev->caps.num_mgms);
1071                 }
1072         } else {
1073                 /* Remove entry from AMGM */
1074                 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1075                 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1076                 if (err)
1077                         goto out;
1078
1079                 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1080
1081                 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1082                 if (err)
1083                         goto out;
1084
1085                 if (index < dev->caps.num_mgms)
1086                         mlx4_warn(dev, "entry %d had next AMGM index %d < %d",
1087                                   prev, index, dev->caps.num_mgms);
1088                 else
1089                         mlx4_bitmap_free(&priv->mcg_table.bitmap,
1090                                          index - dev->caps.num_mgms);
1091         }
1092
1093 out:
1094         mutex_unlock(&priv->mcg_table.mutex);
1095
1096         mlx4_free_cmd_mailbox(dev, mailbox);
1097         return err;
1098 }
1099
1100 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1101                           u8 gid[16], u8 attach, u8 block_loopback,
1102                           enum mlx4_protocol prot)
1103 {
1104         struct mlx4_cmd_mailbox *mailbox;
1105         int err = 0;
1106         int qpn;
1107
1108         if (!mlx4_is_mfunc(dev))
1109                 return -EBADF;
1110
1111         mailbox = mlx4_alloc_cmd_mailbox(dev);
1112         if (IS_ERR(mailbox))
1113                 return PTR_ERR(mailbox);
1114
1115         memcpy(mailbox->buf, gid, 16);
1116         qpn = qp->qpn;
1117         qpn |= (prot << 28);
1118         if (attach && block_loopback)
1119                 qpn |= (1 << 31);
1120
1121         err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1122                        MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1123                        MLX4_CMD_WRAPPED);
1124
1125         mlx4_free_cmd_mailbox(dev, mailbox);
1126         return err;
1127 }
1128
1129 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1130                           u8 port, int block_mcast_loopback,
1131                           enum mlx4_protocol prot, u64 *reg_id)
1132 {
1133
1134         switch (dev->caps.steering_mode) {
1135         case MLX4_STEERING_MODE_A0:
1136                 if (prot == MLX4_PROT_ETH)
1137                         return 0;
1138
1139         case MLX4_STEERING_MODE_B0:
1140                 if (prot == MLX4_PROT_ETH)
1141                         gid[7] |= (MLX4_MC_STEER << 1);
1142
1143                 if (mlx4_is_mfunc(dev))
1144                         return mlx4_QP_ATTACH(dev, qp, gid, 1,
1145                                               block_mcast_loopback, prot);
1146                 return mlx4_qp_attach_common(dev, qp, gid,
1147                                              block_mcast_loopback, prot,
1148                                              MLX4_MC_STEER);
1149
1150         case MLX4_STEERING_MODE_DEVICE_MANAGED: {
1151                 struct mlx4_spec_list spec = { {NULL} };
1152                 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1153
1154                 struct mlx4_net_trans_rule rule = {
1155                         .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1156                         .exclusive = 0,
1157                         .promisc_mode = MLX4_FS_REGULAR,
1158                         .priority = MLX4_DOMAIN_NIC,
1159                 };
1160
1161                 rule.allow_loopback = !block_mcast_loopback;
1162                 rule.port = port;
1163                 rule.qpn = qp->qpn;
1164                 INIT_LIST_HEAD(&rule.list);
1165
1166                 switch (prot) {
1167                 case MLX4_PROT_ETH:
1168                         spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1169                         memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1170                         memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1171                         break;
1172
1173                 case MLX4_PROT_IB_IPV6:
1174                         spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1175                         memcpy(spec.ib.dst_gid, gid, 16);
1176                         memset(&spec.ib.dst_gid_msk, 0xff, 16);
1177                         break;
1178                 default:
1179                         return -EINVAL;
1180                 }
1181                 list_add_tail(&spec.list, &rule.list);
1182
1183                 return mlx4_flow_attach(dev, &rule, reg_id);
1184         }
1185
1186         default:
1187                 return -EINVAL;
1188         }
1189 }
1190 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1191
1192 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1193                           enum mlx4_protocol prot, u64 reg_id)
1194 {
1195         switch (dev->caps.steering_mode) {
1196         case MLX4_STEERING_MODE_A0:
1197                 if (prot == MLX4_PROT_ETH)
1198                         return 0;
1199
1200         case MLX4_STEERING_MODE_B0:
1201                 if (prot == MLX4_PROT_ETH)
1202                         gid[7] |= (MLX4_MC_STEER << 1);
1203
1204                 if (mlx4_is_mfunc(dev))
1205                         return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1206
1207                 return mlx4_qp_detach_common(dev, qp, gid, prot,
1208                                              MLX4_MC_STEER);
1209
1210         case MLX4_STEERING_MODE_DEVICE_MANAGED:
1211                 return mlx4_flow_detach(dev, reg_id);
1212
1213         default:
1214                 return -EINVAL;
1215         }
1216 }
1217 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1218
1219 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1220                                 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1221 {
1222         struct mlx4_net_trans_rule rule;
1223         u64 *regid_p;
1224
1225         switch (mode) {
1226         case MLX4_FS_ALL_DEFAULT:
1227                 regid_p = &dev->regid_promisc_array[port];
1228                 break;
1229         case MLX4_FS_MC_DEFAULT:
1230                 regid_p = &dev->regid_allmulti_array[port];
1231                 break;
1232         default:
1233                 return -1;
1234         }
1235
1236         if (*regid_p != 0)
1237                 return -1;
1238
1239         rule.promisc_mode = mode;
1240         rule.port = port;
1241         rule.qpn = qpn;
1242         INIT_LIST_HEAD(&rule.list);
1243         mlx4_err(dev, "going promisc on %x\n", port);
1244
1245         return  mlx4_flow_attach(dev, &rule, regid_p);
1246 }
1247 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1248
1249 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1250                                    enum mlx4_net_trans_promisc_mode mode)
1251 {
1252         int ret;
1253         u64 *regid_p;
1254
1255         switch (mode) {
1256         case MLX4_FS_ALL_DEFAULT:
1257                 regid_p = &dev->regid_promisc_array[port];
1258                 break;
1259         case MLX4_FS_MC_DEFAULT:
1260                 regid_p = &dev->regid_allmulti_array[port];
1261                 break;
1262         default:
1263                 return -1;
1264         }
1265
1266         if (*regid_p == 0)
1267                 return -1;
1268
1269         ret =  mlx4_flow_detach(dev, *regid_p);
1270         if (ret == 0)
1271                 *regid_p = 0;
1272
1273         return ret;
1274 }
1275 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1276
1277 int mlx4_unicast_attach(struct mlx4_dev *dev,
1278                         struct mlx4_qp *qp, u8 gid[16],
1279                         int block_mcast_loopback, enum mlx4_protocol prot)
1280 {
1281         if (prot == MLX4_PROT_ETH)
1282                 gid[7] |= (MLX4_UC_STEER << 1);
1283
1284         if (mlx4_is_mfunc(dev))
1285                 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1286                                         block_mcast_loopback, prot);
1287
1288         return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1289                                         prot, MLX4_UC_STEER);
1290 }
1291 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1292
1293 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1294                                u8 gid[16], enum mlx4_protocol prot)
1295 {
1296         if (prot == MLX4_PROT_ETH)
1297                 gid[7] |= (MLX4_UC_STEER << 1);
1298
1299         if (mlx4_is_mfunc(dev))
1300                 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1301
1302         return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1303 }
1304 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1305
1306 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1307                          struct mlx4_vhcr *vhcr,
1308                          struct mlx4_cmd_mailbox *inbox,
1309                          struct mlx4_cmd_mailbox *outbox,
1310                          struct mlx4_cmd_info *cmd)
1311 {
1312         u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1313         u8 port = vhcr->in_param >> 62;
1314         enum mlx4_steer_type steer = vhcr->in_modifier;
1315
1316         /* Promiscuous unicast is not allowed in mfunc */
1317         if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1318                 return 0;
1319
1320         if (vhcr->op_modifier)
1321                 return add_promisc_qp(dev, port, steer, qpn);
1322         else
1323                 return remove_promisc_qp(dev, port, steer, qpn);
1324 }
1325
1326 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1327                         enum mlx4_steer_type steer, u8 add, u8 port)
1328 {
1329         return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1330                         MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1331                         MLX4_CMD_WRAPPED);
1332 }
1333
1334 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1335 {
1336         if (mlx4_is_mfunc(dev))
1337                 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1338
1339         return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1340 }
1341 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1342
1343 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1344 {
1345         if (mlx4_is_mfunc(dev))
1346                 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1347
1348         return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1349 }
1350 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1351
1352 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1353 {
1354         if (mlx4_is_mfunc(dev))
1355                 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1356
1357         return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1358 }
1359 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1360
1361 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1362 {
1363         if (mlx4_is_mfunc(dev))
1364                 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1365
1366         return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1367 }
1368 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1369
1370 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1371 {
1372         struct mlx4_priv *priv = mlx4_priv(dev);
1373         int err;
1374
1375         /* No need for mcg_table when fw managed the mcg table*/
1376         if (dev->caps.steering_mode ==
1377             MLX4_STEERING_MODE_DEVICE_MANAGED)
1378                 return 0;
1379         err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1380                                dev->caps.num_amgms - 1, 0, 0);
1381         if (err)
1382                 return err;
1383
1384         mutex_init(&priv->mcg_table.mutex);
1385
1386         return 0;
1387 }
1388
1389 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1390 {
1391         if (dev->caps.steering_mode !=
1392             MLX4_STEERING_MODE_DEVICE_MANAGED)
1393                 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);
1394 }