2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
65 MLX4_FS_L2_L3_L4_HASH,
70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71 #define MLX4_RATELIMIT_DEFAULT 0xffff
73 struct mlx4_set_port_prio2tc_context {
77 struct mlx4_port_scheduler_tc_cfg_be {
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
84 struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
120 MLX4_MR_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
153 MLX4_NUM_OF_RESOURCE_TYPE
156 enum mlx4_alloc_mode {
158 RES_OP_RESERVE_AND_MAP,
162 enum mlx4_res_tracker_free_type {
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
188 struct mlx4_vhcr_cmd {
199 struct mlx4_cmd_info {
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
219 #define mlx4_dbg(mdev, format, arg...) \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
246 unsigned long *table;
250 unsigned long **bits;
251 unsigned int *num_free;
258 struct mlx4_icm_table {
266 struct mlx4_icm **icm;
270 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
272 struct mlx4_mpt_entry {
286 __be32 first_byte_offset;
290 * Must be packed because start is 64 bits but only aligned to 32 bits.
292 struct mlx4_eq_context {
306 __be32 mtt_base_addr_l;
308 __be32 consumer_index;
309 __be32 producer_index;
313 struct mlx4_cq_context {
317 __be32 logsize_usrpage;
325 __be32 mtt_base_addr_l;
326 __be32 last_notified_index;
327 __be32 solicit_producer_index;
328 __be32 consumer_index;
329 __be32 producer_index;
334 struct mlx4_srq_context {
335 __be32 state_logsize_srqn;
339 __be32 pg_offset_cqn;
344 __be32 mtt_base_addr_l;
346 __be16 limit_watermark;
355 struct mlx4_dev *dev;
356 void __iomem *doorbell;
362 struct mlx4_buf_list *page_list;
366 struct mlx4_slave_eqe {
372 struct mlx4_slave_event_eq_info {
377 struct mlx4_profile {
391 struct mlx4_icm *fw_icm;
392 struct mlx4_icm *aux_icm;
406 MLX4_MCAST_CONFIG = 0,
407 MLX4_MCAST_DISABLE = 1,
408 MLX4_MCAST_ENABLE = 2,
411 #define VLAN_FLTR_SIZE 128
413 struct mlx4_vlan_fltr {
414 __be32 entry[VLAN_FLTR_SIZE];
417 struct mlx4_mcast_entry {
418 struct list_head list;
422 struct mlx4_promisc_qp {
423 struct list_head list;
427 struct mlx4_steer_index {
428 struct list_head list;
430 struct list_head duplicates;
433 #define MLX4_EVENT_TYPES_NUM 64
435 struct mlx4_slave_state {
442 u16 mtu[MLX4_MAX_PORTS + 1];
443 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
444 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
445 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
446 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
447 /* event type to eq number lookup */
448 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
452 /*initialized via the kzalloc*/
453 u8 is_slave_going_down;
455 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
460 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
463 struct mlx4_resource_tracker {
465 /* tree for each resources */
466 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
467 /* num_of_slave's lists, one per slave */
468 struct slave_list *slave_list;
471 #define SLAVE_EVENT_EQ_SIZE 128
472 struct mlx4_slave_event_eq {
476 spinlock_t event_lock;
477 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
480 struct mlx4_master_qp0_state {
481 int proxy_qp0_active;
486 struct mlx4_mfunc_master_ctx {
487 struct mlx4_slave_state *slave_state;
488 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
489 int init_port_ref[MLX4_MAX_PORTS + 1];
490 u16 max_mtu[MLX4_MAX_PORTS + 1];
491 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
492 struct mlx4_resource_tracker res_tracker;
493 struct workqueue_struct *comm_wq;
494 struct work_struct comm_work;
495 struct work_struct slave_event_work;
496 struct work_struct slave_flr_event_work;
497 spinlock_t slave_state_lock;
498 __be32 comm_arm_bit_vector[4];
499 struct mlx4_eqe cmd_eqe;
500 struct mlx4_slave_event_eq slave_eq;
501 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
505 struct mlx4_comm __iomem *comm;
506 struct mlx4_vhcr_cmd *vhcr;
509 struct mlx4_mfunc_master_ctx master;
513 struct pci_pool *pool;
515 struct mutex hcr_mutex;
516 struct mutex slave_cmd_mutex;
517 struct semaphore poll_sem;
518 struct semaphore event_sem;
520 spinlock_t context_lock;
522 struct mlx4_cmd_context *context;
529 struct mlx4_uar_table {
530 struct mlx4_bitmap bitmap;
533 struct mlx4_mr_table {
534 struct mlx4_bitmap mpt_bitmap;
535 struct mlx4_buddy mtt_buddy;
538 struct mlx4_icm_table mtt_table;
539 struct mlx4_icm_table dmpt_table;
542 struct mlx4_cq_table {
543 struct mlx4_bitmap bitmap;
545 struct radix_tree_root tree;
546 struct mlx4_icm_table table;
547 struct mlx4_icm_table cmpt_table;
550 struct mlx4_eq_table {
551 struct mlx4_bitmap bitmap;
553 void __iomem *clr_int;
554 void __iomem **uar_map;
557 struct mlx4_icm_table table;
558 struct mlx4_icm_table cmpt_table;
563 struct mlx4_srq_table {
564 struct mlx4_bitmap bitmap;
566 struct radix_tree_root tree;
567 struct mlx4_icm_table table;
568 struct mlx4_icm_table cmpt_table;
571 struct mlx4_qp_table {
572 struct mlx4_bitmap bitmap;
576 struct mlx4_icm_table qp_table;
577 struct mlx4_icm_table auxc_table;
578 struct mlx4_icm_table altc_table;
579 struct mlx4_icm_table rdmarc_table;
580 struct mlx4_icm_table cmpt_table;
583 struct mlx4_mcg_table {
585 struct mlx4_bitmap bitmap;
586 struct mlx4_icm_table table;
589 struct mlx4_catas_err {
591 struct timer_list timer;
592 struct list_head list;
595 #define MLX4_MAX_MAC_NUM 128
596 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
598 struct mlx4_mac_table {
599 __be64 entries[MLX4_MAX_MAC_NUM];
600 int refs[MLX4_MAX_MAC_NUM];
606 #define MLX4_MAX_VLAN_NUM 128
607 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
609 struct mlx4_vlan_table {
610 __be32 entries[MLX4_MAX_VLAN_NUM];
611 int refs[MLX4_MAX_VLAN_NUM];
617 #define SET_PORT_GEN_ALL_VALID 0x7
618 #define SET_PORT_PROMISC_SHIFT 31
619 #define SET_PORT_MC_PROMISC_SHIFT 30
622 MCAST_DIRECT_ONLY = 0,
628 struct mlx4_set_port_general_context {
641 struct mlx4_set_port_rqp_calc_context {
659 struct mlx4_mac_entry {
664 struct mlx4_port_info {
665 struct mlx4_dev *dev;
668 struct device_attribute port_attr;
669 enum mlx4_port_type tmp_type;
670 char dev_mtu_name[16];
671 struct device_attribute port_mtu_attr;
672 struct mlx4_mac_table mac_table;
673 struct radix_tree_root mac_tree;
674 struct mlx4_vlan_table vlan_table;
679 struct mlx4_dev *dev;
680 u8 do_sense_port[MLX4_MAX_PORTS + 1];
681 u8 sense_allowed[MLX4_MAX_PORTS + 1];
682 struct delayed_work sense_poll;
685 struct mlx4_msix_ctl {
687 struct mutex pool_lock;
691 struct list_head promisc_qps[MLX4_NUM_STEERS];
692 struct list_head steer_entries[MLX4_NUM_STEERS];
695 struct mlx4_net_trans_rule_hw_ctrl {
702 struct mlx4_net_trans_rule_hw_ib {
713 struct mlx4_net_trans_rule_hw_eth {
726 u8 ether_type_enable;
732 struct mlx4_net_trans_rule_hw_tcp_udp {
746 struct mlx4_net_trans_rule_hw_ipv4 {
764 struct mlx4_net_trans_rule_hw_eth eth;
765 struct mlx4_net_trans_rule_hw_ib ib;
766 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
767 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
772 MLX4_PCI_DEV_IS_VF = 1 << 0,
773 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
779 struct list_head dev_list;
780 struct list_head ctx_list;
785 struct list_head pgdir_list;
786 struct mutex pgdir_mutex;
790 struct mlx4_mfunc mfunc;
792 struct mlx4_bitmap pd_bitmap;
793 struct mlx4_bitmap xrcd_bitmap;
794 struct mlx4_uar_table uar_table;
795 struct mlx4_mr_table mr_table;
796 struct mlx4_cq_table cq_table;
797 struct mlx4_eq_table eq_table;
798 struct mlx4_srq_table srq_table;
799 struct mlx4_qp_table qp_table;
800 struct mlx4_mcg_table mcg_table;
801 struct mlx4_bitmap counters_bitmap;
803 struct mlx4_catas_err catas_err;
805 void __iomem *clr_base;
807 struct mlx4_uar driver_uar;
809 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
810 struct mlx4_sense sense;
811 struct mutex port_mutex;
812 struct mlx4_msix_ctl msix_ctl;
813 struct mlx4_steer *steer;
814 struct list_head bf_list;
815 struct mutex bf_mutex;
816 struct io_mapping *bf_mapping;
819 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
820 __be64 slave_node_guids[MLX4_MFUNC_MAX];
824 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
826 return container_of(dev, struct mlx4_priv, dev);
829 #define MLX4_SENSE_RANGE (HZ * 3)
831 extern struct workqueue_struct *mlx4_wq;
833 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
834 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
835 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
836 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
837 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
838 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
839 u32 reserved_bot, u32 resetrved_top);
840 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
842 int mlx4_reset(struct mlx4_dev *dev);
844 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
845 void mlx4_free_eq_table(struct mlx4_dev *dev);
847 int mlx4_init_pd_table(struct mlx4_dev *dev);
848 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
849 int mlx4_init_uar_table(struct mlx4_dev *dev);
850 int mlx4_init_mr_table(struct mlx4_dev *dev);
851 int mlx4_init_eq_table(struct mlx4_dev *dev);
852 int mlx4_init_cq_table(struct mlx4_dev *dev);
853 int mlx4_init_qp_table(struct mlx4_dev *dev);
854 int mlx4_init_srq_table(struct mlx4_dev *dev);
855 int mlx4_init_mcg_table(struct mlx4_dev *dev);
857 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
858 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
859 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
860 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
861 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
862 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
863 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
864 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
865 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
866 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
867 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
868 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
869 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
870 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
871 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
872 int __mlx4_mr_reserve(struct mlx4_dev *dev);
873 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
874 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
875 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
876 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
877 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
879 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
880 struct mlx4_vhcr *vhcr,
881 struct mlx4_cmd_mailbox *inbox,
882 struct mlx4_cmd_mailbox *outbox,
883 struct mlx4_cmd_info *cmd);
884 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
885 struct mlx4_vhcr *vhcr,
886 struct mlx4_cmd_mailbox *inbox,
887 struct mlx4_cmd_mailbox *outbox,
888 struct mlx4_cmd_info *cmd);
889 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
890 struct mlx4_vhcr *vhcr,
891 struct mlx4_cmd_mailbox *inbox,
892 struct mlx4_cmd_mailbox *outbox,
893 struct mlx4_cmd_info *cmd);
894 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
895 struct mlx4_vhcr *vhcr,
896 struct mlx4_cmd_mailbox *inbox,
897 struct mlx4_cmd_mailbox *outbox,
898 struct mlx4_cmd_info *cmd);
899 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
916 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
917 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
918 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
919 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
920 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
921 int start_index, int npages, u64 *page_list);
922 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
923 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
924 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
925 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
927 void mlx4_start_catas_poll(struct mlx4_dev *dev);
928 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
929 void mlx4_catas_init(void);
930 int mlx4_restart_one(struct pci_dev *pdev);
931 int mlx4_register_device(struct mlx4_dev *dev);
932 void mlx4_unregister_device(struct mlx4_dev *dev);
933 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
934 unsigned long param);
937 struct mlx4_init_hca_param;
939 u64 mlx4_make_profile(struct mlx4_dev *dev,
940 struct mlx4_profile *request,
941 struct mlx4_dev_cap *dev_cap,
942 struct mlx4_init_hca_param *init_hca);
943 void mlx4_master_comm_channel(struct work_struct *work);
944 void mlx4_gen_slave_eqe(struct work_struct *work);
945 void mlx4_master_handle_slave_flr(struct work_struct *work);
947 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
959 struct mlx4_cmd_mailbox *outbox,
960 struct mlx4_cmd_info *cmd);
961 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
962 struct mlx4_vhcr *vhcr,
963 struct mlx4_cmd_mailbox *inbox,
964 struct mlx4_cmd_mailbox *outbox,
965 struct mlx4_cmd_info *cmd);
966 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
967 struct mlx4_vhcr *vhcr,
968 struct mlx4_cmd_mailbox *inbox,
969 struct mlx4_cmd_mailbox *outbox,
970 struct mlx4_cmd_info *cmd);
971 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
972 struct mlx4_vhcr *vhcr,
973 struct mlx4_cmd_mailbox *inbox,
974 struct mlx4_cmd_mailbox *outbox,
975 struct mlx4_cmd_info *cmd);
976 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
977 struct mlx4_vhcr *vhcr,
978 struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd);
981 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
982 struct mlx4_vhcr *vhcr,
983 struct mlx4_cmd_mailbox *inbox,
984 struct mlx4_cmd_mailbox *outbox,
985 struct mlx4_cmd_info *cmd);
986 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd);
996 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr,
998 struct mlx4_cmd_mailbox *inbox,
999 struct mlx4_cmd_mailbox *outbox,
1000 struct mlx4_cmd_info *cmd);
1001 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1002 struct mlx4_vhcr *vhcr,
1003 struct mlx4_cmd_mailbox *inbox,
1004 struct mlx4_cmd_mailbox *outbox,
1005 struct mlx4_cmd_info *cmd);
1006 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1007 struct mlx4_vhcr *vhcr,
1008 struct mlx4_cmd_mailbox *inbox,
1009 struct mlx4_cmd_mailbox *outbox,
1010 struct mlx4_cmd_info *cmd);
1011 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1012 struct mlx4_vhcr *vhcr,
1013 struct mlx4_cmd_mailbox *inbox,
1014 struct mlx4_cmd_mailbox *outbox,
1015 struct mlx4_cmd_info *cmd);
1016 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr,
1018 struct mlx4_cmd_mailbox *inbox,
1019 struct mlx4_cmd_mailbox *outbox,
1020 struct mlx4_cmd_info *cmd);
1021 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1022 struct mlx4_vhcr *vhcr,
1023 struct mlx4_cmd_mailbox *inbox,
1024 struct mlx4_cmd_mailbox *outbox,
1025 struct mlx4_cmd_info *cmd);
1026 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1027 struct mlx4_vhcr *vhcr,
1028 struct mlx4_cmd_mailbox *inbox,
1029 struct mlx4_cmd_mailbox *outbox,
1030 struct mlx4_cmd_info *cmd);
1031 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1032 struct mlx4_vhcr *vhcr,
1033 struct mlx4_cmd_mailbox *inbox,
1034 struct mlx4_cmd_mailbox *outbox,
1035 struct mlx4_cmd_info *cmd);
1036 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1037 struct mlx4_vhcr *vhcr,
1038 struct mlx4_cmd_mailbox *inbox,
1039 struct mlx4_cmd_mailbox *outbox,
1040 struct mlx4_cmd_info *cmd);
1041 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1042 struct mlx4_vhcr *vhcr,
1043 struct mlx4_cmd_mailbox *inbox,
1044 struct mlx4_cmd_mailbox *outbox,
1045 struct mlx4_cmd_info *cmd);
1046 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd);
1051 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1052 struct mlx4_vhcr *vhcr,
1053 struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1082 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1084 int mlx4_cmd_init(struct mlx4_dev *dev);
1085 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1086 int mlx4_multi_func_init(struct mlx4_dev *dev);
1087 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1088 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1089 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1090 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1092 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1093 unsigned long timeout);
1095 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1096 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1098 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1100 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1102 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1104 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1105 enum mlx4_port_type *type);
1106 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1107 enum mlx4_port_type *stype,
1108 enum mlx4_port_type *defaults);
1109 void mlx4_start_sense(struct mlx4_dev *dev);
1110 void mlx4_stop_sense(struct mlx4_dev *dev);
1111 void mlx4_sense_init(struct mlx4_dev *dev);
1112 int mlx4_check_port_params(struct mlx4_dev *dev,
1113 enum mlx4_port_type *port_type);
1114 int mlx4_change_port_types(struct mlx4_dev *dev,
1115 enum mlx4_port_type *port_types);
1117 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1118 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1120 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1121 /* resource tracker functions*/
1122 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1123 enum mlx4_resource resource_type,
1124 u64 resource_id, int *slave);
1125 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1126 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1128 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1129 enum mlx4_res_tracker_free_type type);
1131 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1132 struct mlx4_vhcr *vhcr,
1133 struct mlx4_cmd_mailbox *inbox,
1134 struct mlx4_cmd_mailbox *outbox,
1135 struct mlx4_cmd_info *cmd);
1136 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1137 struct mlx4_vhcr *vhcr,
1138 struct mlx4_cmd_mailbox *inbox,
1139 struct mlx4_cmd_mailbox *outbox,
1140 struct mlx4_cmd_info *cmd);
1141 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1142 struct mlx4_vhcr *vhcr,
1143 struct mlx4_cmd_mailbox *inbox,
1144 struct mlx4_cmd_mailbox *outbox,
1145 struct mlx4_cmd_info *cmd);
1146 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1147 struct mlx4_vhcr *vhcr,
1148 struct mlx4_cmd_mailbox *inbox,
1149 struct mlx4_cmd_mailbox *outbox,
1150 struct mlx4_cmd_info *cmd);
1151 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1152 struct mlx4_vhcr *vhcr,
1153 struct mlx4_cmd_mailbox *inbox,
1154 struct mlx4_cmd_mailbox *outbox,
1155 struct mlx4_cmd_info *cmd);
1156 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1157 struct mlx4_vhcr *vhcr,
1158 struct mlx4_cmd_mailbox *inbox,
1159 struct mlx4_cmd_mailbox *outbox,
1160 struct mlx4_cmd_info *cmd);
1161 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1163 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1164 int *gid_tbl_len, int *pkey_tbl_len);
1166 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1167 struct mlx4_vhcr *vhcr,
1168 struct mlx4_cmd_mailbox *inbox,
1169 struct mlx4_cmd_mailbox *outbox,
1170 struct mlx4_cmd_info *cmd);
1172 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1173 struct mlx4_vhcr *vhcr,
1174 struct mlx4_cmd_mailbox *inbox,
1175 struct mlx4_cmd_mailbox *outbox,
1176 struct mlx4_cmd_info *cmd);
1177 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1178 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1179 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1180 int block_mcast_loopback, enum mlx4_protocol prot,
1181 enum mlx4_steer_type steer);
1182 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1183 struct mlx4_vhcr *vhcr,
1184 struct mlx4_cmd_mailbox *inbox,
1185 struct mlx4_cmd_mailbox *outbox,
1186 struct mlx4_cmd_info *cmd);
1187 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1188 struct mlx4_vhcr *vhcr,
1189 struct mlx4_cmd_mailbox *inbox,
1190 struct mlx4_cmd_mailbox *outbox,
1191 struct mlx4_cmd_info *cmd);
1192 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1193 int port, void *buf);
1194 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1195 struct mlx4_cmd_mailbox *outbox);
1196 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1197 struct mlx4_vhcr *vhcr,
1198 struct mlx4_cmd_mailbox *inbox,
1199 struct mlx4_cmd_mailbox *outbox,
1200 struct mlx4_cmd_info *cmd);
1201 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1202 struct mlx4_vhcr *vhcr,
1203 struct mlx4_cmd_mailbox *inbox,
1204 struct mlx4_cmd_mailbox *outbox,
1205 struct mlx4_cmd_info *cmd);
1206 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1207 struct mlx4_vhcr *vhcr,
1208 struct mlx4_cmd_mailbox *inbox,
1209 struct mlx4_cmd_mailbox *outbox,
1210 struct mlx4_cmd_info *cmd);
1211 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1212 struct mlx4_vhcr *vhcr,
1213 struct mlx4_cmd_mailbox *inbox,
1214 struct mlx4_cmd_mailbox *outbox,
1215 struct mlx4_cmd_info *cmd);
1216 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1217 struct mlx4_vhcr *vhcr,
1218 struct mlx4_cmd_mailbox *inbox,
1219 struct mlx4_cmd_mailbox *outbox,
1220 struct mlx4_cmd_info *cmd);
1222 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1223 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1225 static inline void set_param_l(u64 *arg, u32 val)
1227 *((u32 *)arg) = val;
1230 static inline void set_param_h(u64 *arg, u32 val)
1232 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1235 static inline u32 get_param_l(u64 *arg)
1237 return (u32) (*arg & 0xffffffff);
1240 static inline u32 get_param_h(u64 *arg)
1242 return (u32)(*arg >> 32);
1245 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1247 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1250 #define NOT_MASKED_PD_BITS 17