2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 MLX4_FS_L2_L3_L4_HASH,
72 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
73 #define MLX4_RATELIMIT_DEFAULT 0xffff
75 struct mlx4_set_port_prio2tc_context {
79 struct mlx4_port_scheduler_tc_cfg_be {
82 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
86 struct mlx4_set_port_scheduler_context {
87 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
91 MLX4_HCR_BASE = 0x80680,
92 MLX4_HCR_SIZE = 0x0001c,
93 MLX4_CLR_INT_SIZE = 0x00008,
94 MLX4_SLAVE_COMM_BASE = 0x0,
95 MLX4_COMM_PAGESIZE = 0x1000
99 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
100 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
101 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
102 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
103 MLX4_MTT_ENTRY_PER_SEG = 8,
107 MLX4_NUM_PDS = 1 << 15
111 MLX4_CMPT_TYPE_QP = 0,
112 MLX4_CMPT_TYPE_SRQ = 1,
113 MLX4_CMPT_TYPE_CQ = 2,
114 MLX4_CMPT_TYPE_EQ = 3,
119 MLX4_CMPT_SHIFT = 24,
120 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
123 enum mlx4_mpt_state {
124 MLX4_MPT_DISABLED = 0,
129 #define MLX4_COMM_TIME 10000
135 MLX4_COMM_CMD_VHCR_EN,
136 MLX4_COMM_CMD_VHCR_POST,
137 MLX4_COMM_CMD_FLR = 254
140 /*The flag indicates that the slave should delay the RESET cmd*/
141 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
142 /*indicates how many retries will be done if we are in the middle of FLR*/
143 #define NUM_OF_RESET_RETRIES 10
144 #define SLEEP_TIME_IN_RESET (2 * 1000)
157 MLX4_NUM_OF_RESOURCE_TYPE
160 enum mlx4_alloc_mode {
162 RES_OP_RESERVE_AND_MAP,
166 enum mlx4_res_tracker_free_type {
168 RES_TR_FREE_SLAVES_ONLY,
169 RES_TR_FREE_STRUCTS_ONLY,
173 *Virtual HCR structures.
174 * mlx4_vhcr is the sw representation, in machine endianess
176 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
177 * to FW to go through communication channel.
178 * It is big endian, and has the same structure as the physical HCR
179 * used by command interface
192 struct mlx4_vhcr_cmd {
203 struct mlx4_cmd_info {
208 bool encode_slave_id;
209 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
210 struct mlx4_cmd_mailbox *inbox);
211 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
212 struct mlx4_cmd_mailbox *inbox,
213 struct mlx4_cmd_mailbox *outbox,
214 struct mlx4_cmd_info *cmd);
217 #ifdef CONFIG_MLX4_DEBUG
218 extern int mlx4_debug_level;
219 #else /* CONFIG_MLX4_DEBUG */
220 #define mlx4_debug_level (0)
221 #endif /* CONFIG_MLX4_DEBUG */
223 #define mlx4_dbg(mdev, format, arg...) \
225 if (mlx4_debug_level) \
226 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
229 #define mlx4_err(mdev, format, arg...) \
230 dev_err(&mdev->pdev->dev, format, ##arg)
231 #define mlx4_info(mdev, format, arg...) \
232 dev_info(&mdev->pdev->dev, format, ##arg)
233 #define mlx4_warn(mdev, format, arg...) \
234 dev_warn(&mdev->pdev->dev, format, ##arg)
236 extern int mlx4_log_num_mgm_entry_size;
237 extern int log_mtts_per_seg;
239 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
240 #define ALL_SLAVES 0xff
250 unsigned long *table;
254 unsigned long **bits;
255 unsigned int *num_free;
262 struct mlx4_icm_table {
270 struct mlx4_icm **icm;
273 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
274 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
275 #define MLX4_MPT_FLAG_MIO (1 << 17)
276 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
277 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
278 #define MLX4_MPT_FLAG_REGION (1 << 8)
280 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
281 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
282 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
284 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
286 #define MLX4_MPT_STATUS_SW 0xF0
287 #define MLX4_MPT_STATUS_HW 0x00
290 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
292 struct mlx4_mpt_entry {
306 __be32 first_byte_offset;
310 * Must be packed because start is 64 bits but only aligned to 32 bits.
312 struct mlx4_eq_context {
326 __be32 mtt_base_addr_l;
328 __be32 consumer_index;
329 __be32 producer_index;
333 struct mlx4_cq_context {
337 __be32 logsize_usrpage;
345 __be32 mtt_base_addr_l;
346 __be32 last_notified_index;
347 __be32 solicit_producer_index;
348 __be32 consumer_index;
349 __be32 producer_index;
354 struct mlx4_srq_context {
355 __be32 state_logsize_srqn;
359 __be32 pg_offset_cqn;
364 __be32 mtt_base_addr_l;
366 __be16 limit_watermark;
375 struct mlx4_dev *dev;
376 void __iomem *doorbell;
382 struct mlx4_buf_list *page_list;
386 struct mlx4_slave_eqe {
392 struct mlx4_slave_event_eq_info {
397 struct mlx4_profile {
411 struct mlx4_icm *fw_icm;
412 struct mlx4_icm *aux_icm;
426 MLX4_MCAST_CONFIG = 0,
427 MLX4_MCAST_DISABLE = 1,
428 MLX4_MCAST_ENABLE = 2,
431 #define VLAN_FLTR_SIZE 128
433 struct mlx4_vlan_fltr {
434 __be32 entry[VLAN_FLTR_SIZE];
437 struct mlx4_mcast_entry {
438 struct list_head list;
442 struct mlx4_promisc_qp {
443 struct list_head list;
447 struct mlx4_steer_index {
448 struct list_head list;
450 struct list_head duplicates;
453 #define MLX4_EVENT_TYPES_NUM 64
455 struct mlx4_slave_state {
462 u16 mtu[MLX4_MAX_PORTS + 1];
463 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
464 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
465 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
466 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
467 /* event type to eq number lookup */
468 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
472 /*initialized via the kzalloc*/
473 u8 is_slave_going_down;
475 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
480 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
483 struct mlx4_resource_tracker {
485 /* tree for each resources */
486 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
487 /* num_of_slave's lists, one per slave */
488 struct slave_list *slave_list;
491 #define SLAVE_EVENT_EQ_SIZE 128
492 struct mlx4_slave_event_eq {
496 spinlock_t event_lock;
497 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
500 struct mlx4_master_qp0_state {
501 int proxy_qp0_active;
506 struct mlx4_mfunc_master_ctx {
507 struct mlx4_slave_state *slave_state;
508 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
509 int init_port_ref[MLX4_MAX_PORTS + 1];
510 u16 max_mtu[MLX4_MAX_PORTS + 1];
511 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
512 struct mlx4_resource_tracker res_tracker;
513 struct workqueue_struct *comm_wq;
514 struct work_struct comm_work;
515 struct work_struct slave_event_work;
516 struct work_struct slave_flr_event_work;
517 spinlock_t slave_state_lock;
518 __be32 comm_arm_bit_vector[4];
519 struct mlx4_eqe cmd_eqe;
520 struct mlx4_slave_event_eq slave_eq;
521 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
525 struct mlx4_comm __iomem *comm;
526 struct mlx4_vhcr_cmd *vhcr;
529 struct mlx4_mfunc_master_ctx master;
533 struct pci_pool *pool;
535 struct mutex hcr_mutex;
536 struct mutex slave_cmd_mutex;
537 struct semaphore poll_sem;
538 struct semaphore event_sem;
540 spinlock_t context_lock;
542 struct mlx4_cmd_context *context;
549 struct mlx4_uar_table {
550 struct mlx4_bitmap bitmap;
553 struct mlx4_mr_table {
554 struct mlx4_bitmap mpt_bitmap;
555 struct mlx4_buddy mtt_buddy;
558 struct mlx4_icm_table mtt_table;
559 struct mlx4_icm_table dmpt_table;
562 struct mlx4_cq_table {
563 struct mlx4_bitmap bitmap;
565 struct radix_tree_root tree;
566 struct mlx4_icm_table table;
567 struct mlx4_icm_table cmpt_table;
570 struct mlx4_eq_table {
571 struct mlx4_bitmap bitmap;
573 void __iomem *clr_int;
574 void __iomem **uar_map;
577 struct mlx4_icm_table table;
578 struct mlx4_icm_table cmpt_table;
583 struct mlx4_srq_table {
584 struct mlx4_bitmap bitmap;
586 struct radix_tree_root tree;
587 struct mlx4_icm_table table;
588 struct mlx4_icm_table cmpt_table;
591 struct mlx4_qp_table {
592 struct mlx4_bitmap bitmap;
596 struct mlx4_icm_table qp_table;
597 struct mlx4_icm_table auxc_table;
598 struct mlx4_icm_table altc_table;
599 struct mlx4_icm_table rdmarc_table;
600 struct mlx4_icm_table cmpt_table;
603 struct mlx4_mcg_table {
605 struct mlx4_bitmap bitmap;
606 struct mlx4_icm_table table;
609 struct mlx4_catas_err {
611 struct timer_list timer;
612 struct list_head list;
615 #define MLX4_MAX_MAC_NUM 128
616 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
618 struct mlx4_mac_table {
619 __be64 entries[MLX4_MAX_MAC_NUM];
620 int refs[MLX4_MAX_MAC_NUM];
626 #define MLX4_MAX_VLAN_NUM 128
627 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
629 struct mlx4_vlan_table {
630 __be32 entries[MLX4_MAX_VLAN_NUM];
631 int refs[MLX4_MAX_VLAN_NUM];
637 #define SET_PORT_GEN_ALL_VALID 0x7
638 #define SET_PORT_PROMISC_SHIFT 31
639 #define SET_PORT_MC_PROMISC_SHIFT 30
642 MCAST_DIRECT_ONLY = 0,
648 struct mlx4_set_port_general_context {
661 struct mlx4_set_port_rqp_calc_context {
679 struct mlx4_mac_entry {
684 struct mlx4_port_info {
685 struct mlx4_dev *dev;
688 struct device_attribute port_attr;
689 enum mlx4_port_type tmp_type;
690 char dev_mtu_name[16];
691 struct device_attribute port_mtu_attr;
692 struct mlx4_mac_table mac_table;
693 struct radix_tree_root mac_tree;
694 struct mlx4_vlan_table vlan_table;
699 struct mlx4_dev *dev;
700 u8 do_sense_port[MLX4_MAX_PORTS + 1];
701 u8 sense_allowed[MLX4_MAX_PORTS + 1];
702 struct delayed_work sense_poll;
705 struct mlx4_msix_ctl {
707 struct mutex pool_lock;
711 struct list_head promisc_qps[MLX4_NUM_STEERS];
712 struct list_head steer_entries[MLX4_NUM_STEERS];
715 struct mlx4_net_trans_rule_hw_ctrl {
722 struct mlx4_net_trans_rule_hw_ib {
733 struct mlx4_net_trans_rule_hw_eth {
746 u8 ether_type_enable;
752 struct mlx4_net_trans_rule_hw_tcp_udp {
766 struct mlx4_net_trans_rule_hw_ipv4 {
784 struct mlx4_net_trans_rule_hw_eth eth;
785 struct mlx4_net_trans_rule_hw_ib ib;
786 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
787 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
792 MLX4_PCI_DEV_IS_VF = 1 << 0,
793 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
799 struct list_head dev_list;
800 struct list_head ctx_list;
805 struct list_head pgdir_list;
806 struct mutex pgdir_mutex;
810 struct mlx4_mfunc mfunc;
812 struct mlx4_bitmap pd_bitmap;
813 struct mlx4_bitmap xrcd_bitmap;
814 struct mlx4_uar_table uar_table;
815 struct mlx4_mr_table mr_table;
816 struct mlx4_cq_table cq_table;
817 struct mlx4_eq_table eq_table;
818 struct mlx4_srq_table srq_table;
819 struct mlx4_qp_table qp_table;
820 struct mlx4_mcg_table mcg_table;
821 struct mlx4_bitmap counters_bitmap;
823 struct mlx4_catas_err catas_err;
825 void __iomem *clr_base;
827 struct mlx4_uar driver_uar;
829 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
830 struct mlx4_sense sense;
831 struct mutex port_mutex;
832 struct mlx4_msix_ctl msix_ctl;
833 struct mlx4_steer *steer;
834 struct list_head bf_list;
835 struct mutex bf_mutex;
836 struct io_mapping *bf_mapping;
839 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
840 __be64 slave_node_guids[MLX4_MFUNC_MAX];
844 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
846 return container_of(dev, struct mlx4_priv, dev);
849 #define MLX4_SENSE_RANGE (HZ * 3)
851 extern struct workqueue_struct *mlx4_wq;
853 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
854 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
855 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
856 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
857 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
858 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
859 u32 reserved_bot, u32 resetrved_top);
860 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
862 int mlx4_reset(struct mlx4_dev *dev);
864 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
865 void mlx4_free_eq_table(struct mlx4_dev *dev);
867 int mlx4_init_pd_table(struct mlx4_dev *dev);
868 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
869 int mlx4_init_uar_table(struct mlx4_dev *dev);
870 int mlx4_init_mr_table(struct mlx4_dev *dev);
871 int mlx4_init_eq_table(struct mlx4_dev *dev);
872 int mlx4_init_cq_table(struct mlx4_dev *dev);
873 int mlx4_init_qp_table(struct mlx4_dev *dev);
874 int mlx4_init_srq_table(struct mlx4_dev *dev);
875 int mlx4_init_mcg_table(struct mlx4_dev *dev);
877 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
878 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
879 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
880 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
881 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
882 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
883 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
884 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
885 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
886 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
887 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
888 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
889 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
890 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
891 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
892 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
893 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
894 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
895 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
896 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
897 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
899 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr,
916 struct mlx4_cmd_mailbox *inbox,
917 struct mlx4_cmd_mailbox *outbox,
918 struct mlx4_cmd_info *cmd);
919 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr,
921 struct mlx4_cmd_mailbox *inbox,
922 struct mlx4_cmd_mailbox *outbox,
923 struct mlx4_cmd_info *cmd);
924 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
925 struct mlx4_vhcr *vhcr,
926 struct mlx4_cmd_mailbox *inbox,
927 struct mlx4_cmd_mailbox *outbox,
928 struct mlx4_cmd_info *cmd);
929 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
936 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
937 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
938 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
939 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
940 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
941 int start_index, int npages, u64 *page_list);
942 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
943 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
944 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
945 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
947 void mlx4_start_catas_poll(struct mlx4_dev *dev);
948 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
949 void mlx4_catas_init(void);
950 int mlx4_restart_one(struct pci_dev *pdev);
951 int mlx4_register_device(struct mlx4_dev *dev);
952 void mlx4_unregister_device(struct mlx4_dev *dev);
953 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
954 unsigned long param);
957 struct mlx4_init_hca_param;
959 u64 mlx4_make_profile(struct mlx4_dev *dev,
960 struct mlx4_profile *request,
961 struct mlx4_dev_cap *dev_cap,
962 struct mlx4_init_hca_param *init_hca);
963 void mlx4_master_comm_channel(struct work_struct *work);
964 void mlx4_gen_slave_eqe(struct work_struct *work);
965 void mlx4_master_handle_slave_flr(struct work_struct *work);
967 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd);
981 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
982 struct mlx4_vhcr *vhcr,
983 struct mlx4_cmd_mailbox *inbox,
984 struct mlx4_cmd_mailbox *outbox,
985 struct mlx4_cmd_info *cmd);
986 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd);
996 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr,
998 struct mlx4_cmd_mailbox *inbox,
999 struct mlx4_cmd_mailbox *outbox,
1000 struct mlx4_cmd_info *cmd);
1001 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1002 struct mlx4_vhcr *vhcr,
1003 struct mlx4_cmd_mailbox *inbox,
1004 struct mlx4_cmd_mailbox *outbox,
1005 struct mlx4_cmd_info *cmd);
1006 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1007 struct mlx4_vhcr *vhcr,
1008 struct mlx4_cmd_mailbox *inbox,
1009 struct mlx4_cmd_mailbox *outbox,
1010 struct mlx4_cmd_info *cmd);
1011 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1012 struct mlx4_vhcr *vhcr,
1013 struct mlx4_cmd_mailbox *inbox,
1014 struct mlx4_cmd_mailbox *outbox,
1015 struct mlx4_cmd_info *cmd);
1016 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr,
1018 struct mlx4_cmd_mailbox *inbox,
1019 struct mlx4_cmd_mailbox *outbox,
1020 struct mlx4_cmd_info *cmd);
1021 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1022 struct mlx4_vhcr *vhcr,
1023 struct mlx4_cmd_mailbox *inbox,
1024 struct mlx4_cmd_mailbox *outbox,
1025 struct mlx4_cmd_info *cmd);
1026 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1027 struct mlx4_vhcr *vhcr,
1028 struct mlx4_cmd_mailbox *inbox,
1029 struct mlx4_cmd_mailbox *outbox,
1030 struct mlx4_cmd_info *cmd);
1031 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1032 struct mlx4_vhcr *vhcr,
1033 struct mlx4_cmd_mailbox *inbox,
1034 struct mlx4_cmd_mailbox *outbox,
1035 struct mlx4_cmd_info *cmd);
1036 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1037 struct mlx4_vhcr *vhcr,
1038 struct mlx4_cmd_mailbox *inbox,
1039 struct mlx4_cmd_mailbox *outbox,
1040 struct mlx4_cmd_info *cmd);
1041 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1042 struct mlx4_vhcr *vhcr,
1043 struct mlx4_cmd_mailbox *inbox,
1044 struct mlx4_cmd_mailbox *outbox,
1045 struct mlx4_cmd_info *cmd);
1046 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd);
1051 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1052 struct mlx4_vhcr *vhcr,
1053 struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1087 struct mlx4_vhcr *vhcr,
1088 struct mlx4_cmd_mailbox *inbox,
1089 struct mlx4_cmd_mailbox *outbox,
1090 struct mlx4_cmd_info *cmd);
1091 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd);
1096 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
1102 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1104 int mlx4_cmd_init(struct mlx4_dev *dev);
1105 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1106 int mlx4_multi_func_init(struct mlx4_dev *dev);
1107 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1108 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1109 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1110 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1112 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1113 unsigned long timeout);
1115 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1116 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1118 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1120 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1122 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1124 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1125 enum mlx4_port_type *type);
1126 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1127 enum mlx4_port_type *stype,
1128 enum mlx4_port_type *defaults);
1129 void mlx4_start_sense(struct mlx4_dev *dev);
1130 void mlx4_stop_sense(struct mlx4_dev *dev);
1131 void mlx4_sense_init(struct mlx4_dev *dev);
1132 int mlx4_check_port_params(struct mlx4_dev *dev,
1133 enum mlx4_port_type *port_type);
1134 int mlx4_change_port_types(struct mlx4_dev *dev,
1135 enum mlx4_port_type *port_types);
1137 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1138 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1140 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1141 /* resource tracker functions*/
1142 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1143 enum mlx4_resource resource_type,
1144 u64 resource_id, int *slave);
1145 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1146 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1148 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1149 enum mlx4_res_tracker_free_type type);
1151 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1152 struct mlx4_vhcr *vhcr,
1153 struct mlx4_cmd_mailbox *inbox,
1154 struct mlx4_cmd_mailbox *outbox,
1155 struct mlx4_cmd_info *cmd);
1156 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1157 struct mlx4_vhcr *vhcr,
1158 struct mlx4_cmd_mailbox *inbox,
1159 struct mlx4_cmd_mailbox *outbox,
1160 struct mlx4_cmd_info *cmd);
1161 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1162 struct mlx4_vhcr *vhcr,
1163 struct mlx4_cmd_mailbox *inbox,
1164 struct mlx4_cmd_mailbox *outbox,
1165 struct mlx4_cmd_info *cmd);
1166 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1167 struct mlx4_vhcr *vhcr,
1168 struct mlx4_cmd_mailbox *inbox,
1169 struct mlx4_cmd_mailbox *outbox,
1170 struct mlx4_cmd_info *cmd);
1171 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1172 struct mlx4_vhcr *vhcr,
1173 struct mlx4_cmd_mailbox *inbox,
1174 struct mlx4_cmd_mailbox *outbox,
1175 struct mlx4_cmd_info *cmd);
1176 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1177 struct mlx4_vhcr *vhcr,
1178 struct mlx4_cmd_mailbox *inbox,
1179 struct mlx4_cmd_mailbox *outbox,
1180 struct mlx4_cmd_info *cmd);
1181 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1183 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1184 int *gid_tbl_len, int *pkey_tbl_len);
1186 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1187 struct mlx4_vhcr *vhcr,
1188 struct mlx4_cmd_mailbox *inbox,
1189 struct mlx4_cmd_mailbox *outbox,
1190 struct mlx4_cmd_info *cmd);
1192 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1193 struct mlx4_vhcr *vhcr,
1194 struct mlx4_cmd_mailbox *inbox,
1195 struct mlx4_cmd_mailbox *outbox,
1196 struct mlx4_cmd_info *cmd);
1197 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1198 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1199 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1200 int block_mcast_loopback, enum mlx4_protocol prot,
1201 enum mlx4_steer_type steer);
1202 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1203 struct mlx4_vhcr *vhcr,
1204 struct mlx4_cmd_mailbox *inbox,
1205 struct mlx4_cmd_mailbox *outbox,
1206 struct mlx4_cmd_info *cmd);
1207 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1208 struct mlx4_vhcr *vhcr,
1209 struct mlx4_cmd_mailbox *inbox,
1210 struct mlx4_cmd_mailbox *outbox,
1211 struct mlx4_cmd_info *cmd);
1212 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1213 int port, void *buf);
1214 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1215 struct mlx4_cmd_mailbox *outbox);
1216 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1217 struct mlx4_vhcr *vhcr,
1218 struct mlx4_cmd_mailbox *inbox,
1219 struct mlx4_cmd_mailbox *outbox,
1220 struct mlx4_cmd_info *cmd);
1221 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1222 struct mlx4_vhcr *vhcr,
1223 struct mlx4_cmd_mailbox *inbox,
1224 struct mlx4_cmd_mailbox *outbox,
1225 struct mlx4_cmd_info *cmd);
1226 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1227 struct mlx4_vhcr *vhcr,
1228 struct mlx4_cmd_mailbox *inbox,
1229 struct mlx4_cmd_mailbox *outbox,
1230 struct mlx4_cmd_info *cmd);
1231 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1232 struct mlx4_vhcr *vhcr,
1233 struct mlx4_cmd_mailbox *inbox,
1234 struct mlx4_cmd_mailbox *outbox,
1235 struct mlx4_cmd_info *cmd);
1236 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1237 struct mlx4_vhcr *vhcr,
1238 struct mlx4_cmd_mailbox *inbox,
1239 struct mlx4_cmd_mailbox *outbox,
1240 struct mlx4_cmd_info *cmd);
1242 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1243 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1245 static inline void set_param_l(u64 *arg, u32 val)
1247 *((u32 *)arg) = val;
1250 static inline void set_param_h(u64 *arg, u32 val)
1252 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1255 static inline u32 get_param_l(u64 *arg)
1257 return (u32) (*arg & 0xffffffff);
1260 static inline u32 get_param_h(u64 *arg)
1262 return (u32)(*arg >> 32);
1265 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1267 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1270 #define NOT_MASKED_PD_BITS 17