2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #ifdef CONFIG_MLX4_EN_DCB
44 #include <linux/dcbnl.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/qp.h>
49 #include <linux/mlx4/cq.h>
50 #include <linux/mlx4/srq.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
56 #define DRV_NAME "mlx4_en"
57 #define DRV_VERSION "2.0"
58 #define DRV_RELDATE "Dec 2011"
60 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
67 #define MLX4_EN_PAGE_SHIFT 12
68 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
69 #define MAX_RX_RINGS 16
70 #define MIN_RX_RINGS 4
72 #define HEADROOM (2048 / TXBB_SIZE + 1)
73 #define STAMP_STRIDE 64
74 #define STAMP_DWORDS (STAMP_STRIDE / 4)
75 #define STAMP_SHIFT 31
76 #define STAMP_VAL 0x7fffffff
77 #define STATS_DELAY (HZ / 4)
79 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
80 #define MAX_DESC_SIZE 512
81 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
84 * OS related constants and tunables
87 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
89 /* Use the maximum between 16384 and a single page */
90 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
91 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
93 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
95 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
96 * and 4K allocations) */
98 FRAG_SZ0 = 512 - NET_IP_ALIGN,
101 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
103 #define MLX4_EN_MAX_RX_FRAGS 4
105 /* Maximum ring sizes */
106 #define MLX4_EN_MAX_TX_SIZE 8192
107 #define MLX4_EN_MAX_RX_SIZE 8192
109 /* Minimum ring size for our page-allocation sceme to work */
110 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
111 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
113 #define MLX4_EN_SMALL_PKT_SIZE 64
114 #define MLX4_EN_NUM_TX_RINGS 8
115 #define MLX4_EN_NUM_PPP_RINGS 8
116 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
117 #define MLX4_EN_NUM_UP 8
118 #define MLX4_EN_DEF_TX_RING_SIZE 512
119 #define MLX4_EN_DEF_RX_RING_SIZE 1024
121 /* Target number of packets to coalesce with interrupt moderation */
122 #define MLX4_EN_RX_COAL_TARGET 44
123 #define MLX4_EN_RX_COAL_TIME 0x10
125 #define MLX4_EN_TX_COAL_PKTS 5
126 #define MLX4_EN_TX_COAL_TIME 0x80
128 #define MLX4_EN_RX_RATE_LOW 400000
129 #define MLX4_EN_RX_COAL_TIME_LOW 0
130 #define MLX4_EN_RX_RATE_HIGH 450000
131 #define MLX4_EN_RX_COAL_TIME_HIGH 128
132 #define MLX4_EN_RX_SIZE_THRESH 1024
133 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
134 #define MLX4_EN_SAMPLE_INTERVAL 0
135 #define MLX4_EN_AVG_PKT_SMALL 256
137 #define MLX4_EN_AUTO_CONF 0xffff
139 #define MLX4_EN_DEF_RX_PAUSE 1
140 #define MLX4_EN_DEF_TX_PAUSE 1
142 /* Interval between successive polls in the Tx routine when polling is used
143 instead of interrupts (in per-core Tx rings) - should be power of 2 */
144 #define MLX4_EN_TX_POLL_MODER 16
145 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
147 #define ETH_LLC_SNAP_SIZE 8
149 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
150 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
151 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
153 #define MLX4_EN_MIN_MTU 46
154 #define ETH_BCAST 0xffffffffffffULL
156 #define MLX4_EN_LOOPBACK_RETRIES 5
157 #define MLX4_EN_LOOPBACK_TIMEOUT 100
159 #ifdef MLX4_EN_PERF_STAT
160 /* Number of samples to 'average' */
162 #define AVG_FACTOR 1024
163 #define NUM_PERF_STATS NUM_PERF_COUNTERS
165 #define INC_PERF_COUNTER(cnt) (++(cnt))
166 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
167 #define AVG_PERF_COUNTER(cnt, sample) \
168 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
169 #define GET_PERF_COUNTER(cnt) (cnt)
170 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
174 #define NUM_PERF_STATS 0
175 #define INC_PERF_COUNTER(cnt) do {} while (0)
176 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
177 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
178 #define GET_PERF_COUNTER(cnt) (0)
179 #define GET_AVG_PERF_COUNTER(cnt) (0)
180 #endif /* MLX4_EN_PERF_STAT */
195 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
196 #define XNOR(x, y) (!(x) == !(y))
197 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
200 struct mlx4_en_tx_info {
209 #define MLX4_EN_BIT_DESC_OWN 0x80000000
210 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
211 #define MLX4_EN_MEMTYPE_PAD 0x100
212 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
215 struct mlx4_en_tx_desc {
216 struct mlx4_wqe_ctrl_seg ctrl;
218 struct mlx4_wqe_data_seg data; /* at least one data segment */
219 struct mlx4_wqe_lso_seg lso;
220 struct mlx4_wqe_inline_seg inl;
224 #define MLX4_EN_USE_SRQ 0x01000000
226 #define MLX4_EN_CX3_LOW_ID 0x1000
227 #define MLX4_EN_CX3_HIGH_ID 0x1005
229 struct mlx4_en_rx_alloc {
234 struct mlx4_en_tx_ring {
235 struct mlx4_hwq_resources wqres;
236 u32 size ; /* number of TXBBs */
239 u16 cqn; /* index of port CQ associated with this ring */
247 struct mlx4_en_tx_info *tx_info;
251 struct mlx4_qp_context context;
253 enum mlx4_qp_state qp_state;
254 struct mlx4_srq dummy;
256 unsigned long packets;
257 unsigned long tx_csum;
258 spinlock_t comp_lock;
263 struct mlx4_en_rx_desc {
264 /* actual number of entries depends on rx ring stride */
265 struct mlx4_wqe_data_seg data[0];
268 struct mlx4_en_rx_ring {
269 struct mlx4_hwq_resources wqres;
270 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
271 u32 size ; /* number of Rx descs*/
276 u16 cqn; /* index of port CQ associated with this ring */
284 unsigned long packets;
285 unsigned long csum_ok;
286 unsigned long csum_none;
290 static inline int mlx4_en_can_lro(__be16 status)
292 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
293 MLX4_CQE_STATUS_IPV4F |
294 MLX4_CQE_STATUS_IPV6 |
295 MLX4_CQE_STATUS_IPV4OPT |
296 MLX4_CQE_STATUS_TCP |
297 MLX4_CQE_STATUS_UDP |
298 MLX4_CQE_STATUS_IPOK)) ==
299 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
300 MLX4_CQE_STATUS_IPOK |
301 MLX4_CQE_STATUS_TCP);
306 struct mlx4_hwq_resources wqres;
309 struct net_device *dev;
310 struct napi_struct napi;
311 /* Per-core Tx cq processing support */
312 struct timer_list timer;
319 struct mlx4_cqe *buf;
320 #define MLX4_EN_OPCODE_ERROR 0x1e
323 struct mlx4_en_port_profile {
336 struct mlx4_en_profile {
343 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
347 struct mlx4_dev *dev;
348 struct pci_dev *pdev;
349 struct mutex state_lock;
350 struct net_device *pndev[MLX4_MAX_PORTS + 1];
353 struct mlx4_en_profile profile;
355 struct workqueue_struct *workqueue;
356 struct device *dma_device;
357 void __iomem *uar_map;
358 struct mlx4_uar priv_uar;
362 u8 mac_removed[MLX4_MAX_PORTS + 1];
366 struct mlx4_en_rss_map {
368 struct mlx4_qp qps[MAX_RX_RINGS];
369 enum mlx4_qp_state state[MAX_RX_RINGS];
370 struct mlx4_qp indir_qp;
371 enum mlx4_qp_state indir_state;
374 struct mlx4_en_port_state {
380 struct mlx4_en_pkt_stats {
381 unsigned long broadcast;
382 unsigned long rx_prio[8];
383 unsigned long tx_prio[8];
384 #define NUM_PKT_STATS 17
387 struct mlx4_en_port_stats {
388 unsigned long tso_packets;
389 unsigned long queue_stopped;
390 unsigned long wake_queue;
391 unsigned long tx_timeout;
392 unsigned long rx_alloc_failed;
393 unsigned long rx_chksum_good;
394 unsigned long rx_chksum_none;
395 unsigned long tx_chksum_offload;
396 #define NUM_PORT_STATS 8
399 struct mlx4_en_perf_stats {
406 #define NUM_PERF_COUNTERS 6
409 struct mlx4_en_frag_info {
411 u16 frag_prefix_size;
418 #ifdef CONFIG_MLX4_EN_DCB
419 /* Minimal TC BW - setting to 0 will block traffic */
420 #define MLX4_EN_BW_MIN 1
421 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
423 #define MLX4_EN_TC_ETS 7
427 struct mlx4_en_priv {
428 struct mlx4_en_dev *mdev;
429 struct mlx4_en_port_profile *prof;
430 struct net_device *dev;
431 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
432 struct net_device_stats stats;
433 struct net_device_stats ret_stats;
434 struct mlx4_en_port_state port_state;
435 spinlock_t stats_lock;
437 unsigned long last_moder_packets[MAX_RX_RINGS];
438 unsigned long last_moder_tx_packets;
439 unsigned long last_moder_bytes[MAX_RX_RINGS];
440 unsigned long last_moder_jiffies;
441 int last_moder_time[MAX_RX_RINGS];
451 u16 adaptive_rx_coal;
454 u32 validate_loopback;
456 struct mlx4_hwq_resources res;
469 struct mlx4_en_rss_map rss_map;
472 #define MLX4_EN_FLAG_PROMISC 0x1
473 #define MLX4_EN_FLAG_MC_PROMISC 0x2
477 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
481 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
482 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
483 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
484 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
485 struct work_struct mcast_task;
486 struct work_struct mac_task;
487 struct work_struct watchdog_task;
488 struct work_struct linkstate_task;
489 struct delayed_work stats_task;
490 struct mlx4_en_perf_stats pstats;
491 struct mlx4_en_pkt_stats pkstats;
492 struct mlx4_en_port_stats port_stats;
496 struct mlx4_en_stat_out_mbox hw_stats;
501 #ifdef CONFIG_MLX4_EN_DCB
503 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
508 MLX4_EN_WOL_MAGIC = (1ULL << 61),
509 MLX4_EN_WOL_ENABLED = (1ULL << 62),
512 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
514 void mlx4_en_destroy_netdev(struct net_device *dev);
515 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
516 struct mlx4_en_port_profile *prof);
518 int mlx4_en_start_port(struct net_device *dev);
519 void mlx4_en_stop_port(struct net_device *dev);
521 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
522 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
524 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
525 int entries, int ring, enum cq_type mode);
526 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
527 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
529 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
530 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
531 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
533 void mlx4_en_poll_tx_cq(unsigned long data);
534 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
535 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
536 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
538 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
539 int qpn, u32 size, u16 stride);
540 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
541 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
542 struct mlx4_en_tx_ring *ring,
543 int cq, int user_prio);
544 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
545 struct mlx4_en_tx_ring *ring);
547 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
548 struct mlx4_en_rx_ring *ring,
549 u32 size, u16 stride);
550 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
551 struct mlx4_en_rx_ring *ring,
552 u32 size, u16 stride);
553 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
554 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
555 struct mlx4_en_rx_ring *ring);
556 int mlx4_en_process_rx_cq(struct net_device *dev,
557 struct mlx4_en_cq *cq,
559 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
560 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
561 int is_tx, int rss, int qpn, int cqn, int user_prio,
562 struct mlx4_qp_context *context);
563 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
564 int mlx4_en_map_buffer(struct mlx4_buf *buf);
565 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
567 void mlx4_en_calc_rx_buf(struct net_device *dev);
568 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
569 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
570 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
571 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
573 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
574 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
576 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
577 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
579 #ifdef CONFIG_MLX4_EN_DCB
580 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
583 #define MLX4_EN_NUM_SELF_TEST 5
584 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
585 u64 mlx4_en_mac_to_u64(u8 *addr);
590 extern const struct ethtool_ops mlx4_en_ethtool_ops;
595 * printk / logging functions
599 int en_print(const char *level, const struct mlx4_en_priv *priv,
600 const char *format, ...);
602 #define en_dbg(mlevel, priv, format, arg...) \
604 if (NETIF_MSG_##mlevel & priv->msg_enable) \
605 en_print(KERN_DEBUG, priv, format, ##arg); \
607 #define en_warn(priv, format, arg...) \
608 en_print(KERN_WARNING, priv, format, ##arg)
609 #define en_err(priv, format, arg...) \
610 en_print(KERN_ERR, priv, format, ##arg)
611 #define en_info(priv, format, arg...) \
612 en_print(KERN_INFO, priv, format, ## arg)
614 #define mlx4_err(mdev, format, arg...) \
615 pr_err("%s %s: " format, DRV_NAME, \
616 dev_name(&mdev->pdev->dev), ##arg)
617 #define mlx4_info(mdev, format, arg...) \
618 pr_info("%s %s: " format, DRV_NAME, \
619 dev_name(&mdev->pdev->dev), ##arg)
620 #define mlx4_warn(mdev, format, arg...) \
621 pr_warning("%s %s: " format, DRV_NAME, \
622 dev_name(&mdev->pdev->dev), ##arg)