2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
61 table->max = 1 << dev->caps.log_num_macs;
65 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
78 static int validate_index(struct mlx4_dev *dev,
79 struct mlx4_mac_table *table, int index)
83 if (index < 0 || index >= table->max || !table->entries[index]) {
84 mlx4_warn(dev, "No valid Mac entry for the given index\n");
90 static int find_index(struct mlx4_dev *dev,
91 struct mlx4_mac_table *table, u64 mac)
95 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
96 if ((mac & MLX4_MAC_MASK) ==
97 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
104 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
107 struct mlx4_cmd_mailbox *mailbox;
111 mailbox = mlx4_alloc_cmd_mailbox(dev);
113 return PTR_ERR(mailbox);
115 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
117 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
119 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
120 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
122 mlx4_free_cmd_mailbox(dev, mailbox);
126 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx)
128 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
129 struct mlx4_mac_table *table = &info->mac_table;
132 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
136 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
144 EXPORT_SYMBOL_GPL(mlx4_find_cached_mac);
146 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
148 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
149 struct mlx4_mac_table *table = &info->mac_table;
153 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
154 (unsigned long long) mac, port);
156 mutex_lock(&table->mutex);
157 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
158 if (free < 0 && !table->entries[i]) {
163 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
164 /* MAC already registered, increment ref count */
171 mlx4_dbg(dev, "Free MAC index is %d\n", free);
173 if (table->total == table->max) {
174 /* No free mac entries */
179 /* Register new MAC */
180 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
182 err = mlx4_set_port_mac_table(dev, port, table->entries);
184 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
185 (unsigned long long) mac);
186 table->entries[free] = 0;
189 table->refs[free] = 1;
193 mutex_unlock(&table->mutex);
196 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
198 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
203 if (mlx4_is_mfunc(dev)) {
204 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
205 err = mlx4_cmd_imm(dev, mac, &out_param,
206 ((u32) port) << 8 | (u32) RES_MAC,
207 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
208 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
210 if (err && err == -EINVAL && mlx4_is_slave(dev)) {
211 /* retry using old REG_MAC format */
212 set_param_l(&out_param, port);
213 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
214 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
215 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
217 dev->flags |= MLX4_FLAG_OLD_REG_MAC;
222 return get_param_l(&out_param);
224 return __mlx4_register_mac(dev, port, mac);
226 EXPORT_SYMBOL_GPL(mlx4_register_mac);
228 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
230 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
231 (port - 1) * (1 << dev->caps.log_num_macs);
233 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
235 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
237 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
238 struct mlx4_mac_table *table = &info->mac_table;
241 mutex_lock(&table->mutex);
242 index = find_index(dev, table, mac);
244 if (validate_index(dev, table, index))
246 if (--table->refs[index]) {
247 mlx4_dbg(dev, "Have more references for index %d, no need to modify mac table\n",
252 table->entries[index] = 0;
253 mlx4_set_port_mac_table(dev, port, table->entries);
256 mutex_unlock(&table->mutex);
258 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
260 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
264 if (mlx4_is_mfunc(dev)) {
265 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
266 (void) mlx4_cmd_imm(dev, mac, &out_param,
267 ((u32) port) << 8 | (u32) RES_MAC,
268 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
269 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
271 /* use old unregister mac format */
272 set_param_l(&out_param, port);
273 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
274 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
275 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
279 __mlx4_unregister_mac(dev, port, mac);
282 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
284 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
286 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
287 struct mlx4_mac_table *table = &info->mac_table;
288 int index = qpn - info->base_qpn;
291 /* CX1 doesn't support multi-functions */
292 mutex_lock(&table->mutex);
294 err = validate_index(dev, table, index);
298 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
300 err = mlx4_set_port_mac_table(dev, port, table->entries);
302 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
303 (unsigned long long) new_mac);
304 table->entries[index] = 0;
307 mutex_unlock(&table->mutex);
310 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
312 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
315 struct mlx4_cmd_mailbox *mailbox;
319 mailbox = mlx4_alloc_cmd_mailbox(dev);
321 return PTR_ERR(mailbox);
323 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
324 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
325 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
326 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
328 mlx4_free_cmd_mailbox(dev, mailbox);
333 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
335 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
338 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
339 if (table->refs[i] &&
340 (vid == (MLX4_VLAN_MASK &
341 be32_to_cpu(table->entries[i])))) {
342 /* VLAN already registered, increase reference count */
350 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
352 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
355 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
359 mutex_lock(&table->mutex);
361 if (table->total == table->max) {
362 /* No free vlan entries */
367 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
368 if (free < 0 && (table->refs[i] == 0)) {
373 if (table->refs[i] &&
374 (vlan == (MLX4_VLAN_MASK &
375 be32_to_cpu(table->entries[i])))) {
376 /* Vlan already registered, increase references count */
388 /* Register new VLAN */
389 table->refs[free] = 1;
390 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
392 err = mlx4_set_port_vlan_table(dev, port, table->entries);
394 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
395 table->refs[free] = 0;
396 table->entries[free] = 0;
403 mutex_unlock(&table->mutex);
407 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
415 if (mlx4_is_mfunc(dev)) {
416 err = mlx4_cmd_imm(dev, vlan, &out_param,
417 ((u32) port) << 8 | (u32) RES_VLAN,
418 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
419 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
421 *index = get_param_l(&out_param);
425 return __mlx4_register_vlan(dev, port, vlan, index);
427 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
429 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
431 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
434 mutex_lock(&table->mutex);
435 if (mlx4_find_cached_vlan(dev, port, vlan, &index)) {
436 mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan);
440 if (index < MLX4_VLAN_REGULAR) {
441 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
445 if (--table->refs[index]) {
446 mlx4_dbg(dev, "Have %d more references for index %d, no need to modify vlan table\n",
447 table->refs[index], index);
450 table->entries[index] = 0;
451 mlx4_set_port_vlan_table(dev, port, table->entries);
454 mutex_unlock(&table->mutex);
457 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
461 if (mlx4_is_mfunc(dev)) {
462 (void) mlx4_cmd_imm(dev, vlan, &out_param,
463 ((u32) port) << 8 | (u32) RES_VLAN,
464 RES_OP_RESERVE_AND_MAP,
465 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
469 __mlx4_unregister_vlan(dev, port, vlan);
471 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
473 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
475 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
479 inmailbox = mlx4_alloc_cmd_mailbox(dev);
480 if (IS_ERR(inmailbox))
481 return PTR_ERR(inmailbox);
483 outmailbox = mlx4_alloc_cmd_mailbox(dev);
484 if (IS_ERR(outmailbox)) {
485 mlx4_free_cmd_mailbox(dev, inmailbox);
486 return PTR_ERR(outmailbox);
489 inbuf = inmailbox->buf;
490 outbuf = outmailbox->buf;
495 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
496 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
498 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
499 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
502 *caps = *(__be32 *) (outbuf + 84);
503 mlx4_free_cmd_mailbox(dev, inmailbox);
504 mlx4_free_cmd_mailbox(dev, outmailbox);
507 static struct mlx4_roce_gid_entry zgid_entry;
509 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port)
512 int slave_gid = slave;
514 struct mlx4_slaves_pport slaves_pport;
515 struct mlx4_active_ports actv_ports;
516 unsigned max_port_p_one;
519 return MLX4_ROCE_PF_GIDS;
522 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
523 actv_ports = mlx4_get_active_ports(dev, slave);
524 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
525 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
527 for (i = 1; i < max_port_p_one; i++) {
528 struct mlx4_active_ports exclusive_ports;
529 struct mlx4_slaves_pport slaves_pport_actv;
530 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
531 set_bit(i - 1, exclusive_ports.ports);
534 slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
535 dev, &exclusive_ports);
536 slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
539 vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
540 if (slave_gid <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % vfs))
541 return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs) + 1;
542 return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs;
545 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port)
549 int slave_gid = slave;
552 struct mlx4_slaves_pport slaves_pport;
553 struct mlx4_active_ports actv_ports;
554 unsigned max_port_p_one;
559 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
560 actv_ports = mlx4_get_active_ports(dev, slave);
561 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
562 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
564 for (i = 1; i < max_port_p_one; i++) {
565 struct mlx4_active_ports exclusive_ports;
566 struct mlx4_slaves_pport slaves_pport_actv;
567 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
568 set_bit(i - 1, exclusive_ports.ports);
571 slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
572 dev, &exclusive_ports);
573 slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
576 gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
577 vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
578 if (slave_gid <= gids % vfs)
579 return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave_gid - 1);
581 return MLX4_ROCE_PF_GIDS + (gids % vfs) +
582 ((gids / vfs) * (slave_gid - 1));
584 EXPORT_SYMBOL_GPL(mlx4_get_base_gid_ix);
586 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
587 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
589 struct mlx4_priv *priv = mlx4_priv(dev);
590 struct mlx4_port_info *port_info;
591 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
592 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
593 struct mlx4_set_port_rqp_calc_context *qpn_context;
594 struct mlx4_set_port_general_context *gen_context;
595 struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1;
596 int reset_qkey_viols;
608 __be32 slave_cap_mask;
611 port = in_mod & 0xff;
612 in_modifier = in_mod >> 8;
614 port_info = &priv->port[port];
616 /* Slaves cannot perform SET_PORT operations except changing MTU */
618 if (slave != dev->caps.function &&
619 in_modifier != MLX4_SET_PORT_GENERAL &&
620 in_modifier != MLX4_SET_PORT_GID_TABLE) {
621 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
625 switch (in_modifier) {
626 case MLX4_SET_PORT_RQP_CALC:
627 qpn_context = inbox->buf;
628 qpn_context->base_qpn =
629 cpu_to_be32(port_info->base_qpn);
630 qpn_context->n_mac = 0x7;
631 promisc = be32_to_cpu(qpn_context->promisc) >>
632 SET_PORT_PROMISC_SHIFT;
633 qpn_context->promisc = cpu_to_be32(
634 promisc << SET_PORT_PROMISC_SHIFT |
635 port_info->base_qpn);
636 promisc = be32_to_cpu(qpn_context->mcast) >>
637 SET_PORT_MC_PROMISC_SHIFT;
638 qpn_context->mcast = cpu_to_be32(
639 promisc << SET_PORT_MC_PROMISC_SHIFT |
640 port_info->base_qpn);
642 case MLX4_SET_PORT_GENERAL:
643 gen_context = inbox->buf;
644 /* Mtu is configured as the max MTU among all the
645 * the functions on the port. */
646 mtu = be16_to_cpu(gen_context->mtu);
647 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
648 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
649 prev_mtu = slave_st->mtu[port];
650 slave_st->mtu[port] = mtu;
651 if (mtu > master->max_mtu[port])
652 master->max_mtu[port] = mtu;
653 if (mtu < prev_mtu && prev_mtu ==
654 master->max_mtu[port]) {
655 slave_st->mtu[port] = mtu;
656 master->max_mtu[port] = mtu;
657 for (i = 0; i < dev->num_slaves; i++) {
658 master->max_mtu[port] =
659 max(master->max_mtu[port],
660 master->slave_state[i].mtu[port]);
664 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
666 case MLX4_SET_PORT_GID_TABLE:
667 /* change to MULTIPLE entries: number of guest's gids
668 * need a FOR-loop here over number of gids the guest has.
669 * 1. Check no duplicates in gids passed by slave
671 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
672 base = mlx4_get_base_gid_ix(dev, slave, port);
673 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
674 for (i = 0; i < num_gids; gid_entry_mbox++, i++) {
675 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
678 gid_entry_mb1 = gid_entry_mbox + 1;
679 for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) {
680 if (!memcmp(gid_entry_mb1->raw,
681 zgid_entry.raw, sizeof(zgid_entry)))
683 if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw,
684 sizeof(gid_entry_mbox->raw))) {
685 /* found duplicate */
691 /* 2. Check that do not have duplicates in OTHER
692 * entries in the port GID table
694 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
695 if (i >= base && i < base + num_gids)
696 continue; /* don't compare to slave's current gids */
697 gid_entry_tbl = &priv->roce_gids[port - 1][i];
698 if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry)))
700 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
701 for (j = 0; j < num_gids; gid_entry_mbox++, j++) {
702 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
705 if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw,
706 sizeof(gid_entry_tbl->raw))) {
707 /* found duplicate */
708 mlx4_warn(dev, "requested gid entry for slave:%d is a duplicate of gid at index %d\n",
715 /* insert slave GIDs with memcpy, starting at slave's base index */
716 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
717 for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++)
718 memcpy(priv->roce_gids[port - 1][offset].raw, gid_entry_mbox->raw, 16);
720 /* Now, copy roce port gids table to current mailbox for passing to FW */
721 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
722 for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
723 memcpy(gid_entry_mbox->raw, priv->roce_gids[port - 1][i].raw, 16);
727 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
728 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
732 /* For IB, we only consider:
733 * - The capability mask, which is set to the aggregate of all
734 * slave function capabilities
735 * - The QKey violatin counter - reset according to each request.
738 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
739 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
740 new_cap_mask = ((__be32 *) inbox->buf)[2];
742 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
743 new_cap_mask = ((__be32 *) inbox->buf)[1];
746 /* slave may not set the IS_SM capability for the port */
747 if (slave != mlx4_master_func_num(dev) &&
748 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
751 /* No DEV_MGMT in multifunc mode */
752 if (mlx4_is_mfunc(dev) &&
753 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
758 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
759 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
760 for (i = 0; i < dev->num_slaves; i++)
762 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
764 /* only clear mailbox for guests. Master may be setting
765 * MTU or PKEY table size
767 if (slave != dev->caps.function)
768 memset(inbox->buf, 0, 256);
769 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
770 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
771 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
773 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
774 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
777 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
778 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
780 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
785 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
786 struct mlx4_vhcr *vhcr,
787 struct mlx4_cmd_mailbox *inbox,
788 struct mlx4_cmd_mailbox *outbox,
789 struct mlx4_cmd_info *cmd)
791 int port = mlx4_slave_convert_port(
792 dev, slave, vhcr->in_modifier & 0xFF);
797 vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) |
800 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
801 vhcr->op_modifier, inbox);
804 /* bit locations for set port command with zero op modifier */
806 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
807 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
808 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
809 MLX4_CHANGE_PORT_VL_CAP = 21,
810 MLX4_CHANGE_PORT_MTU_CAP = 22,
813 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
815 struct mlx4_cmd_mailbox *mailbox;
816 int err, vl_cap, pkey_tbl_flag = 0;
818 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
821 mailbox = mlx4_alloc_cmd_mailbox(dev);
823 return PTR_ERR(mailbox);
825 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
827 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
829 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
832 /* IB VL CAP enum isn't used by the firmware, just numerical values */
833 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
834 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
835 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
836 (1 << MLX4_CHANGE_PORT_VL_CAP) |
837 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
838 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
839 (vl_cap << MLX4_SET_PORT_VL_CAP));
840 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
841 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
846 mlx4_free_cmd_mailbox(dev, mailbox);
850 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
851 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
853 struct mlx4_cmd_mailbox *mailbox;
854 struct mlx4_set_port_general_context *context;
858 mailbox = mlx4_alloc_cmd_mailbox(dev);
860 return PTR_ERR(mailbox);
861 context = mailbox->buf;
862 context->flags = SET_PORT_GEN_ALL_VALID;
863 context->mtu = cpu_to_be16(mtu);
864 context->pptx = (pptx * (!pfctx)) << 7;
865 context->pfctx = pfctx;
866 context->pprx = (pprx * (!pfcrx)) << 7;
867 context->pfcrx = pfcrx;
869 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
870 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
871 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
873 mlx4_free_cmd_mailbox(dev, mailbox);
876 EXPORT_SYMBOL(mlx4_SET_PORT_general);
878 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
881 struct mlx4_cmd_mailbox *mailbox;
882 struct mlx4_set_port_rqp_calc_context *context;
885 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
886 MCAST_DIRECT : MCAST_DEFAULT;
888 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
891 mailbox = mlx4_alloc_cmd_mailbox(dev);
893 return PTR_ERR(mailbox);
894 context = mailbox->buf;
895 context->base_qpn = cpu_to_be32(base_qpn);
896 context->n_mac = dev->caps.log_num_macs;
897 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
899 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
901 context->intra_no_vlan = 0;
902 context->no_vlan = MLX4_NO_VLAN_IDX;
903 context->intra_vlan_miss = 0;
904 context->vlan_miss = MLX4_VLAN_MISS_IDX;
906 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
907 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
908 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
910 mlx4_free_cmd_mailbox(dev, mailbox);
913 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
915 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
917 struct mlx4_cmd_mailbox *mailbox;
918 struct mlx4_set_port_prio2tc_context *context;
923 mailbox = mlx4_alloc_cmd_mailbox(dev);
925 return PTR_ERR(mailbox);
926 context = mailbox->buf;
927 for (i = 0; i < MLX4_NUM_UP; i += 2)
928 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
930 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
931 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
932 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
934 mlx4_free_cmd_mailbox(dev, mailbox);
937 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
939 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
940 u8 *pg, u16 *ratelimit)
942 struct mlx4_cmd_mailbox *mailbox;
943 struct mlx4_set_port_scheduler_context *context;
948 mailbox = mlx4_alloc_cmd_mailbox(dev);
950 return PTR_ERR(mailbox);
951 context = mailbox->buf;
953 for (i = 0; i < MLX4_NUM_TC; i++) {
954 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
955 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
956 MLX4_RATELIMIT_DEFAULT;
958 tc->pg = htons(pg[i]);
959 tc->bw_precentage = htons(tc_tx_bw[i]);
961 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
962 tc->max_bw_value = htons(r);
965 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
966 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
967 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
969 mlx4_free_cmd_mailbox(dev, mailbox);
972 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
975 VXLAN_ENABLE_MODIFY = 1 << 7,
976 VXLAN_STEERING_MODIFY = 1 << 6,
978 VXLAN_ENABLE = 1 << 7,
981 struct mlx4_set_port_vxlan_context {
989 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable)
993 struct mlx4_cmd_mailbox *mailbox;
994 struct mlx4_set_port_vxlan_context *context;
996 mailbox = mlx4_alloc_cmd_mailbox(dev);
998 return PTR_ERR(mailbox);
999 context = mailbox->buf;
1000 memset(context, 0, sizeof(*context));
1002 context->modify_flags = VXLAN_ENABLE_MODIFY | VXLAN_STEERING_MODIFY;
1004 context->enable_flags = VXLAN_ENABLE;
1005 context->steering = steering;
1007 in_mod = MLX4_SET_PORT_VXLAN << 8 | port;
1008 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1009 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1011 mlx4_free_cmd_mailbox(dev, mailbox);
1014 EXPORT_SYMBOL(mlx4_SET_PORT_VXLAN);
1016 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr,
1018 struct mlx4_cmd_mailbox *inbox,
1019 struct mlx4_cmd_mailbox *outbox,
1020 struct mlx4_cmd_info *cmd)
1027 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
1028 u64 mac, u64 clear, u8 mode)
1030 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
1031 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
1034 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
1036 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1037 struct mlx4_vhcr *vhcr,
1038 struct mlx4_cmd_mailbox *inbox,
1039 struct mlx4_cmd_mailbox *outbox,
1040 struct mlx4_cmd_info *cmd)
1047 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
1048 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
1050 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
1051 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
1055 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd)
1061 if (slave != dev->caps.function)
1063 return mlx4_common_dump_eth_stats(dev, slave,
1064 vhcr->in_modifier, outbox);
1067 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
1069 if (!mlx4_is_mfunc(dev)) {
1074 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
1075 MLX4_STATS_TRAFFIC_DROPS_MASK |
1076 MLX4_STATS_PORT_COUNTERS_MASK);
1078 if (mlx4_is_master(dev))
1079 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
1081 EXPORT_SYMBOL(mlx4_set_stats_bitmap);
1083 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1086 struct mlx4_priv *priv = mlx4_priv(dev);
1087 int i, found_ix = -1;
1088 int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1089 struct mlx4_slaves_pport slaves_pport;
1093 if (!mlx4_is_mfunc(dev))
1096 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
1097 num_vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
1099 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1100 if (!memcmp(priv->roce_gids[port - 1][i].raw, gid, 16)) {
1106 if (found_ix >= 0) {
1107 /* Calculate a slave_gid which is the slave number in the gid
1108 * table and not a globally unique slave number.
1110 if (found_ix < MLX4_ROCE_PF_GIDS)
1112 else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % num_vfs) *
1113 (vf_gids / num_vfs + 1))
1114 slave_gid = ((found_ix - MLX4_ROCE_PF_GIDS) /
1115 (vf_gids / num_vfs + 1)) + 1;
1118 ((found_ix - MLX4_ROCE_PF_GIDS -
1119 ((vf_gids % num_vfs) * ((vf_gids / num_vfs + 1)))) /
1120 (vf_gids / num_vfs)) + vf_gids % num_vfs + 1;
1122 /* Calculate the globally unique slave id */
1124 struct mlx4_active_ports exclusive_ports;
1125 struct mlx4_active_ports actv_ports;
1126 struct mlx4_slaves_pport slaves_pport_actv;
1127 unsigned max_port_p_one;
1128 int num_vfs_before = 0;
1129 int candidate_slave_gid;
1131 /* Calculate how many VFs are on the previous port, if exists */
1132 for (i = 1; i < port; i++) {
1133 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
1134 set_bit(i - 1, exclusive_ports.ports);
1136 mlx4_phys_to_slaves_pport_actv(
1137 dev, &exclusive_ports);
1138 num_vfs_before += bitmap_weight(
1139 slaves_pport_actv.slaves,
1143 /* candidate_slave_gid isn't necessarily the correct slave, but
1144 * it has the same number of ports and is assigned to the same
1145 * ports as the real slave we're looking for. On dual port VF,
1146 * slave_gid = [single port VFs on port <port>] +
1147 * [offset of the current slave from the first dual port VF] +
1150 candidate_slave_gid = slave_gid + num_vfs_before;
1152 actv_ports = mlx4_get_active_ports(dev, candidate_slave_gid);
1153 max_port_p_one = find_first_bit(
1154 actv_ports.ports, dev->caps.num_ports) +
1155 bitmap_weight(actv_ports.ports,
1156 dev->caps.num_ports) + 1;
1158 /* Calculate the real slave number */
1159 for (i = 1; i < max_port_p_one; i++) {
1162 bitmap_zero(exclusive_ports.ports,
1163 dev->caps.num_ports);
1164 set_bit(i - 1, exclusive_ports.ports);
1166 mlx4_phys_to_slaves_pport_actv(
1167 dev, &exclusive_ports);
1168 slave_gid += bitmap_weight(
1169 slaves_pport_actv.slaves,
1173 *slave_id = slave_gid;
1176 return (found_ix >= 0) ? 0 : -EINVAL;
1178 EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid);
1180 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1183 struct mlx4_priv *priv = mlx4_priv(dev);
1185 if (!mlx4_is_master(dev))
1188 memcpy(gid, priv->roce_gids[port - 1][slave_id].raw, 16);
1191 EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave);