2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
61 table->max = 1 << dev->caps.log_num_macs;
65 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
78 static int validate_index(struct mlx4_dev *dev,
79 struct mlx4_mac_table *table, int index)
83 if (index < 0 || index >= table->max || !table->entries[index]) {
84 mlx4_warn(dev, "No valid Mac entry for the given index\n");
90 static int find_index(struct mlx4_dev *dev,
91 struct mlx4_mac_table *table, u64 mac)
95 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
96 if ((mac & MLX4_MAC_MASK) ==
97 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
104 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
107 struct mlx4_cmd_mailbox *mailbox;
111 mailbox = mlx4_alloc_cmd_mailbox(dev);
113 return PTR_ERR(mailbox);
115 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
117 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
119 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
120 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
122 mlx4_free_cmd_mailbox(dev, mailbox);
126 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
128 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
129 struct mlx4_mac_table *table = &info->mac_table;
133 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
134 (unsigned long long) mac, port);
136 mutex_lock(&table->mutex);
137 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
138 if (free < 0 && !table->entries[i]) {
143 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
144 /* MAC already registered, increment ref count */
151 mlx4_dbg(dev, "Free MAC index is %d\n", free);
153 if (table->total == table->max) {
154 /* No free mac entries */
159 /* Register new MAC */
160 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
162 err = mlx4_set_port_mac_table(dev, port, table->entries);
164 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
165 (unsigned long long) mac);
166 table->entries[free] = 0;
169 table->refs[free] = 1;
173 mutex_unlock(&table->mutex);
176 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
178 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
183 if (mlx4_is_mfunc(dev)) {
184 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
185 err = mlx4_cmd_imm(dev, mac, &out_param,
186 ((u32) port) << 8 | (u32) RES_MAC,
187 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
188 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
190 if (err && err == -EINVAL && mlx4_is_slave(dev)) {
191 /* retry using old REG_MAC format */
192 set_param_l(&out_param, port);
193 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
194 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
195 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
197 dev->flags |= MLX4_FLAG_OLD_REG_MAC;
202 return get_param_l(&out_param);
204 return __mlx4_register_mac(dev, port, mac);
206 EXPORT_SYMBOL_GPL(mlx4_register_mac);
208 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
210 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
211 (port - 1) * (1 << dev->caps.log_num_macs);
213 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
215 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
217 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
218 struct mlx4_mac_table *table = &info->mac_table;
221 mutex_lock(&table->mutex);
222 index = find_index(dev, table, mac);
224 if (validate_index(dev, table, index))
226 if (--table->refs[index]) {
227 mlx4_dbg(dev, "Have more references for index %d,"
228 "no need to modify mac table\n", index);
232 table->entries[index] = 0;
233 mlx4_set_port_mac_table(dev, port, table->entries);
236 mutex_unlock(&table->mutex);
238 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
240 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
244 if (mlx4_is_mfunc(dev)) {
245 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
246 (void) mlx4_cmd_imm(dev, mac, &out_param,
247 ((u32) port) << 8 | (u32) RES_MAC,
248 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
249 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
251 /* use old unregister mac format */
252 set_param_l(&out_param, port);
253 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
254 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
255 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
259 __mlx4_unregister_mac(dev, port, mac);
262 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
264 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
266 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
267 struct mlx4_mac_table *table = &info->mac_table;
268 int index = qpn - info->base_qpn;
271 /* CX1 doesn't support multi-functions */
272 mutex_lock(&table->mutex);
274 err = validate_index(dev, table, index);
278 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
280 err = mlx4_set_port_mac_table(dev, port, table->entries);
282 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
283 (unsigned long long) new_mac);
284 table->entries[index] = 0;
287 mutex_unlock(&table->mutex);
290 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
292 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
295 struct mlx4_cmd_mailbox *mailbox;
299 mailbox = mlx4_alloc_cmd_mailbox(dev);
301 return PTR_ERR(mailbox);
303 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
304 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
305 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
306 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
308 mlx4_free_cmd_mailbox(dev, mailbox);
313 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
315 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
318 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
319 if (table->refs[i] &&
320 (vid == (MLX4_VLAN_MASK &
321 be32_to_cpu(table->entries[i])))) {
322 /* VLAN already registered, increase reference count */
330 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
332 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
335 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
339 mutex_lock(&table->mutex);
341 if (table->total == table->max) {
342 /* No free vlan entries */
347 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
348 if (free < 0 && (table->refs[i] == 0)) {
353 if (table->refs[i] &&
354 (vlan == (MLX4_VLAN_MASK &
355 be32_to_cpu(table->entries[i])))) {
356 /* Vlan already registered, increase references count */
368 /* Register new VLAN */
369 table->refs[free] = 1;
370 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
372 err = mlx4_set_port_vlan_table(dev, port, table->entries);
374 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
375 table->refs[free] = 0;
376 table->entries[free] = 0;
383 mutex_unlock(&table->mutex);
387 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
395 if (mlx4_is_mfunc(dev)) {
396 err = mlx4_cmd_imm(dev, vlan, &out_param,
397 ((u32) port) << 8 | (u32) RES_VLAN,
398 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
399 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
401 *index = get_param_l(&out_param);
405 return __mlx4_register_vlan(dev, port, vlan, index);
407 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
409 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
411 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
413 if (index < MLX4_VLAN_REGULAR) {
414 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
418 mutex_lock(&table->mutex);
419 if (!table->refs[index]) {
420 mlx4_warn(dev, "No vlan entry for index %d\n", index);
423 if (--table->refs[index]) {
424 mlx4_dbg(dev, "Have more references for index %d,"
425 "no need to modify vlan table\n", index);
428 table->entries[index] = 0;
429 mlx4_set_port_vlan_table(dev, port, table->entries);
432 mutex_unlock(&table->mutex);
435 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
439 if (mlx4_is_mfunc(dev)) {
440 (void) mlx4_cmd_imm(dev, index, &out_param,
441 ((u32) port) << 8 | (u32) RES_VLAN,
442 RES_OP_RESERVE_AND_MAP,
443 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
447 __mlx4_unregister_vlan(dev, port, index);
449 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
451 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
453 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
457 inmailbox = mlx4_alloc_cmd_mailbox(dev);
458 if (IS_ERR(inmailbox))
459 return PTR_ERR(inmailbox);
461 outmailbox = mlx4_alloc_cmd_mailbox(dev);
462 if (IS_ERR(outmailbox)) {
463 mlx4_free_cmd_mailbox(dev, inmailbox);
464 return PTR_ERR(outmailbox);
467 inbuf = inmailbox->buf;
468 outbuf = outmailbox->buf;
469 memset(inbuf, 0, 256);
470 memset(outbuf, 0, 256);
475 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
476 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
478 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
479 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
482 *caps = *(__be32 *) (outbuf + 84);
483 mlx4_free_cmd_mailbox(dev, inmailbox);
484 mlx4_free_cmd_mailbox(dev, outmailbox);
488 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
489 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
491 struct mlx4_priv *priv = mlx4_priv(dev);
492 struct mlx4_port_info *port_info;
493 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
494 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
495 struct mlx4_set_port_rqp_calc_context *qpn_context;
496 struct mlx4_set_port_general_context *gen_context;
497 int reset_qkey_viols;
506 __be32 slave_cap_mask;
509 port = in_mod & 0xff;
510 in_modifier = in_mod >> 8;
512 port_info = &priv->port[port];
514 /* Slaves cannot perform SET_PORT operations except changing MTU */
516 if (slave != dev->caps.function &&
517 in_modifier != MLX4_SET_PORT_GENERAL) {
518 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
522 switch (in_modifier) {
523 case MLX4_SET_PORT_RQP_CALC:
524 qpn_context = inbox->buf;
525 qpn_context->base_qpn =
526 cpu_to_be32(port_info->base_qpn);
527 qpn_context->n_mac = 0x7;
528 promisc = be32_to_cpu(qpn_context->promisc) >>
529 SET_PORT_PROMISC_SHIFT;
530 qpn_context->promisc = cpu_to_be32(
531 promisc << SET_PORT_PROMISC_SHIFT |
532 port_info->base_qpn);
533 promisc = be32_to_cpu(qpn_context->mcast) >>
534 SET_PORT_MC_PROMISC_SHIFT;
535 qpn_context->mcast = cpu_to_be32(
536 promisc << SET_PORT_MC_PROMISC_SHIFT |
537 port_info->base_qpn);
539 case MLX4_SET_PORT_GENERAL:
540 gen_context = inbox->buf;
541 /* Mtu is configured as the max MTU among all the
542 * the functions on the port. */
543 mtu = be16_to_cpu(gen_context->mtu);
544 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
545 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
546 prev_mtu = slave_st->mtu[port];
547 slave_st->mtu[port] = mtu;
548 if (mtu > master->max_mtu[port])
549 master->max_mtu[port] = mtu;
550 if (mtu < prev_mtu && prev_mtu ==
551 master->max_mtu[port]) {
552 slave_st->mtu[port] = mtu;
553 master->max_mtu[port] = mtu;
554 for (i = 0; i < dev->num_slaves; i++) {
555 master->max_mtu[port] =
556 max(master->max_mtu[port],
557 master->slave_state[i].mtu[port]);
561 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
564 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
565 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
569 /* For IB, we only consider:
570 * - The capability mask, which is set to the aggregate of all
571 * slave function capabilities
572 * - The QKey violatin counter - reset according to each request.
575 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
576 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
577 new_cap_mask = ((__be32 *) inbox->buf)[2];
579 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
580 new_cap_mask = ((__be32 *) inbox->buf)[1];
583 /* slave may not set the IS_SM capability for the port */
584 if (slave != mlx4_master_func_num(dev) &&
585 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
588 /* No DEV_MGMT in multifunc mode */
589 if (mlx4_is_mfunc(dev) &&
590 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
595 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
596 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
597 for (i = 0; i < dev->num_slaves; i++)
599 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
601 /* only clear mailbox for guests. Master may be setting
602 * MTU or PKEY table size
604 if (slave != dev->caps.function)
605 memset(inbox->buf, 0, 256);
606 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
607 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
608 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
610 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
611 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
614 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
615 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
617 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
622 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
623 struct mlx4_vhcr *vhcr,
624 struct mlx4_cmd_mailbox *inbox,
625 struct mlx4_cmd_mailbox *outbox,
626 struct mlx4_cmd_info *cmd)
628 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
629 vhcr->op_modifier, inbox);
632 /* bit locations for set port command with zero op modifier */
634 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
635 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
636 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
637 MLX4_CHANGE_PORT_VL_CAP = 21,
638 MLX4_CHANGE_PORT_MTU_CAP = 22,
641 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
643 struct mlx4_cmd_mailbox *mailbox;
644 int err, vl_cap, pkey_tbl_flag = 0;
646 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
649 mailbox = mlx4_alloc_cmd_mailbox(dev);
651 return PTR_ERR(mailbox);
653 memset(mailbox->buf, 0, 256);
655 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
657 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
659 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
662 /* IB VL CAP enum isn't used by the firmware, just numerical values */
663 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
664 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
665 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
666 (1 << MLX4_CHANGE_PORT_VL_CAP) |
667 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
668 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
669 (vl_cap << MLX4_SET_PORT_VL_CAP));
670 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
671 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
676 mlx4_free_cmd_mailbox(dev, mailbox);
680 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
681 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
683 struct mlx4_cmd_mailbox *mailbox;
684 struct mlx4_set_port_general_context *context;
688 mailbox = mlx4_alloc_cmd_mailbox(dev);
690 return PTR_ERR(mailbox);
691 context = mailbox->buf;
692 memset(context, 0, sizeof *context);
694 context->flags = SET_PORT_GEN_ALL_VALID;
695 context->mtu = cpu_to_be16(mtu);
696 context->pptx = (pptx * (!pfctx)) << 7;
697 context->pfctx = pfctx;
698 context->pprx = (pprx * (!pfcrx)) << 7;
699 context->pfcrx = pfcrx;
701 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
702 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
703 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
705 mlx4_free_cmd_mailbox(dev, mailbox);
708 EXPORT_SYMBOL(mlx4_SET_PORT_general);
710 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
713 struct mlx4_cmd_mailbox *mailbox;
714 struct mlx4_set_port_rqp_calc_context *context;
717 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
718 MCAST_DIRECT : MCAST_DEFAULT;
720 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
723 mailbox = mlx4_alloc_cmd_mailbox(dev);
725 return PTR_ERR(mailbox);
726 context = mailbox->buf;
727 memset(context, 0, sizeof *context);
729 context->base_qpn = cpu_to_be32(base_qpn);
730 context->n_mac = dev->caps.log_num_macs;
731 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
733 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
735 context->intra_no_vlan = 0;
736 context->no_vlan = MLX4_NO_VLAN_IDX;
737 context->intra_vlan_miss = 0;
738 context->vlan_miss = MLX4_VLAN_MISS_IDX;
740 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
741 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
742 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
744 mlx4_free_cmd_mailbox(dev, mailbox);
747 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
749 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
751 struct mlx4_cmd_mailbox *mailbox;
752 struct mlx4_set_port_prio2tc_context *context;
757 mailbox = mlx4_alloc_cmd_mailbox(dev);
759 return PTR_ERR(mailbox);
760 context = mailbox->buf;
761 memset(context, 0, sizeof *context);
763 for (i = 0; i < MLX4_NUM_UP; i += 2)
764 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
766 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
767 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
768 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
770 mlx4_free_cmd_mailbox(dev, mailbox);
773 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
775 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
776 u8 *pg, u16 *ratelimit)
778 struct mlx4_cmd_mailbox *mailbox;
779 struct mlx4_set_port_scheduler_context *context;
784 mailbox = mlx4_alloc_cmd_mailbox(dev);
786 return PTR_ERR(mailbox);
787 context = mailbox->buf;
788 memset(context, 0, sizeof *context);
790 for (i = 0; i < MLX4_NUM_TC; i++) {
791 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
792 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
793 MLX4_RATELIMIT_DEFAULT;
795 tc->pg = htons(pg[i]);
796 tc->bw_precentage = htons(tc_tx_bw[i]);
798 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
799 tc->max_bw_value = htons(r);
802 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
803 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
804 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
806 mlx4_free_cmd_mailbox(dev, mailbox);
809 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
811 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
812 struct mlx4_vhcr *vhcr,
813 struct mlx4_cmd_mailbox *inbox,
814 struct mlx4_cmd_mailbox *outbox,
815 struct mlx4_cmd_info *cmd)
822 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
823 u64 mac, u64 clear, u8 mode)
825 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
826 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
829 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
831 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
832 struct mlx4_vhcr *vhcr,
833 struct mlx4_cmd_mailbox *inbox,
834 struct mlx4_cmd_mailbox *outbox,
835 struct mlx4_cmd_info *cmd)
842 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
843 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
845 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
846 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
850 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
851 struct mlx4_vhcr *vhcr,
852 struct mlx4_cmd_mailbox *inbox,
853 struct mlx4_cmd_mailbox *outbox,
854 struct mlx4_cmd_info *cmd)
856 if (slave != dev->caps.function)
858 return mlx4_common_dump_eth_stats(dev, slave,
859 vhcr->in_modifier, outbox);
862 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
864 if (!mlx4_is_mfunc(dev)) {
869 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
870 MLX4_STATS_TRAFFIC_DROPS_MASK |
871 MLX4_STATS_PORT_COUNTERS_MASK);
873 if (mlx4_is_master(dev))
874 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
876 EXPORT_SYMBOL(mlx4_set_stats_bitmap);