2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
61 table->max = 1 << dev->caps.log_num_macs;
65 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
78 static int validate_index(struct mlx4_dev *dev,
79 struct mlx4_mac_table *table, int index)
83 if (index < 0 || index >= table->max || !table->entries[index]) {
84 mlx4_warn(dev, "No valid Mac entry for the given index\n");
90 static int find_index(struct mlx4_dev *dev,
91 struct mlx4_mac_table *table, u64 mac)
95 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
96 if ((mac & MLX4_MAC_MASK) ==
97 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
104 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
107 struct mlx4_cmd_mailbox *mailbox;
111 mailbox = mlx4_alloc_cmd_mailbox(dev);
113 return PTR_ERR(mailbox);
115 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
117 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
119 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
120 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
122 mlx4_free_cmd_mailbox(dev, mailbox);
126 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
128 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
129 struct mlx4_mac_table *table = &info->mac_table;
133 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
134 (unsigned long long) mac, port);
136 mutex_lock(&table->mutex);
137 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
138 if (free < 0 && !table->entries[i]) {
143 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
144 /* MAC already registered, increment ref count */
151 mlx4_dbg(dev, "Free MAC index is %d\n", free);
153 if (table->total == table->max) {
154 /* No free mac entries */
159 /* Register new MAC */
160 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
162 err = mlx4_set_port_mac_table(dev, port, table->entries);
164 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
165 (unsigned long long) mac);
166 table->entries[free] = 0;
169 table->refs[free] = 1;
173 mutex_unlock(&table->mutex);
176 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
178 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
183 if (mlx4_is_mfunc(dev)) {
184 set_param_l(&out_param, port);
185 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
186 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
187 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
191 return get_param_l(&out_param);
193 return __mlx4_register_mac(dev, port, mac);
195 EXPORT_SYMBOL_GPL(mlx4_register_mac);
197 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
199 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
200 (port - 1) * (1 << dev->caps.log_num_macs);
202 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
204 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
206 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
207 struct mlx4_mac_table *table = &info->mac_table;
210 mutex_lock(&table->mutex);
211 index = find_index(dev, table, mac);
213 if (validate_index(dev, table, index))
215 if (--table->refs[index]) {
216 mlx4_dbg(dev, "Have more references for index %d,"
217 "no need to modify mac table\n", index);
221 table->entries[index] = 0;
222 mlx4_set_port_mac_table(dev, port, table->entries);
225 mutex_unlock(&table->mutex);
227 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
229 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
233 if (mlx4_is_mfunc(dev)) {
234 set_param_l(&out_param, port);
235 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
236 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
237 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
240 __mlx4_unregister_mac(dev, port, mac);
243 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
245 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
247 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
248 struct mlx4_mac_table *table = &info->mac_table;
249 int index = qpn - info->base_qpn;
252 /* CX1 doesn't support multi-functions */
253 mutex_lock(&table->mutex);
255 err = validate_index(dev, table, index);
259 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
261 err = mlx4_set_port_mac_table(dev, port, table->entries);
263 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
264 (unsigned long long) new_mac);
265 table->entries[index] = 0;
268 mutex_unlock(&table->mutex);
271 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
273 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
276 struct mlx4_cmd_mailbox *mailbox;
280 mailbox = mlx4_alloc_cmd_mailbox(dev);
282 return PTR_ERR(mailbox);
284 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
285 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
286 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
287 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
289 mlx4_free_cmd_mailbox(dev, mailbox);
294 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
296 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
299 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
300 if (table->refs[i] &&
301 (vid == (MLX4_VLAN_MASK &
302 be32_to_cpu(table->entries[i])))) {
303 /* VLAN already registered, increase reference count */
311 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
313 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
316 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
320 mutex_lock(&table->mutex);
322 if (table->total == table->max) {
323 /* No free vlan entries */
328 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
329 if (free < 0 && (table->refs[i] == 0)) {
334 if (table->refs[i] &&
335 (vlan == (MLX4_VLAN_MASK &
336 be32_to_cpu(table->entries[i])))) {
337 /* Vlan already registered, increase references count */
349 /* Register new VLAN */
350 table->refs[free] = 1;
351 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
353 err = mlx4_set_port_vlan_table(dev, port, table->entries);
355 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
356 table->refs[free] = 0;
357 table->entries[free] = 0;
364 mutex_unlock(&table->mutex);
368 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
376 if (mlx4_is_mfunc(dev)) {
377 set_param_l(&out_param, port);
378 err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN,
379 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
380 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
382 *index = get_param_l(&out_param);
386 return __mlx4_register_vlan(dev, port, vlan, index);
388 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
390 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
392 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
394 if (index < MLX4_VLAN_REGULAR) {
395 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
399 mutex_lock(&table->mutex);
400 if (!table->refs[index]) {
401 mlx4_warn(dev, "No vlan entry for index %d\n", index);
404 if (--table->refs[index]) {
405 mlx4_dbg(dev, "Have more references for index %d,"
406 "no need to modify vlan table\n", index);
409 table->entries[index] = 0;
410 mlx4_set_port_vlan_table(dev, port, table->entries);
413 mutex_unlock(&table->mutex);
416 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
420 if (mlx4_is_mfunc(dev)) {
421 set_param_l(&out_param, port);
422 (void) mlx4_cmd_imm(dev, index, &out_param, RES_VLAN,
423 RES_OP_RESERVE_AND_MAP,
424 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
428 __mlx4_unregister_vlan(dev, port, index);
430 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
432 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
434 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
438 inmailbox = mlx4_alloc_cmd_mailbox(dev);
439 if (IS_ERR(inmailbox))
440 return PTR_ERR(inmailbox);
442 outmailbox = mlx4_alloc_cmd_mailbox(dev);
443 if (IS_ERR(outmailbox)) {
444 mlx4_free_cmd_mailbox(dev, inmailbox);
445 return PTR_ERR(outmailbox);
448 inbuf = inmailbox->buf;
449 outbuf = outmailbox->buf;
450 memset(inbuf, 0, 256);
451 memset(outbuf, 0, 256);
456 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
457 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
459 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
460 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
463 *caps = *(__be32 *) (outbuf + 84);
464 mlx4_free_cmd_mailbox(dev, inmailbox);
465 mlx4_free_cmd_mailbox(dev, outmailbox);
469 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
470 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
472 struct mlx4_priv *priv = mlx4_priv(dev);
473 struct mlx4_port_info *port_info;
474 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
475 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
476 struct mlx4_set_port_rqp_calc_context *qpn_context;
477 struct mlx4_set_port_general_context *gen_context;
478 int reset_qkey_viols;
487 __be32 slave_cap_mask;
490 port = in_mod & 0xff;
491 in_modifier = in_mod >> 8;
493 port_info = &priv->port[port];
495 /* Slaves cannot perform SET_PORT operations except changing MTU */
497 if (slave != dev->caps.function &&
498 in_modifier != MLX4_SET_PORT_GENERAL) {
499 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
503 switch (in_modifier) {
504 case MLX4_SET_PORT_RQP_CALC:
505 qpn_context = inbox->buf;
506 qpn_context->base_qpn =
507 cpu_to_be32(port_info->base_qpn);
508 qpn_context->n_mac = 0x7;
509 promisc = be32_to_cpu(qpn_context->promisc) >>
510 SET_PORT_PROMISC_SHIFT;
511 qpn_context->promisc = cpu_to_be32(
512 promisc << SET_PORT_PROMISC_SHIFT |
513 port_info->base_qpn);
514 promisc = be32_to_cpu(qpn_context->mcast) >>
515 SET_PORT_MC_PROMISC_SHIFT;
516 qpn_context->mcast = cpu_to_be32(
517 promisc << SET_PORT_MC_PROMISC_SHIFT |
518 port_info->base_qpn);
520 case MLX4_SET_PORT_GENERAL:
521 gen_context = inbox->buf;
522 /* Mtu is configured as the max MTU among all the
523 * the functions on the port. */
524 mtu = be16_to_cpu(gen_context->mtu);
525 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
526 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
527 prev_mtu = slave_st->mtu[port];
528 slave_st->mtu[port] = mtu;
529 if (mtu > master->max_mtu[port])
530 master->max_mtu[port] = mtu;
531 if (mtu < prev_mtu && prev_mtu ==
532 master->max_mtu[port]) {
533 slave_st->mtu[port] = mtu;
534 master->max_mtu[port] = mtu;
535 for (i = 0; i < dev->num_slaves; i++) {
536 master->max_mtu[port] =
537 max(master->max_mtu[port],
538 master->slave_state[i].mtu[port]);
542 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
545 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
546 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
550 /* For IB, we only consider:
551 * - The capability mask, which is set to the aggregate of all
552 * slave function capabilities
553 * - The QKey violatin counter - reset according to each request.
556 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
557 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
558 new_cap_mask = ((__be32 *) inbox->buf)[2];
560 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
561 new_cap_mask = ((__be32 *) inbox->buf)[1];
564 /* slave may not set the IS_SM capability for the port */
565 if (slave != mlx4_master_func_num(dev) &&
566 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
569 /* No DEV_MGMT in multifunc mode */
570 if (mlx4_is_mfunc(dev) &&
571 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
576 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
577 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
578 for (i = 0; i < dev->num_slaves; i++)
580 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
582 /* only clear mailbox for guests. Master may be setting
583 * MTU or PKEY table size
585 if (slave != dev->caps.function)
586 memset(inbox->buf, 0, 256);
587 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
588 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
589 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
591 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
592 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
595 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
596 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
598 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
603 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
604 struct mlx4_vhcr *vhcr,
605 struct mlx4_cmd_mailbox *inbox,
606 struct mlx4_cmd_mailbox *outbox,
607 struct mlx4_cmd_info *cmd)
609 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
610 vhcr->op_modifier, inbox);
613 /* bit locations for set port command with zero op modifier */
615 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
616 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
617 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
618 MLX4_CHANGE_PORT_VL_CAP = 21,
619 MLX4_CHANGE_PORT_MTU_CAP = 22,
622 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
624 struct mlx4_cmd_mailbox *mailbox;
625 int err, vl_cap, pkey_tbl_flag = 0;
627 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
630 mailbox = mlx4_alloc_cmd_mailbox(dev);
632 return PTR_ERR(mailbox);
634 memset(mailbox->buf, 0, 256);
636 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
638 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
640 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
643 /* IB VL CAP enum isn't used by the firmware, just numerical values */
644 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
645 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
646 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
647 (1 << MLX4_CHANGE_PORT_VL_CAP) |
648 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
649 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
650 (vl_cap << MLX4_SET_PORT_VL_CAP));
651 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
652 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
657 mlx4_free_cmd_mailbox(dev, mailbox);
661 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
662 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
664 struct mlx4_cmd_mailbox *mailbox;
665 struct mlx4_set_port_general_context *context;
669 mailbox = mlx4_alloc_cmd_mailbox(dev);
671 return PTR_ERR(mailbox);
672 context = mailbox->buf;
673 memset(context, 0, sizeof *context);
675 context->flags = SET_PORT_GEN_ALL_VALID;
676 context->mtu = cpu_to_be16(mtu);
677 context->pptx = (pptx * (!pfctx)) << 7;
678 context->pfctx = pfctx;
679 context->pprx = (pprx * (!pfcrx)) << 7;
680 context->pfcrx = pfcrx;
682 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
683 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
684 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
686 mlx4_free_cmd_mailbox(dev, mailbox);
689 EXPORT_SYMBOL(mlx4_SET_PORT_general);
691 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
694 struct mlx4_cmd_mailbox *mailbox;
695 struct mlx4_set_port_rqp_calc_context *context;
698 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
699 MCAST_DIRECT : MCAST_DEFAULT;
701 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
704 mailbox = mlx4_alloc_cmd_mailbox(dev);
706 return PTR_ERR(mailbox);
707 context = mailbox->buf;
708 memset(context, 0, sizeof *context);
710 context->base_qpn = cpu_to_be32(base_qpn);
711 context->n_mac = dev->caps.log_num_macs;
712 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
714 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
716 context->intra_no_vlan = 0;
717 context->no_vlan = MLX4_NO_VLAN_IDX;
718 context->intra_vlan_miss = 0;
719 context->vlan_miss = MLX4_VLAN_MISS_IDX;
721 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
722 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
723 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
725 mlx4_free_cmd_mailbox(dev, mailbox);
728 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
730 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
732 struct mlx4_cmd_mailbox *mailbox;
733 struct mlx4_set_port_prio2tc_context *context;
738 mailbox = mlx4_alloc_cmd_mailbox(dev);
740 return PTR_ERR(mailbox);
741 context = mailbox->buf;
742 memset(context, 0, sizeof *context);
744 for (i = 0; i < MLX4_NUM_UP; i += 2)
745 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
747 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
748 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
749 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
751 mlx4_free_cmd_mailbox(dev, mailbox);
754 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
756 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
757 u8 *pg, u16 *ratelimit)
759 struct mlx4_cmd_mailbox *mailbox;
760 struct mlx4_set_port_scheduler_context *context;
765 mailbox = mlx4_alloc_cmd_mailbox(dev);
767 return PTR_ERR(mailbox);
768 context = mailbox->buf;
769 memset(context, 0, sizeof *context);
771 for (i = 0; i < MLX4_NUM_TC; i++) {
772 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
773 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
774 MLX4_RATELIMIT_DEFAULT;
776 tc->pg = htons(pg[i]);
777 tc->bw_precentage = htons(tc_tx_bw[i]);
779 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
780 tc->max_bw_value = htons(r);
783 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
784 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
785 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
787 mlx4_free_cmd_mailbox(dev, mailbox);
790 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
792 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
793 struct mlx4_vhcr *vhcr,
794 struct mlx4_cmd_mailbox *inbox,
795 struct mlx4_cmd_mailbox *outbox,
796 struct mlx4_cmd_info *cmd)
803 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
804 u64 mac, u64 clear, u8 mode)
806 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
807 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
810 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
812 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd)
823 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
824 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
826 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
827 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
831 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
832 struct mlx4_vhcr *vhcr,
833 struct mlx4_cmd_mailbox *inbox,
834 struct mlx4_cmd_mailbox *outbox,
835 struct mlx4_cmd_info *cmd)
837 if (slave != dev->caps.function)
839 return mlx4_common_dump_eth_stats(dev, slave,
840 vhcr->in_modifier, outbox);
843 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
845 if (!mlx4_is_mfunc(dev)) {
850 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
851 MLX4_STATS_TRAFFIC_DROPS_MASK |
852 MLX4_STATS_PORT_COUNTERS_MASK);
854 if (mlx4_is_master(dev))
855 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
857 EXPORT_SYMBOL(mlx4_set_stats_bitmap);