drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <asm-generic/kmap_types.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 enum {
  79         MLX5_CMD_STAT_OK                        = 0x0,
  80         MLX5_CMD_STAT_INT_ERR                   = 0x1,
  81         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
  82         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
  83         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
  84         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
  85         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
  86         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
  87         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
  88         MLX5_CMD_STAT_IX_ERR                    = 0xa,
  89         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
  90         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
  91         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
  92         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
  93         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
  94         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
  95 };
  96
  97 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  98                                            struct mlx5_cmd_msg *in,
  99                                            struct mlx5_cmd_msg *out,
 100                                            void *uout, int uout_size,
 101                                            mlx5_cmd_cbk_t cbk,
 102                                            void *context, int page_queue)
 103 {
 104         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
 105         struct mlx5_cmd_work_ent *ent;
 106
 107         ent = kzalloc(sizeof(*ent), alloc_flags);
 108         if (!ent)
 109                 return ERR_PTR(-ENOMEM);
 110
 111         ent->in         = in;
 112         ent->out        = out;
 113         ent->uout       = uout;
 114         ent->uout_size  = uout_size;
 115         ent->callback   = cbk;
 116         ent->context    = context;
 117         ent->cmd        = cmd;
 118         ent->page_queue = page_queue;
 119
 120         return ent;
 121 }
 122
 123 static u8 alloc_token(struct mlx5_cmd *cmd)
 124 {
 125         u8 token;
 126
 127         spin_lock(&cmd->token_lock);
 128         token = cmd->token++ % 255 + 1;
 129         spin_unlock(&cmd->token_lock);
 130
 131         return token;
 132 }
 133
 134 static int alloc_ent(struct mlx5_cmd *cmd)
 135 {
 136         unsigned long flags;
 137         int ret;
 138
 139         spin_lock_irqsave(&cmd->alloc_lock, flags);
 140         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 141         if (ret < cmd->max_reg_cmds)
 142                 clear_bit(ret, &cmd->bitmask);
 143         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 144
 145         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 146 }
 147
 148 static void free_ent(struct mlx5_cmd *cmd, int idx)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&cmd->alloc_lock, flags);
 153         set_bit(idx, &cmd->bitmask);
 154         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 155 }
 156
 157 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 158 {
 159         return cmd->cmd_buf + (idx << cmd->log_stride);
 160 }
 161
 162 static u8 xor8_buf(void *buf, int len)
 163 {
 164         u8 *ptr = buf;
 165         u8 sum = 0;
 166         int i;
 167
 168         for (i = 0; i < len; i++)
 169                 sum ^= ptr[i];
 170
 171         return sum;
 172 }
 173
 174 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 175 {
 176         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 177                 return -EINVAL;
 178
 179         if (xor8_buf(block, sizeof(*block)) != 0xff)
 180                 return -EINVAL;
 181
 182         return 0;
 183 }
 184
 185 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 186                            int csum)
 187 {
 188         block->token = token;
 189         if (csum) {
 190                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 191                                             sizeof(block->data) - 2);
 192                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 193         }
 194 }
 195
 196 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 197 {
 198         struct mlx5_cmd_mailbox *next = msg->next;
 199
 200         while (next) {
 201                 calc_block_sig(next->buf, token, csum);
 202                 next = next->next;
 203         }
 204 }
 205
 206 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 207 {
 208         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 209         calc_chain_sig(ent->in, ent->token, csum);
 210         calc_chain_sig(ent->out, ent->token, csum);
 211 }
 212
 213 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 214 {
 215         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 216         u8 own;
 217
 218         do {
 219                 own = ent->lay->status_own;
 220                 if (!(own & CMD_OWNER_HW)) {
 221                         ent->ret = 0;
 222                         return;
 223                 }
 224                 usleep_range(5000, 10000);
 225         } while (time_before(jiffies, poll_end));
 226
 227         ent->ret = -ETIMEDOUT;
 228 }
 229
 230 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 231 {
 232         kfree(ent);
 233 }
 234
 235
 236 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 237 {
 238         struct mlx5_cmd_mailbox *next = ent->out->next;
 239         int err;
 240         u8 sig;
 241
 242         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 243         if (sig != 0xff)
 244                 return -EINVAL;
 245
 246         while (next) {
 247                 err = verify_block_sig(next->buf);
 248                 if (err)
 249                         return err;
 250
 251                 next = next->next;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void dump_buf(void *buf, int size, int data_only, int offset)
 258 {
 259         __be32 *p = buf;
 260         int i;
 261
 262         for (i = 0; i < size; i += 16) {
 263                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 264                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 265                          be32_to_cpu(p[3]));
 266                 p += 4;
 267                 offset += 16;
 268         }
 269         if (!data_only)
 270                 pr_debug("\n");
 271 }
 272
 273 const char *mlx5_command_str(int command)
 274 {
 275         switch (command) {
 276         case MLX5_CMD_OP_QUERY_HCA_CAP:
 277                 return "QUERY_HCA_CAP";
 278
 279         case MLX5_CMD_OP_SET_HCA_CAP:
 280                 return "SET_HCA_CAP";
 281
 282         case MLX5_CMD_OP_QUERY_ADAPTER:
 283                 return "QUERY_ADAPTER";
 284
 285         case MLX5_CMD_OP_INIT_HCA:
 286                 return "INIT_HCA";
 287
 288         case MLX5_CMD_OP_TEARDOWN_HCA:
 289                 return "TEARDOWN_HCA";
 290
 291         case MLX5_CMD_OP_ENABLE_HCA:
 292                 return "MLX5_CMD_OP_ENABLE_HCA";
 293
 294         case MLX5_CMD_OP_DISABLE_HCA:
 295                 return "MLX5_CMD_OP_DISABLE_HCA";
 296
 297         case MLX5_CMD_OP_QUERY_PAGES:
 298                 return "QUERY_PAGES";
 299
 300         case MLX5_CMD_OP_MANAGE_PAGES:
 301                 return "MANAGE_PAGES";
 302
 303         case MLX5_CMD_OP_CREATE_MKEY:
 304                 return "CREATE_MKEY";
 305
 306         case MLX5_CMD_OP_QUERY_MKEY:
 307                 return "QUERY_MKEY";
 308
 309         case MLX5_CMD_OP_DESTROY_MKEY:
 310                 return "DESTROY_MKEY";
 311
 312         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 313                 return "QUERY_SPECIAL_CONTEXTS";
 314
 315         case MLX5_CMD_OP_CREATE_EQ:
 316                 return "CREATE_EQ";
 317
 318         case MLX5_CMD_OP_DESTROY_EQ:
 319                 return "DESTROY_EQ";
 320
 321         case MLX5_CMD_OP_QUERY_EQ:
 322                 return "QUERY_EQ";
 323
 324         case MLX5_CMD_OP_CREATE_CQ:
 325                 return "CREATE_CQ";
 326
 327         case MLX5_CMD_OP_DESTROY_CQ:
 328                 return "DESTROY_CQ";
 329
 330         case MLX5_CMD_OP_QUERY_CQ:
 331                 return "QUERY_CQ";
 332
 333         case MLX5_CMD_OP_MODIFY_CQ:
 334                 return "MODIFY_CQ";
 335
 336         case MLX5_CMD_OP_CREATE_QP:
 337                 return "CREATE_QP";
 338
 339         case MLX5_CMD_OP_DESTROY_QP:
 340                 return "DESTROY_QP";
 341
 342         case MLX5_CMD_OP_RST2INIT_QP:
 343                 return "RST2INIT_QP";
 344
 345         case MLX5_CMD_OP_INIT2RTR_QP:
 346                 return "INIT2RTR_QP";
 347
 348         case MLX5_CMD_OP_RTR2RTS_QP:
 349                 return "RTR2RTS_QP";
 350
 351         case MLX5_CMD_OP_RTS2RTS_QP:
 352                 return "RTS2RTS_QP";
 353
 354         case MLX5_CMD_OP_SQERR2RTS_QP:
 355                 return "SQERR2RTS_QP";
 356
 357         case MLX5_CMD_OP_2ERR_QP:
 358                 return "2ERR_QP";
 359
 360         case MLX5_CMD_OP_2RST_QP:
 361                 return "2RST_QP";
 362
 363         case MLX5_CMD_OP_QUERY_QP:
 364                 return "QUERY_QP";
 365
 366         case MLX5_CMD_OP_MAD_IFC:
 367                 return "MAD_IFC";
 368
 369         case MLX5_CMD_OP_INIT2INIT_QP:
 370                 return "INIT2INIT_QP";
 371
 372         case MLX5_CMD_OP_CREATE_PSV:
 373                 return "CREATE_PSV";
 374
 375         case MLX5_CMD_OP_DESTROY_PSV:
 376                 return "DESTROY_PSV";
 377
 378         case MLX5_CMD_OP_CREATE_SRQ:
 379                 return "CREATE_SRQ";
 380
 381         case MLX5_CMD_OP_DESTROY_SRQ:
 382                 return "DESTROY_SRQ";
 383
 384         case MLX5_CMD_OP_QUERY_SRQ:
 385                 return "QUERY_SRQ";
 386
 387         case MLX5_CMD_OP_ARM_RQ:
 388                 return "ARM_RQ";
 389
 390         case MLX5_CMD_OP_RESIZE_SRQ:
 391                 return "RESIZE_SRQ";
 392
 393         case MLX5_CMD_OP_ALLOC_PD:
 394                 return "ALLOC_PD";
 395
 396         case MLX5_CMD_OP_DEALLOC_PD:
 397                 return "DEALLOC_PD";
 398
 399         case MLX5_CMD_OP_ALLOC_UAR:
 400                 return "ALLOC_UAR";
 401
 402         case MLX5_CMD_OP_DEALLOC_UAR:
 403                 return "DEALLOC_UAR";
 404
 405         case MLX5_CMD_OP_ATTACH_TO_MCG:
 406                 return "ATTACH_TO_MCG";
 407
 408         case MLX5_CMD_OP_DETACH_FROM_MCG:
 409                 return "DETACH_FROM_MCG";
 410
 411         case MLX5_CMD_OP_ALLOC_XRCD:
 412                 return "ALLOC_XRCD";
 413
 414         case MLX5_CMD_OP_DEALLOC_XRCD:
 415                 return "DEALLOC_XRCD";
 416
 417         case MLX5_CMD_OP_ACCESS_REG:
 418                 return "MLX5_CMD_OP_ACCESS_REG";
 419
 420         default: return "unknown command opcode";
 421         }
 422 }
 423
 424 static void dump_command(struct mlx5_core_dev *dev,
 425                          struct mlx5_cmd_work_ent *ent, int input)
 426 {
 427         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 428         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 429         struct mlx5_cmd_mailbox *next = msg->next;
 430         int data_only;
 431         u32 offset = 0;
 432         int dump_len;
 433
 434         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 435
 436         if (data_only)
 437                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 438                                    "dump command data %s(0x%x) %s\n",
 439                                    mlx5_command_str(op), op,
 440                                    input ? "INPUT" : "OUTPUT");
 441         else
 442                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 443                               mlx5_command_str(op), op,
 444                               input ? "INPUT" : "OUTPUT");
 445
 446         if (data_only) {
 447                 if (input) {
 448                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 449                         offset += sizeof(ent->lay->in);
 450                 } else {
 451                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 452                         offset += sizeof(ent->lay->out);
 453                 }
 454         } else {
 455                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 456                 offset += sizeof(*ent->lay);
 457         }
 458
 459         while (next && offset < msg->len) {
 460                 if (data_only) {
 461                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 462                         dump_buf(next->buf, dump_len, 1, offset);
 463                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 464                 } else {
 465                         mlx5_core_dbg(dev, "command block:\n");
 466                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 467                         offset += sizeof(struct mlx5_cmd_prot_block);
 468                 }
 469                 next = next->next;
 470         }
 471
 472         if (data_only)
 473                 pr_debug("\n");
 474 }
 475
 476 static void cmd_work_handler(struct work_struct *work)
 477 {
 478         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 479         struct mlx5_cmd *cmd = ent->cmd;
 480         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 481         struct mlx5_cmd_layout *lay;
 482         struct semaphore *sem;
 483
 484         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 485         down(sem);
 486         if (!ent->page_queue) {
 487                 ent->idx = alloc_ent(cmd);
 488                 if (ent->idx < 0) {
 489                         mlx5_core_err(dev, "failed to allocate command entry\n");
 490                         up(sem);
 491                         return;
 492                 }
 493         } else {
 494                 ent->idx = cmd->max_reg_cmds;
 495         }
 496
 497         ent->token = alloc_token(cmd);
 498         cmd->ent_arr[ent->idx] = ent;
 499         lay = get_inst(cmd, ent->idx);
 500         ent->lay = lay;
 501         memset(lay, 0, sizeof(*lay));
 502         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 503         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 504         if (ent->in->next)
 505                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 506         lay->inlen = cpu_to_be32(ent->in->len);
 507         if (ent->out->next)
 508                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 509         lay->outlen = cpu_to_be32(ent->out->len);
 510         lay->type = MLX5_PCI_CMD_XPORT;
 511         lay->token = ent->token;
 512         lay->status_own = CMD_OWNER_HW;
 513         set_signature(ent, !cmd->checksum_disabled);
 514         dump_command(dev, ent, 1);
 515         ent->ts1 = ktime_get_ns();
 516
 517         /* ring doorbell after the descriptor is valid */
 518         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 519         wmb();
 520         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 521         mmiowb();
 522         /* if not in polling don't use ent after this point */
 523         if (cmd->mode == CMD_MODE_POLLING) {
 524                 poll_timeout(ent);
 525                 /* make sure we read the descriptor after ownership is SW */
 526                 rmb();
 527                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 528         }
 529 }
 530
 531 static const char *deliv_status_to_str(u8 status)
 532 {
 533         switch (status) {
 534         case MLX5_CMD_DELIVERY_STAT_OK:
 535                 return "no errors";
 536         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 537                 return "signature error";
 538         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 539                 return "token error";
 540         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 541                 return "bad block number";
 542         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 543                 return "output pointer not aligned to block size";
 544         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 545                 return "input pointer not aligned to block size";
 546         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 547                 return "firmware internal error";
 548         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 549                 return "command input length error";
 550         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 551                 return "command ouput length error";
 552         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 553                 return "reserved fields not cleared";
 554         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 555                 return "bad command descriptor type";
 556         default:
 557                 return "unknown status code";
 558         }
 559 }
 560
 561 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 562 {
 563         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 564
 565         return be16_to_cpu(hdr->opcode);
 566 }
 567
 568 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 569 {
 570         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 571         struct mlx5_cmd *cmd = &dev->cmd;
 572         int err;
 573
 574         if (cmd->mode == CMD_MODE_POLLING) {
 575                 wait_for_completion(&ent->done);
 576                 err = ent->ret;
 577         } else {
 578                 if (!wait_for_completion_timeout(&ent->done, timeout))
 579                         err = -ETIMEDOUT;
 580                 else
 581                         err = 0;
 582         }
 583         if (err == -ETIMEDOUT) {
 584                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 585                                mlx5_command_str(msg_to_opcode(ent->in)),
 586                                msg_to_opcode(ent->in));
 587         }
 588         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 589                       err, deliv_status_to_str(ent->status), ent->status);
 590
 591         return err;
 592 }
 593
 594 /*  Notes:
 595  *    1. Callback functions may not sleep
 596  *    2. page queue commands do not support asynchrous completion
 597  */
 598 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 599                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 600                            mlx5_cmd_cbk_t callback,
 601                            void *context, int page_queue, u8 *status)
 602 {
 603         struct mlx5_cmd *cmd = &dev->cmd;
 604         struct mlx5_cmd_work_ent *ent;
 605         struct mlx5_cmd_stats *stats;
 606         int err = 0;
 607         s64 ds;
 608         u16 op;
 609
 610         if (callback && page_queue)
 611                 return -EINVAL;
 612
 613         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 614                         page_queue);
 615         if (IS_ERR(ent))
 616                 return PTR_ERR(ent);
 617
 618         if (!callback)
 619                 init_completion(&ent->done);
 620
 621         INIT_WORK(&ent->work, cmd_work_handler);
 622         if (page_queue) {
 623                 cmd_work_handler(&ent->work);
 624         } else if (!queue_work(cmd->wq, &ent->work)) {
 625                 mlx5_core_warn(dev, "failed to queue work\n");
 626                 err = -ENOMEM;
 627                 goto out_free;
 628         }
 629
 630         if (!callback) {
 631                 err = wait_func(dev, ent);
 632                 if (err == -ETIMEDOUT)
 633                         goto out;
 634
 635                 ds = ent->ts2 - ent->ts1;
 636                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 637                 if (op < ARRAY_SIZE(cmd->stats)) {
 638                         stats = &cmd->stats[op];
 639                         spin_lock_irq(&stats->lock);
 640                         stats->sum += ds;
 641                         ++stats->n;
 642                         spin_unlock_irq(&stats->lock);
 643                 }
 644                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 645                                    "fw exec time for %s is %lld nsec\n",
 646                                    mlx5_command_str(op), ds);
 647                 *status = ent->status;
 648                 free_cmd(ent);
 649         }
 650
 651         return err;
 652
 653 out_free:
 654         free_cmd(ent);
 655 out:
 656         return err;
 657 }
 658
 659 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 660                          size_t count, loff_t *pos)
 661 {
 662         struct mlx5_core_dev *dev = filp->private_data;
 663         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 664         char lbuf[3];
 665         int err;
 666
 667         if (!dbg->in_msg || !dbg->out_msg)
 668                 return -ENOMEM;
 669
 670         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 671                 return -EFAULT;
 672
 673         lbuf[sizeof(lbuf) - 1] = 0;
 674
 675         if (strcmp(lbuf, "go"))
 676                 return -EINVAL;
 677
 678         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 679
 680         return err ? err : count;
 681 }
 682
 683
 684 static const struct file_operations fops = {
 685         .owner  = THIS_MODULE,
 686         .open   = simple_open,
 687         .write  = dbg_write,
 688 };
 689
 690 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 691 {
 692         struct mlx5_cmd_prot_block *block;
 693         struct mlx5_cmd_mailbox *next;
 694         int copy;
 695
 696         if (!to || !from)
 697                 return -ENOMEM;
 698
 699         copy = min_t(int, size, sizeof(to->first.data));
 700         memcpy(to->first.data, from, copy);
 701         size -= copy;
 702         from += copy;
 703
 704         next = to->next;
 705         while (size) {
 706                 if (!next) {
 707                         /* this is a BUG */
 708                         return -ENOMEM;
 709                 }
 710
 711                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 712                 block = next->buf;
 713                 memcpy(block->data, from, copy);
 714                 from += copy;
 715                 size -= copy;
 716                 next = next->next;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 723 {
 724         struct mlx5_cmd_prot_block *block;
 725         struct mlx5_cmd_mailbox *next;
 726         int copy;
 727
 728         if (!to || !from)
 729                 return -ENOMEM;
 730
 731         copy = min_t(int, size, sizeof(from->first.data));
 732         memcpy(to, from->first.data, copy);
 733         size -= copy;
 734         to += copy;
 735
 736         next = from->next;
 737         while (size) {
 738                 if (!next) {
 739                         /* this is a BUG */
 740                         return -ENOMEM;
 741                 }
 742
 743                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 744                 block = next->buf;
 745
 746                 memcpy(to, block->data, copy);
 747                 to += copy;
 748                 size -= copy;
 749                 next = next->next;
 750         }
 751
 752         return 0;
 753 }
 754
 755 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 756                                               gfp_t flags)
 757 {
 758         struct mlx5_cmd_mailbox *mailbox;
 759
 760         mailbox = kmalloc(sizeof(*mailbox), flags);
 761         if (!mailbox)
 762                 return ERR_PTR(-ENOMEM);
 763
 764         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 765                                       &mailbox->dma);
 766         if (!mailbox->buf) {
 767                 mlx5_core_dbg(dev, "failed allocation\n");
 768                 kfree(mailbox);
 769                 return ERR_PTR(-ENOMEM);
 770         }
 771         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 772         mailbox->next = NULL;
 773
 774         return mailbox;
 775 }
 776
 777 static void free_cmd_box(struct mlx5_core_dev *dev,
 778                          struct mlx5_cmd_mailbox *mailbox)
 779 {
 780         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 781         kfree(mailbox);
 782 }
 783
 784 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 785                                                gfp_t flags, int size)
 786 {
 787         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 788         struct mlx5_cmd_prot_block *block;
 789         struct mlx5_cmd_msg *msg;
 790         int blen;
 791         int err;
 792         int n;
 793         int i;
 794
 795         msg = kzalloc(sizeof(*msg), flags);
 796         if (!msg)
 797                 return ERR_PTR(-ENOMEM);
 798
 799         blen = size - min_t(int, sizeof(msg->first.data), size);
 800         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 801
 802         for (i = 0; i < n; i++) {
 803                 tmp = alloc_cmd_box(dev, flags);
 804                 if (IS_ERR(tmp)) {
 805                         mlx5_core_warn(dev, "failed allocating block\n");
 806                         err = PTR_ERR(tmp);
 807                         goto err_alloc;
 808                 }
 809
 810                 block = tmp->buf;
 811                 tmp->next = head;
 812                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 813                 block->block_num = cpu_to_be32(n - i - 1);
 814                 head = tmp;
 815         }
 816         msg->next = head;
 817         msg->len = size;
 818         return msg;
 819
 820 err_alloc:
 821         while (head) {
 822                 tmp = head->next;
 823                 free_cmd_box(dev, head);
 824                 head = tmp;
 825         }
 826         kfree(msg);
 827
 828         return ERR_PTR(err);
 829 }
 830
 831 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 832                                   struct mlx5_cmd_msg *msg)
 833 {
 834         struct mlx5_cmd_mailbox *head = msg->next;
 835         struct mlx5_cmd_mailbox *next;
 836
 837         while (head) {
 838                 next = head->next;
 839                 free_cmd_box(dev, head);
 840                 head = next;
 841         }
 842         kfree(msg);
 843 }
 844
 845 static ssize_t data_write(struct file *filp, const char __user *buf,
 846                           size_t count, loff_t *pos)
 847 {
 848         struct mlx5_core_dev *dev = filp->private_data;
 849         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 850         void *ptr;
 851         int err;
 852
 853         if (*pos != 0)
 854                 return -EINVAL;
 855
 856         kfree(dbg->in_msg);
 857         dbg->in_msg = NULL;
 858         dbg->inlen = 0;
 859
 860         ptr = kzalloc(count, GFP_KERNEL);
 861         if (!ptr)
 862                 return -ENOMEM;
 863
 864         if (copy_from_user(ptr, buf, count)) {
 865                 err = -EFAULT;
 866                 goto out;
 867         }
 868         dbg->in_msg = ptr;
 869         dbg->inlen = count;
 870
 871         *pos = count;
 872
 873         return count;
 874
 875 out:
 876         kfree(ptr);
 877         return err;
 878 }
 879
 880 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
 881                          loff_t *pos)
 882 {
 883         struct mlx5_core_dev *dev = filp->private_data;
 884         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 885         int copy;
 886
 887         if (*pos)
 888                 return 0;
 889
 890         if (!dbg->out_msg)
 891                 return -ENOMEM;
 892
 893         copy = min_t(int, count, dbg->outlen);
 894         if (copy_to_user(buf, dbg->out_msg, copy))
 895                 return -EFAULT;
 896
 897         *pos += copy;
 898
 899         return copy;
 900 }
 901
 902 static const struct file_operations dfops = {
 903         .owner  = THIS_MODULE,
 904         .open   = simple_open,
 905         .write  = data_write,
 906         .read   = data_read,
 907 };
 908
 909 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
 910                            loff_t *pos)
 911 {
 912         struct mlx5_core_dev *dev = filp->private_data;
 913         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 914         char outlen[8];
 915         int err;
 916
 917         if (*pos)
 918                 return 0;
 919
 920         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
 921         if (err < 0)
 922                 return err;
 923
 924         if (copy_to_user(buf, &outlen, err))
 925                 return -EFAULT;
 926
 927         *pos += err;
 928
 929         return err;
 930 }
 931
 932 static ssize_t outlen_write(struct file *filp, const char __user *buf,
 933                             size_t count, loff_t *pos)
 934 {
 935         struct mlx5_core_dev *dev = filp->private_data;
 936         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 937         char outlen_str[8];
 938         int outlen;
 939         void *ptr;
 940         int err;
 941
 942         if (*pos != 0 || count > 6)
 943                 return -EINVAL;
 944
 945         kfree(dbg->out_msg);
 946         dbg->out_msg = NULL;
 947         dbg->outlen = 0;
 948
 949         if (copy_from_user(outlen_str, buf, count))
 950                 return -EFAULT;
 951
 952         outlen_str[7] = 0;
 953
 954         err = sscanf(outlen_str, "%d", &outlen);
 955         if (err < 0)
 956                 return err;
 957
 958         ptr = kzalloc(outlen, GFP_KERNEL);
 959         if (!ptr)
 960                 return -ENOMEM;
 961
 962         dbg->out_msg = ptr;
 963         dbg->outlen = outlen;
 964
 965         *pos = count;
 966
 967         return count;
 968 }
 969
 970 static const struct file_operations olfops = {
 971         .owner  = THIS_MODULE,
 972         .open   = simple_open,
 973         .write  = outlen_write,
 974         .read   = outlen_read,
 975 };
 976
 977 static void set_wqname(struct mlx5_core_dev *dev)
 978 {
 979         struct mlx5_cmd *cmd = &dev->cmd;
 980
 981         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
 982                  dev_name(&dev->pdev->dev));
 983 }
 984
 985 static void clean_debug_files(struct mlx5_core_dev *dev)
 986 {
 987         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 988
 989         if (!mlx5_debugfs_root)
 990                 return;
 991
 992         mlx5_cmdif_debugfs_cleanup(dev);
 993         debugfs_remove_recursive(dbg->dbg_root);
 994 }
 995
 996 static int create_debugfs_files(struct mlx5_core_dev *dev)
 997 {
 998         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 999         int err = -ENOMEM;
1000
1001         if (!mlx5_debugfs_root)
1002                 return 0;
1003
1004         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1005         if (!dbg->dbg_root)
1006                 return err;
1007
1008         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1009                                           dev, &dfops);
1010         if (!dbg->dbg_in)
1011                 goto err_dbg;
1012
1013         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1014                                            dev, &dfops);
1015         if (!dbg->dbg_out)
1016                 goto err_dbg;
1017
1018         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1019                                               dev, &olfops);
1020         if (!dbg->dbg_outlen)
1021                 goto err_dbg;
1022
1023         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1024                                             &dbg->status);
1025         if (!dbg->dbg_status)
1026                 goto err_dbg;
1027
1028         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1029         if (!dbg->dbg_run)
1030                 goto err_dbg;
1031
1032         mlx5_cmdif_debugfs_init(dev);
1033
1034         return 0;
1035
1036 err_dbg:
1037         clean_debug_files(dev);
1038         return err;
1039 }
1040
1041 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1042 {
1043         struct mlx5_cmd *cmd = &dev->cmd;
1044         int i;
1045
1046         for (i = 0; i < cmd->max_reg_cmds; i++)
1047                 down(&cmd->sem);
1048
1049         down(&cmd->pages_sem);
1050
1051         flush_workqueue(cmd->wq);
1052
1053         cmd->mode = CMD_MODE_EVENTS;
1054
1055         up(&cmd->pages_sem);
1056         for (i = 0; i < cmd->max_reg_cmds; i++)
1057                 up(&cmd->sem);
1058 }
1059
1060 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1061 {
1062         struct mlx5_cmd *cmd = &dev->cmd;
1063         int i;
1064
1065         for (i = 0; i < cmd->max_reg_cmds; i++)
1066                 down(&cmd->sem);
1067
1068         down(&cmd->pages_sem);
1069
1070         flush_workqueue(cmd->wq);
1071         cmd->mode = CMD_MODE_POLLING;
1072
1073         up(&cmd->pages_sem);
1074         for (i = 0; i < cmd->max_reg_cmds; i++)
1075                 up(&cmd->sem);
1076 }
1077
1078 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1079 {
1080         unsigned long flags;
1081
1082         if (msg->cache) {
1083                 spin_lock_irqsave(&msg->cache->lock, flags);
1084                 list_add_tail(&msg->list, &msg->cache->head);
1085                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1086         } else {
1087                 mlx5_free_cmd_msg(dev, msg);
1088         }
1089 }
1090
1091 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector)
1092 {
1093         struct mlx5_cmd *cmd = &dev->cmd;
1094         struct mlx5_cmd_work_ent *ent;
1095         mlx5_cmd_cbk_t callback;
1096         void *context;
1097         int err;
1098         int i;
1099         s64 ds;
1100         struct mlx5_cmd_stats *stats;
1101         unsigned long flags;
1102
1103         for (i = 0; i < (1 << cmd->log_sz); i++) {
1104                 if (test_bit(i, &vector)) {
1105                         struct semaphore *sem;
1106
1107                         ent = cmd->ent_arr[i];
1108                         if (ent->page_queue)
1109                                 sem = &cmd->pages_sem;
1110                         else
1111                                 sem = &cmd->sem;
1112                         ent->ts2 = ktime_get_ns();
1113                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1114                         dump_command(dev, ent, 0);
1115                         if (!ent->ret) {
1116                                 if (!cmd->checksum_disabled)
1117                                         ent->ret = verify_signature(ent);
1118                                 else
1119                                         ent->ret = 0;
1120                                 ent->status = ent->lay->status_own >> 1;
1121                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1122                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1123                         }
1124                         free_ent(cmd, ent->idx);
1125                         if (ent->callback) {
1126                                 ds = ent->ts2 - ent->ts1;
1127                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1128                                         stats = &cmd->stats[ent->op];
1129                                         spin_lock_irqsave(&stats->lock, flags);
1130                                         stats->sum += ds;
1131                                         ++stats->n;
1132                                         spin_unlock_irqrestore(&stats->lock, flags);
1133                                 }
1134
1135                                 callback = ent->callback;
1136                                 context = ent->context;
1137                                 err = ent->ret;
1138                                 if (!err)
1139                                         err = mlx5_copy_from_msg(ent->uout,
1140                                                                  ent->out,
1141                                                                  ent->uout_size);
1142
1143                                 mlx5_free_cmd_msg(dev, ent->out);
1144                                 free_msg(dev, ent->in);
1145
1146                                 free_cmd(ent);
1147                                 callback(err, context);
1148                         } else {
1149                                 complete(&ent->done);
1150                         }
1151                         up(sem);
1152                 }
1153         }
1154 }
1155 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1156
1157 static int status_to_err(u8 status)
1158 {
1159         return status ? -1 : 0; /* TBD more meaningful codes */
1160 }
1161
1162 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1163                                       gfp_t gfp)
1164 {
1165         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1166         struct mlx5_cmd *cmd = &dev->cmd;
1167         struct cache_ent *ent = NULL;
1168
1169         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1170                 ent = &cmd->cache.large;
1171         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1172                 ent = &cmd->cache.med;
1173
1174         if (ent) {
1175                 spin_lock_irq(&ent->lock);
1176                 if (!list_empty(&ent->head)) {
1177                         msg = list_entry(ent->head.next, typeof(*msg), list);
1178                         /* For cached lists, we must explicitly state what is
1179                          * the real size
1180                          */
1181                         msg->len = in_size;
1182                         list_del(&msg->list);
1183                 }
1184                 spin_unlock_irq(&ent->lock);
1185         }
1186
1187         if (IS_ERR(msg))
1188                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1189
1190         return msg;
1191 }
1192
1193 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1194 {
1195         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1196 }
1197
1198 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1199                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1200 {
1201         struct mlx5_cmd_msg *inb;
1202         struct mlx5_cmd_msg *outb;
1203         int pages_queue;
1204         gfp_t gfp;
1205         int err;
1206         u8 status = 0;
1207
1208         pages_queue = is_manage_pages(in);
1209         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1210
1211         inb = alloc_msg(dev, in_size, gfp);
1212         if (IS_ERR(inb)) {
1213                 err = PTR_ERR(inb);
1214                 return err;
1215         }
1216
1217         err = mlx5_copy_to_msg(inb, in, in_size);
1218         if (err) {
1219                 mlx5_core_warn(dev, "err %d\n", err);
1220                 goto out_in;
1221         }
1222
1223         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1224         if (IS_ERR(outb)) {
1225                 err = PTR_ERR(outb);
1226                 goto out_in;
1227         }
1228
1229         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1230                               pages_queue, &status);
1231         if (err)
1232                 goto out_out;
1233
1234         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1235         if (status) {
1236                 err = status_to_err(status);
1237                 goto out_out;
1238         }
1239
1240         if (!callback)
1241                 err = mlx5_copy_from_msg(out, outb, out_size);
1242
1243 out_out:
1244         if (!callback)
1245                 mlx5_free_cmd_msg(dev, outb);
1246
1247 out_in:
1248         if (!callback)
1249                 free_msg(dev, inb);
1250         return err;
1251 }
1252
1253 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1254                   int out_size)
1255 {
1256         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1257 }
1258 EXPORT_SYMBOL(mlx5_cmd_exec);
1259
1260 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1261                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1262                      void *context)
1263 {
1264         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1265 }
1266 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1267
1268 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1269 {
1270         struct mlx5_cmd *cmd = &dev->cmd;
1271         struct mlx5_cmd_msg *msg;
1272         struct mlx5_cmd_msg *n;
1273
1274         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1275                 list_del(&msg->list);
1276                 mlx5_free_cmd_msg(dev, msg);
1277         }
1278
1279         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1280                 list_del(&msg->list);
1281                 mlx5_free_cmd_msg(dev, msg);
1282         }
1283 }
1284
1285 static int create_msg_cache(struct mlx5_core_dev *dev)
1286 {
1287         struct mlx5_cmd *cmd = &dev->cmd;
1288         struct mlx5_cmd_msg *msg;
1289         int err;
1290         int i;
1291
1292         spin_lock_init(&cmd->cache.large.lock);
1293         INIT_LIST_HEAD(&cmd->cache.large.head);
1294         spin_lock_init(&cmd->cache.med.lock);
1295         INIT_LIST_HEAD(&cmd->cache.med.head);
1296
1297         for (i = 0; i < NUM_LONG_LISTS; i++) {
1298                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1299                 if (IS_ERR(msg)) {
1300                         err = PTR_ERR(msg);
1301                         goto ex_err;
1302                 }
1303                 msg->cache = &cmd->cache.large;
1304                 list_add_tail(&msg->list, &cmd->cache.large.head);
1305         }
1306
1307         for (i = 0; i < NUM_MED_LISTS; i++) {
1308                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1309                 if (IS_ERR(msg)) {
1310                         err = PTR_ERR(msg);
1311                         goto ex_err;
1312                 }
1313                 msg->cache = &cmd->cache.med;
1314                 list_add_tail(&msg->list, &cmd->cache.med.head);
1315         }
1316
1317         return 0;
1318
1319 ex_err:
1320         destroy_msg_cache(dev);
1321         return err;
1322 }
1323
1324 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1325 {
1326         struct device *ddev = &dev->pdev->dev;
1327
1328         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1329                                                  &cmd->alloc_dma, GFP_KERNEL);
1330         if (!cmd->cmd_alloc_buf)
1331                 return -ENOMEM;
1332
1333         /* make sure it is aligned to 4K */
1334         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1335                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1336                 cmd->dma = cmd->alloc_dma;
1337                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1338                 return 0;
1339         }
1340
1341         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1342                           cmd->alloc_dma);
1343         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1344                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1345                                                  &cmd->alloc_dma, GFP_KERNEL);
1346         if (!cmd->cmd_alloc_buf)
1347                 return -ENOMEM;
1348
1349         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1350         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1351         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1352         return 0;
1353 }
1354
1355 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1356 {
1357         struct device *ddev = &dev->pdev->dev;
1358
1359         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1360                           cmd->alloc_dma);
1361 }
1362
1363 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1364 {
1365         int size = sizeof(struct mlx5_cmd_prot_block);
1366         int align = roundup_pow_of_two(size);
1367         struct mlx5_cmd *cmd = &dev->cmd;
1368         u32 cmd_h, cmd_l;
1369         u16 cmd_if_rev;
1370         int err;
1371         int i;
1372
1373         cmd_if_rev = cmdif_rev(dev);
1374         if (cmd_if_rev != CMD_IF_REV) {
1375                 dev_err(&dev->pdev->dev,
1376                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1377                         CMD_IF_REV, cmd_if_rev);
1378                 return -EINVAL;
1379         }
1380
1381         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1382         if (!cmd->pool)
1383                 return -ENOMEM;
1384
1385         err = alloc_cmd_page(dev, cmd);
1386         if (err)
1387                 goto err_free_pool;
1388
1389         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1390         cmd->log_sz = cmd_l >> 4 & 0xf;
1391         cmd->log_stride = cmd_l & 0xf;
1392         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1393                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1394                         1 << cmd->log_sz);
1395                 err = -EINVAL;
1396                 goto err_free_page;
1397         }
1398
1399         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1400                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1401                 err = -EINVAL;
1402                 goto err_free_page;
1403         }
1404
1405         cmd->checksum_disabled = 1;
1406         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1407         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1408
1409         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1410         if (cmd->cmdif_rev > CMD_IF_REV) {
1411                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1412                         CMD_IF_REV, cmd->cmdif_rev);
1413                 err = -ENOTSUPP;
1414                 goto err_free_page;
1415         }
1416
1417         spin_lock_init(&cmd->alloc_lock);
1418         spin_lock_init(&cmd->token_lock);
1419         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1420                 spin_lock_init(&cmd->stats[i].lock);
1421
1422         sema_init(&cmd->sem, cmd->max_reg_cmds);
1423         sema_init(&cmd->pages_sem, 1);
1424
1425         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1426         cmd_l = (u32)(cmd->dma);
1427         if (cmd_l & 0xfff) {
1428                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1429                 err = -ENOMEM;
1430                 goto err_free_page;
1431         }
1432
1433         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1434         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1435
1436         /* Make sure firmware sees the complete address before we proceed */
1437         wmb();
1438
1439         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1440
1441         cmd->mode = CMD_MODE_POLLING;
1442
1443         err = create_msg_cache(dev);
1444         if (err) {
1445                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1446                 goto err_free_page;
1447         }
1448
1449         set_wqname(dev);
1450         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1451         if (!cmd->wq) {
1452                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1453                 err = -ENOMEM;
1454                 goto err_cache;
1455         }
1456
1457         err = create_debugfs_files(dev);
1458         if (err) {
1459                 err = -ENOMEM;
1460                 goto err_wq;
1461         }
1462
1463         return 0;
1464
1465 err_wq:
1466         destroy_workqueue(cmd->wq);
1467
1468 err_cache:
1469         destroy_msg_cache(dev);
1470
1471 err_free_page:
1472         free_cmd_page(dev, cmd);
1473
1474 err_free_pool:
1475         pci_pool_destroy(cmd->pool);
1476
1477         return err;
1478 }
1479 EXPORT_SYMBOL(mlx5_cmd_init);
1480
1481 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1482 {
1483         struct mlx5_cmd *cmd = &dev->cmd;
1484
1485         clean_debug_files(dev);
1486         destroy_workqueue(cmd->wq);
1487         destroy_msg_cache(dev);
1488         free_cmd_page(dev, cmd);
1489         pci_pool_destroy(cmd->pool);
1490 }
1491 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1492
1493 static const char *cmd_status_str(u8 status)
1494 {
1495         switch (status) {
1496         case MLX5_CMD_STAT_OK:
1497                 return "OK";
1498         case MLX5_CMD_STAT_INT_ERR:
1499                 return "internal error";
1500         case MLX5_CMD_STAT_BAD_OP_ERR:
1501                 return "bad operation";
1502         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1503                 return "bad parameter";
1504         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1505                 return "bad system state";
1506         case MLX5_CMD_STAT_BAD_RES_ERR:
1507                 return "bad resource";
1508         case MLX5_CMD_STAT_RES_BUSY:
1509                 return "resource busy";
1510         case MLX5_CMD_STAT_LIM_ERR:
1511                 return "limits exceeded";
1512         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1513                 return "bad resource state";
1514         case MLX5_CMD_STAT_IX_ERR:
1515                 return "bad index";
1516         case MLX5_CMD_STAT_NO_RES_ERR:
1517                 return "no resources";
1518         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1519                 return "bad input length";
1520         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1521                 return "bad output length";
1522         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1523                 return "bad QP state";
1524         case MLX5_CMD_STAT_BAD_PKT_ERR:
1525                 return "bad packet (discarded)";
1526         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1527                 return "bad size too many outstanding CQEs";
1528         default:
1529                 return "unknown status";
1530         }
1531 }
1532
1533 static int cmd_status_to_err(u8 status)
1534 {
1535         switch (status) {
1536         case MLX5_CMD_STAT_OK:                          return 0;
1537         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1538         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1539         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1540         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1541         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1542         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1543         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1544         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1545         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1546         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1547         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1548         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1549         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1550         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1551         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1552         default:                                        return -EIO;
1553         }
1554 }
1555
1556 /* this will be available till all the commands use set/get macros */
1557 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1558 {
1559         if (!hdr->status)
1560                 return 0;
1561
1562         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1563                 cmd_status_str(hdr->status), hdr->status,
1564                 be32_to_cpu(hdr->syndrome));
1565
1566         return cmd_status_to_err(hdr->status);
1567 }
1568
1569 int mlx5_cmd_status_to_err_v2(void *ptr)
1570 {
1571         u32     syndrome;
1572         u8      status;
1573
1574         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1575         if (!status)
1576                 return 0;
1577
1578         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1579
1580         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1581                 cmd_status_str(status), status, syndrome);
1582
1583         return cmd_status_to_err(status);
1584 }