drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151
 152         for (i = 0; i < len; i++)
 153                 sum ^= ptr[i];
 154
 155         return sum;
 156 }
 157
 158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 159 {
 160         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 161                 return -EINVAL;
 162
 163         if (xor8_buf(block, sizeof(*block)) != 0xff)
 164                 return -EINVAL;
 165
 166         return 0;
 167 }
 168
 169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 170                            int csum)
 171 {
 172         block->token = token;
 173         if (csum) {
 174                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 175                                             sizeof(block->data) - 2);
 176                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 177         }
 178 }
 179
 180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 181 {
 182         struct mlx5_cmd_mailbox *next = msg->next;
 183
 184         while (next) {
 185                 calc_block_sig(next->buf, token, csum);
 186                 next = next->next;
 187         }
 188 }
 189
 190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 191 {
 192         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 193         calc_chain_sig(ent->in, ent->token, csum);
 194         calc_chain_sig(ent->out, ent->token, csum);
 195 }
 196
 197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 198 {
 199         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 200         u8 own;
 201
 202         do {
 203                 own = ent->lay->status_own;
 204                 if (!(own & CMD_OWNER_HW)) {
 205                         ent->ret = 0;
 206                         return;
 207                 }
 208                 usleep_range(5000, 10000);
 209         } while (time_before(jiffies, poll_end));
 210
 211         ent->ret = -ETIMEDOUT;
 212 }
 213
 214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 215 {
 216         kfree(ent);
 217 }
 218
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225
 226         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 227         if (sig != 0xff)
 228                 return -EINVAL;
 229
 230         while (next) {
 231                 err = verify_block_sig(next->buf);
 232                 if (err)
 233                         return err;
 234
 235                 next = next->next;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void dump_buf(void *buf, int size, int data_only, int offset)
 242 {
 243         __be32 *p = buf;
 244         int i;
 245
 246         for (i = 0; i < size; i += 16) {
 247                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 248                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 249                          be32_to_cpu(p[3]));
 250                 p += 4;
 251                 offset += 16;
 252         }
 253         if (!data_only)
 254                 pr_debug("\n");
 255 }
 256
 257 enum {
 258         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 259         MLX5_DRIVER_SYND = 0xbadd00de,
 260 };
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DEALLOC_PD:
 282         case MLX5_CMD_OP_DEALLOC_UAR:
 283         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 284         case MLX5_CMD_OP_DEALLOC_XRCD:
 285         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 286         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 287         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 288         case MLX5_CMD_OP_DESTROY_TIR:
 289         case MLX5_CMD_OP_DESTROY_SQ:
 290         case MLX5_CMD_OP_DESTROY_RQ:
 291         case MLX5_CMD_OP_DESTROY_RMP:
 292         case MLX5_CMD_OP_DESTROY_TIS:
 293         case MLX5_CMD_OP_DESTROY_RQT:
 294         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 295         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 296         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 297         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 298                 return MLX5_CMD_STAT_OK;
 299
 300         case MLX5_CMD_OP_QUERY_HCA_CAP:
 301         case MLX5_CMD_OP_QUERY_ADAPTER:
 302         case MLX5_CMD_OP_INIT_HCA:
 303         case MLX5_CMD_OP_ENABLE_HCA:
 304         case MLX5_CMD_OP_QUERY_PAGES:
 305         case MLX5_CMD_OP_SET_HCA_CAP:
 306         case MLX5_CMD_OP_QUERY_ISSI:
 307         case MLX5_CMD_OP_SET_ISSI:
 308         case MLX5_CMD_OP_CREATE_MKEY:
 309         case MLX5_CMD_OP_QUERY_MKEY:
 310         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 311         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 312         case MLX5_CMD_OP_CREATE_EQ:
 313         case MLX5_CMD_OP_QUERY_EQ:
 314         case MLX5_CMD_OP_GEN_EQE:
 315         case MLX5_CMD_OP_CREATE_CQ:
 316         case MLX5_CMD_OP_QUERY_CQ:
 317         case MLX5_CMD_OP_MODIFY_CQ:
 318         case MLX5_CMD_OP_CREATE_QP:
 319         case MLX5_CMD_OP_RST2INIT_QP:
 320         case MLX5_CMD_OP_INIT2RTR_QP:
 321         case MLX5_CMD_OP_RTR2RTS_QP:
 322         case MLX5_CMD_OP_RTS2RTS_QP:
 323         case MLX5_CMD_OP_SQERR2RTS_QP:
 324         case MLX5_CMD_OP_2ERR_QP:
 325         case MLX5_CMD_OP_2RST_QP:
 326         case MLX5_CMD_OP_QUERY_QP:
 327         case MLX5_CMD_OP_SQD_RTS_QP:
 328         case MLX5_CMD_OP_INIT2INIT_QP:
 329         case MLX5_CMD_OP_CREATE_PSV:
 330         case MLX5_CMD_OP_CREATE_SRQ:
 331         case MLX5_CMD_OP_QUERY_SRQ:
 332         case MLX5_CMD_OP_ARM_RQ:
 333         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 334         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 335         case MLX5_CMD_OP_ARM_XRC_SRQ:
 336         case MLX5_CMD_OP_CREATE_DCT:
 337         case MLX5_CMD_OP_DRAIN_DCT:
 338         case MLX5_CMD_OP_QUERY_DCT:
 339         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 340         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 341         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 342         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 343         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 344         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 345         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 346         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 347         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 348         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 349         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 350         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 351         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 352         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 353         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 354         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 355         case MLX5_CMD_OP_ALLOC_PD:
 356         case MLX5_CMD_OP_ALLOC_UAR:
 357         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 358         case MLX5_CMD_OP_ACCESS_REG:
 359         case MLX5_CMD_OP_ATTACH_TO_MCG:
 360         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 361         case MLX5_CMD_OP_MAD_IFC:
 362         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 363         case MLX5_CMD_OP_SET_MAD_DEMUX:
 364         case MLX5_CMD_OP_NOP:
 365         case MLX5_CMD_OP_ALLOC_XRCD:
 366         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 367         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 368         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 369         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 370         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 371         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 372         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 373         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 374         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 375         case MLX5_CMD_OP_CREATE_TIR:
 376         case MLX5_CMD_OP_MODIFY_TIR:
 377         case MLX5_CMD_OP_QUERY_TIR:
 378         case MLX5_CMD_OP_CREATE_SQ:
 379         case MLX5_CMD_OP_MODIFY_SQ:
 380         case MLX5_CMD_OP_QUERY_SQ:
 381         case MLX5_CMD_OP_CREATE_RQ:
 382         case MLX5_CMD_OP_MODIFY_RQ:
 383         case MLX5_CMD_OP_QUERY_RQ:
 384         case MLX5_CMD_OP_CREATE_RMP:
 385         case MLX5_CMD_OP_MODIFY_RMP:
 386         case MLX5_CMD_OP_QUERY_RMP:
 387         case MLX5_CMD_OP_CREATE_TIS:
 388         case MLX5_CMD_OP_MODIFY_TIS:
 389         case MLX5_CMD_OP_QUERY_TIS:
 390         case MLX5_CMD_OP_CREATE_RQT:
 391         case MLX5_CMD_OP_MODIFY_RQT:
 392         case MLX5_CMD_OP_QUERY_RQT:
 393         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 394         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 395         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 396         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 397         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 398         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 399         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 400         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 401                 *status = MLX5_DRIVER_STATUS_ABORTED;
 402                 *synd = MLX5_DRIVER_SYND;
 403                 return -EIO;
 404         default:
 405                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 406                 return -EINVAL;
 407         }
 408 }
 409
 410 const char *mlx5_command_str(int command)
 411 {
 412 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 413
 414         switch (command) {
 415         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 416         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 417         MLX5_COMMAND_STR_CASE(INIT_HCA);
 418         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 419         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 420         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 421         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 422         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 423         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 424         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 425         MLX5_COMMAND_STR_CASE(SET_ISSI);
 426         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 427         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 428         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 429         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 430         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 431         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 432         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 433         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 434         MLX5_COMMAND_STR_CASE(GEN_EQE);
 435         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 436         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 437         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 438         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 439         MLX5_COMMAND_STR_CASE(CREATE_QP);
 440         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 441         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 442         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 443         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 444         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 445         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 446         MLX5_COMMAND_STR_CASE(2ERR_QP);
 447         MLX5_COMMAND_STR_CASE(2RST_QP);
 448         MLX5_COMMAND_STR_CASE(QUERY_QP);
 449         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 450         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 451         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 452         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 453         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 454         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 455         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 456         MLX5_COMMAND_STR_CASE(ARM_RQ);
 457         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 460         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 461         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 462         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 463         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 464         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 465         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 466         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 467         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 468         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 469         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 470         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 471         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 472         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 473         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 474         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 475         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 476         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 477         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 478         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 479         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 480         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 481         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 482         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 483         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 484         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 485         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 486         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 487         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 488         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 489         MLX5_COMMAND_STR_CASE(DETTACH_FROM_MCG);
 490         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 491         MLX5_COMMAND_STR_CASE(MAD_IFC);
 492         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 493         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 494         MLX5_COMMAND_STR_CASE(NOP);
 495         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 496         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 497         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 498         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 499         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 500         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 501         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 502         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 503         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 504         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 505         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 506         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 507         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 508         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 509         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 510         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 511         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 512         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 513         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 514         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 515         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 516         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 517         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 518         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 519         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 520         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 521         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 522         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 523         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 524         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 525         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 526         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 527         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 528         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 529         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 530         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 531         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 532         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 533         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 534         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 535         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 536         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 537         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 538         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 539         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 540         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 541         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 542         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 544         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 545         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 546         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 547         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 548         default: return "unknown command opcode";
 549         }
 550 }
 551
 552 static void dump_command(struct mlx5_core_dev *dev,
 553                          struct mlx5_cmd_work_ent *ent, int input)
 554 {
 555         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 556         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 557         struct mlx5_cmd_mailbox *next = msg->next;
 558         int data_only;
 559         u32 offset = 0;
 560         int dump_len;
 561
 562         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 563
 564         if (data_only)
 565                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 566                                    "dump command data %s(0x%x) %s\n",
 567                                    mlx5_command_str(op), op,
 568                                    input ? "INPUT" : "OUTPUT");
 569         else
 570                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 571                               mlx5_command_str(op), op,
 572                               input ? "INPUT" : "OUTPUT");
 573
 574         if (data_only) {
 575                 if (input) {
 576                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 577                         offset += sizeof(ent->lay->in);
 578                 } else {
 579                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 580                         offset += sizeof(ent->lay->out);
 581                 }
 582         } else {
 583                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 584                 offset += sizeof(*ent->lay);
 585         }
 586
 587         while (next && offset < msg->len) {
 588                 if (data_only) {
 589                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 590                         dump_buf(next->buf, dump_len, 1, offset);
 591                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 592                 } else {
 593                         mlx5_core_dbg(dev, "command block:\n");
 594                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 595                         offset += sizeof(struct mlx5_cmd_prot_block);
 596                 }
 597                 next = next->next;
 598         }
 599
 600         if (data_only)
 601                 pr_debug("\n");
 602 }
 603
 604 static void cmd_work_handler(struct work_struct *work)
 605 {
 606         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 607         struct mlx5_cmd *cmd = ent->cmd;
 608         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 609         struct mlx5_cmd_layout *lay;
 610         struct semaphore *sem;
 611         unsigned long flags;
 612
 613         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 614         down(sem);
 615         if (!ent->page_queue) {
 616                 ent->idx = alloc_ent(cmd);
 617                 if (ent->idx < 0) {
 618                         mlx5_core_err(dev, "failed to allocate command entry\n");
 619                         up(sem);
 620                         return;
 621                 }
 622         } else {
 623                 ent->idx = cmd->max_reg_cmds;
 624                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 625                 clear_bit(ent->idx, &cmd->bitmask);
 626                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 627         }
 628
 629         ent->token = alloc_token(cmd);
 630         cmd->ent_arr[ent->idx] = ent;
 631         lay = get_inst(cmd, ent->idx);
 632         ent->lay = lay;
 633         memset(lay, 0, sizeof(*lay));
 634         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 635         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 636         if (ent->in->next)
 637                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 638         lay->inlen = cpu_to_be32(ent->in->len);
 639         if (ent->out->next)
 640                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 641         lay->outlen = cpu_to_be32(ent->out->len);
 642         lay->type = MLX5_PCI_CMD_XPORT;
 643         lay->token = ent->token;
 644         lay->status_own = CMD_OWNER_HW;
 645         set_signature(ent, !cmd->checksum_disabled);
 646         dump_command(dev, ent, 1);
 647         ent->ts1 = ktime_get_ns();
 648
 649         /* ring doorbell after the descriptor is valid */
 650         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 651         wmb();
 652         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 653         mmiowb();
 654         /* if not in polling don't use ent after this point */
 655         if (cmd->mode == CMD_MODE_POLLING) {
 656                 poll_timeout(ent);
 657                 /* make sure we read the descriptor after ownership is SW */
 658                 rmb();
 659                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 660         }
 661 }
 662
 663 static const char *deliv_status_to_str(u8 status)
 664 {
 665         switch (status) {
 666         case MLX5_CMD_DELIVERY_STAT_OK:
 667                 return "no errors";
 668         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 669                 return "signature error";
 670         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 671                 return "token error";
 672         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 673                 return "bad block number";
 674         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 675                 return "output pointer not aligned to block size";
 676         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 677                 return "input pointer not aligned to block size";
 678         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 679                 return "firmware internal error";
 680         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 681                 return "command input length error";
 682         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 683                 return "command ouput length error";
 684         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 685                 return "reserved fields not cleared";
 686         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 687                 return "bad command descriptor type";
 688         default:
 689                 return "unknown status code";
 690         }
 691 }
 692
 693 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 694 {
 695         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 696
 697         return be16_to_cpu(hdr->opcode);
 698 }
 699
 700 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 701 {
 702         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 703         struct mlx5_cmd *cmd = &dev->cmd;
 704         int err;
 705
 706         if (cmd->mode == CMD_MODE_POLLING) {
 707                 wait_for_completion(&ent->done);
 708                 err = ent->ret;
 709         } else {
 710                 if (!wait_for_completion_timeout(&ent->done, timeout))
 711                         err = -ETIMEDOUT;
 712                 else
 713                         err = 0;
 714         }
 715         if (err == -ETIMEDOUT) {
 716                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 717                                mlx5_command_str(msg_to_opcode(ent->in)),
 718                                msg_to_opcode(ent->in));
 719         }
 720         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 721                       err, deliv_status_to_str(ent->status), ent->status);
 722
 723         return err;
 724 }
 725
 726 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 727 {
 728         return &out->syndrome;
 729 }
 730
 731 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 732 {
 733         return &out->status;
 734 }
 735
 736 /*  Notes:
 737  *    1. Callback functions may not sleep
 738  *    2. page queue commands do not support asynchrous completion
 739  */
 740 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 741                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 742                            mlx5_cmd_cbk_t callback,
 743                            void *context, int page_queue, u8 *status)
 744 {
 745         struct mlx5_cmd *cmd = &dev->cmd;
 746         struct mlx5_cmd_work_ent *ent;
 747         struct mlx5_cmd_stats *stats;
 748         int err = 0;
 749         s64 ds;
 750         u16 op;
 751
 752         if (callback && page_queue)
 753                 return -EINVAL;
 754
 755         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 756                         page_queue);
 757         if (IS_ERR(ent))
 758                 return PTR_ERR(ent);
 759
 760         if (!callback)
 761                 init_completion(&ent->done);
 762
 763         INIT_WORK(&ent->work, cmd_work_handler);
 764         if (page_queue) {
 765                 cmd_work_handler(&ent->work);
 766         } else if (!queue_work(cmd->wq, &ent->work)) {
 767                 mlx5_core_warn(dev, "failed to queue work\n");
 768                 err = -ENOMEM;
 769                 goto out_free;
 770         }
 771
 772         if (!callback) {
 773                 err = wait_func(dev, ent);
 774                 if (err == -ETIMEDOUT)
 775                         goto out;
 776
 777                 ds = ent->ts2 - ent->ts1;
 778                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 779                 if (op < ARRAY_SIZE(cmd->stats)) {
 780                         stats = &cmd->stats[op];
 781                         spin_lock_irq(&stats->lock);
 782                         stats->sum += ds;
 783                         ++stats->n;
 784                         spin_unlock_irq(&stats->lock);
 785                 }
 786                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 787                                    "fw exec time for %s is %lld nsec\n",
 788                                    mlx5_command_str(op), ds);
 789                 *status = ent->status;
 790                 free_cmd(ent);
 791         }
 792
 793         return err;
 794
 795 out_free:
 796         free_cmd(ent);
 797 out:
 798         return err;
 799 }
 800
 801 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 802                          size_t count, loff_t *pos)
 803 {
 804         struct mlx5_core_dev *dev = filp->private_data;
 805         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 806         char lbuf[3];
 807         int err;
 808
 809         if (!dbg->in_msg || !dbg->out_msg)
 810                 return -ENOMEM;
 811
 812         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 813                 return -EFAULT;
 814
 815         lbuf[sizeof(lbuf) - 1] = 0;
 816
 817         if (strcmp(lbuf, "go"))
 818                 return -EINVAL;
 819
 820         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 821
 822         return err ? err : count;
 823 }
 824
 825
 826 static const struct file_operations fops = {
 827         .owner  = THIS_MODULE,
 828         .open   = simple_open,
 829         .write  = dbg_write,
 830 };
 831
 832 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 833 {
 834         struct mlx5_cmd_prot_block *block;
 835         struct mlx5_cmd_mailbox *next;
 836         int copy;
 837
 838         if (!to || !from)
 839                 return -ENOMEM;
 840
 841         copy = min_t(int, size, sizeof(to->first.data));
 842         memcpy(to->first.data, from, copy);
 843         size -= copy;
 844         from += copy;
 845
 846         next = to->next;
 847         while (size) {
 848                 if (!next) {
 849                         /* this is a BUG */
 850                         return -ENOMEM;
 851                 }
 852
 853                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 854                 block = next->buf;
 855                 memcpy(block->data, from, copy);
 856                 from += copy;
 857                 size -= copy;
 858                 next = next->next;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 865 {
 866         struct mlx5_cmd_prot_block *block;
 867         struct mlx5_cmd_mailbox *next;
 868         int copy;
 869
 870         if (!to || !from)
 871                 return -ENOMEM;
 872
 873         copy = min_t(int, size, sizeof(from->first.data));
 874         memcpy(to, from->first.data, copy);
 875         size -= copy;
 876         to += copy;
 877
 878         next = from->next;
 879         while (size) {
 880                 if (!next) {
 881                         /* this is a BUG */
 882                         return -ENOMEM;
 883                 }
 884
 885                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 886                 block = next->buf;
 887
 888                 memcpy(to, block->data, copy);
 889                 to += copy;
 890                 size -= copy;
 891                 next = next->next;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 898                                               gfp_t flags)
 899 {
 900         struct mlx5_cmd_mailbox *mailbox;
 901
 902         mailbox = kmalloc(sizeof(*mailbox), flags);
 903         if (!mailbox)
 904                 return ERR_PTR(-ENOMEM);
 905
 906         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 907                                       &mailbox->dma);
 908         if (!mailbox->buf) {
 909                 mlx5_core_dbg(dev, "failed allocation\n");
 910                 kfree(mailbox);
 911                 return ERR_PTR(-ENOMEM);
 912         }
 913         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 914         mailbox->next = NULL;
 915
 916         return mailbox;
 917 }
 918
 919 static void free_cmd_box(struct mlx5_core_dev *dev,
 920                          struct mlx5_cmd_mailbox *mailbox)
 921 {
 922         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 923         kfree(mailbox);
 924 }
 925
 926 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 927                                                gfp_t flags, int size)
 928 {
 929         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 930         struct mlx5_cmd_prot_block *block;
 931         struct mlx5_cmd_msg *msg;
 932         int blen;
 933         int err;
 934         int n;
 935         int i;
 936
 937         msg = kzalloc(sizeof(*msg), flags);
 938         if (!msg)
 939                 return ERR_PTR(-ENOMEM);
 940
 941         blen = size - min_t(int, sizeof(msg->first.data), size);
 942         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 943
 944         for (i = 0; i < n; i++) {
 945                 tmp = alloc_cmd_box(dev, flags);
 946                 if (IS_ERR(tmp)) {
 947                         mlx5_core_warn(dev, "failed allocating block\n");
 948                         err = PTR_ERR(tmp);
 949                         goto err_alloc;
 950                 }
 951
 952                 block = tmp->buf;
 953                 tmp->next = head;
 954                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 955                 block->block_num = cpu_to_be32(n - i - 1);
 956                 head = tmp;
 957         }
 958         msg->next = head;
 959         msg->len = size;
 960         return msg;
 961
 962 err_alloc:
 963         while (head) {
 964                 tmp = head->next;
 965                 free_cmd_box(dev, head);
 966                 head = tmp;
 967         }
 968         kfree(msg);
 969
 970         return ERR_PTR(err);
 971 }
 972
 973 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 974                                   struct mlx5_cmd_msg *msg)
 975 {
 976         struct mlx5_cmd_mailbox *head = msg->next;
 977         struct mlx5_cmd_mailbox *next;
 978
 979         while (head) {
 980                 next = head->next;
 981                 free_cmd_box(dev, head);
 982                 head = next;
 983         }
 984         kfree(msg);
 985 }
 986
 987 static ssize_t data_write(struct file *filp, const char __user *buf,
 988                           size_t count, loff_t *pos)
 989 {
 990         struct mlx5_core_dev *dev = filp->private_data;
 991         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 992         void *ptr;
 993         int err;
 994
 995         if (*pos != 0)
 996                 return -EINVAL;
 997
 998         kfree(dbg->in_msg);
 999         dbg->in_msg = NULL;
1000         dbg->inlen = 0;
1001
1002         ptr = kzalloc(count, GFP_KERNEL);
1003         if (!ptr)
1004                 return -ENOMEM;
1005
1006         if (copy_from_user(ptr, buf, count)) {
1007                 err = -EFAULT;
1008                 goto out;
1009         }
1010         dbg->in_msg = ptr;
1011         dbg->inlen = count;
1012
1013         *pos = count;
1014
1015         return count;
1016
1017 out:
1018         kfree(ptr);
1019         return err;
1020 }
1021
1022 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1023                          loff_t *pos)
1024 {
1025         struct mlx5_core_dev *dev = filp->private_data;
1026         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1027         int copy;
1028
1029         if (*pos)
1030                 return 0;
1031
1032         if (!dbg->out_msg)
1033                 return -ENOMEM;
1034
1035         copy = min_t(int, count, dbg->outlen);
1036         if (copy_to_user(buf, dbg->out_msg, copy))
1037                 return -EFAULT;
1038
1039         *pos += copy;
1040
1041         return copy;
1042 }
1043
1044 static const struct file_operations dfops = {
1045         .owner  = THIS_MODULE,
1046         .open   = simple_open,
1047         .write  = data_write,
1048         .read   = data_read,
1049 };
1050
1051 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1052                            loff_t *pos)
1053 {
1054         struct mlx5_core_dev *dev = filp->private_data;
1055         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1056         char outlen[8];
1057         int err;
1058
1059         if (*pos)
1060                 return 0;
1061
1062         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1063         if (err < 0)
1064                 return err;
1065
1066         if (copy_to_user(buf, &outlen, err))
1067                 return -EFAULT;
1068
1069         *pos += err;
1070
1071         return err;
1072 }
1073
1074 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1075                             size_t count, loff_t *pos)
1076 {
1077         struct mlx5_core_dev *dev = filp->private_data;
1078         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1079         char outlen_str[8];
1080         int outlen;
1081         void *ptr;
1082         int err;
1083
1084         if (*pos != 0 || count > 6)
1085                 return -EINVAL;
1086
1087         kfree(dbg->out_msg);
1088         dbg->out_msg = NULL;
1089         dbg->outlen = 0;
1090
1091         if (copy_from_user(outlen_str, buf, count))
1092                 return -EFAULT;
1093
1094         outlen_str[7] = 0;
1095
1096         err = sscanf(outlen_str, "%d", &outlen);
1097         if (err < 0)
1098                 return err;
1099
1100         ptr = kzalloc(outlen, GFP_KERNEL);
1101         if (!ptr)
1102                 return -ENOMEM;
1103
1104         dbg->out_msg = ptr;
1105         dbg->outlen = outlen;
1106
1107         *pos = count;
1108
1109         return count;
1110 }
1111
1112 static const struct file_operations olfops = {
1113         .owner  = THIS_MODULE,
1114         .open   = simple_open,
1115         .write  = outlen_write,
1116         .read   = outlen_read,
1117 };
1118
1119 static void set_wqname(struct mlx5_core_dev *dev)
1120 {
1121         struct mlx5_cmd *cmd = &dev->cmd;
1122
1123         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1124                  dev_name(&dev->pdev->dev));
1125 }
1126
1127 static void clean_debug_files(struct mlx5_core_dev *dev)
1128 {
1129         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1130
1131         if (!mlx5_debugfs_root)
1132                 return;
1133
1134         mlx5_cmdif_debugfs_cleanup(dev);
1135         debugfs_remove_recursive(dbg->dbg_root);
1136 }
1137
1138 static int create_debugfs_files(struct mlx5_core_dev *dev)
1139 {
1140         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1141         int err = -ENOMEM;
1142
1143         if (!mlx5_debugfs_root)
1144                 return 0;
1145
1146         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1147         if (!dbg->dbg_root)
1148                 return err;
1149
1150         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1151                                           dev, &dfops);
1152         if (!dbg->dbg_in)
1153                 goto err_dbg;
1154
1155         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1156                                            dev, &dfops);
1157         if (!dbg->dbg_out)
1158                 goto err_dbg;
1159
1160         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1161                                               dev, &olfops);
1162         if (!dbg->dbg_outlen)
1163                 goto err_dbg;
1164
1165         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1166                                             &dbg->status);
1167         if (!dbg->dbg_status)
1168                 goto err_dbg;
1169
1170         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1171         if (!dbg->dbg_run)
1172                 goto err_dbg;
1173
1174         mlx5_cmdif_debugfs_init(dev);
1175
1176         return 0;
1177
1178 err_dbg:
1179         clean_debug_files(dev);
1180         return err;
1181 }
1182
1183 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1184 {
1185         struct mlx5_cmd *cmd = &dev->cmd;
1186         int i;
1187
1188         for (i = 0; i < cmd->max_reg_cmds; i++)
1189                 down(&cmd->sem);
1190
1191         down(&cmd->pages_sem);
1192
1193         flush_workqueue(cmd->wq);
1194
1195         cmd->mode = CMD_MODE_EVENTS;
1196
1197         up(&cmd->pages_sem);
1198         for (i = 0; i < cmd->max_reg_cmds; i++)
1199                 up(&cmd->sem);
1200 }
1201
1202 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1203 {
1204         struct mlx5_cmd *cmd = &dev->cmd;
1205         int i;
1206
1207         for (i = 0; i < cmd->max_reg_cmds; i++)
1208                 down(&cmd->sem);
1209
1210         down(&cmd->pages_sem);
1211
1212         flush_workqueue(cmd->wq);
1213         cmd->mode = CMD_MODE_POLLING;
1214
1215         up(&cmd->pages_sem);
1216         for (i = 0; i < cmd->max_reg_cmds; i++)
1217                 up(&cmd->sem);
1218 }
1219
1220 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1221 {
1222         unsigned long flags;
1223
1224         if (msg->cache) {
1225                 spin_lock_irqsave(&msg->cache->lock, flags);
1226                 list_add_tail(&msg->list, &msg->cache->head);
1227                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1228         } else {
1229                 mlx5_free_cmd_msg(dev, msg);
1230         }
1231 }
1232
1233 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1234 {
1235         struct mlx5_cmd *cmd = &dev->cmd;
1236         struct mlx5_cmd_work_ent *ent;
1237         mlx5_cmd_cbk_t callback;
1238         void *context;
1239         int err;
1240         int i;
1241         s64 ds;
1242         struct mlx5_cmd_stats *stats;
1243         unsigned long flags;
1244         unsigned long vector;
1245
1246         /* there can be at most 32 command queues */
1247         vector = vec & 0xffffffff;
1248         for (i = 0; i < (1 << cmd->log_sz); i++) {
1249                 if (test_bit(i, &vector)) {
1250                         struct semaphore *sem;
1251
1252                         ent = cmd->ent_arr[i];
1253                         if (ent->page_queue)
1254                                 sem = &cmd->pages_sem;
1255                         else
1256                                 sem = &cmd->sem;
1257                         ent->ts2 = ktime_get_ns();
1258                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1259                         dump_command(dev, ent, 0);
1260                         if (!ent->ret) {
1261                                 if (!cmd->checksum_disabled)
1262                                         ent->ret = verify_signature(ent);
1263                                 else
1264                                         ent->ret = 0;
1265                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1266                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1267                                 else
1268                                         ent->status = ent->lay->status_own >> 1;
1269
1270                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1271                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1272                         }
1273                         free_ent(cmd, ent->idx);
1274
1275                         if (ent->callback) {
1276                                 ds = ent->ts2 - ent->ts1;
1277                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1278                                         stats = &cmd->stats[ent->op];
1279                                         spin_lock_irqsave(&stats->lock, flags);
1280                                         stats->sum += ds;
1281                                         ++stats->n;
1282                                         spin_unlock_irqrestore(&stats->lock, flags);
1283                                 }
1284
1285                                 callback = ent->callback;
1286                                 context = ent->context;
1287                                 err = ent->ret;
1288                                 if (!err)
1289                                         err = mlx5_copy_from_msg(ent->uout,
1290                                                                  ent->out,
1291                                                                  ent->uout_size);
1292
1293                                 mlx5_free_cmd_msg(dev, ent->out);
1294                                 free_msg(dev, ent->in);
1295
1296                                 err = err ? err : ent->status;
1297                                 free_cmd(ent);
1298                                 callback(err, context);
1299                         } else {
1300                                 complete(&ent->done);
1301                         }
1302                         up(sem);
1303                 }
1304         }
1305 }
1306 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1307
1308 static int status_to_err(u8 status)
1309 {
1310         return status ? -1 : 0; /* TBD more meaningful codes */
1311 }
1312
1313 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1314                                       gfp_t gfp)
1315 {
1316         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1317         struct mlx5_cmd *cmd = &dev->cmd;
1318         struct cache_ent *ent = NULL;
1319
1320         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1321                 ent = &cmd->cache.large;
1322         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1323                 ent = &cmd->cache.med;
1324
1325         if (ent) {
1326                 spin_lock_irq(&ent->lock);
1327                 if (!list_empty(&ent->head)) {
1328                         msg = list_entry(ent->head.next, typeof(*msg), list);
1329                         /* For cached lists, we must explicitly state what is
1330                          * the real size
1331                          */
1332                         msg->len = in_size;
1333                         list_del(&msg->list);
1334                 }
1335                 spin_unlock_irq(&ent->lock);
1336         }
1337
1338         if (IS_ERR(msg))
1339                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1340
1341         return msg;
1342 }
1343
1344 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1345 {
1346         return be16_to_cpu(in->opcode);
1347 }
1348
1349 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1350 {
1351         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1352 }
1353
1354 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1355                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1356 {
1357         struct mlx5_cmd_msg *inb;
1358         struct mlx5_cmd_msg *outb;
1359         int pages_queue;
1360         gfp_t gfp;
1361         int err;
1362         u8 status = 0;
1363         u32 drv_synd;
1364
1365         if (pci_channel_offline(dev->pdev) ||
1366             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1367                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1368                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1369                 *get_status_ptr(out) = status;
1370                 return err;
1371         }
1372
1373         pages_queue = is_manage_pages(in);
1374         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1375
1376         inb = alloc_msg(dev, in_size, gfp);
1377         if (IS_ERR(inb)) {
1378                 err = PTR_ERR(inb);
1379                 return err;
1380         }
1381
1382         err = mlx5_copy_to_msg(inb, in, in_size);
1383         if (err) {
1384                 mlx5_core_warn(dev, "err %d\n", err);
1385                 goto out_in;
1386         }
1387
1388         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1389         if (IS_ERR(outb)) {
1390                 err = PTR_ERR(outb);
1391                 goto out_in;
1392         }
1393
1394         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1395                               pages_queue, &status);
1396         if (err)
1397                 goto out_out;
1398
1399         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1400         if (status) {
1401                 err = status_to_err(status);
1402                 goto out_out;
1403         }
1404
1405         if (!callback)
1406                 err = mlx5_copy_from_msg(out, outb, out_size);
1407
1408 out_out:
1409         if (!callback)
1410                 mlx5_free_cmd_msg(dev, outb);
1411
1412 out_in:
1413         if (!callback)
1414                 free_msg(dev, inb);
1415         return err;
1416 }
1417
1418 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1419                   int out_size)
1420 {
1421         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1422 }
1423 EXPORT_SYMBOL(mlx5_cmd_exec);
1424
1425 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1426                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1427                      void *context)
1428 {
1429         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1430 }
1431 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1432
1433 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1434 {
1435         struct mlx5_cmd *cmd = &dev->cmd;
1436         struct mlx5_cmd_msg *msg;
1437         struct mlx5_cmd_msg *n;
1438
1439         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1440                 list_del(&msg->list);
1441                 mlx5_free_cmd_msg(dev, msg);
1442         }
1443
1444         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1445                 list_del(&msg->list);
1446                 mlx5_free_cmd_msg(dev, msg);
1447         }
1448 }
1449
1450 static int create_msg_cache(struct mlx5_core_dev *dev)
1451 {
1452         struct mlx5_cmd *cmd = &dev->cmd;
1453         struct mlx5_cmd_msg *msg;
1454         int err;
1455         int i;
1456
1457         spin_lock_init(&cmd->cache.large.lock);
1458         INIT_LIST_HEAD(&cmd->cache.large.head);
1459         spin_lock_init(&cmd->cache.med.lock);
1460         INIT_LIST_HEAD(&cmd->cache.med.head);
1461
1462         for (i = 0; i < NUM_LONG_LISTS; i++) {
1463                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1464                 if (IS_ERR(msg)) {
1465                         err = PTR_ERR(msg);
1466                         goto ex_err;
1467                 }
1468                 msg->cache = &cmd->cache.large;
1469                 list_add_tail(&msg->list, &cmd->cache.large.head);
1470         }
1471
1472         for (i = 0; i < NUM_MED_LISTS; i++) {
1473                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1474                 if (IS_ERR(msg)) {
1475                         err = PTR_ERR(msg);
1476                         goto ex_err;
1477                 }
1478                 msg->cache = &cmd->cache.med;
1479                 list_add_tail(&msg->list, &cmd->cache.med.head);
1480         }
1481
1482         return 0;
1483
1484 ex_err:
1485         destroy_msg_cache(dev);
1486         return err;
1487 }
1488
1489 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1490 {
1491         struct device *ddev = &dev->pdev->dev;
1492
1493         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1494                                                  &cmd->alloc_dma, GFP_KERNEL);
1495         if (!cmd->cmd_alloc_buf)
1496                 return -ENOMEM;
1497
1498         /* make sure it is aligned to 4K */
1499         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1500                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1501                 cmd->dma = cmd->alloc_dma;
1502                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1503                 return 0;
1504         }
1505
1506         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1507                           cmd->alloc_dma);
1508         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1509                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1510                                                  &cmd->alloc_dma, GFP_KERNEL);
1511         if (!cmd->cmd_alloc_buf)
1512                 return -ENOMEM;
1513
1514         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1515         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1516         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1517         return 0;
1518 }
1519
1520 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1521 {
1522         struct device *ddev = &dev->pdev->dev;
1523
1524         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1525                           cmd->alloc_dma);
1526 }
1527
1528 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1529 {
1530         int size = sizeof(struct mlx5_cmd_prot_block);
1531         int align = roundup_pow_of_two(size);
1532         struct mlx5_cmd *cmd = &dev->cmd;
1533         u32 cmd_h, cmd_l;
1534         u16 cmd_if_rev;
1535         int err;
1536         int i;
1537
1538         memset(cmd, 0, sizeof(*cmd));
1539         cmd_if_rev = cmdif_rev(dev);
1540         if (cmd_if_rev != CMD_IF_REV) {
1541                 dev_err(&dev->pdev->dev,
1542                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1543                         CMD_IF_REV, cmd_if_rev);
1544                 return -EINVAL;
1545         }
1546
1547         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1548         if (!cmd->pool)
1549                 return -ENOMEM;
1550
1551         err = alloc_cmd_page(dev, cmd);
1552         if (err)
1553                 goto err_free_pool;
1554
1555         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1556         cmd->log_sz = cmd_l >> 4 & 0xf;
1557         cmd->log_stride = cmd_l & 0xf;
1558         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1559                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1560                         1 << cmd->log_sz);
1561                 err = -EINVAL;
1562                 goto err_free_page;
1563         }
1564
1565         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1566                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1567                 err = -EINVAL;
1568                 goto err_free_page;
1569         }
1570
1571         cmd->checksum_disabled = 1;
1572         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1573         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1574
1575         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1576         if (cmd->cmdif_rev > CMD_IF_REV) {
1577                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1578                         CMD_IF_REV, cmd->cmdif_rev);
1579                 err = -ENOTSUPP;
1580                 goto err_free_page;
1581         }
1582
1583         spin_lock_init(&cmd->alloc_lock);
1584         spin_lock_init(&cmd->token_lock);
1585         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1586                 spin_lock_init(&cmd->stats[i].lock);
1587
1588         sema_init(&cmd->sem, cmd->max_reg_cmds);
1589         sema_init(&cmd->pages_sem, 1);
1590
1591         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1592         cmd_l = (u32)(cmd->dma);
1593         if (cmd_l & 0xfff) {
1594                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1595                 err = -ENOMEM;
1596                 goto err_free_page;
1597         }
1598
1599         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1600         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1601
1602         /* Make sure firmware sees the complete address before we proceed */
1603         wmb();
1604
1605         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1606
1607         cmd->mode = CMD_MODE_POLLING;
1608
1609         err = create_msg_cache(dev);
1610         if (err) {
1611                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1612                 goto err_free_page;
1613         }
1614
1615         set_wqname(dev);
1616         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1617         if (!cmd->wq) {
1618                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1619                 err = -ENOMEM;
1620                 goto err_cache;
1621         }
1622
1623         err = create_debugfs_files(dev);
1624         if (err) {
1625                 err = -ENOMEM;
1626                 goto err_wq;
1627         }
1628
1629         return 0;
1630
1631 err_wq:
1632         destroy_workqueue(cmd->wq);
1633
1634 err_cache:
1635         destroy_msg_cache(dev);
1636
1637 err_free_page:
1638         free_cmd_page(dev, cmd);
1639
1640 err_free_pool:
1641         pci_pool_destroy(cmd->pool);
1642
1643         return err;
1644 }
1645 EXPORT_SYMBOL(mlx5_cmd_init);
1646
1647 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1648 {
1649         struct mlx5_cmd *cmd = &dev->cmd;
1650
1651         clean_debug_files(dev);
1652         destroy_workqueue(cmd->wq);
1653         destroy_msg_cache(dev);
1654         free_cmd_page(dev, cmd);
1655         pci_pool_destroy(cmd->pool);
1656 }
1657 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1658
1659 static const char *cmd_status_str(u8 status)
1660 {
1661         switch (status) {
1662         case MLX5_CMD_STAT_OK:
1663                 return "OK";
1664         case MLX5_CMD_STAT_INT_ERR:
1665                 return "internal error";
1666         case MLX5_CMD_STAT_BAD_OP_ERR:
1667                 return "bad operation";
1668         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1669                 return "bad parameter";
1670         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1671                 return "bad system state";
1672         case MLX5_CMD_STAT_BAD_RES_ERR:
1673                 return "bad resource";
1674         case MLX5_CMD_STAT_RES_BUSY:
1675                 return "resource busy";
1676         case MLX5_CMD_STAT_LIM_ERR:
1677                 return "limits exceeded";
1678         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1679                 return "bad resource state";
1680         case MLX5_CMD_STAT_IX_ERR:
1681                 return "bad index";
1682         case MLX5_CMD_STAT_NO_RES_ERR:
1683                 return "no resources";
1684         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1685                 return "bad input length";
1686         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1687                 return "bad output length";
1688         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1689                 return "bad QP state";
1690         case MLX5_CMD_STAT_BAD_PKT_ERR:
1691                 return "bad packet (discarded)";
1692         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1693                 return "bad size too many outstanding CQEs";
1694         default:
1695                 return "unknown status";
1696         }
1697 }
1698
1699 static int cmd_status_to_err(u8 status)
1700 {
1701         switch (status) {
1702         case MLX5_CMD_STAT_OK:                          return 0;
1703         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1704         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1705         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1706         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1707         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1708         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1709         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1710         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1711         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1712         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1713         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1714         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1715         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1716         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1717         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1718         default:                                        return -EIO;
1719         }
1720 }
1721
1722 /* this will be available till all the commands use set/get macros */
1723 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1724 {
1725         if (!hdr->status)
1726                 return 0;
1727
1728         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1729                 cmd_status_str(hdr->status), hdr->status,
1730                 be32_to_cpu(hdr->syndrome));
1731
1732         return cmd_status_to_err(hdr->status);
1733 }
1734
1735 int mlx5_cmd_status_to_err_v2(void *ptr)
1736 {
1737         u32     syndrome;
1738         u8      status;
1739
1740         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1741         if (!status)
1742                 return 0;
1743
1744         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1745
1746         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1747                 cmd_status_str(status), status, syndrome);
1748
1749         return cmd_status_to_err(status);
1750 }