drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151
 152         for (i = 0; i < len; i++)
 153                 sum ^= ptr[i];
 154
 155         return sum;
 156 }
 157
 158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 159 {
 160         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 161                 return -EINVAL;
 162
 163         if (xor8_buf(block, sizeof(*block)) != 0xff)
 164                 return -EINVAL;
 165
 166         return 0;
 167 }
 168
 169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 170                            int csum)
 171 {
 172         block->token = token;
 173         if (csum) {
 174                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 175                                             sizeof(block->data) - 2);
 176                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 177         }
 178 }
 179
 180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 181 {
 182         struct mlx5_cmd_mailbox *next = msg->next;
 183
 184         while (next) {
 185                 calc_block_sig(next->buf, token, csum);
 186                 next = next->next;
 187         }
 188 }
 189
 190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 191 {
 192         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 193         calc_chain_sig(ent->in, ent->token, csum);
 194         calc_chain_sig(ent->out, ent->token, csum);
 195 }
 196
 197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 198 {
 199         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 200         u8 own;
 201
 202         do {
 203                 own = ent->lay->status_own;
 204                 if (!(own & CMD_OWNER_HW)) {
 205                         ent->ret = 0;
 206                         return;
 207                 }
 208                 usleep_range(5000, 10000);
 209         } while (time_before(jiffies, poll_end));
 210
 211         ent->ret = -ETIMEDOUT;
 212 }
 213
 214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 215 {
 216         kfree(ent);
 217 }
 218
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225
 226         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 227         if (sig != 0xff)
 228                 return -EINVAL;
 229
 230         while (next) {
 231                 err = verify_block_sig(next->buf);
 232                 if (err)
 233                         return err;
 234
 235                 next = next->next;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void dump_buf(void *buf, int size, int data_only, int offset)
 242 {
 243         __be32 *p = buf;
 244         int i;
 245
 246         for (i = 0; i < size; i += 16) {
 247                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 248                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 249                          be32_to_cpu(p[3]));
 250                 p += 4;
 251                 offset += 16;
 252         }
 253         if (!data_only)
 254                 pr_debug("\n");
 255 }
 256
 257 enum {
 258         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 259         MLX5_DRIVER_SYND = 0xbadd00de,
 260 };
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DEALLOC_PD:
 282         case MLX5_CMD_OP_DEALLOC_UAR:
 283         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 284         case MLX5_CMD_OP_DEALLOC_XRCD:
 285         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 286         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 287         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 288         case MLX5_CMD_OP_DESTROY_TIR:
 289         case MLX5_CMD_OP_DESTROY_SQ:
 290         case MLX5_CMD_OP_DESTROY_RQ:
 291         case MLX5_CMD_OP_DESTROY_RMP:
 292         case MLX5_CMD_OP_DESTROY_TIS:
 293         case MLX5_CMD_OP_DESTROY_RQT:
 294         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 295         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 296         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 297                 return MLX5_CMD_STAT_OK;
 298
 299         case MLX5_CMD_OP_QUERY_HCA_CAP:
 300         case MLX5_CMD_OP_QUERY_ADAPTER:
 301         case MLX5_CMD_OP_INIT_HCA:
 302         case MLX5_CMD_OP_ENABLE_HCA:
 303         case MLX5_CMD_OP_QUERY_PAGES:
 304         case MLX5_CMD_OP_SET_HCA_CAP:
 305         case MLX5_CMD_OP_QUERY_ISSI:
 306         case MLX5_CMD_OP_SET_ISSI:
 307         case MLX5_CMD_OP_CREATE_MKEY:
 308         case MLX5_CMD_OP_QUERY_MKEY:
 309         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 310         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 311         case MLX5_CMD_OP_CREATE_EQ:
 312         case MLX5_CMD_OP_QUERY_EQ:
 313         case MLX5_CMD_OP_GEN_EQE:
 314         case MLX5_CMD_OP_CREATE_CQ:
 315         case MLX5_CMD_OP_QUERY_CQ:
 316         case MLX5_CMD_OP_MODIFY_CQ:
 317         case MLX5_CMD_OP_CREATE_QP:
 318         case MLX5_CMD_OP_RST2INIT_QP:
 319         case MLX5_CMD_OP_INIT2RTR_QP:
 320         case MLX5_CMD_OP_RTR2RTS_QP:
 321         case MLX5_CMD_OP_RTS2RTS_QP:
 322         case MLX5_CMD_OP_SQERR2RTS_QP:
 323         case MLX5_CMD_OP_2ERR_QP:
 324         case MLX5_CMD_OP_2RST_QP:
 325         case MLX5_CMD_OP_QUERY_QP:
 326         case MLX5_CMD_OP_SQD_RTS_QP:
 327         case MLX5_CMD_OP_INIT2INIT_QP:
 328         case MLX5_CMD_OP_CREATE_PSV:
 329         case MLX5_CMD_OP_CREATE_SRQ:
 330         case MLX5_CMD_OP_QUERY_SRQ:
 331         case MLX5_CMD_OP_ARM_RQ:
 332         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 333         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 334         case MLX5_CMD_OP_ARM_XRC_SRQ:
 335         case MLX5_CMD_OP_CREATE_DCT:
 336         case MLX5_CMD_OP_DRAIN_DCT:
 337         case MLX5_CMD_OP_QUERY_DCT:
 338         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 339         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 340         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 341         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 342         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 343         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 344         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 345         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 346         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 347         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 348         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 349         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 350         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 351         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 352         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 353         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 354         case MLX5_CMD_OP_ALLOC_PD:
 355         case MLX5_CMD_OP_ALLOC_UAR:
 356         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 357         case MLX5_CMD_OP_ACCESS_REG:
 358         case MLX5_CMD_OP_ATTACH_TO_MCG:
 359         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 360         case MLX5_CMD_OP_MAD_IFC:
 361         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 362         case MLX5_CMD_OP_SET_MAD_DEMUX:
 363         case MLX5_CMD_OP_NOP:
 364         case MLX5_CMD_OP_ALLOC_XRCD:
 365         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 366         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 367         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 368         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 369         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 370         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 371         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 372         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 373         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 374         case MLX5_CMD_OP_CREATE_TIR:
 375         case MLX5_CMD_OP_MODIFY_TIR:
 376         case MLX5_CMD_OP_QUERY_TIR:
 377         case MLX5_CMD_OP_CREATE_SQ:
 378         case MLX5_CMD_OP_MODIFY_SQ:
 379         case MLX5_CMD_OP_QUERY_SQ:
 380         case MLX5_CMD_OP_CREATE_RQ:
 381         case MLX5_CMD_OP_MODIFY_RQ:
 382         case MLX5_CMD_OP_QUERY_RQ:
 383         case MLX5_CMD_OP_CREATE_RMP:
 384         case MLX5_CMD_OP_MODIFY_RMP:
 385         case MLX5_CMD_OP_QUERY_RMP:
 386         case MLX5_CMD_OP_CREATE_TIS:
 387         case MLX5_CMD_OP_MODIFY_TIS:
 388         case MLX5_CMD_OP_QUERY_TIS:
 389         case MLX5_CMD_OP_CREATE_RQT:
 390         case MLX5_CMD_OP_MODIFY_RQT:
 391         case MLX5_CMD_OP_QUERY_RQT:
 392         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 393         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 394         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 395         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 396         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 397         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 398                 *status = MLX5_DRIVER_STATUS_ABORTED;
 399                 *synd = MLX5_DRIVER_SYND;
 400                 return -EIO;
 401         default:
 402                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 403                 return -EINVAL;
 404         }
 405 }
 406
 407 const char *mlx5_command_str(int command)
 408 {
 409         switch (command) {
 410         case MLX5_CMD_OP_QUERY_HCA_CAP:
 411                 return "QUERY_HCA_CAP";
 412
 413         case MLX5_CMD_OP_SET_HCA_CAP:
 414                 return "SET_HCA_CAP";
 415
 416         case MLX5_CMD_OP_QUERY_ADAPTER:
 417                 return "QUERY_ADAPTER";
 418
 419         case MLX5_CMD_OP_INIT_HCA:
 420                 return "INIT_HCA";
 421
 422         case MLX5_CMD_OP_TEARDOWN_HCA:
 423                 return "TEARDOWN_HCA";
 424
 425         case MLX5_CMD_OP_ENABLE_HCA:
 426                 return "MLX5_CMD_OP_ENABLE_HCA";
 427
 428         case MLX5_CMD_OP_DISABLE_HCA:
 429                 return "MLX5_CMD_OP_DISABLE_HCA";
 430
 431         case MLX5_CMD_OP_QUERY_PAGES:
 432                 return "QUERY_PAGES";
 433
 434         case MLX5_CMD_OP_MANAGE_PAGES:
 435                 return "MANAGE_PAGES";
 436
 437         case MLX5_CMD_OP_CREATE_MKEY:
 438                 return "CREATE_MKEY";
 439
 440         case MLX5_CMD_OP_QUERY_MKEY:
 441                 return "QUERY_MKEY";
 442
 443         case MLX5_CMD_OP_DESTROY_MKEY:
 444                 return "DESTROY_MKEY";
 445
 446         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 447                 return "QUERY_SPECIAL_CONTEXTS";
 448
 449         case MLX5_CMD_OP_CREATE_EQ:
 450                 return "CREATE_EQ";
 451
 452         case MLX5_CMD_OP_DESTROY_EQ:
 453                 return "DESTROY_EQ";
 454
 455         case MLX5_CMD_OP_QUERY_EQ:
 456                 return "QUERY_EQ";
 457
 458         case MLX5_CMD_OP_CREATE_CQ:
 459                 return "CREATE_CQ";
 460
 461         case MLX5_CMD_OP_DESTROY_CQ:
 462                 return "DESTROY_CQ";
 463
 464         case MLX5_CMD_OP_QUERY_CQ:
 465                 return "QUERY_CQ";
 466
 467         case MLX5_CMD_OP_MODIFY_CQ:
 468                 return "MODIFY_CQ";
 469
 470         case MLX5_CMD_OP_CREATE_QP:
 471                 return "CREATE_QP";
 472
 473         case MLX5_CMD_OP_DESTROY_QP:
 474                 return "DESTROY_QP";
 475
 476         case MLX5_CMD_OP_RST2INIT_QP:
 477                 return "RST2INIT_QP";
 478
 479         case MLX5_CMD_OP_INIT2RTR_QP:
 480                 return "INIT2RTR_QP";
 481
 482         case MLX5_CMD_OP_RTR2RTS_QP:
 483                 return "RTR2RTS_QP";
 484
 485         case MLX5_CMD_OP_RTS2RTS_QP:
 486                 return "RTS2RTS_QP";
 487
 488         case MLX5_CMD_OP_SQERR2RTS_QP:
 489                 return "SQERR2RTS_QP";
 490
 491         case MLX5_CMD_OP_2ERR_QP:
 492                 return "2ERR_QP";
 493
 494         case MLX5_CMD_OP_2RST_QP:
 495                 return "2RST_QP";
 496
 497         case MLX5_CMD_OP_QUERY_QP:
 498                 return "QUERY_QP";
 499
 500         case MLX5_CMD_OP_MAD_IFC:
 501                 return "MAD_IFC";
 502
 503         case MLX5_CMD_OP_INIT2INIT_QP:
 504                 return "INIT2INIT_QP";
 505
 506         case MLX5_CMD_OP_CREATE_PSV:
 507                 return "CREATE_PSV";
 508
 509         case MLX5_CMD_OP_DESTROY_PSV:
 510                 return "DESTROY_PSV";
 511
 512         case MLX5_CMD_OP_CREATE_SRQ:
 513                 return "CREATE_SRQ";
 514
 515         case MLX5_CMD_OP_DESTROY_SRQ:
 516                 return "DESTROY_SRQ";
 517
 518         case MLX5_CMD_OP_QUERY_SRQ:
 519                 return "QUERY_SRQ";
 520
 521         case MLX5_CMD_OP_ARM_RQ:
 522                 return "ARM_RQ";
 523
 524         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 525                 return "CREATE_XRC_SRQ";
 526
 527         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 528                 return "DESTROY_XRC_SRQ";
 529
 530         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 531                 return "QUERY_XRC_SRQ";
 532
 533         case MLX5_CMD_OP_ARM_XRC_SRQ:
 534                 return "ARM_XRC_SRQ";
 535
 536         case MLX5_CMD_OP_ALLOC_PD:
 537                 return "ALLOC_PD";
 538
 539         case MLX5_CMD_OP_DEALLOC_PD:
 540                 return "DEALLOC_PD";
 541
 542         case MLX5_CMD_OP_ALLOC_UAR:
 543                 return "ALLOC_UAR";
 544
 545         case MLX5_CMD_OP_DEALLOC_UAR:
 546                 return "DEALLOC_UAR";
 547
 548         case MLX5_CMD_OP_ATTACH_TO_MCG:
 549                 return "ATTACH_TO_MCG";
 550
 551         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 552                 return "DETTACH_FROM_MCG";
 553
 554         case MLX5_CMD_OP_ALLOC_XRCD:
 555                 return "ALLOC_XRCD";
 556
 557         case MLX5_CMD_OP_DEALLOC_XRCD:
 558                 return "DEALLOC_XRCD";
 559
 560         case MLX5_CMD_OP_ACCESS_REG:
 561                 return "MLX5_CMD_OP_ACCESS_REG";
 562
 563         case MLX5_CMD_OP_SET_WOL_ROL:
 564                 return "SET_WOL_ROL";
 565
 566         case MLX5_CMD_OP_QUERY_WOL_ROL:
 567                 return "QUERY_WOL_ROL";
 568
 569         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 570                 return "ADD_VXLAN_UDP_DPORT";
 571
 572         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 573                 return "DELETE_VXLAN_UDP_DPORT";
 574
 575         default: return "unknown command opcode";
 576         }
 577 }
 578
 579 static void dump_command(struct mlx5_core_dev *dev,
 580                          struct mlx5_cmd_work_ent *ent, int input)
 581 {
 582         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 583         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 584         struct mlx5_cmd_mailbox *next = msg->next;
 585         int data_only;
 586         u32 offset = 0;
 587         int dump_len;
 588
 589         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 590
 591         if (data_only)
 592                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 593                                    "dump command data %s(0x%x) %s\n",
 594                                    mlx5_command_str(op), op,
 595                                    input ? "INPUT" : "OUTPUT");
 596         else
 597                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 598                               mlx5_command_str(op), op,
 599                               input ? "INPUT" : "OUTPUT");
 600
 601         if (data_only) {
 602                 if (input) {
 603                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 604                         offset += sizeof(ent->lay->in);
 605                 } else {
 606                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 607                         offset += sizeof(ent->lay->out);
 608                 }
 609         } else {
 610                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 611                 offset += sizeof(*ent->lay);
 612         }
 613
 614         while (next && offset < msg->len) {
 615                 if (data_only) {
 616                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 617                         dump_buf(next->buf, dump_len, 1, offset);
 618                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 619                 } else {
 620                         mlx5_core_dbg(dev, "command block:\n");
 621                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 622                         offset += sizeof(struct mlx5_cmd_prot_block);
 623                 }
 624                 next = next->next;
 625         }
 626
 627         if (data_only)
 628                 pr_debug("\n");
 629 }
 630
 631 static void cmd_work_handler(struct work_struct *work)
 632 {
 633         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 634         struct mlx5_cmd *cmd = ent->cmd;
 635         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 636         struct mlx5_cmd_layout *lay;
 637         struct semaphore *sem;
 638         unsigned long flags;
 639
 640         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 641         down(sem);
 642         if (!ent->page_queue) {
 643                 ent->idx = alloc_ent(cmd);
 644                 if (ent->idx < 0) {
 645                         mlx5_core_err(dev, "failed to allocate command entry\n");
 646                         up(sem);
 647                         return;
 648                 }
 649         } else {
 650                 ent->idx = cmd->max_reg_cmds;
 651                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 652                 clear_bit(ent->idx, &cmd->bitmask);
 653                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 654         }
 655
 656         ent->token = alloc_token(cmd);
 657         cmd->ent_arr[ent->idx] = ent;
 658         lay = get_inst(cmd, ent->idx);
 659         ent->lay = lay;
 660         memset(lay, 0, sizeof(*lay));
 661         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 662         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 663         if (ent->in->next)
 664                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 665         lay->inlen = cpu_to_be32(ent->in->len);
 666         if (ent->out->next)
 667                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 668         lay->outlen = cpu_to_be32(ent->out->len);
 669         lay->type = MLX5_PCI_CMD_XPORT;
 670         lay->token = ent->token;
 671         lay->status_own = CMD_OWNER_HW;
 672         set_signature(ent, !cmd->checksum_disabled);
 673         dump_command(dev, ent, 1);
 674         ent->ts1 = ktime_get_ns();
 675
 676         /* ring doorbell after the descriptor is valid */
 677         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 678         wmb();
 679         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 680         mmiowb();
 681         /* if not in polling don't use ent after this point */
 682         if (cmd->mode == CMD_MODE_POLLING) {
 683                 poll_timeout(ent);
 684                 /* make sure we read the descriptor after ownership is SW */
 685                 rmb();
 686                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 687         }
 688 }
 689
 690 static const char *deliv_status_to_str(u8 status)
 691 {
 692         switch (status) {
 693         case MLX5_CMD_DELIVERY_STAT_OK:
 694                 return "no errors";
 695         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 696                 return "signature error";
 697         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 698                 return "token error";
 699         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 700                 return "bad block number";
 701         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 702                 return "output pointer not aligned to block size";
 703         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 704                 return "input pointer not aligned to block size";
 705         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 706                 return "firmware internal error";
 707         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 708                 return "command input length error";
 709         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 710                 return "command ouput length error";
 711         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 712                 return "reserved fields not cleared";
 713         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 714                 return "bad command descriptor type";
 715         default:
 716                 return "unknown status code";
 717         }
 718 }
 719
 720 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 721 {
 722         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 723
 724         return be16_to_cpu(hdr->opcode);
 725 }
 726
 727 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 728 {
 729         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 730         struct mlx5_cmd *cmd = &dev->cmd;
 731         int err;
 732
 733         if (cmd->mode == CMD_MODE_POLLING) {
 734                 wait_for_completion(&ent->done);
 735                 err = ent->ret;
 736         } else {
 737                 if (!wait_for_completion_timeout(&ent->done, timeout))
 738                         err = -ETIMEDOUT;
 739                 else
 740                         err = 0;
 741         }
 742         if (err == -ETIMEDOUT) {
 743                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 744                                mlx5_command_str(msg_to_opcode(ent->in)),
 745                                msg_to_opcode(ent->in));
 746         }
 747         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 748                       err, deliv_status_to_str(ent->status), ent->status);
 749
 750         return err;
 751 }
 752
 753 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 754 {
 755         return &out->syndrome;
 756 }
 757
 758 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 759 {
 760         return &out->status;
 761 }
 762
 763 /*  Notes:
 764  *    1. Callback functions may not sleep
 765  *    2. page queue commands do not support asynchrous completion
 766  */
 767 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 768                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 769                            mlx5_cmd_cbk_t callback,
 770                            void *context, int page_queue, u8 *status)
 771 {
 772         struct mlx5_cmd *cmd = &dev->cmd;
 773         struct mlx5_cmd_work_ent *ent;
 774         struct mlx5_cmd_stats *stats;
 775         int err = 0;
 776         s64 ds;
 777         u16 op;
 778
 779         if (callback && page_queue)
 780                 return -EINVAL;
 781
 782         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 783                         page_queue);
 784         if (IS_ERR(ent))
 785                 return PTR_ERR(ent);
 786
 787         if (!callback)
 788                 init_completion(&ent->done);
 789
 790         INIT_WORK(&ent->work, cmd_work_handler);
 791         if (page_queue) {
 792                 cmd_work_handler(&ent->work);
 793         } else if (!queue_work(cmd->wq, &ent->work)) {
 794                 mlx5_core_warn(dev, "failed to queue work\n");
 795                 err = -ENOMEM;
 796                 goto out_free;
 797         }
 798
 799         if (!callback) {
 800                 err = wait_func(dev, ent);
 801                 if (err == -ETIMEDOUT)
 802                         goto out;
 803
 804                 ds = ent->ts2 - ent->ts1;
 805                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 806                 if (op < ARRAY_SIZE(cmd->stats)) {
 807                         stats = &cmd->stats[op];
 808                         spin_lock_irq(&stats->lock);
 809                         stats->sum += ds;
 810                         ++stats->n;
 811                         spin_unlock_irq(&stats->lock);
 812                 }
 813                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 814                                    "fw exec time for %s is %lld nsec\n",
 815                                    mlx5_command_str(op), ds);
 816                 *status = ent->status;
 817                 free_cmd(ent);
 818         }
 819
 820         return err;
 821
 822 out_free:
 823         free_cmd(ent);
 824 out:
 825         return err;
 826 }
 827
 828 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 829                          size_t count, loff_t *pos)
 830 {
 831         struct mlx5_core_dev *dev = filp->private_data;
 832         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 833         char lbuf[3];
 834         int err;
 835
 836         if (!dbg->in_msg || !dbg->out_msg)
 837                 return -ENOMEM;
 838
 839         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 840                 return -EFAULT;
 841
 842         lbuf[sizeof(lbuf) - 1] = 0;
 843
 844         if (strcmp(lbuf, "go"))
 845                 return -EINVAL;
 846
 847         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 848
 849         return err ? err : count;
 850 }
 851
 852
 853 static const struct file_operations fops = {
 854         .owner  = THIS_MODULE,
 855         .open   = simple_open,
 856         .write  = dbg_write,
 857 };
 858
 859 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 860 {
 861         struct mlx5_cmd_prot_block *block;
 862         struct mlx5_cmd_mailbox *next;
 863         int copy;
 864
 865         if (!to || !from)
 866                 return -ENOMEM;
 867
 868         copy = min_t(int, size, sizeof(to->first.data));
 869         memcpy(to->first.data, from, copy);
 870         size -= copy;
 871         from += copy;
 872
 873         next = to->next;
 874         while (size) {
 875                 if (!next) {
 876                         /* this is a BUG */
 877                         return -ENOMEM;
 878                 }
 879
 880                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 881                 block = next->buf;
 882                 memcpy(block->data, from, copy);
 883                 from += copy;
 884                 size -= copy;
 885                 next = next->next;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 892 {
 893         struct mlx5_cmd_prot_block *block;
 894         struct mlx5_cmd_mailbox *next;
 895         int copy;
 896
 897         if (!to || !from)
 898                 return -ENOMEM;
 899
 900         copy = min_t(int, size, sizeof(from->first.data));
 901         memcpy(to, from->first.data, copy);
 902         size -= copy;
 903         to += copy;
 904
 905         next = from->next;
 906         while (size) {
 907                 if (!next) {
 908                         /* this is a BUG */
 909                         return -ENOMEM;
 910                 }
 911
 912                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 913                 block = next->buf;
 914
 915                 memcpy(to, block->data, copy);
 916                 to += copy;
 917                 size -= copy;
 918                 next = next->next;
 919         }
 920
 921         return 0;
 922 }
 923
 924 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 925                                               gfp_t flags)
 926 {
 927         struct mlx5_cmd_mailbox *mailbox;
 928
 929         mailbox = kmalloc(sizeof(*mailbox), flags);
 930         if (!mailbox)
 931                 return ERR_PTR(-ENOMEM);
 932
 933         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 934                                       &mailbox->dma);
 935         if (!mailbox->buf) {
 936                 mlx5_core_dbg(dev, "failed allocation\n");
 937                 kfree(mailbox);
 938                 return ERR_PTR(-ENOMEM);
 939         }
 940         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 941         mailbox->next = NULL;
 942
 943         return mailbox;
 944 }
 945
 946 static void free_cmd_box(struct mlx5_core_dev *dev,
 947                          struct mlx5_cmd_mailbox *mailbox)
 948 {
 949         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 950         kfree(mailbox);
 951 }
 952
 953 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 954                                                gfp_t flags, int size)
 955 {
 956         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 957         struct mlx5_cmd_prot_block *block;
 958         struct mlx5_cmd_msg *msg;
 959         int blen;
 960         int err;
 961         int n;
 962         int i;
 963
 964         msg = kzalloc(sizeof(*msg), flags);
 965         if (!msg)
 966                 return ERR_PTR(-ENOMEM);
 967
 968         blen = size - min_t(int, sizeof(msg->first.data), size);
 969         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 970
 971         for (i = 0; i < n; i++) {
 972                 tmp = alloc_cmd_box(dev, flags);
 973                 if (IS_ERR(tmp)) {
 974                         mlx5_core_warn(dev, "failed allocating block\n");
 975                         err = PTR_ERR(tmp);
 976                         goto err_alloc;
 977                 }
 978
 979                 block = tmp->buf;
 980                 tmp->next = head;
 981                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 982                 block->block_num = cpu_to_be32(n - i - 1);
 983                 head = tmp;
 984         }
 985         msg->next = head;
 986         msg->len = size;
 987         return msg;
 988
 989 err_alloc:
 990         while (head) {
 991                 tmp = head->next;
 992                 free_cmd_box(dev, head);
 993                 head = tmp;
 994         }
 995         kfree(msg);
 996
 997         return ERR_PTR(err);
 998 }
 999
1000 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1001                                   struct mlx5_cmd_msg *msg)
1002 {
1003         struct mlx5_cmd_mailbox *head = msg->next;
1004         struct mlx5_cmd_mailbox *next;
1005
1006         while (head) {
1007                 next = head->next;
1008                 free_cmd_box(dev, head);
1009                 head = next;
1010         }
1011         kfree(msg);
1012 }
1013
1014 static ssize_t data_write(struct file *filp, const char __user *buf,
1015                           size_t count, loff_t *pos)
1016 {
1017         struct mlx5_core_dev *dev = filp->private_data;
1018         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1019         void *ptr;
1020         int err;
1021
1022         if (*pos != 0)
1023                 return -EINVAL;
1024
1025         kfree(dbg->in_msg);
1026         dbg->in_msg = NULL;
1027         dbg->inlen = 0;
1028
1029         ptr = kzalloc(count, GFP_KERNEL);
1030         if (!ptr)
1031                 return -ENOMEM;
1032
1033         if (copy_from_user(ptr, buf, count)) {
1034                 err = -EFAULT;
1035                 goto out;
1036         }
1037         dbg->in_msg = ptr;
1038         dbg->inlen = count;
1039
1040         *pos = count;
1041
1042         return count;
1043
1044 out:
1045         kfree(ptr);
1046         return err;
1047 }
1048
1049 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1050                          loff_t *pos)
1051 {
1052         struct mlx5_core_dev *dev = filp->private_data;
1053         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1054         int copy;
1055
1056         if (*pos)
1057                 return 0;
1058
1059         if (!dbg->out_msg)
1060                 return -ENOMEM;
1061
1062         copy = min_t(int, count, dbg->outlen);
1063         if (copy_to_user(buf, dbg->out_msg, copy))
1064                 return -EFAULT;
1065
1066         *pos += copy;
1067
1068         return copy;
1069 }
1070
1071 static const struct file_operations dfops = {
1072         .owner  = THIS_MODULE,
1073         .open   = simple_open,
1074         .write  = data_write,
1075         .read   = data_read,
1076 };
1077
1078 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1079                            loff_t *pos)
1080 {
1081         struct mlx5_core_dev *dev = filp->private_data;
1082         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1083         char outlen[8];
1084         int err;
1085
1086         if (*pos)
1087                 return 0;
1088
1089         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1090         if (err < 0)
1091                 return err;
1092
1093         if (copy_to_user(buf, &outlen, err))
1094                 return -EFAULT;
1095
1096         *pos += err;
1097
1098         return err;
1099 }
1100
1101 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1102                             size_t count, loff_t *pos)
1103 {
1104         struct mlx5_core_dev *dev = filp->private_data;
1105         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1106         char outlen_str[8];
1107         int outlen;
1108         void *ptr;
1109         int err;
1110
1111         if (*pos != 0 || count > 6)
1112                 return -EINVAL;
1113
1114         kfree(dbg->out_msg);
1115         dbg->out_msg = NULL;
1116         dbg->outlen = 0;
1117
1118         if (copy_from_user(outlen_str, buf, count))
1119                 return -EFAULT;
1120
1121         outlen_str[7] = 0;
1122
1123         err = sscanf(outlen_str, "%d", &outlen);
1124         if (err < 0)
1125                 return err;
1126
1127         ptr = kzalloc(outlen, GFP_KERNEL);
1128         if (!ptr)
1129                 return -ENOMEM;
1130
1131         dbg->out_msg = ptr;
1132         dbg->outlen = outlen;
1133
1134         *pos = count;
1135
1136         return count;
1137 }
1138
1139 static const struct file_operations olfops = {
1140         .owner  = THIS_MODULE,
1141         .open   = simple_open,
1142         .write  = outlen_write,
1143         .read   = outlen_read,
1144 };
1145
1146 static void set_wqname(struct mlx5_core_dev *dev)
1147 {
1148         struct mlx5_cmd *cmd = &dev->cmd;
1149
1150         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1151                  dev_name(&dev->pdev->dev));
1152 }
1153
1154 static void clean_debug_files(struct mlx5_core_dev *dev)
1155 {
1156         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1157
1158         if (!mlx5_debugfs_root)
1159                 return;
1160
1161         mlx5_cmdif_debugfs_cleanup(dev);
1162         debugfs_remove_recursive(dbg->dbg_root);
1163 }
1164
1165 static int create_debugfs_files(struct mlx5_core_dev *dev)
1166 {
1167         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1168         int err = -ENOMEM;
1169
1170         if (!mlx5_debugfs_root)
1171                 return 0;
1172
1173         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1174         if (!dbg->dbg_root)
1175                 return err;
1176
1177         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1178                                           dev, &dfops);
1179         if (!dbg->dbg_in)
1180                 goto err_dbg;
1181
1182         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1183                                            dev, &dfops);
1184         if (!dbg->dbg_out)
1185                 goto err_dbg;
1186
1187         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1188                                               dev, &olfops);
1189         if (!dbg->dbg_outlen)
1190                 goto err_dbg;
1191
1192         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1193                                             &dbg->status);
1194         if (!dbg->dbg_status)
1195                 goto err_dbg;
1196
1197         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1198         if (!dbg->dbg_run)
1199                 goto err_dbg;
1200
1201         mlx5_cmdif_debugfs_init(dev);
1202
1203         return 0;
1204
1205 err_dbg:
1206         clean_debug_files(dev);
1207         return err;
1208 }
1209
1210 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1211 {
1212         struct mlx5_cmd *cmd = &dev->cmd;
1213         int i;
1214
1215         for (i = 0; i < cmd->max_reg_cmds; i++)
1216                 down(&cmd->sem);
1217
1218         down(&cmd->pages_sem);
1219
1220         flush_workqueue(cmd->wq);
1221
1222         cmd->mode = CMD_MODE_EVENTS;
1223
1224         up(&cmd->pages_sem);
1225         for (i = 0; i < cmd->max_reg_cmds; i++)
1226                 up(&cmd->sem);
1227 }
1228
1229 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1230 {
1231         struct mlx5_cmd *cmd = &dev->cmd;
1232         int i;
1233
1234         for (i = 0; i < cmd->max_reg_cmds; i++)
1235                 down(&cmd->sem);
1236
1237         down(&cmd->pages_sem);
1238
1239         flush_workqueue(cmd->wq);
1240         cmd->mode = CMD_MODE_POLLING;
1241
1242         up(&cmd->pages_sem);
1243         for (i = 0; i < cmd->max_reg_cmds; i++)
1244                 up(&cmd->sem);
1245 }
1246
1247 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1248 {
1249         unsigned long flags;
1250
1251         if (msg->cache) {
1252                 spin_lock_irqsave(&msg->cache->lock, flags);
1253                 list_add_tail(&msg->list, &msg->cache->head);
1254                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1255         } else {
1256                 mlx5_free_cmd_msg(dev, msg);
1257         }
1258 }
1259
1260 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1261 {
1262         struct mlx5_cmd *cmd = &dev->cmd;
1263         struct mlx5_cmd_work_ent *ent;
1264         mlx5_cmd_cbk_t callback;
1265         void *context;
1266         int err;
1267         int i;
1268         s64 ds;
1269         struct mlx5_cmd_stats *stats;
1270         unsigned long flags;
1271         unsigned long vector;
1272
1273         /* there can be at most 32 command queues */
1274         vector = vec & 0xffffffff;
1275         for (i = 0; i < (1 << cmd->log_sz); i++) {
1276                 if (test_bit(i, &vector)) {
1277                         struct semaphore *sem;
1278
1279                         ent = cmd->ent_arr[i];
1280                         if (ent->page_queue)
1281                                 sem = &cmd->pages_sem;
1282                         else
1283                                 sem = &cmd->sem;
1284                         ent->ts2 = ktime_get_ns();
1285                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1286                         dump_command(dev, ent, 0);
1287                         if (!ent->ret) {
1288                                 if (!cmd->checksum_disabled)
1289                                         ent->ret = verify_signature(ent);
1290                                 else
1291                                         ent->ret = 0;
1292                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1293                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1294                                 else
1295                                         ent->status = ent->lay->status_own >> 1;
1296
1297                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1298                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1299                         }
1300                         free_ent(cmd, ent->idx);
1301
1302                         if (ent->callback) {
1303                                 ds = ent->ts2 - ent->ts1;
1304                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1305                                         stats = &cmd->stats[ent->op];
1306                                         spin_lock_irqsave(&stats->lock, flags);
1307                                         stats->sum += ds;
1308                                         ++stats->n;
1309                                         spin_unlock_irqrestore(&stats->lock, flags);
1310                                 }
1311
1312                                 callback = ent->callback;
1313                                 context = ent->context;
1314                                 err = ent->ret;
1315                                 if (!err)
1316                                         err = mlx5_copy_from_msg(ent->uout,
1317                                                                  ent->out,
1318                                                                  ent->uout_size);
1319
1320                                 mlx5_free_cmd_msg(dev, ent->out);
1321                                 free_msg(dev, ent->in);
1322
1323                                 err = err ? err : ent->status;
1324                                 free_cmd(ent);
1325                                 callback(err, context);
1326                         } else {
1327                                 complete(&ent->done);
1328                         }
1329                         up(sem);
1330                 }
1331         }
1332 }
1333 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1334
1335 static int status_to_err(u8 status)
1336 {
1337         return status ? -1 : 0; /* TBD more meaningful codes */
1338 }
1339
1340 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1341                                       gfp_t gfp)
1342 {
1343         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1344         struct mlx5_cmd *cmd = &dev->cmd;
1345         struct cache_ent *ent = NULL;
1346
1347         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1348                 ent = &cmd->cache.large;
1349         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1350                 ent = &cmd->cache.med;
1351
1352         if (ent) {
1353                 spin_lock_irq(&ent->lock);
1354                 if (!list_empty(&ent->head)) {
1355                         msg = list_entry(ent->head.next, typeof(*msg), list);
1356                         /* For cached lists, we must explicitly state what is
1357                          * the real size
1358                          */
1359                         msg->len = in_size;
1360                         list_del(&msg->list);
1361                 }
1362                 spin_unlock_irq(&ent->lock);
1363         }
1364
1365         if (IS_ERR(msg))
1366                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1367
1368         return msg;
1369 }
1370
1371 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1372 {
1373         return be16_to_cpu(in->opcode);
1374 }
1375
1376 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1377 {
1378         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1379 }
1380
1381 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1382                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1383 {
1384         struct mlx5_cmd_msg *inb;
1385         struct mlx5_cmd_msg *outb;
1386         int pages_queue;
1387         gfp_t gfp;
1388         int err;
1389         u8 status = 0;
1390         u32 drv_synd;
1391
1392         if (pci_channel_offline(dev->pdev) ||
1393             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1394                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1395                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1396                 *get_status_ptr(out) = status;
1397                 return err;
1398         }
1399
1400         pages_queue = is_manage_pages(in);
1401         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1402
1403         inb = alloc_msg(dev, in_size, gfp);
1404         if (IS_ERR(inb)) {
1405                 err = PTR_ERR(inb);
1406                 return err;
1407         }
1408
1409         err = mlx5_copy_to_msg(inb, in, in_size);
1410         if (err) {
1411                 mlx5_core_warn(dev, "err %d\n", err);
1412                 goto out_in;
1413         }
1414
1415         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1416         if (IS_ERR(outb)) {
1417                 err = PTR_ERR(outb);
1418                 goto out_in;
1419         }
1420
1421         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1422                               pages_queue, &status);
1423         if (err)
1424                 goto out_out;
1425
1426         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1427         if (status) {
1428                 err = status_to_err(status);
1429                 goto out_out;
1430         }
1431
1432         if (!callback)
1433                 err = mlx5_copy_from_msg(out, outb, out_size);
1434
1435 out_out:
1436         if (!callback)
1437                 mlx5_free_cmd_msg(dev, outb);
1438
1439 out_in:
1440         if (!callback)
1441                 free_msg(dev, inb);
1442         return err;
1443 }
1444
1445 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1446                   int out_size)
1447 {
1448         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1449 }
1450 EXPORT_SYMBOL(mlx5_cmd_exec);
1451
1452 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1453                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1454                      void *context)
1455 {
1456         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1457 }
1458 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1459
1460 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1461 {
1462         struct mlx5_cmd *cmd = &dev->cmd;
1463         struct mlx5_cmd_msg *msg;
1464         struct mlx5_cmd_msg *n;
1465
1466         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1467                 list_del(&msg->list);
1468                 mlx5_free_cmd_msg(dev, msg);
1469         }
1470
1471         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1472                 list_del(&msg->list);
1473                 mlx5_free_cmd_msg(dev, msg);
1474         }
1475 }
1476
1477 static int create_msg_cache(struct mlx5_core_dev *dev)
1478 {
1479         struct mlx5_cmd *cmd = &dev->cmd;
1480         struct mlx5_cmd_msg *msg;
1481         int err;
1482         int i;
1483
1484         spin_lock_init(&cmd->cache.large.lock);
1485         INIT_LIST_HEAD(&cmd->cache.large.head);
1486         spin_lock_init(&cmd->cache.med.lock);
1487         INIT_LIST_HEAD(&cmd->cache.med.head);
1488
1489         for (i = 0; i < NUM_LONG_LISTS; i++) {
1490                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1491                 if (IS_ERR(msg)) {
1492                         err = PTR_ERR(msg);
1493                         goto ex_err;
1494                 }
1495                 msg->cache = &cmd->cache.large;
1496                 list_add_tail(&msg->list, &cmd->cache.large.head);
1497         }
1498
1499         for (i = 0; i < NUM_MED_LISTS; i++) {
1500                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1501                 if (IS_ERR(msg)) {
1502                         err = PTR_ERR(msg);
1503                         goto ex_err;
1504                 }
1505                 msg->cache = &cmd->cache.med;
1506                 list_add_tail(&msg->list, &cmd->cache.med.head);
1507         }
1508
1509         return 0;
1510
1511 ex_err:
1512         destroy_msg_cache(dev);
1513         return err;
1514 }
1515
1516 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1517 {
1518         struct device *ddev = &dev->pdev->dev;
1519
1520         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1521                                                  &cmd->alloc_dma, GFP_KERNEL);
1522         if (!cmd->cmd_alloc_buf)
1523                 return -ENOMEM;
1524
1525         /* make sure it is aligned to 4K */
1526         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1527                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1528                 cmd->dma = cmd->alloc_dma;
1529                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1530                 return 0;
1531         }
1532
1533         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1534                           cmd->alloc_dma);
1535         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1536                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1537                                                  &cmd->alloc_dma, GFP_KERNEL);
1538         if (!cmd->cmd_alloc_buf)
1539                 return -ENOMEM;
1540
1541         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1542         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1543         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1544         return 0;
1545 }
1546
1547 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1548 {
1549         struct device *ddev = &dev->pdev->dev;
1550
1551         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1552                           cmd->alloc_dma);
1553 }
1554
1555 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1556 {
1557         int size = sizeof(struct mlx5_cmd_prot_block);
1558         int align = roundup_pow_of_two(size);
1559         struct mlx5_cmd *cmd = &dev->cmd;
1560         u32 cmd_h, cmd_l;
1561         u16 cmd_if_rev;
1562         int err;
1563         int i;
1564
1565         memset(cmd, 0, sizeof(*cmd));
1566         cmd_if_rev = cmdif_rev(dev);
1567         if (cmd_if_rev != CMD_IF_REV) {
1568                 dev_err(&dev->pdev->dev,
1569                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1570                         CMD_IF_REV, cmd_if_rev);
1571                 return -EINVAL;
1572         }
1573
1574         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1575         if (!cmd->pool)
1576                 return -ENOMEM;
1577
1578         err = alloc_cmd_page(dev, cmd);
1579         if (err)
1580                 goto err_free_pool;
1581
1582         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1583         cmd->log_sz = cmd_l >> 4 & 0xf;
1584         cmd->log_stride = cmd_l & 0xf;
1585         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1586                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1587                         1 << cmd->log_sz);
1588                 err = -EINVAL;
1589                 goto err_free_page;
1590         }
1591
1592         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1593                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1594                 err = -EINVAL;
1595                 goto err_free_page;
1596         }
1597
1598         cmd->checksum_disabled = 1;
1599         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1600         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1601
1602         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1603         if (cmd->cmdif_rev > CMD_IF_REV) {
1604                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1605                         CMD_IF_REV, cmd->cmdif_rev);
1606                 err = -ENOTSUPP;
1607                 goto err_free_page;
1608         }
1609
1610         spin_lock_init(&cmd->alloc_lock);
1611         spin_lock_init(&cmd->token_lock);
1612         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1613                 spin_lock_init(&cmd->stats[i].lock);
1614
1615         sema_init(&cmd->sem, cmd->max_reg_cmds);
1616         sema_init(&cmd->pages_sem, 1);
1617
1618         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1619         cmd_l = (u32)(cmd->dma);
1620         if (cmd_l & 0xfff) {
1621                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1622                 err = -ENOMEM;
1623                 goto err_free_page;
1624         }
1625
1626         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1627         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1628
1629         /* Make sure firmware sees the complete address before we proceed */
1630         wmb();
1631
1632         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1633
1634         cmd->mode = CMD_MODE_POLLING;
1635
1636         err = create_msg_cache(dev);
1637         if (err) {
1638                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1639                 goto err_free_page;
1640         }
1641
1642         set_wqname(dev);
1643         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1644         if (!cmd->wq) {
1645                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1646                 err = -ENOMEM;
1647                 goto err_cache;
1648         }
1649
1650         err = create_debugfs_files(dev);
1651         if (err) {
1652                 err = -ENOMEM;
1653                 goto err_wq;
1654         }
1655
1656         return 0;
1657
1658 err_wq:
1659         destroy_workqueue(cmd->wq);
1660
1661 err_cache:
1662         destroy_msg_cache(dev);
1663
1664 err_free_page:
1665         free_cmd_page(dev, cmd);
1666
1667 err_free_pool:
1668         pci_pool_destroy(cmd->pool);
1669
1670         return err;
1671 }
1672 EXPORT_SYMBOL(mlx5_cmd_init);
1673
1674 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1675 {
1676         struct mlx5_cmd *cmd = &dev->cmd;
1677
1678         clean_debug_files(dev);
1679         destroy_workqueue(cmd->wq);
1680         destroy_msg_cache(dev);
1681         free_cmd_page(dev, cmd);
1682         pci_pool_destroy(cmd->pool);
1683 }
1684 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1685
1686 static const char *cmd_status_str(u8 status)
1687 {
1688         switch (status) {
1689         case MLX5_CMD_STAT_OK:
1690                 return "OK";
1691         case MLX5_CMD_STAT_INT_ERR:
1692                 return "internal error";
1693         case MLX5_CMD_STAT_BAD_OP_ERR:
1694                 return "bad operation";
1695         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1696                 return "bad parameter";
1697         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1698                 return "bad system state";
1699         case MLX5_CMD_STAT_BAD_RES_ERR:
1700                 return "bad resource";
1701         case MLX5_CMD_STAT_RES_BUSY:
1702                 return "resource busy";
1703         case MLX5_CMD_STAT_LIM_ERR:
1704                 return "limits exceeded";
1705         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1706                 return "bad resource state";
1707         case MLX5_CMD_STAT_IX_ERR:
1708                 return "bad index";
1709         case MLX5_CMD_STAT_NO_RES_ERR:
1710                 return "no resources";
1711         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1712                 return "bad input length";
1713         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1714                 return "bad output length";
1715         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1716                 return "bad QP state";
1717         case MLX5_CMD_STAT_BAD_PKT_ERR:
1718                 return "bad packet (discarded)";
1719         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1720                 return "bad size too many outstanding CQEs";
1721         default:
1722                 return "unknown status";
1723         }
1724 }
1725
1726 static int cmd_status_to_err(u8 status)
1727 {
1728         switch (status) {
1729         case MLX5_CMD_STAT_OK:                          return 0;
1730         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1731         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1732         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1733         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1734         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1735         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1736         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1737         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1738         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1739         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1740         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1741         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1742         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1743         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1744         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1745         default:                                        return -EIO;
1746         }
1747 }
1748
1749 /* this will be available till all the commands use set/get macros */
1750 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1751 {
1752         if (!hdr->status)
1753                 return 0;
1754
1755         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1756                 cmd_status_str(hdr->status), hdr->status,
1757                 be32_to_cpu(hdr->syndrome));
1758
1759         return cmd_status_to_err(hdr->status);
1760 }
1761
1762 int mlx5_cmd_status_to_err_v2(void *ptr)
1763 {
1764         u32     syndrome;
1765         u8      status;
1766
1767         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1768         if (!status)
1769                 return 0;
1770
1771         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1772
1773         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1774                 cmd_status_str(status), status, syndrome);
1775
1776         return cmd_status_to_err(status);
1777 }