2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
53 #define MLX5E_MAX_NUM_TC 8
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
67 #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
70 #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
71 #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\
72 MLX5_MPWRQ_LOG_STRIDE_SIZE)
73 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
74 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
75 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
77 MLX5_MPWRQ_WQE_PAGE_ORDER)
78 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
79 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
80 #define MLX5_UMR_ALIGN (2048)
81 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
83 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
85 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
87 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
88 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
89 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
91 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
92 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
93 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
94 #define MLX5E_TX_CQ_POLL_BUDGET 128
95 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
96 #define MLX5E_SQ_BF_BUDGET 16
98 #define MLX5E_NUM_MAIN_GROUPS 9
100 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
103 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
107 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
112 static inline int mlx5_min_log_rq_size(int wq_type)
115 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
118 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
122 static inline int mlx5_max_log_rq_size(int wq_type)
125 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
128 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
132 struct mlx5e_tx_wqe {
133 struct mlx5_wqe_ctrl_seg ctrl;
134 struct mlx5_wqe_eth_seg eth;
137 struct mlx5e_rx_wqe {
138 struct mlx5_wqe_srq_next_seg next;
139 struct mlx5_wqe_data_seg data;
142 struct mlx5e_umr_wqe {
143 struct mlx5_wqe_ctrl_seg ctrl;
144 struct mlx5_wqe_umr_ctrl_seg uctrl;
145 struct mlx5_mkey_seg mkc;
146 struct mlx5_wqe_data_seg data;
149 #ifdef CONFIG_MLX5_CORE_EN_DCB
150 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
151 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
154 struct mlx5e_params {
160 bool rx_cqe_compress_admin;
161 bool rx_cqe_compress;
162 u16 rx_cq_moderation_usec;
163 u16 rx_cq_moderation_pkts;
164 u16 tx_cq_moderation_usec;
165 u16 tx_cq_moderation_pkts;
171 u8 toeplitz_hash_key[40];
172 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
173 bool vlan_strip_disable;
174 #ifdef CONFIG_MLX5_CORE_EN_DCB
179 struct mlx5e_tstamp {
181 struct cyclecounter cycles;
182 struct timecounter clock;
183 struct hwtstamp_config hwtstamp_config;
185 unsigned long overflow_period;
186 struct delayed_work overflow_work;
187 struct mlx5_core_dev *mdev;
188 struct ptp_clock *ptp;
189 struct ptp_clock_info ptp_info;
193 MLX5E_RQ_STATE_POST_WQES_ENABLE,
194 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
198 /* data path - accessed per cqe */
201 /* data path - accessed per napi poll */
202 struct napi_struct *napi;
203 struct mlx5_core_cq mcq;
204 struct mlx5e_channel *channel;
205 struct mlx5e_priv *priv;
207 /* cqe decompression */
208 struct mlx5_cqe64 title;
209 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
212 u16 decmprs_wqe_counter;
215 struct mlx5_wq_ctrl wq_ctrl;
216 } ____cacheline_aligned_in_smp;
219 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
220 struct mlx5_cqe64 *cqe);
221 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
224 struct mlx5e_dma_info {
231 struct mlx5_wq_ll wq;
233 struct sk_buff **skb;
234 struct mlx5e_mpw_info *wqe_info;
239 struct net_device *netdev;
240 struct mlx5e_tstamp *tstamp;
241 struct mlx5e_rq_stats stats;
243 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
244 mlx5e_fp_alloc_wqe alloc_wqe;
250 struct mlx5_wq_ctrl wq_ctrl;
253 struct mlx5e_channel *channel;
254 struct mlx5e_priv *priv;
255 } ____cacheline_aligned_in_smp;
257 struct mlx5e_umr_dma_info {
259 __be64 *mtt_no_align;
261 struct mlx5e_dma_info *dma_info;
264 struct mlx5e_mpw_info {
266 struct mlx5e_dma_info dma_info;
267 struct mlx5e_umr_dma_info umr;
269 u16 consumed_strides;
270 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
272 void (*dma_pre_sync)(struct device *pdev,
273 struct mlx5e_mpw_info *wi,
274 u32 wqe_offset, u32 len);
275 void (*add_skb_frag)(struct device *pdev,
277 struct mlx5e_mpw_info *wi,
278 u32 page_idx, u32 frag_offset, u32 len);
279 void (*copy_skb_header)(struct device *pdev,
281 struct mlx5e_mpw_info *wi,
282 u32 page_idx, u32 offset,
284 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
287 struct mlx5e_tx_wqe_info {
293 enum mlx5e_dma_map_type {
294 MLX5E_DMA_MAP_SINGLE,
298 struct mlx5e_sq_dma {
301 enum mlx5e_dma_map_type type;
305 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
306 MLX5E_SQ_STATE_BF_ENABLE,
309 struct mlx5e_ico_wqe_info {
317 /* dirtied @completion */
322 u16 pc ____cacheline_aligned_in_smp;
327 struct mlx5e_sq_stats stats;
331 /* pointers to per packet info: write@xmit, read@completion */
332 struct sk_buff **skb;
333 struct mlx5e_sq_dma *dma_fifo;
334 struct mlx5e_tx_wqe_info *wqe_info;
337 struct mlx5_wq_cyc wq;
339 void __iomem *uar_map;
340 struct netdev_queue *txq;
346 struct mlx5e_tstamp *tstamp;
351 struct mlx5_wq_ctrl wq_ctrl;
353 struct mlx5e_channel *channel;
355 struct mlx5e_ico_wqe_info *ico_wqe_info;
356 } ____cacheline_aligned_in_smp;
358 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
360 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
365 MLX5E_CHANNEL_NAPI_SCHED = 1,
368 struct mlx5e_channel {
371 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
372 struct mlx5e_sq icosq; /* internal control operations */
373 struct napi_struct napi;
375 struct net_device *netdev;
381 struct mlx5e_priv *priv;
386 enum mlx5e_traffic_types {
391 MLX5E_TT_IPV4_IPSEC_AH,
392 MLX5E_TT_IPV6_IPSEC_AH,
393 MLX5E_TT_IPV4_IPSEC_ESP,
394 MLX5E_TT_IPV6_IPSEC_ESP,
399 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
403 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
405 MLX5E_STATE_DESTROYING,
408 struct mlx5e_vxlan_db {
409 spinlock_t lock; /* protect vxlan table */
410 struct radix_tree_root tree;
413 struct mlx5e_l2_rule {
414 u8 addr[ETH_ALEN + 2];
415 struct mlx5_flow_rule *rule;
418 struct mlx5e_flow_table {
420 struct mlx5_flow_table *t;
421 struct mlx5_flow_group **g;
424 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
426 struct mlx5e_tc_table {
427 struct mlx5_flow_table *t;
429 struct rhashtable_params ht_params;
430 struct rhashtable ht;
433 struct mlx5e_vlan_table {
434 struct mlx5e_flow_table ft;
435 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
436 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
437 struct mlx5_flow_rule *untagged_rule;
438 struct mlx5_flow_rule *any_vlan_rule;
439 bool filter_disabled;
442 struct mlx5e_l2_table {
443 struct mlx5e_flow_table ft;
444 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
445 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
446 struct mlx5e_l2_rule broadcast;
447 struct mlx5e_l2_rule allmulti;
448 struct mlx5e_l2_rule promisc;
449 bool broadcast_enabled;
450 bool allmulti_enabled;
451 bool promisc_enabled;
454 /* L3/L4 traffic type classifier */
455 struct mlx5e_ttc_table {
456 struct mlx5e_flow_table ft;
457 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
460 #define ARFS_HASH_SHIFT BITS_PER_BYTE
461 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
463 struct mlx5e_flow_table ft;
464 struct mlx5_flow_rule *default_rule;
465 struct hlist_head rules_hash[ARFS_HASH_SIZE];
476 struct mlx5e_arfs_tables {
477 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
478 /* Protect aRFS rules list */
479 spinlock_t arfs_lock;
480 struct list_head rules;
482 struct workqueue_struct *wq;
487 MLX5E_VLAN_FT_LEVEL = 0,
493 struct mlx5e_flow_steering {
494 struct mlx5_flow_namespace *ns;
495 struct mlx5e_tc_table tc;
496 struct mlx5e_vlan_table vlan;
497 struct mlx5e_l2_table l2;
498 struct mlx5e_ttc_table ttc;
499 struct mlx5e_arfs_tables arfs;
502 struct mlx5e_direct_tir {
513 /* priv data path fields - start */
514 struct mlx5e_sq **txq_to_sq_map;
515 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
516 /* priv data path fields - end */
519 struct mutex state_lock; /* Protects Interface state */
520 struct mlx5_uar cq_uar;
523 struct mlx5_core_mkey mkey;
524 struct mlx5_core_mkey umr_mkey;
525 struct mlx5e_rq drop_rq;
527 struct mlx5e_channel **channel;
528 u32 tisn[MLX5E_MAX_NUM_TC];
530 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
531 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
533 struct mlx5e_flow_steering fs;
534 struct mlx5e_vxlan_db vxlan;
536 struct mlx5e_params params;
537 struct workqueue_struct *wq;
538 struct work_struct update_carrier_work;
539 struct work_struct set_rx_mode_work;
540 struct delayed_work update_stats_work;
542 struct mlx5_core_dev *mdev;
543 struct net_device *netdev;
544 struct mlx5e_stats stats;
545 struct mlx5e_tstamp tstamp;
549 enum mlx5e_link_mode {
550 MLX5E_1000BASE_CX_SGMII = 0,
551 MLX5E_1000BASE_KX = 1,
552 MLX5E_10GBASE_CX4 = 2,
553 MLX5E_10GBASE_KX4 = 3,
554 MLX5E_10GBASE_KR = 4,
555 MLX5E_20GBASE_KR2 = 5,
556 MLX5E_40GBASE_CR4 = 6,
557 MLX5E_40GBASE_KR4 = 7,
558 MLX5E_56GBASE_R4 = 8,
559 MLX5E_10GBASE_CR = 12,
560 MLX5E_10GBASE_SR = 13,
561 MLX5E_10GBASE_ER = 14,
562 MLX5E_40GBASE_SR4 = 15,
563 MLX5E_40GBASE_LR4 = 16,
564 MLX5E_100GBASE_CR4 = 20,
565 MLX5E_100GBASE_SR4 = 21,
566 MLX5E_100GBASE_KR4 = 22,
567 MLX5E_100GBASE_LR4 = 23,
568 MLX5E_100BASE_TX = 24,
569 MLX5E_1000BASE_T = 25,
570 MLX5E_10GBASE_T = 26,
571 MLX5E_25GBASE_CR = 27,
572 MLX5E_25GBASE_KR = 28,
573 MLX5E_25GBASE_SR = 29,
574 MLX5E_50GBASE_CR2 = 30,
575 MLX5E_50GBASE_KR2 = 31,
576 MLX5E_LINK_MODES_NUMBER,
579 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
581 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
582 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
583 void *accel_priv, select_queue_fallback_t fallback);
584 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
586 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
587 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
588 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
589 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
590 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
592 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
593 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
594 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
595 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
596 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
597 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
598 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
599 struct mlx5_cqe64 *cqe,
601 struct mlx5e_mpw_info *wi,
602 struct sk_buff *skb);
603 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
604 struct mlx5_cqe64 *cqe,
606 struct mlx5e_mpw_info *wi,
607 struct sk_buff *skb);
608 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
609 struct mlx5e_mpw_info *wi);
610 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
611 struct mlx5e_mpw_info *wi);
612 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
614 void mlx5e_update_stats(struct mlx5e_priv *priv);
616 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
617 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
618 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
619 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
620 void mlx5e_set_rx_mode_work(struct work_struct *work);
622 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
623 struct skb_shared_hwtstamps *hwts);
624 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
625 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
626 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
627 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
628 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
630 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
632 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
634 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
635 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
637 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
639 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
640 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
642 int mlx5e_open_locked(struct net_device *netdev);
643 int mlx5e_close_locked(struct net_device *netdev);
644 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
645 u32 *indirection_rqt, int len,
648 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
649 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
651 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
653 /* ensure wqe is visible to device before updating doorbell record */
656 *sq->wq.db = cpu_to_be32(sq->pc);
658 /* ensure doorbell record is visible to device before ringing the
663 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
665 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
666 /* flush the write-combining mapped buffer */
669 sq->bf_offset ^= sq->bf_buf_size;
672 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
674 struct mlx5_core_cq *mcq;
677 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
680 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
682 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
683 MLX5E_MAX_NUM_CHANNELS);
686 static inline int mlx5e_get_mtt_octw(int npages)
688 return ALIGN(npages, 8) / 2;
691 extern const struct ethtool_ops mlx5e_ethtool_ops;
692 #ifdef CONFIG_MLX5_CORE_EN_DCB
693 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
694 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
697 #ifndef CONFIG_RFS_ACCEL
698 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
703 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
705 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
710 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
715 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
716 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
717 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
718 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
719 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
720 u16 rxq_index, u32 flow_id);
723 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
725 #endif /* __MLX5_EN_H__ */