2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
50 #define MLX5E_MAX_NUM_TC 8
52 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
53 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
54 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
56 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
57 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
64 #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */
65 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
66 #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
67 #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
68 #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\
69 MLX5_MPWRQ_LOG_STRIDE_SIZE)
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_TX_CQ_POLL_BUDGET 128
92 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
93 #define MLX5E_SQ_BF_BUDGET 16
95 #define MLX5E_NUM_MAIN_GROUPS 9
97 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
100 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
101 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
109 static inline int mlx5_min_log_rq_size(int wq_type)
112 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
113 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
115 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
119 static inline int mlx5_max_log_rq_size(int wq_type)
122 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
123 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
125 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
129 struct mlx5e_tx_wqe {
130 struct mlx5_wqe_ctrl_seg ctrl;
131 struct mlx5_wqe_eth_seg eth;
134 struct mlx5e_rx_wqe {
135 struct mlx5_wqe_srq_next_seg next;
136 struct mlx5_wqe_data_seg data;
139 struct mlx5e_umr_wqe {
140 struct mlx5_wqe_ctrl_seg ctrl;
141 struct mlx5_wqe_umr_ctrl_seg uctrl;
142 struct mlx5_mkey_seg mkc;
143 struct mlx5_wqe_data_seg data;
146 #ifdef CONFIG_MLX5_CORE_EN_DCB
147 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
148 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
151 static const char vport_strings[][ETH_GSTRING_LEN] = {
152 /* vport statistics */
161 "rx_unicast_packets",
163 "tx_unicast_packets",
165 "rx_multicast_packets",
166 "rx_multicast_bytes",
167 "tx_multicast_packets",
168 "tx_multicast_bytes",
169 "rx_broadcast_packets",
170 "rx_broadcast_bytes",
171 "tx_broadcast_packets",
172 "tx_broadcast_bytes",
194 struct mlx5e_vport_stats {
200 u64 rx_error_packets;
202 u64 tx_error_packets;
204 u64 rx_unicast_packets;
205 u64 rx_unicast_bytes;
206 u64 tx_unicast_packets;
207 u64 tx_unicast_bytes;
208 u64 rx_multicast_packets;
209 u64 rx_multicast_bytes;
210 u64 tx_multicast_packets;
211 u64 tx_multicast_bytes;
212 u64 rx_broadcast_packets;
213 u64 rx_broadcast_bytes;
214 u64 tx_broadcast_packets;
215 u64 tx_broadcast_bytes;
220 u64 tso_inner_packets;
229 u64 tx_queue_stopped;
231 u64 tx_queue_dropped;
236 #define NUM_VPORT_COUNTERS 37
239 static const char pport_strings[][ETH_GSTRING_LEN] = {
240 /* IEEE802.3 counters */
251 "in_range_len_errors",
261 /* RFC2863 counters */
273 "out_multicast_pkts",
274 "out_broadcast_pkts",
276 /* RFC2819 counters */
297 "p8192to10239octets",
300 #define NUM_IEEE_802_3_COUNTERS 19
301 #define NUM_RFC_2863_COUNTERS 13
302 #define NUM_RFC_2819_COUNTERS 21
303 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
304 NUM_RFC_2863_COUNTERS + \
305 NUM_RFC_2819_COUNTERS)
307 struct mlx5e_pport_stats {
308 __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
309 __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
310 __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
313 static const char qcounter_stats_strings[][ETH_GSTRING_LEN] = {
317 struct mlx5e_qcounter_stats {
318 u32 rx_out_of_buffer;
319 #define NUM_Q_COUNTERS 1
322 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
334 struct mlx5e_rq_stats {
344 #define NUM_RQ_STATS 9
347 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
354 "csum_offload_inner",
362 struct mlx5e_sq_stats {
363 /* commonly accessed in data path */
368 u64 tso_inner_packets;
370 u64 csum_offload_inner;
372 /* less likely accessed in data path */
373 u64 csum_offload_none;
377 #define NUM_SQ_STATS 12
381 struct mlx5e_vport_stats vport;
382 struct mlx5e_pport_stats pport;
383 struct mlx5e_qcounter_stats qcnt;
386 struct mlx5e_params {
392 u16 rx_cq_moderation_usec;
393 u16 rx_cq_moderation_pkts;
394 u16 tx_cq_moderation_usec;
395 u16 tx_cq_moderation_pkts;
401 u8 toeplitz_hash_key[40];
402 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
403 #ifdef CONFIG_MLX5_CORE_EN_DCB
408 struct mlx5e_tstamp {
410 struct cyclecounter cycles;
411 struct timecounter clock;
412 struct hwtstamp_config hwtstamp_config;
414 unsigned long overflow_period;
415 struct delayed_work overflow_work;
416 struct mlx5_core_dev *mdev;
417 struct ptp_clock *ptp;
418 struct ptp_clock_info ptp_info;
422 MLX5E_RQ_STATE_POST_WQES_ENABLE,
423 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
427 /* data path - accessed per cqe */
430 /* data path - accessed per napi poll */
431 struct napi_struct *napi;
432 struct mlx5_core_cq mcq;
433 struct mlx5e_channel *channel;
434 struct mlx5e_priv *priv;
437 struct mlx5_wq_ctrl wq_ctrl;
438 } ____cacheline_aligned_in_smp;
441 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
442 struct mlx5_cqe64 *cqe);
443 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
446 struct mlx5e_dma_info {
453 struct mlx5_wq_ll wq;
455 struct sk_buff **skb;
456 struct mlx5e_mpw_info *wqe_info;
461 struct net_device *netdev;
462 struct mlx5e_tstamp *tstamp;
463 struct mlx5e_rq_stats stats;
465 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
466 mlx5e_fp_alloc_wqe alloc_wqe;
472 struct mlx5_wq_ctrl wq_ctrl;
475 struct mlx5e_channel *channel;
476 struct mlx5e_priv *priv;
477 } ____cacheline_aligned_in_smp;
479 struct mlx5e_umr_dma_info {
481 __be64 *mtt_no_align;
483 struct mlx5e_dma_info *dma_info;
486 struct mlx5e_mpw_info {
488 struct mlx5e_dma_info dma_info;
489 struct mlx5e_umr_dma_info umr;
491 u16 consumed_strides;
492 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
494 void (*dma_pre_sync)(struct device *pdev,
495 struct mlx5e_mpw_info *wi,
496 u32 wqe_offset, u32 len);
497 void (*add_skb_frag)(struct device *pdev,
499 struct mlx5e_mpw_info *wi,
500 u32 page_idx, u32 frag_offset, u32 len);
501 void (*copy_skb_header)(struct device *pdev,
503 struct mlx5e_mpw_info *wi,
504 u32 page_idx, u32 offset,
506 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
509 struct mlx5e_tx_wqe_info {
515 enum mlx5e_dma_map_type {
516 MLX5E_DMA_MAP_SINGLE,
520 struct mlx5e_sq_dma {
523 enum mlx5e_dma_map_type type;
527 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
528 MLX5E_SQ_STATE_BF_ENABLE,
531 struct mlx5e_ico_wqe_info {
539 /* dirtied @completion */
544 u16 pc ____cacheline_aligned_in_smp;
549 struct mlx5e_sq_stats stats;
553 /* pointers to per packet info: write@xmit, read@completion */
554 struct sk_buff **skb;
555 struct mlx5e_sq_dma *dma_fifo;
556 struct mlx5e_tx_wqe_info *wqe_info;
559 struct mlx5_wq_cyc wq;
561 void __iomem *uar_map;
562 struct netdev_queue *txq;
568 struct mlx5e_tstamp *tstamp;
573 struct mlx5_wq_ctrl wq_ctrl;
575 struct mlx5e_channel *channel;
577 struct mlx5e_ico_wqe_info *ico_wqe_info;
578 } ____cacheline_aligned_in_smp;
580 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
582 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
587 MLX5E_CHANNEL_NAPI_SCHED = 1,
590 struct mlx5e_channel {
593 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
594 struct mlx5e_sq icosq; /* internal control operations */
595 struct napi_struct napi;
597 struct net_device *netdev;
603 struct mlx5e_priv *priv;
608 enum mlx5e_traffic_types {
613 MLX5E_TT_IPV4_IPSEC_AH,
614 MLX5E_TT_IPV6_IPSEC_AH,
615 MLX5E_TT_IPV4_IPSEC_ESP,
616 MLX5E_TT_IPV6_IPSEC_ESP,
623 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
626 MLX5E_INDIRECTION_RQT,
631 struct mlx5e_eth_addr_info {
632 u8 addr[ETH_ALEN + 2];
634 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
637 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
639 struct mlx5e_eth_addr_db {
640 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
641 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
642 struct mlx5e_eth_addr_info broadcast;
643 struct mlx5e_eth_addr_info allmulti;
644 struct mlx5e_eth_addr_info promisc;
645 bool broadcast_enabled;
646 bool allmulti_enabled;
647 bool promisc_enabled;
651 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
653 MLX5E_STATE_DESTROYING,
656 struct mlx5e_vlan_db {
657 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
658 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
659 struct mlx5_flow_rule *untagged_rule;
660 struct mlx5_flow_rule *any_vlan_rule;
661 bool filter_disabled;
664 struct mlx5e_vxlan_db {
665 spinlock_t lock; /* protect vxlan table */
666 struct radix_tree_root tree;
669 struct mlx5e_flow_table {
671 struct mlx5_flow_table *t;
672 struct mlx5_flow_group **g;
675 struct mlx5e_tc_flow_table {
676 struct mlx5_flow_table *t;
678 struct rhashtable_params ht_params;
679 struct rhashtable ht;
682 struct mlx5e_flow_tables {
683 struct mlx5_flow_namespace *ns;
684 struct mlx5e_tc_flow_table tc;
685 struct mlx5e_flow_table vlan;
686 struct mlx5e_flow_table main;
690 /* priv data path fields - start */
691 struct mlx5e_sq **txq_to_sq_map;
692 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
693 /* priv data path fields - end */
696 struct mutex state_lock; /* Protects Interface state */
697 struct mlx5_uar cq_uar;
700 struct mlx5_core_mkey mkey;
701 struct mlx5_core_mkey umr_mkey;
702 struct mlx5e_rq drop_rq;
704 struct mlx5e_channel **channel;
705 u32 tisn[MLX5E_MAX_NUM_TC];
706 u32 rqtn[MLX5E_NUM_RQT];
707 u32 tirn[MLX5E_NUM_TT];
709 struct mlx5e_flow_tables fts;
710 struct mlx5e_eth_addr_db eth_addr;
711 struct mlx5e_vlan_db vlan;
712 struct mlx5e_vxlan_db vxlan;
714 struct mlx5e_params params;
715 struct work_struct update_carrier_work;
716 struct work_struct set_rx_mode_work;
717 struct delayed_work update_stats_work;
719 struct mlx5_core_dev *mdev;
720 struct net_device *netdev;
721 struct mlx5e_stats stats;
722 struct mlx5e_tstamp tstamp;
726 enum mlx5e_link_mode {
727 MLX5E_1000BASE_CX_SGMII = 0,
728 MLX5E_1000BASE_KX = 1,
729 MLX5E_10GBASE_CX4 = 2,
730 MLX5E_10GBASE_KX4 = 3,
731 MLX5E_10GBASE_KR = 4,
732 MLX5E_20GBASE_KR2 = 5,
733 MLX5E_40GBASE_CR4 = 6,
734 MLX5E_40GBASE_KR4 = 7,
735 MLX5E_56GBASE_R4 = 8,
736 MLX5E_10GBASE_CR = 12,
737 MLX5E_10GBASE_SR = 13,
738 MLX5E_10GBASE_ER = 14,
739 MLX5E_40GBASE_SR4 = 15,
740 MLX5E_40GBASE_LR4 = 16,
741 MLX5E_100GBASE_CR4 = 20,
742 MLX5E_100GBASE_SR4 = 21,
743 MLX5E_100GBASE_KR4 = 22,
744 MLX5E_100GBASE_LR4 = 23,
745 MLX5E_100BASE_TX = 24,
746 MLX5E_100BASE_T = 25,
747 MLX5E_10GBASE_T = 26,
748 MLX5E_25GBASE_CR = 27,
749 MLX5E_25GBASE_KR = 28,
750 MLX5E_25GBASE_SR = 29,
751 MLX5E_50GBASE_CR2 = 30,
752 MLX5E_50GBASE_KR2 = 31,
753 MLX5E_LINK_MODES_NUMBER,
756 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
758 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
759 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
760 void *accel_priv, select_queue_fallback_t fallback);
761 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
763 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
764 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
765 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
766 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
767 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
769 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
770 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
771 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
772 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
773 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
774 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
775 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
776 struct mlx5_cqe64 *cqe,
778 struct mlx5e_mpw_info *wi,
779 struct sk_buff *skb);
780 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
781 struct mlx5_cqe64 *cqe,
783 struct mlx5e_mpw_info *wi,
784 struct sk_buff *skb);
785 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
786 struct mlx5e_mpw_info *wi);
787 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
788 struct mlx5e_mpw_info *wi);
789 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
791 void mlx5e_update_stats(struct mlx5e_priv *priv);
793 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
794 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
795 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
796 void mlx5e_set_rx_mode_work(struct work_struct *work);
798 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
799 struct skb_shared_hwtstamps *hwts);
800 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
801 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
802 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
803 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
805 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
807 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
809 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
810 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
812 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
813 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
815 int mlx5e_open_locked(struct net_device *netdev);
816 int mlx5e_close_locked(struct net_device *netdev);
817 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
818 u32 *indirection_rqt, int len,
821 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
822 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
824 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
826 /* ensure wqe is visible to device before updating doorbell record */
829 *sq->wq.db = cpu_to_be32(sq->pc);
831 /* ensure doorbell record is visible to device before ringing the
836 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
838 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
839 /* flush the write-combining mapped buffer */
842 sq->bf_offset ^= sq->bf_buf_size;
845 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
847 struct mlx5_core_cq *mcq;
850 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
853 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
855 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
856 MLX5E_MAX_NUM_CHANNELS);
859 static inline int mlx5e_get_mtt_octw(int npages)
861 return ALIGN(npages, 8) / 2;
864 extern const struct ethtool_ops mlx5e_ethtool_ops;
865 #ifdef CONFIG_MLX5_CORE_EN_DCB
866 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
867 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
870 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
872 #endif /* __MLX5_EN_H__ */