2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
49 #include "mlx5_core.h"
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
54 #define MLX5E_MAX_NUM_TC 8
56 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
57 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
70 #define MLX5_MPWRQ_LOG_WQE_SZ 17
71 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
72 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
73 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
74 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
75 MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
77 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
78 #define MLX5_UMR_ALIGN (2048)
79 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
81 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
87 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
88 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
90 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
91 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
92 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
93 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
94 #define MLX5E_TX_CQ_POLL_BUDGET 128
95 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
96 #define MLX5E_SQ_BF_BUDGET 16
98 #define MLX5E_NUM_MAIN_GROUPS 9
100 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
103 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
107 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
112 static inline int mlx5_min_log_rq_size(int wq_type)
115 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
118 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
122 static inline int mlx5_max_log_rq_size(int wq_type)
125 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
128 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
133 MLX5E_INLINE_MODE_L2,
134 MLX5E_INLINE_MODE_VPORT_CONTEXT,
135 MLX5_INLINE_MODE_NOT_REQUIRED,
138 struct mlx5e_tx_wqe {
139 struct mlx5_wqe_ctrl_seg ctrl;
140 struct mlx5_wqe_eth_seg eth;
143 struct mlx5e_rx_wqe {
144 struct mlx5_wqe_srq_next_seg next;
145 struct mlx5_wqe_data_seg data;
148 struct mlx5e_umr_wqe {
149 struct mlx5_wqe_ctrl_seg ctrl;
150 struct mlx5_wqe_umr_ctrl_seg uctrl;
151 struct mlx5_mkey_seg mkc;
152 struct mlx5_wqe_data_seg data;
155 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
159 enum mlx5e_priv_flag {
160 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
163 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
166 priv->pflags |= pflag; \
168 priv->pflags &= ~pflag; \
171 #ifdef CONFIG_MLX5_CORE_EN_DCB
172 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
175 struct mlx5e_cq_moder {
180 struct mlx5e_params {
183 u8 mpwqe_log_stride_sz;
184 u8 mpwqe_log_num_strides;
188 u8 rx_cq_period_mode;
189 bool rx_cqe_compress_admin;
190 bool rx_cqe_compress;
191 struct mlx5e_cq_moder rx_cq_moderation;
192 struct mlx5e_cq_moder tx_cq_moderation;
197 u8 tx_min_inline_mode;
199 u8 toeplitz_hash_key[40];
200 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
201 bool vlan_strip_disable;
202 #ifdef CONFIG_MLX5_CORE_EN_DCB
208 struct mlx5e_tstamp {
210 struct cyclecounter cycles;
211 struct timecounter clock;
212 struct hwtstamp_config hwtstamp_config;
214 unsigned long overflow_period;
215 struct delayed_work overflow_work;
216 struct mlx5_core_dev *mdev;
217 struct ptp_clock *ptp;
218 struct ptp_clock_info ptp_info;
222 MLX5E_RQ_STATE_POST_WQES_ENABLE,
223 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
224 MLX5E_RQ_STATE_FLUSH_TIMEOUT,
229 /* data path - accessed per cqe */
232 /* data path - accessed per napi poll */
234 struct napi_struct *napi;
235 struct mlx5_core_cq mcq;
236 struct mlx5e_channel *channel;
237 struct mlx5e_priv *priv;
239 /* cqe decompression */
240 struct mlx5_cqe64 title;
241 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
244 u16 decmprs_wqe_counter;
247 struct mlx5_wq_ctrl wq_ctrl;
248 } ____cacheline_aligned_in_smp;
251 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
252 struct mlx5_cqe64 *cqe);
253 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
256 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
258 struct mlx5e_dma_info {
263 struct mlx5e_rx_am_stats {
264 int ppms; /* packets per msec */
265 int epms; /* events per msec */
268 struct mlx5e_rx_am_sample {
270 unsigned int pkt_ctr;
274 struct mlx5e_rx_am { /* Adaptive Moderation */
276 struct mlx5e_rx_am_stats prev_stats;
277 struct mlx5e_rx_am_sample start_sample;
278 struct work_struct work;
289 struct mlx5_wq_ll wq;
291 struct sk_buff **skb;
292 struct mlx5e_mpw_info *wqe_info;
297 struct net_device *netdev;
298 struct mlx5e_tstamp *tstamp;
299 struct mlx5e_rq_stats stats;
301 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
302 mlx5e_fp_alloc_wqe alloc_wqe;
303 mlx5e_fp_dealloc_wqe dealloc_wqe;
308 struct mlx5e_rx_am am; /* Adaptive Moderation */
311 struct mlx5_wq_ctrl wq_ctrl;
314 u32 mpwqe_num_strides;
316 struct mlx5e_channel *channel;
317 struct mlx5e_priv *priv;
318 } ____cacheline_aligned_in_smp;
320 struct mlx5e_umr_dma_info {
322 __be64 *mtt_no_align;
324 struct mlx5e_dma_info *dma_info;
327 struct mlx5e_mpw_info {
329 struct mlx5e_dma_info dma_info;
330 struct mlx5e_umr_dma_info umr;
332 u16 consumed_strides;
333 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
335 void (*dma_pre_sync)(struct device *pdev,
336 struct mlx5e_mpw_info *wi,
337 u32 wqe_offset, u32 len);
338 void (*add_skb_frag)(struct mlx5e_rq *rq,
340 struct mlx5e_mpw_info *wi,
341 u32 page_idx, u32 frag_offset, u32 len);
342 void (*copy_skb_header)(struct device *pdev,
344 struct mlx5e_mpw_info *wi,
345 u32 page_idx, u32 offset,
347 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
350 struct mlx5e_tx_wqe_info {
356 enum mlx5e_dma_map_type {
357 MLX5E_DMA_MAP_SINGLE,
361 struct mlx5e_sq_dma {
364 enum mlx5e_dma_map_type type;
368 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
369 MLX5E_SQ_STATE_BF_ENABLE,
370 MLX5E_SQ_STATE_TX_TIMEOUT,
373 struct mlx5e_ico_wqe_info {
381 /* dirtied @completion */
386 u16 pc ____cacheline_aligned_in_smp;
391 struct mlx5e_sq_stats stats;
395 /* pointers to per packet info: write@xmit, read@completion */
396 struct sk_buff **skb;
397 struct mlx5e_sq_dma *dma_fifo;
398 struct mlx5e_tx_wqe_info *wqe_info;
401 struct mlx5_wq_cyc wq;
403 void __iomem *uar_map;
404 struct netdev_queue *txq;
411 struct mlx5e_tstamp *tstamp;
416 struct mlx5_wq_ctrl wq_ctrl;
418 struct mlx5e_channel *channel;
420 struct mlx5e_ico_wqe_info *ico_wqe_info;
422 } ____cacheline_aligned_in_smp;
424 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
426 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
431 MLX5E_CHANNEL_NAPI_SCHED = 1,
434 struct mlx5e_channel {
437 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
438 struct mlx5e_sq icosq; /* internal control operations */
439 struct napi_struct napi;
441 struct net_device *netdev;
447 struct mlx5e_priv *priv;
452 enum mlx5e_traffic_types {
457 MLX5E_TT_IPV4_IPSEC_AH,
458 MLX5E_TT_IPV6_IPSEC_AH,
459 MLX5E_TT_IPV4_IPSEC_ESP,
460 MLX5E_TT_IPV6_IPSEC_ESP,
465 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
469 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
471 MLX5E_STATE_DESTROYING,
474 struct mlx5e_vxlan_db {
475 spinlock_t lock; /* protect vxlan table */
476 struct radix_tree_root tree;
479 struct mlx5e_l2_rule {
480 u8 addr[ETH_ALEN + 2];
481 struct mlx5_flow_rule *rule;
484 struct mlx5e_flow_table {
486 struct mlx5_flow_table *t;
487 struct mlx5_flow_group **g;
490 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
492 struct mlx5e_tc_table {
493 struct mlx5_flow_table *t;
495 struct rhashtable_params ht_params;
496 struct rhashtable ht;
499 struct mlx5e_vlan_table {
500 struct mlx5e_flow_table ft;
501 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
502 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
503 struct mlx5_flow_rule *untagged_rule;
504 struct mlx5_flow_rule *any_vlan_rule;
505 bool filter_disabled;
508 struct mlx5e_l2_table {
509 struct mlx5e_flow_table ft;
510 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
511 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
512 struct mlx5e_l2_rule broadcast;
513 struct mlx5e_l2_rule allmulti;
514 struct mlx5e_l2_rule promisc;
515 bool broadcast_enabled;
516 bool allmulti_enabled;
517 bool promisc_enabled;
520 /* L3/L4 traffic type classifier */
521 struct mlx5e_ttc_table {
522 struct mlx5e_flow_table ft;
523 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
526 #define ARFS_HASH_SHIFT BITS_PER_BYTE
527 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
529 struct mlx5e_flow_table ft;
530 struct mlx5_flow_rule *default_rule;
531 struct hlist_head rules_hash[ARFS_HASH_SIZE];
542 struct mlx5e_arfs_tables {
543 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
544 /* Protect aRFS rules list */
545 spinlock_t arfs_lock;
546 struct list_head rules;
548 struct workqueue_struct *wq;
553 MLX5E_VLAN_FT_LEVEL = 0,
559 struct mlx5e_ethtool_table {
560 struct mlx5_flow_table *ft;
564 #define ETHTOOL_NUM_L3_L4_FTS 7
565 #define ETHTOOL_NUM_L2_FTS 4
567 struct mlx5e_ethtool_steering {
568 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
569 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
570 struct list_head rules;
574 struct mlx5e_flow_steering {
575 struct mlx5_flow_namespace *ns;
576 struct mlx5e_ethtool_steering ethtool;
577 struct mlx5e_tc_table tc;
578 struct mlx5e_vlan_table vlan;
579 struct mlx5e_l2_table l2;
580 struct mlx5e_ttc_table ttc;
581 struct mlx5e_arfs_tables arfs;
591 struct mlx5e_rqt rqt;
592 struct list_head list;
600 struct mlx5e_profile {
601 void (*init)(struct mlx5_core_dev *mdev,
602 struct net_device *netdev,
603 const struct mlx5e_profile *profile, void *ppriv);
604 void (*cleanup)(struct mlx5e_priv *priv);
605 int (*init_rx)(struct mlx5e_priv *priv);
606 void (*cleanup_rx)(struct mlx5e_priv *priv);
607 int (*init_tx)(struct mlx5e_priv *priv);
608 void (*cleanup_tx)(struct mlx5e_priv *priv);
609 void (*enable)(struct mlx5e_priv *priv);
610 void (*disable)(struct mlx5e_priv *priv);
611 void (*update_stats)(struct mlx5e_priv *priv);
612 int (*max_nch)(struct mlx5_core_dev *mdev);
617 /* priv data path fields - start */
618 struct mlx5e_sq **txq_to_sq_map;
619 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
620 /* priv data path fields - end */
623 struct mutex state_lock; /* Protects Interface state */
624 struct mlx5_core_mkey umr_mkey;
625 struct mlx5e_rq drop_rq;
627 struct mlx5e_channel **channel;
628 u32 tisn[MLX5E_MAX_NUM_TC];
629 struct mlx5e_rqt indir_rqt;
630 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
631 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
632 u32 tx_rates[MLX5E_MAX_NUM_SQS];
634 struct mlx5e_flow_steering fs;
635 struct mlx5e_vxlan_db vxlan;
637 struct mlx5e_params params;
638 struct workqueue_struct *wq;
639 struct work_struct update_carrier_work;
640 struct work_struct set_rx_mode_work;
641 struct work_struct tx_timeout_work;
642 struct delayed_work update_stats_work;
645 struct mlx5_core_dev *mdev;
646 struct net_device *netdev;
647 struct mlx5e_stats stats;
648 struct mlx5e_tstamp tstamp;
650 const struct mlx5e_profile *profile;
654 enum mlx5e_link_mode {
655 MLX5E_1000BASE_CX_SGMII = 0,
656 MLX5E_1000BASE_KX = 1,
657 MLX5E_10GBASE_CX4 = 2,
658 MLX5E_10GBASE_KX4 = 3,
659 MLX5E_10GBASE_KR = 4,
660 MLX5E_20GBASE_KR2 = 5,
661 MLX5E_40GBASE_CR4 = 6,
662 MLX5E_40GBASE_KR4 = 7,
663 MLX5E_56GBASE_R4 = 8,
664 MLX5E_10GBASE_CR = 12,
665 MLX5E_10GBASE_SR = 13,
666 MLX5E_10GBASE_ER = 14,
667 MLX5E_40GBASE_SR4 = 15,
668 MLX5E_40GBASE_LR4 = 16,
669 MLX5E_50GBASE_SR2 = 18,
670 MLX5E_100GBASE_CR4 = 20,
671 MLX5E_100GBASE_SR4 = 21,
672 MLX5E_100GBASE_KR4 = 22,
673 MLX5E_100GBASE_LR4 = 23,
674 MLX5E_100BASE_TX = 24,
675 MLX5E_1000BASE_T = 25,
676 MLX5E_10GBASE_T = 26,
677 MLX5E_25GBASE_CR = 27,
678 MLX5E_25GBASE_KR = 28,
679 MLX5E_25GBASE_SR = 29,
680 MLX5E_50GBASE_CR2 = 30,
681 MLX5E_50GBASE_KR2 = 31,
682 MLX5E_LINK_MODES_NUMBER,
685 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
688 void mlx5e_build_ptys2ethtool_map(void);
690 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
691 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
692 void *accel_priv, select_queue_fallback_t fallback);
693 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
695 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
696 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
697 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
698 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
699 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
700 void mlx5e_free_tx_descs(struct mlx5e_sq *sq);
701 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
703 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
704 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
705 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
706 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
707 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
708 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
709 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
710 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
711 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
712 struct mlx5_cqe64 *cqe,
714 struct mlx5e_mpw_info *wi,
715 struct sk_buff *skb);
716 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
717 struct mlx5_cqe64 *cqe,
719 struct mlx5e_mpw_info *wi,
720 struct sk_buff *skb);
721 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
722 struct mlx5e_mpw_info *wi);
723 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
724 struct mlx5e_mpw_info *wi);
725 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
727 void mlx5e_rx_am(struct mlx5e_rq *rq);
728 void mlx5e_rx_am_work(struct work_struct *work);
729 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
731 void mlx5e_update_stats(struct mlx5e_priv *priv);
733 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
734 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
735 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
736 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
737 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
739 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
740 struct ethtool_rxnfc *info, u32 *rule_locs);
741 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
742 struct ethtool_rx_flow_spec *fs);
743 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
745 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
746 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
747 void mlx5e_set_rx_mode_work(struct work_struct *work);
749 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
750 struct skb_shared_hwtstamps *hwts);
751 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
752 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
753 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
754 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
755 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
757 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
759 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
761 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
762 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
764 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
766 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
767 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
769 int mlx5e_open_locked(struct net_device *netdev);
770 int mlx5e_close_locked(struct net_device *netdev);
771 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
772 u32 *indirection_rqt, int len,
774 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
776 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
779 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
780 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
782 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
784 /* ensure wqe is visible to device before updating doorbell record */
787 *sq->wq.db = cpu_to_be32(sq->pc);
789 /* ensure doorbell record is visible to device before ringing the
794 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
796 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
797 /* flush the write-combining mapped buffer */
800 sq->bf_offset ^= sq->bf_buf_size;
803 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
805 struct mlx5_core_cq *mcq;
808 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
811 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
813 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
814 MLX5E_MAX_NUM_CHANNELS);
817 static inline int mlx5e_get_mtt_octw(int npages)
819 return ALIGN(npages, 8) / 2;
822 extern const struct ethtool_ops mlx5e_ethtool_ops;
823 #ifdef CONFIG_MLX5_CORE_EN_DCB
824 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
825 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
828 #ifndef CONFIG_RFS_ACCEL
829 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
834 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
836 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
841 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
846 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
847 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
848 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
849 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
850 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
851 u16 rxq_index, u32 flow_id);
854 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
855 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
856 struct mlx5e_tir *tir, u32 *in, int inlen);
857 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
858 struct mlx5e_tir *tir);
859 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
860 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
861 int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev);
863 struct mlx5_eswitch_rep;
864 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
865 struct mlx5_eswitch_rep *rep);
866 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
867 struct mlx5_eswitch_rep *rep);
868 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
869 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
870 struct mlx5_eswitch_rep *rep);
871 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
872 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
873 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
875 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
876 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
877 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
878 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
879 int mlx5e_create_tises(struct mlx5e_priv *priv);
880 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
881 int mlx5e_close(struct net_device *netdev);
882 int mlx5e_open(struct net_device *netdev);
883 void mlx5e_update_stats_work(struct work_struct *work);
884 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
885 const struct mlx5e_profile *profile, void *ppriv);
886 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
887 struct rtnl_link_stats64 *
888 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
890 #endif /* __MLX5_EN_H__ */