drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44         u16                        max_inline;
  45 };
  46
  47 struct mlx5e_cq_param {
  48         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        eq_ix;
  51 };
  52
  53 struct mlx5e_channel_param {
  54         struct mlx5e_rq_param      rq;
  55         struct mlx5e_sq_param      sq;
  56         struct mlx5e_cq_param      rx_cq;
  57         struct mlx5e_cq_param      tx_cq;
  58 };
  59
  60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  61 {
  62         struct mlx5_core_dev *mdev = priv->mdev;
  63         u8 port_state;
  64
  65         port_state = mlx5_query_vport_state(mdev,
  66                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  67
  68         if (port_state == VPORT_STATE_UP)
  69                 netif_carrier_on(priv->netdev);
  70         else
  71                 netif_carrier_off(priv->netdev);
  72 }
  73
  74 static void mlx5e_update_carrier_work(struct work_struct *work)
  75 {
  76         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  77                                                update_carrier_work);
  78
  79         mutex_lock(&priv->state_lock);
  80         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  81                 mlx5e_update_carrier(priv);
  82         mutex_unlock(&priv->state_lock);
  83 }
  84
  85 void mlx5e_update_stats(struct mlx5e_priv *priv)
  86 {
  87         struct mlx5_core_dev *mdev = priv->mdev;
  88         struct mlx5e_vport_stats *s = &priv->stats.vport;
  89         struct mlx5e_rq_stats *rq_stats;
  90         struct mlx5e_sq_stats *sq_stats;
  91         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  92         u32 *out;
  93         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  94         u64 tx_offload_none;
  95         int i, j;
  96
  97         out = mlx5_vzalloc(outlen);
  98         if (!out)
  99                 return;
 100
 101         /* Collect firts the SW counters and then HW for consistency */
 102         s->tso_packets          = 0;
 103         s->tso_bytes            = 0;
 104         s->tx_queue_stopped     = 0;
 105         s->tx_queue_wake        = 0;
 106         s->tx_queue_dropped     = 0;
 107         tx_offload_none         = 0;
 108         s->lro_packets          = 0;
 109         s->lro_bytes            = 0;
 110         s->rx_csum_none         = 0;
 111         s->rx_wqe_err           = 0;
 112         for (i = 0; i < priv->params.num_channels; i++) {
 113                 rq_stats = &priv->channel[i]->rq.stats;
 114
 115                 s->lro_packets  += rq_stats->lro_packets;
 116                 s->lro_bytes    += rq_stats->lro_bytes;
 117                 s->rx_csum_none += rq_stats->csum_none;
 118                 s->rx_wqe_err   += rq_stats->wqe_err;
 119
 120                 for (j = 0; j < priv->num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tso_packets          += sq_stats->tso_packets;
 124                         s->tso_bytes            += sq_stats->tso_bytes;
 125                         s->tx_queue_stopped     += sq_stats->stopped;
 126                         s->tx_queue_wake        += sq_stats->wake;
 127                         s->tx_queue_dropped     += sq_stats->dropped;
 128                         tx_offload_none         += sq_stats->csum_offload_none;
 129                 }
 130         }
 131
 132         /* HW counters */
 133         memset(in, 0, sizeof(in));
 134
 135         MLX5_SET(query_vport_counter_in, in, opcode,
 136                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 137         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 138         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 139
 140         memset(out, 0, outlen);
 141
 142         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 143                 goto free_out;
 144
 145 #define MLX5_GET_CTR(p, x) \
 146         MLX5_GET64(query_vport_counter_out, p, x)
 147
 148         s->rx_error_packets     =
 149                 MLX5_GET_CTR(out, received_errors.packets);
 150         s->rx_error_bytes       =
 151                 MLX5_GET_CTR(out, received_errors.octets);
 152         s->tx_error_packets     =
 153                 MLX5_GET_CTR(out, transmit_errors.packets);
 154         s->tx_error_bytes       =
 155                 MLX5_GET_CTR(out, transmit_errors.octets);
 156
 157         s->rx_unicast_packets   =
 158                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 159         s->rx_unicast_bytes     =
 160                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 161         s->tx_unicast_packets   =
 162                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 163         s->tx_unicast_bytes     =
 164                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 165
 166         s->rx_multicast_packets =
 167                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 168         s->rx_multicast_bytes   =
 169                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 170         s->tx_multicast_packets =
 171                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 172         s->tx_multicast_bytes   =
 173                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 174
 175         s->rx_broadcast_packets =
 176                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 177         s->rx_broadcast_bytes   =
 178                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 179         s->tx_broadcast_packets =
 180                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 181         s->tx_broadcast_bytes   =
 182                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 183
 184         s->rx_packets =
 185                 s->rx_unicast_packets +
 186                 s->rx_multicast_packets +
 187                 s->rx_broadcast_packets;
 188         s->rx_bytes =
 189                 s->rx_unicast_bytes +
 190                 s->rx_multicast_bytes +
 191                 s->rx_broadcast_bytes;
 192         s->tx_packets =
 193                 s->tx_unicast_packets +
 194                 s->tx_multicast_packets +
 195                 s->tx_broadcast_packets;
 196         s->tx_bytes =
 197                 s->tx_unicast_bytes +
 198                 s->tx_multicast_bytes +
 199                 s->tx_broadcast_bytes;
 200
 201         /* Update calculated offload counters */
 202         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 203         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 204
 205 free_out:
 206         kvfree(out);
 207 }
 208
 209 static void mlx5e_update_stats_work(struct work_struct *work)
 210 {
 211         struct delayed_work *dwork = to_delayed_work(work);
 212         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 213                                                update_stats_work);
 214         mutex_lock(&priv->state_lock);
 215         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 216                 mlx5e_update_stats(priv);
 217                 schedule_delayed_work(dwork,
 218                                       msecs_to_jiffies(
 219                                               MLX5E_UPDATE_STATS_INTERVAL));
 220         }
 221         mutex_unlock(&priv->state_lock);
 222 }
 223
 224 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 225                                 enum mlx5_dev_event event)
 226 {
 227         switch (event) {
 228         case MLX5_DEV_EVENT_PORT_UP:
 229         case MLX5_DEV_EVENT_PORT_DOWN:
 230                 schedule_work(&priv->update_carrier_work);
 231                 break;
 232
 233         default:
 234                 break;
 235         }
 236 }
 237
 238 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 239                               enum mlx5_dev_event event, unsigned long param)
 240 {
 241         struct mlx5e_priv *priv = vpriv;
 242
 243         spin_lock(&priv->async_events_spinlock);
 244         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 245                 __mlx5e_async_event(priv, event);
 246         spin_unlock(&priv->async_events_spinlock);
 247 }
 248
 249 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 250 {
 251         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 252 }
 253
 254 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 255 {
 256         spin_lock_irq(&priv->async_events_spinlock);
 257         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 258         spin_unlock_irq(&priv->async_events_spinlock);
 259 }
 260
 261 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 262 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 263
 264 static int mlx5e_create_rq(struct mlx5e_channel *c,
 265                            struct mlx5e_rq_param *param,
 266                            struct mlx5e_rq *rq)
 267 {
 268         struct mlx5e_priv *priv = c->priv;
 269         struct mlx5_core_dev *mdev = priv->mdev;
 270         void *rqc = param->rqc;
 271         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 272         int wq_sz;
 273         int err;
 274         int i;
 275
 276         param->wq.db_numa_node = cpu_to_node(c->cpu);
 277
 278         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 279                                 &rq->wq_ctrl);
 280         if (err)
 281                 return err;
 282
 283         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 284
 285         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 286         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 287                                cpu_to_node(c->cpu));
 288         if (!rq->skb) {
 289                 err = -ENOMEM;
 290                 goto err_rq_wq_destroy;
 291         }
 292
 293         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 294                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 295         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 296
 297         for (i = 0; i < wq_sz; i++) {
 298                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 299                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 300
 301                 wqe->data.lkey       = c->mkey_be;
 302                 wqe->data.byte_count =
 303                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 304         }
 305
 306         rq->pdev    = c->pdev;
 307         rq->netdev  = c->netdev;
 308         rq->channel = c;
 309         rq->ix      = c->ix;
 310
 311         return 0;
 312
 313 err_rq_wq_destroy:
 314         mlx5_wq_destroy(&rq->wq_ctrl);
 315
 316         return err;
 317 }
 318
 319 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 320 {
 321         kfree(rq->skb);
 322         mlx5_wq_destroy(&rq->wq_ctrl);
 323 }
 324
 325 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 326 {
 327         struct mlx5e_channel *c = rq->channel;
 328         struct mlx5e_priv *priv = c->priv;
 329         struct mlx5_core_dev *mdev = priv->mdev;
 330
 331         void *in;
 332         void *rqc;
 333         void *wq;
 334         int inlen;
 335         int err;
 336
 337         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 338                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 339         in = mlx5_vzalloc(inlen);
 340         if (!in)
 341                 return -ENOMEM;
 342
 343         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 344         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 345
 346         memcpy(rqc, param->rqc, sizeof(param->rqc));
 347
 348         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
 349         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 350         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 351         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 352                                                 PAGE_SHIFT);
 353         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 354
 355         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 356                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 357
 358         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 359
 360         kvfree(in);
 361
 362         return err;
 363 }
 364
 365 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 366 {
 367         struct mlx5e_channel *c = rq->channel;
 368         struct mlx5e_priv *priv = c->priv;
 369         struct mlx5_core_dev *mdev = priv->mdev;
 370
 371         void *in;
 372         void *rqc;
 373         int inlen;
 374         int err;
 375
 376         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 377         in = mlx5_vzalloc(inlen);
 378         if (!in)
 379                 return -ENOMEM;
 380
 381         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 382
 383         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 384         MLX5_SET(rqc, rqc, state, next_state);
 385
 386         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 387
 388         kvfree(in);
 389
 390         return err;
 391 }
 392
 393 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 394 {
 395         struct mlx5e_channel *c = rq->channel;
 396         struct mlx5e_priv *priv = c->priv;
 397         struct mlx5_core_dev *mdev = priv->mdev;
 398
 399         mlx5_core_destroy_rq(mdev, rq->rqn);
 400 }
 401
 402 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 403 {
 404         struct mlx5e_channel *c = rq->channel;
 405         struct mlx5e_priv *priv = c->priv;
 406         struct mlx5_wq_ll *wq = &rq->wq;
 407         int i;
 408
 409         for (i = 0; i < 1000; i++) {
 410                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 411                         return 0;
 412
 413                 msleep(20);
 414         }
 415
 416         return -ETIMEDOUT;
 417 }
 418
 419 static int mlx5e_open_rq(struct mlx5e_channel *c,
 420                          struct mlx5e_rq_param *param,
 421                          struct mlx5e_rq *rq)
 422 {
 423         int err;
 424
 425         err = mlx5e_create_rq(c, param, rq);
 426         if (err)
 427                 return err;
 428
 429         err = mlx5e_enable_rq(rq, param);
 430         if (err)
 431                 goto err_destroy_rq;
 432
 433         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 434         if (err)
 435                 goto err_disable_rq;
 436
 437         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 438         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 439
 440         return 0;
 441
 442 err_disable_rq:
 443         mlx5e_disable_rq(rq);
 444 err_destroy_rq:
 445         mlx5e_destroy_rq(rq);
 446
 447         return err;
 448 }
 449
 450 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 451 {
 452         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 453         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 454
 455         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 456         while (!mlx5_wq_ll_is_empty(&rq->wq))
 457                 msleep(20);
 458
 459         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 460         napi_synchronize(&rq->channel->napi);
 461
 462         mlx5e_disable_rq(rq);
 463         mlx5e_destroy_rq(rq);
 464 }
 465
 466 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 467 {
 468         kfree(sq->dma_fifo);
 469         kfree(sq->skb);
 470 }
 471
 472 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 473 {
 474         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 475         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 476
 477         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 478         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 479                                     numa);
 480
 481         if (!sq->skb || !sq->dma_fifo) {
 482                 mlx5e_free_sq_db(sq);
 483                 return -ENOMEM;
 484         }
 485
 486         sq->dma_fifo_mask = df_sz - 1;
 487
 488         return 0;
 489 }
 490
 491 static int mlx5e_create_sq(struct mlx5e_channel *c,
 492                            int tc,
 493                            struct mlx5e_sq_param *param,
 494                            struct mlx5e_sq *sq)
 495 {
 496         struct mlx5e_priv *priv = c->priv;
 497         struct mlx5_core_dev *mdev = priv->mdev;
 498
 499         void *sqc = param->sqc;
 500         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 501         int txq_ix;
 502         int err;
 503
 504         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 505         if (err)
 506                 return err;
 507
 508         param->wq.db_numa_node = cpu_to_node(c->cpu);
 509
 510         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 511                                  &sq->wq_ctrl);
 512         if (err)
 513                 goto err_unmap_free_uar;
 514
 515         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 516         sq->uar_map     = sq->uar.map;
 517         sq->uar_bf_map  = sq->uar.bf_map;
 518         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 519         sq->max_inline  = param->max_inline;
 520
 521         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 522         if (err)
 523                 goto err_sq_wq_destroy;
 524
 525         txq_ix = c->ix + tc * priv->params.num_channels;
 526         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 527
 528         sq->pdev      = c->pdev;
 529         sq->mkey_be   = c->mkey_be;
 530         sq->channel   = c;
 531         sq->tc        = tc;
 532         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 533         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 534         priv->txq_to_sq_map[txq_ix] = sq;
 535
 536         return 0;
 537
 538 err_sq_wq_destroy:
 539         mlx5_wq_destroy(&sq->wq_ctrl);
 540
 541 err_unmap_free_uar:
 542         mlx5_unmap_free_uar(mdev, &sq->uar);
 543
 544         return err;
 545 }
 546
 547 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 548 {
 549         struct mlx5e_channel *c = sq->channel;
 550         struct mlx5e_priv *priv = c->priv;
 551
 552         mlx5e_free_sq_db(sq);
 553         mlx5_wq_destroy(&sq->wq_ctrl);
 554         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 555 }
 556
 557 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 558 {
 559         struct mlx5e_channel *c = sq->channel;
 560         struct mlx5e_priv *priv = c->priv;
 561         struct mlx5_core_dev *mdev = priv->mdev;
 562
 563         void *in;
 564         void *sqc;
 565         void *wq;
 566         int inlen;
 567         int err;
 568
 569         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 570                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 571         in = mlx5_vzalloc(inlen);
 572         if (!in)
 573                 return -ENOMEM;
 574
 575         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 576         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 577
 578         memcpy(sqc, param->sqc, sizeof(param->sqc));
 579
 580         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
 581         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 582         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 583         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 584         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 585         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 586
 587         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 588         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 589         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 590                                           PAGE_SHIFT);
 591         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 592
 593         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 594                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 595
 596         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 597
 598         kvfree(in);
 599
 600         return err;
 601 }
 602
 603 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 604 {
 605         struct mlx5e_channel *c = sq->channel;
 606         struct mlx5e_priv *priv = c->priv;
 607         struct mlx5_core_dev *mdev = priv->mdev;
 608
 609         void *in;
 610         void *sqc;
 611         int inlen;
 612         int err;
 613
 614         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 615         in = mlx5_vzalloc(inlen);
 616         if (!in)
 617                 return -ENOMEM;
 618
 619         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 620
 621         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 622         MLX5_SET(sqc, sqc, state, next_state);
 623
 624         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 625
 626         kvfree(in);
 627
 628         return err;
 629 }
 630
 631 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 632 {
 633         struct mlx5e_channel *c = sq->channel;
 634         struct mlx5e_priv *priv = c->priv;
 635         struct mlx5_core_dev *mdev = priv->mdev;
 636
 637         mlx5_core_destroy_sq(mdev, sq->sqn);
 638 }
 639
 640 static int mlx5e_open_sq(struct mlx5e_channel *c,
 641                          int tc,
 642                          struct mlx5e_sq_param *param,
 643                          struct mlx5e_sq *sq)
 644 {
 645         int err;
 646
 647         err = mlx5e_create_sq(c, tc, param, sq);
 648         if (err)
 649                 return err;
 650
 651         err = mlx5e_enable_sq(sq, param);
 652         if (err)
 653                 goto err_destroy_sq;
 654
 655         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 656         if (err)
 657                 goto err_disable_sq;
 658
 659         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 660         netdev_tx_reset_queue(sq->txq);
 661         netif_tx_start_queue(sq->txq);
 662
 663         return 0;
 664
 665 err_disable_sq:
 666         mlx5e_disable_sq(sq);
 667 err_destroy_sq:
 668         mlx5e_destroy_sq(sq);
 669
 670         return err;
 671 }
 672
 673 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 674 {
 675         __netif_tx_lock_bh(txq);
 676         netif_tx_stop_queue(txq);
 677         __netif_tx_unlock_bh(txq);
 678 }
 679
 680 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 681 {
 682         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 683         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 684         netif_tx_disable_queue(sq->txq);
 685
 686         /* ensure hw is notified of all pending wqes */
 687         if (mlx5e_sq_has_room_for(sq, 1))
 688                 mlx5e_send_nop(sq, true);
 689
 690         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 691         while (sq->cc != sq->pc) /* wait till sq is empty */
 692                 msleep(20);
 693
 694         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 695         napi_synchronize(&sq->channel->napi);
 696
 697         mlx5e_disable_sq(sq);
 698         mlx5e_destroy_sq(sq);
 699 }
 700
 701 static int mlx5e_create_cq(struct mlx5e_channel *c,
 702                            struct mlx5e_cq_param *param,
 703                            struct mlx5e_cq *cq)
 704 {
 705         struct mlx5e_priv *priv = c->priv;
 706         struct mlx5_core_dev *mdev = priv->mdev;
 707         struct mlx5_core_cq *mcq = &cq->mcq;
 708         int eqn_not_used;
 709         int irqn;
 710         int err;
 711         u32 i;
 712
 713         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 714         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 715         param->eq_ix   = c->ix;
 716
 717         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 718                                &cq->wq_ctrl);
 719         if (err)
 720                 return err;
 721
 722         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 723
 724         cq->napi        = &c->napi;
 725
 726         mcq->cqe_sz     = 64;
 727         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 728         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 729         *mcq->set_ci_db = 0;
 730         *mcq->arm_db    = 0;
 731         mcq->vector     = param->eq_ix;
 732         mcq->comp       = mlx5e_completion_event;
 733         mcq->event      = mlx5e_cq_error_event;
 734         mcq->irqn       = irqn;
 735         mcq->uar        = &priv->cq_uar;
 736
 737         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 738                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 739
 740                 cqe->op_own = 0xf1;
 741         }
 742
 743         cq->channel = c;
 744
 745         return 0;
 746 }
 747
 748 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 749 {
 750         mlx5_wq_destroy(&cq->wq_ctrl);
 751 }
 752
 753 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 754 {
 755         struct mlx5e_channel *c = cq->channel;
 756         struct mlx5e_priv *priv = c->priv;
 757         struct mlx5_core_dev *mdev = priv->mdev;
 758         struct mlx5_core_cq *mcq = &cq->mcq;
 759
 760         void *in;
 761         void *cqc;
 762         int inlen;
 763         int irqn_not_used;
 764         int eqn;
 765         int err;
 766
 767         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 768                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 769         in = mlx5_vzalloc(inlen);
 770         if (!in)
 771                 return -ENOMEM;
 772
 773         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 774
 775         memcpy(cqc, param->cqc, sizeof(param->cqc));
 776
 777         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 778                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 779
 780         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 781
 782         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 783         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 784         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 785                                             PAGE_SHIFT);
 786         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 787
 788         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 789
 790         kvfree(in);
 791
 792         if (err)
 793                 return err;
 794
 795         mlx5e_cq_arm(cq);
 796
 797         return 0;
 798 }
 799
 800 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 801 {
 802         struct mlx5e_channel *c = cq->channel;
 803         struct mlx5e_priv *priv = c->priv;
 804         struct mlx5_core_dev *mdev = priv->mdev;
 805
 806         mlx5_core_destroy_cq(mdev, &cq->mcq);
 807 }
 808
 809 static int mlx5e_open_cq(struct mlx5e_channel *c,
 810                          struct mlx5e_cq_param *param,
 811                          struct mlx5e_cq *cq,
 812                          u16 moderation_usecs,
 813                          u16 moderation_frames)
 814 {
 815         int err;
 816         struct mlx5e_priv *priv = c->priv;
 817         struct mlx5_core_dev *mdev = priv->mdev;
 818
 819         err = mlx5e_create_cq(c, param, cq);
 820         if (err)
 821                 return err;
 822
 823         err = mlx5e_enable_cq(cq, param);
 824         if (err)
 825                 goto err_destroy_cq;
 826
 827         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 828                                              moderation_usecs,
 829                                              moderation_frames);
 830         if (err)
 831                 goto err_destroy_cq;
 832
 833         return 0;
 834
 835 err_destroy_cq:
 836         mlx5e_destroy_cq(cq);
 837
 838         return err;
 839 }
 840
 841 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 842 {
 843         mlx5e_disable_cq(cq);
 844         mlx5e_destroy_cq(cq);
 845 }
 846
 847 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 848 {
 849         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 850 }
 851
 852 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 853                              struct mlx5e_channel_param *cparam)
 854 {
 855         struct mlx5e_priv *priv = c->priv;
 856         int err;
 857         int tc;
 858
 859         for (tc = 0; tc < c->num_tc; tc++) {
 860                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 861                                     priv->params.tx_cq_moderation_usec,
 862                                     priv->params.tx_cq_moderation_pkts);
 863                 if (err)
 864                         goto err_close_tx_cqs;
 865         }
 866
 867         return 0;
 868
 869 err_close_tx_cqs:
 870         for (tc--; tc >= 0; tc--)
 871                 mlx5e_close_cq(&c->sq[tc].cq);
 872
 873         return err;
 874 }
 875
 876 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 877 {
 878         int tc;
 879
 880         for (tc = 0; tc < c->num_tc; tc++)
 881                 mlx5e_close_cq(&c->sq[tc].cq);
 882 }
 883
 884 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 885                           struct mlx5e_channel_param *cparam)
 886 {
 887         int err;
 888         int tc;
 889
 890         for (tc = 0; tc < c->num_tc; tc++) {
 891                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 892                 if (err)
 893                         goto err_close_sqs;
 894         }
 895
 896         return 0;
 897
 898 err_close_sqs:
 899         for (tc--; tc >= 0; tc--)
 900                 mlx5e_close_sq(&c->sq[tc]);
 901
 902         return err;
 903 }
 904
 905 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 906 {
 907         int tc;
 908
 909         for (tc = 0; tc < c->num_tc; tc++)
 910                 mlx5e_close_sq(&c->sq[tc]);
 911 }
 912
 913 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
 914                                       int num_channels)
 915 {
 916         int i;
 917
 918         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 919                 c->tc_to_txq_map[i] = c->ix + i * num_channels;
 920 }
 921
 922 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 923                               struct mlx5e_channel_param *cparam,
 924                               struct mlx5e_channel **cp)
 925 {
 926         struct net_device *netdev = priv->netdev;
 927         int cpu = mlx5e_get_cpu(priv, ix);
 928         struct mlx5e_channel *c;
 929         int err;
 930
 931         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 932         if (!c)
 933                 return -ENOMEM;
 934
 935         c->priv     = priv;
 936         c->ix       = ix;
 937         c->cpu      = cpu;
 938         c->pdev     = &priv->mdev->pdev->dev;
 939         c->netdev   = priv->netdev;
 940         c->mkey_be  = cpu_to_be32(priv->mr.key);
 941         c->num_tc   = priv->num_tc;
 942
 943         mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
 944
 945         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 946
 947         err = mlx5e_open_tx_cqs(c, cparam);
 948         if (err)
 949                 goto err_napi_del;
 950
 951         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 952                             priv->params.rx_cq_moderation_usec,
 953                             priv->params.rx_cq_moderation_pkts);
 954         if (err)
 955                 goto err_close_tx_cqs;
 956
 957         napi_enable(&c->napi);
 958
 959         err = mlx5e_open_sqs(c, cparam);
 960         if (err)
 961                 goto err_disable_napi;
 962
 963         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 964         if (err)
 965                 goto err_close_sqs;
 966
 967         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 968         *cp = c;
 969
 970         return 0;
 971
 972 err_close_sqs:
 973         mlx5e_close_sqs(c);
 974
 975 err_disable_napi:
 976         napi_disable(&c->napi);
 977         mlx5e_close_cq(&c->rq.cq);
 978
 979 err_close_tx_cqs:
 980         mlx5e_close_tx_cqs(c);
 981
 982 err_napi_del:
 983         netif_napi_del(&c->napi);
 984         kfree(c);
 985
 986         return err;
 987 }
 988
 989 static void mlx5e_close_channel(struct mlx5e_channel *c)
 990 {
 991         mlx5e_close_rq(&c->rq);
 992         mlx5e_close_sqs(c);
 993         napi_disable(&c->napi);
 994         mlx5e_close_cq(&c->rq.cq);
 995         mlx5e_close_tx_cqs(c);
 996         netif_napi_del(&c->napi);
 997         kfree(c);
 998 }
 999
1000 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1001                                  struct mlx5e_rq_param *param)
1002 {
1003         void *rqc = param->rqc;
1004         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1005
1006         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1007         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1008         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1009         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1010         MLX5_SET(wq, wq, pd,               priv->pdn);
1011
1012         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1013         param->wq.linear = 1;
1014 }
1015
1016 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1017                                  struct mlx5e_sq_param *param)
1018 {
1019         void *sqc = param->sqc;
1020         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1021
1022         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1023         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1024         MLX5_SET(wq, wq, pd,            priv->pdn);
1025
1026         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1027         param->max_inline = priv->params.tx_max_inline;
1028 }
1029
1030 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1031                                         struct mlx5e_cq_param *param)
1032 {
1033         void *cqc = param->cqc;
1034
1035         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1036 }
1037
1038 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1039                                     struct mlx5e_cq_param *param)
1040 {
1041         void *cqc = param->cqc;
1042
1043         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1044
1045         mlx5e_build_common_cq_param(priv, param);
1046 }
1047
1048 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1049                                     struct mlx5e_cq_param *param)
1050 {
1051         void *cqc = param->cqc;
1052
1053         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1054
1055         mlx5e_build_common_cq_param(priv, param);
1056 }
1057
1058 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1059                                       struct mlx5e_channel_param *cparam)
1060 {
1061         memset(cparam, 0, sizeof(*cparam));
1062
1063         mlx5e_build_rq_param(priv, &cparam->rq);
1064         mlx5e_build_sq_param(priv, &cparam->sq);
1065         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1066         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1067 }
1068
1069 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1070 {
1071         struct mlx5e_channel_param cparam;
1072         int err = -ENOMEM;
1073         int i;
1074         int j;
1075
1076         priv->channel = kcalloc(priv->params.num_channels,
1077                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1078
1079         priv->txq_to_sq_map = kcalloc(priv->params.num_channels * priv->num_tc,
1080                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1081
1082         if (!priv->channel || !priv->txq_to_sq_map)
1083                 goto err_free_txq_to_sq_map;
1084
1085         mlx5e_build_channel_param(priv, &cparam);
1086         for (i = 0; i < priv->params.num_channels; i++) {
1087                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1088                 if (err)
1089                         goto err_close_channels;
1090         }
1091
1092         for (j = 0; j < priv->params.num_channels; j++) {
1093                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1094                 if (err)
1095                         goto err_close_channels;
1096         }
1097
1098         return 0;
1099
1100 err_close_channels:
1101         for (i--; i >= 0; i--)
1102                 mlx5e_close_channel(priv->channel[i]);
1103
1104 err_free_txq_to_sq_map:
1105         kfree(priv->txq_to_sq_map);
1106         kfree(priv->channel);
1107
1108         return err;
1109 }
1110
1111 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1112 {
1113         int i;
1114
1115         for (i = 0; i < priv->params.num_channels; i++)
1116                 mlx5e_close_channel(priv->channel[i]);
1117
1118         kfree(priv->txq_to_sq_map);
1119         kfree(priv->channel);
1120 }
1121
1122 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1123 {
1124         struct mlx5_core_dev *mdev = priv->mdev;
1125         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1126         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1127
1128         memset(in, 0, sizeof(in));
1129
1130         MLX5_SET(tisc, tisc, prio,  tc);
1131         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1132
1133         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1134 }
1135
1136 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1137 {
1138         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1139 }
1140
1141 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1142 {
1143         int num_tc = priv->num_tc;
1144         int err;
1145         int tc;
1146
1147         for (tc = 0; tc < num_tc; tc++) {
1148                 err = mlx5e_open_tis(priv, tc);
1149                 if (err)
1150                         goto err_close_tises;
1151         }
1152
1153         return 0;
1154
1155 err_close_tises:
1156         for (tc--; tc >= 0; tc--)
1157                 mlx5e_close_tis(priv, tc);
1158
1159         return err;
1160 }
1161
1162 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1163 {
1164         int num_tc = priv->num_tc;
1165         int tc;
1166
1167         for (tc = 0; tc < num_tc; tc++)
1168                 mlx5e_close_tis(priv, tc);
1169 }
1170
1171 static int mlx5e_rx_hash_fn(int hfunc)
1172 {
1173         return (hfunc == ETH_RSS_HASH_TOP) ?
1174                MLX5_RX_HASH_FN_TOEPLITZ :
1175                MLX5_RX_HASH_FN_INVERTED_XOR8;
1176 }
1177
1178 static int mlx5e_bits_invert(unsigned long a, int size)
1179 {
1180         int inv = 0;
1181         int i;
1182
1183         for (i = 0; i < size; i++)
1184                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1185
1186         return inv;
1187 }
1188
1189 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1190 {
1191         struct mlx5_core_dev *mdev = priv->mdev;
1192         u32 *in;
1193         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1194         void *rqtc;
1195         int inlen;
1196         int err;
1197         int log_tbl_sz = priv->params.rx_hash_log_tbl_sz;
1198         int sz = 1 << log_tbl_sz;
1199         int i;
1200
1201         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1202         in = mlx5_vzalloc(inlen);
1203         if (!in)
1204                 return -ENOMEM;
1205
1206         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1207
1208         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1209         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1210
1211         for (i = 0; i < sz; i++) {
1212                 int ix = i;
1213
1214                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1215                         ix = mlx5e_bits_invert(i, log_tbl_sz);
1216
1217                 ix = ix % priv->params.num_channels;
1218                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1219         }
1220
1221         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1222
1223         memset(out, 0, sizeof(out));
1224         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1225         if (!err)
1226                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1227
1228         kvfree(in);
1229
1230         return err;
1231 }
1232
1233 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1234 {
1235         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1236         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1237
1238         memset(in, 0, sizeof(in));
1239
1240         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1241         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1242
1243         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1244                                    sizeof(out));
1245 }
1246
1247 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1248 {
1249         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1250
1251         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1252
1253 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1254
1255 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1256                                  MLX5_HASH_FIELD_SEL_DST_IP)
1257
1258 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1259                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1260                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1261                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1262
1263         if (priv->params.lro_en) {
1264                 MLX5_SET(tirc, tirc, lro_enable_mask,
1265                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1266                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1267                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1268                          (priv->params.lro_wqe_sz -
1269                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1270                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1271                          MLX5_CAP_ETH(priv->mdev,
1272                                       lro_timer_supported_periods[3]));
1273         }
1274
1275         switch (tt) {
1276         case MLX5E_TT_ANY:
1277                 MLX5_SET(tirc, tirc, disp_type,
1278                          MLX5_TIRC_DISP_TYPE_DIRECT);
1279                 MLX5_SET(tirc, tirc, inline_rqn,
1280                          priv->channel[0]->rq.rqn);
1281                 break;
1282         default:
1283                 MLX5_SET(tirc, tirc, disp_type,
1284                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1285                 MLX5_SET(tirc, tirc, indirect_table,
1286                          priv->rqtn);
1287                 MLX5_SET(tirc, tirc, rx_hash_fn,
1288                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1289                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1290                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1291                                                      rx_hash_toeplitz_key);
1292                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1293                                                        rx_hash_toeplitz_key);
1294
1295                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1296                         netdev_rss_key_fill(rss_key, len);
1297                 }
1298                 break;
1299         }
1300
1301         switch (tt) {
1302         case MLX5E_TT_IPV4_TCP:
1303                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1304                          MLX5_L3_PROT_TYPE_IPV4);
1305                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1306                          MLX5_L4_PROT_TYPE_TCP);
1307                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1308                          MLX5_HASH_IP_L4PORTS);
1309                 break;
1310
1311         case MLX5E_TT_IPV6_TCP:
1312                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1313                          MLX5_L3_PROT_TYPE_IPV6);
1314                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1315                          MLX5_L4_PROT_TYPE_TCP);
1316                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1317                          MLX5_HASH_IP_L4PORTS);
1318                 break;
1319
1320         case MLX5E_TT_IPV4_UDP:
1321                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1322                          MLX5_L3_PROT_TYPE_IPV4);
1323                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1324                          MLX5_L4_PROT_TYPE_UDP);
1325                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1326                          MLX5_HASH_IP_L4PORTS);
1327                 break;
1328
1329         case MLX5E_TT_IPV6_UDP:
1330                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1331                          MLX5_L3_PROT_TYPE_IPV6);
1332                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1333                          MLX5_L4_PROT_TYPE_UDP);
1334                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1335                          MLX5_HASH_IP_L4PORTS);
1336                 break;
1337
1338         case MLX5E_TT_IPV4:
1339                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1340                          MLX5_L3_PROT_TYPE_IPV4);
1341                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1342                          MLX5_HASH_IP);
1343                 break;
1344
1345         case MLX5E_TT_IPV6:
1346                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1347                          MLX5_L3_PROT_TYPE_IPV6);
1348                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1349                          MLX5_HASH_IP);
1350                 break;
1351         }
1352 }
1353
1354 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1355 {
1356         struct mlx5_core_dev *mdev = priv->mdev;
1357         u32 *in;
1358         void *tirc;
1359         int inlen;
1360         int err;
1361
1362         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1363         in = mlx5_vzalloc(inlen);
1364         if (!in)
1365                 return -ENOMEM;
1366
1367         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1368
1369         mlx5e_build_tir_ctx(priv, tirc, tt);
1370
1371         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1372
1373         kvfree(in);
1374
1375         return err;
1376 }
1377
1378 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1379 {
1380         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1381 }
1382
1383 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1384 {
1385         int err;
1386         int i;
1387
1388         for (i = 0; i < MLX5E_NUM_TT; i++) {
1389                 err = mlx5e_open_tir(priv, i);
1390                 if (err)
1391                         goto err_close_tirs;
1392         }
1393
1394         return 0;
1395
1396 err_close_tirs:
1397         for (i--; i >= 0; i--)
1398                 mlx5e_close_tir(priv, i);
1399
1400         return err;
1401 }
1402
1403 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1404 {
1405         int i;
1406
1407         for (i = 0; i < MLX5E_NUM_TT; i++)
1408                 mlx5e_close_tir(priv, i);
1409 }
1410
1411 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1412 {
1413         struct mlx5e_priv *priv = netdev_priv(netdev);
1414         struct mlx5_core_dev *mdev = priv->mdev;
1415         int hw_mtu;
1416         int err;
1417
1418         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1419         if (err)
1420                 return err;
1421
1422         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1423
1424         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1425                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1426                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1427
1428         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1429         return 0;
1430 }
1431
1432 int mlx5e_open_locked(struct net_device *netdev)
1433 {
1434         struct mlx5e_priv *priv = netdev_priv(netdev);
1435         int num_txqs;
1436         int err;
1437
1438         num_txqs = priv->params.num_channels * priv->params.num_tc;
1439         netif_set_real_num_tx_queues(netdev, num_txqs);
1440         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1441
1442         err = mlx5e_set_dev_port_mtu(netdev);
1443         if (err)
1444                 return err;
1445
1446         err = mlx5e_open_tises(priv);
1447         if (err) {
1448                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1449                            __func__, err);
1450                 return err;
1451         }
1452
1453         err = mlx5e_open_channels(priv);
1454         if (err) {
1455                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1456                            __func__, err);
1457                 goto err_close_tises;
1458         }
1459
1460         err = mlx5e_open_rqt(priv);
1461         if (err) {
1462                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1463                            __func__, err);
1464                 goto err_close_channels;
1465         }
1466
1467         err = mlx5e_open_tirs(priv);
1468         if (err) {
1469                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1470                            __func__, err);
1471                 goto err_close_rqls;
1472         }
1473
1474         err = mlx5e_open_flow_table(priv);
1475         if (err) {
1476                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1477                            __func__, err);
1478                 goto err_close_tirs;
1479         }
1480
1481         err = mlx5e_add_all_vlan_rules(priv);
1482         if (err) {
1483                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1484                            __func__, err);
1485                 goto err_close_flow_table;
1486         }
1487
1488         mlx5e_init_eth_addr(priv);
1489
1490         set_bit(MLX5E_STATE_OPENED, &priv->state);
1491
1492         mlx5e_update_carrier(priv);
1493         mlx5e_set_rx_mode_core(priv);
1494
1495         schedule_delayed_work(&priv->update_stats_work, 0);
1496         return 0;
1497
1498 err_close_flow_table:
1499         mlx5e_close_flow_table(priv);
1500
1501 err_close_tirs:
1502         mlx5e_close_tirs(priv);
1503
1504 err_close_rqls:
1505         mlx5e_close_rqt(priv);
1506
1507 err_close_channels:
1508         mlx5e_close_channels(priv);
1509
1510 err_close_tises:
1511         mlx5e_close_tises(priv);
1512
1513         return err;
1514 }
1515
1516 static int mlx5e_open(struct net_device *netdev)
1517 {
1518         struct mlx5e_priv *priv = netdev_priv(netdev);
1519         int err;
1520
1521         mutex_lock(&priv->state_lock);
1522         err = mlx5e_open_locked(netdev);
1523         mutex_unlock(&priv->state_lock);
1524
1525         return err;
1526 }
1527
1528 int mlx5e_close_locked(struct net_device *netdev)
1529 {
1530         struct mlx5e_priv *priv = netdev_priv(netdev);
1531
1532         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1533
1534         mlx5e_set_rx_mode_core(priv);
1535         mlx5e_del_all_vlan_rules(priv);
1536         netif_carrier_off(priv->netdev);
1537         mlx5e_close_flow_table(priv);
1538         mlx5e_close_tirs(priv);
1539         mlx5e_close_rqt(priv);
1540         mlx5e_close_channels(priv);
1541         mlx5e_close_tises(priv);
1542
1543         return 0;
1544 }
1545
1546 static int mlx5e_close(struct net_device *netdev)
1547 {
1548         struct mlx5e_priv *priv = netdev_priv(netdev);
1549         int err;
1550
1551         mutex_lock(&priv->state_lock);
1552         err = mlx5e_close_locked(netdev);
1553         mutex_unlock(&priv->state_lock);
1554
1555         return err;
1556 }
1557
1558 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1559                              struct mlx5e_params *new_params)
1560 {
1561         int err = 0;
1562         int was_opened;
1563
1564         WARN_ON(!mutex_is_locked(&priv->state_lock));
1565
1566         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1567         if (was_opened)
1568                 mlx5e_close_locked(priv->netdev);
1569
1570         priv->params = *new_params;
1571
1572         if (was_opened)
1573                 err = mlx5e_open_locked(priv->netdev);
1574
1575         return err;
1576 }
1577
1578 static struct rtnl_link_stats64 *
1579 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1580 {
1581         struct mlx5e_priv *priv = netdev_priv(dev);
1582         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1583
1584         stats->rx_packets = vstats->rx_packets;
1585         stats->rx_bytes   = vstats->rx_bytes;
1586         stats->tx_packets = vstats->tx_packets;
1587         stats->tx_bytes   = vstats->tx_bytes;
1588         stats->multicast  = vstats->rx_multicast_packets +
1589                             vstats->tx_multicast_packets;
1590         stats->tx_errors  = vstats->tx_error_packets;
1591         stats->rx_errors  = vstats->rx_error_packets;
1592         stats->tx_dropped = vstats->tx_queue_dropped;
1593         stats->rx_crc_errors = 0;
1594         stats->rx_length_errors = 0;
1595
1596         return stats;
1597 }
1598
1599 static void mlx5e_set_rx_mode(struct net_device *dev)
1600 {
1601         struct mlx5e_priv *priv = netdev_priv(dev);
1602
1603         schedule_work(&priv->set_rx_mode_work);
1604 }
1605
1606 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1607 {
1608         struct mlx5e_priv *priv = netdev_priv(netdev);
1609         struct sockaddr *saddr = addr;
1610
1611         if (!is_valid_ether_addr(saddr->sa_data))
1612                 return -EADDRNOTAVAIL;
1613
1614         netif_addr_lock_bh(netdev);
1615         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1616         netif_addr_unlock_bh(netdev);
1617
1618         schedule_work(&priv->set_rx_mode_work);
1619
1620         return 0;
1621 }
1622
1623 static int mlx5e_set_features(struct net_device *netdev,
1624                               netdev_features_t features)
1625 {
1626         struct mlx5e_priv *priv = netdev_priv(netdev);
1627         netdev_features_t changes = features ^ netdev->features;
1628         struct mlx5e_params new_params;
1629         bool update_params = false;
1630
1631         mutex_lock(&priv->state_lock);
1632         new_params = priv->params;
1633
1634         if (changes & NETIF_F_LRO) {
1635                 new_params.lro_en = !!(features & NETIF_F_LRO);
1636                 update_params = true;
1637         }
1638
1639         if (update_params)
1640                 mlx5e_update_priv_params(priv, &new_params);
1641
1642         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1643                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1644                         mlx5e_enable_vlan_filter(priv);
1645                 else
1646                         mlx5e_disable_vlan_filter(priv);
1647         }
1648
1649         mutex_unlock(&priv->state_lock);
1650
1651         return 0;
1652 }
1653
1654 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1655 {
1656         struct mlx5e_priv *priv = netdev_priv(netdev);
1657         struct mlx5_core_dev *mdev = priv->mdev;
1658         int max_mtu;
1659         int err;
1660
1661         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1662
1663         if (new_mtu > max_mtu) {
1664                 netdev_err(netdev,
1665                            "%s: Bad MTU (%d) > (%d) Max\n",
1666                            __func__, new_mtu, max_mtu);
1667                 return -EINVAL;
1668         }
1669
1670         mutex_lock(&priv->state_lock);
1671         netdev->mtu = new_mtu;
1672         err = mlx5e_update_priv_params(priv, &priv->params);
1673         mutex_unlock(&priv->state_lock);
1674
1675         return err;
1676 }
1677
1678 static struct net_device_ops mlx5e_netdev_ops = {
1679         .ndo_open                = mlx5e_open,
1680         .ndo_stop                = mlx5e_close,
1681         .ndo_start_xmit          = mlx5e_xmit,
1682         .ndo_get_stats64         = mlx5e_get_stats,
1683         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1684         .ndo_set_mac_address     = mlx5e_set_mac,
1685         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1686         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1687         .ndo_set_features        = mlx5e_set_features,
1688         .ndo_change_mtu          = mlx5e_change_mtu,
1689 };
1690
1691 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1692 {
1693         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1694                 return -ENOTSUPP;
1695         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1696             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1697             !MLX5_CAP_ETH(mdev, csum_cap) ||
1698             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1699             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1700             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1701             MLX5_CAP_FLOWTABLE(mdev,
1702                                flow_table_properties_nic_receive.max_ft_level)
1703                                < 3) {
1704                 mlx5_core_warn(mdev,
1705                                "Not creating net device, some required device capabilities are missing\n");
1706                 return -ENOTSUPP;
1707         }
1708         return 0;
1709 }
1710
1711 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1712 {
1713         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1714
1715         return bf_buf_size -
1716                sizeof(struct mlx5e_tx_wqe) +
1717                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1718 }
1719
1720 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1721                                     struct net_device *netdev,
1722                                     int num_comp_vectors)
1723 {
1724         struct mlx5e_priv *priv = netdev_priv(netdev);
1725
1726         priv->params.log_sq_size           =
1727                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1728         priv->params.log_rq_size           =
1729                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1730         priv->params.rx_cq_moderation_usec =
1731                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1732         priv->params.rx_cq_moderation_pkts =
1733                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1734         priv->params.tx_cq_moderation_usec =
1735                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1736         priv->params.tx_cq_moderation_pkts =
1737                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1738         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
1739         priv->params.min_rx_wqes           =
1740                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1741         priv->params.rx_hash_log_tbl_sz    =
1742                 (order_base_2(num_comp_vectors) >
1743                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1744                 order_base_2(num_comp_vectors)           :
1745                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1746         priv->params.num_tc                = 1;
1747         priv->params.default_vlan_prio     = 0;
1748         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
1749
1750         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1751         priv->params.lro_wqe_sz            =
1752                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1753
1754         priv->mdev                         = mdev;
1755         priv->netdev                       = netdev;
1756         priv->params.num_channels          = num_comp_vectors;
1757         priv->num_tc                       = priv->params.num_tc;
1758         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1759
1760         spin_lock_init(&priv->async_events_spinlock);
1761         mutex_init(&priv->state_lock);
1762
1763         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1764         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1765         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1766 }
1767
1768 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1769 {
1770         struct mlx5e_priv *priv = netdev_priv(netdev);
1771
1772         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1773 }
1774
1775 static void mlx5e_build_netdev(struct net_device *netdev)
1776 {
1777         struct mlx5e_priv *priv = netdev_priv(netdev);
1778         struct mlx5_core_dev *mdev = priv->mdev;
1779
1780         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1781
1782         if (priv->num_tc > 1) {
1783                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1784         }
1785
1786         netdev->netdev_ops        = &mlx5e_netdev_ops;
1787         netdev->watchdog_timeo    = 15 * HZ;
1788
1789         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1790
1791         netdev->vlan_features    |= NETIF_F_SG;
1792         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1793         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1794         netdev->vlan_features    |= NETIF_F_GRO;
1795         netdev->vlan_features    |= NETIF_F_TSO;
1796         netdev->vlan_features    |= NETIF_F_TSO6;
1797         netdev->vlan_features    |= NETIF_F_RXCSUM;
1798         netdev->vlan_features    |= NETIF_F_RXHASH;
1799
1800         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1801                 netdev->vlan_features    |= NETIF_F_LRO;
1802
1803         netdev->hw_features       = netdev->vlan_features;
1804         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1805         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1806
1807         netdev->features          = netdev->hw_features;
1808         if (!priv->params.lro_en)
1809                 netdev->features  &= ~NETIF_F_LRO;
1810
1811         netdev->features         |= NETIF_F_HIGHDMA;
1812
1813         netdev->priv_flags       |= IFF_UNICAST_FLT;
1814
1815         mlx5e_set_netdev_dev_addr(netdev);
1816 }
1817
1818 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1819                              struct mlx5_core_mr *mr)
1820 {
1821         struct mlx5_core_dev *mdev = priv->mdev;
1822         struct mlx5_create_mkey_mbox_in *in;
1823         int err;
1824
1825         in = mlx5_vzalloc(sizeof(*in));
1826         if (!in)
1827                 return -ENOMEM;
1828
1829         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1830                         MLX5_PERM_LOCAL_READ  |
1831                         MLX5_ACCESS_MODE_PA;
1832         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1833         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1834
1835         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1836                                     NULL);
1837
1838         kvfree(in);
1839
1840         return err;
1841 }
1842
1843 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1844 {
1845         struct net_device *netdev;
1846         struct mlx5e_priv *priv;
1847         int ncv = mdev->priv.eq_table.num_comp_vectors;
1848         int err;
1849
1850         if (mlx5e_check_required_hca_cap(mdev))
1851                 return NULL;
1852
1853         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
1854         if (!netdev) {
1855                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1856                 return NULL;
1857         }
1858
1859         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1860         mlx5e_build_netdev(netdev);
1861
1862         netif_carrier_off(netdev);
1863
1864         priv = netdev_priv(netdev);
1865
1866         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1867         if (err) {
1868                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1869                            __func__, err);
1870                 goto err_free_netdev;
1871         }
1872
1873         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1874         if (err) {
1875                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1876                            __func__, err);
1877                 goto err_unmap_free_uar;
1878         }
1879
1880         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1881         if (err) {
1882                 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1883                            __func__, err);
1884                 goto err_dealloc_pd;
1885         }
1886
1887         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1888         if (err) {
1889                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1890                            __func__, err);
1891                 goto err_dealloc_transport_domain;
1892         }
1893
1894         err = register_netdev(netdev);
1895         if (err) {
1896                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1897                            __func__, err);
1898                 goto err_destroy_mkey;
1899         }
1900
1901         mlx5e_enable_async_events(priv);
1902
1903         return priv;
1904
1905 err_destroy_mkey:
1906         mlx5_core_destroy_mkey(mdev, &priv->mr);
1907
1908 err_dealloc_transport_domain:
1909         mlx5_dealloc_transport_domain(mdev, priv->tdn);
1910
1911 err_dealloc_pd:
1912         mlx5_core_dealloc_pd(mdev, priv->pdn);
1913
1914 err_unmap_free_uar:
1915         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1916
1917 err_free_netdev:
1918         free_netdev(netdev);
1919
1920         return NULL;
1921 }
1922
1923 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1924 {
1925         struct mlx5e_priv *priv = vpriv;
1926         struct net_device *netdev = priv->netdev;
1927
1928         unregister_netdev(netdev);
1929         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1930         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
1931         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1932         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1933         mlx5e_disable_async_events(priv);
1934         flush_scheduled_work();
1935         free_netdev(netdev);
1936 }
1937
1938 static void *mlx5e_get_netdev(void *vpriv)
1939 {
1940         struct mlx5e_priv *priv = vpriv;
1941
1942         return priv->netdev;
1943 }
1944
1945 static struct mlx5_interface mlx5e_interface = {
1946         .add       = mlx5e_create_netdev,
1947         .remove    = mlx5e_destroy_netdev,
1948         .event     = mlx5e_async_event,
1949         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1950         .get_dev   = mlx5e_get_netdev,
1951 };
1952
1953 void mlx5e_init(void)
1954 {
1955         mlx5_register_interface(&mlx5e_interface);
1956 }
1957
1958 void mlx5e_cleanup(void)
1959 {
1960         mlx5_unregister_interface(&mlx5e_interface);
1961 }