drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5e_sw_stats *s = &priv->stats.sw;
  97         struct mlx5e_rq_stats *rq_stats;
  98         struct mlx5e_sq_stats *sq_stats;
  99         u64 tx_offload_none = 0;
 100         int i, j;
 101
 102         memset(s, 0, sizeof(*s));
 103         for (i = 0; i < priv->params.num_channels; i++) {
 104                 rq_stats = &priv->channel[i]->rq.stats;
 105
 106                 s->rx_packets   += rq_stats->packets;
 107                 s->rx_bytes     += rq_stats->bytes;
 108                 s->lro_packets  += rq_stats->lro_packets;
 109                 s->lro_bytes    += rq_stats->lro_bytes;
 110                 s->rx_csum_none += rq_stats->csum_none;
 111                 s->rx_csum_sw   += rq_stats->csum_sw;
 112                 s->rx_wqe_err   += rq_stats->wqe_err;
 113                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 114                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 115                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 116
 117                 for (j = 0; j < priv->params.num_tc; j++) {
 118                         sq_stats = &priv->channel[i]->sq[j].stats;
 119
 120                         s->tx_packets           += sq_stats->packets;
 121                         s->tx_bytes             += sq_stats->bytes;
 122                         s->tso_packets          += sq_stats->tso_packets;
 123                         s->tso_bytes            += sq_stats->tso_bytes;
 124                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 125                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 126                         s->tx_queue_stopped     += sq_stats->stopped;
 127                         s->tx_queue_wake        += sq_stats->wake;
 128                         s->tx_queue_dropped     += sq_stats->dropped;
 129                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 130                         tx_offload_none         += sq_stats->csum_offload_none;
 131                 }
 132         }
 133
 134         /* Update calculated offload counters */
 135         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 136         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 137                              s->rx_csum_sw;
 138
 139         s->link_down_events = MLX5_GET(ppcnt_reg,
 140                                 priv->stats.pport.phy_counters,
 141                                 counter_set.phys_layer_cntrs.link_down_events);
 142 }
 143
 144 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 145 {
 146         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 147         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 148         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 149         struct mlx5_core_dev *mdev = priv->mdev;
 150
 151         memset(in, 0, sizeof(in));
 152
 153         MLX5_SET(query_vport_counter_in, in, opcode,
 154                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 155         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 156         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 157
 158         memset(out, 0, outlen);
 159
 160         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 161 }
 162
 163 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 164 {
 165         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 168         int prio;
 169         void *out;
 170         u32 *in;
 171
 172         in = mlx5_vzalloc(sz);
 173         if (!in)
 174                 goto free_out;
 175
 176         MLX5_SET(ppcnt_reg, in, local_port, 1);
 177
 178         out = pstats->IEEE_802_3_counters;
 179         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 180         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 181
 182         out = pstats->RFC_2863_counters;
 183         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 184         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 185
 186         out = pstats->RFC_2819_counters;
 187         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 188         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 189
 190         out = pstats->phy_counters;
 191         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 192         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 193
 194         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 195         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 196                 out = pstats->per_prio_counters[prio];
 197                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 198                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 199                                      MLX5_REG_PPCNT, 0, 0);
 200         }
 201
 202 free_out:
 203         kvfree(in);
 204 }
 205
 206 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 207 {
 208         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 209
 210         if (!priv->q_counter)
 211                 return;
 212
 213         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 214                                       &qcnt->rx_out_of_buffer);
 215 }
 216
 217 void mlx5e_update_stats(struct mlx5e_priv *priv)
 218 {
 219         mlx5e_update_q_counter(priv);
 220         mlx5e_update_vport_counters(priv);
 221         mlx5e_update_pport_counters(priv);
 222         mlx5e_update_sw_counters(priv);
 223 }
 224
 225 static void mlx5e_update_stats_work(struct work_struct *work)
 226 {
 227         struct delayed_work *dwork = to_delayed_work(work);
 228         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 229                                                update_stats_work);
 230         mutex_lock(&priv->state_lock);
 231         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 232                 mlx5e_update_stats(priv);
 233                 schedule_delayed_work(dwork,
 234                                       msecs_to_jiffies(
 235                                               MLX5E_UPDATE_STATS_INTERVAL));
 236         }
 237         mutex_unlock(&priv->state_lock);
 238 }
 239
 240 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 241                               enum mlx5_dev_event event, unsigned long param)
 242 {
 243         struct mlx5e_priv *priv = vpriv;
 244
 245         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 246                 return;
 247
 248         switch (event) {
 249         case MLX5_DEV_EVENT_PORT_UP:
 250         case MLX5_DEV_EVENT_PORT_DOWN:
 251                 schedule_work(&priv->update_carrier_work);
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257 }
 258
 259 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 260 {
 261         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 262 }
 263
 264 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 265 {
 266         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 267         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 268 }
 269
 270 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 271 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 272
 273 static int mlx5e_create_rq(struct mlx5e_channel *c,
 274                            struct mlx5e_rq_param *param,
 275                            struct mlx5e_rq *rq)
 276 {
 277         struct mlx5e_priv *priv = c->priv;
 278         struct mlx5_core_dev *mdev = priv->mdev;
 279         void *rqc = param->rqc;
 280         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 281         u32 byte_count;
 282         int wq_sz;
 283         int err;
 284         int i;
 285
 286         param->wq.db_numa_node = cpu_to_node(c->cpu);
 287
 288         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 289                                 &rq->wq_ctrl);
 290         if (err)
 291                 return err;
 292
 293         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 294
 295         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 296
 297         switch (priv->params.rq_wq_type) {
 298         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 299                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 300                                             GFP_KERNEL, cpu_to_node(c->cpu));
 301                 if (!rq->wqe_info) {
 302                         err = -ENOMEM;
 303                         goto err_rq_wq_destroy;
 304                 }
 305                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 306                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 307
 308                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 309                 byte_count = rq->wqe_sz;
 310                 break;
 311         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 312                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 313                                        cpu_to_node(c->cpu));
 314                 if (!rq->skb) {
 315                         err = -ENOMEM;
 316                         goto err_rq_wq_destroy;
 317                 }
 318                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 319                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 320
 321                 rq->wqe_sz = (priv->params.lro_en) ?
 322                                 priv->params.lro_wqe_sz :
 323                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 324                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 325                 byte_count = rq->wqe_sz;
 326                 byte_count |= MLX5_HW_START_PADDING;
 327         }
 328
 329         for (i = 0; i < wq_sz; i++) {
 330                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 331
 332                 wqe->data.byte_count = cpu_to_be32(byte_count);
 333         }
 334
 335         rq->wq_type = priv->params.rq_wq_type;
 336         rq->pdev    = c->pdev;
 337         rq->netdev  = c->netdev;
 338         rq->tstamp  = &priv->tstamp;
 339         rq->channel = c;
 340         rq->ix      = c->ix;
 341         rq->priv    = c->priv;
 342         rq->mkey_be = c->mkey_be;
 343         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 344
 345         return 0;
 346
 347 err_rq_wq_destroy:
 348         mlx5_wq_destroy(&rq->wq_ctrl);
 349
 350         return err;
 351 }
 352
 353 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 354 {
 355         switch (rq->wq_type) {
 356         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 357                 kfree(rq->wqe_info);
 358                 break;
 359         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 360                 kfree(rq->skb);
 361         }
 362
 363         mlx5_wq_destroy(&rq->wq_ctrl);
 364 }
 365
 366 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 367 {
 368         struct mlx5e_priv *priv = rq->priv;
 369         struct mlx5_core_dev *mdev = priv->mdev;
 370
 371         void *in;
 372         void *rqc;
 373         void *wq;
 374         int inlen;
 375         int err;
 376
 377         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 378                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 379         in = mlx5_vzalloc(inlen);
 380         if (!in)
 381                 return -ENOMEM;
 382
 383         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 384         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 385
 386         memcpy(rqc, param->rqc, sizeof(param->rqc));
 387
 388         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 389         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 390         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 391         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 392         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 393                                                 MLX5_ADAPTER_PAGE_SHIFT);
 394         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 395
 396         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 397                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 398
 399         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 400
 401         kvfree(in);
 402
 403         return err;
 404 }
 405
 406 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 407                                  int next_state)
 408 {
 409         struct mlx5e_channel *c = rq->channel;
 410         struct mlx5e_priv *priv = c->priv;
 411         struct mlx5_core_dev *mdev = priv->mdev;
 412
 413         void *in;
 414         void *rqc;
 415         int inlen;
 416         int err;
 417
 418         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 419         in = mlx5_vzalloc(inlen);
 420         if (!in)
 421                 return -ENOMEM;
 422
 423         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 424
 425         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 426         MLX5_SET(rqc, rqc, state, next_state);
 427
 428         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 429
 430         kvfree(in);
 431
 432         return err;
 433 }
 434
 435 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 436 {
 437         struct mlx5e_channel *c = rq->channel;
 438         struct mlx5e_priv *priv = c->priv;
 439         struct mlx5_core_dev *mdev = priv->mdev;
 440
 441         void *in;
 442         void *rqc;
 443         int inlen;
 444         int err;
 445
 446         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 447         in = mlx5_vzalloc(inlen);
 448         if (!in)
 449                 return -ENOMEM;
 450
 451         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 452
 453         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 454         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 455         MLX5_SET(rqc, rqc, vsd, vsd);
 456         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 457
 458         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 459
 460         kvfree(in);
 461
 462         return err;
 463 }
 464
 465 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 466 {
 467         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 468 }
 469
 470 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 471 {
 472         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 473         struct mlx5e_channel *c = rq->channel;
 474         struct mlx5e_priv *priv = c->priv;
 475         struct mlx5_wq_ll *wq = &rq->wq;
 476
 477         while (time_before(jiffies, exp_time)) {
 478                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 479                         return 0;
 480
 481                 msleep(20);
 482         }
 483
 484         return -ETIMEDOUT;
 485 }
 486
 487 static int mlx5e_open_rq(struct mlx5e_channel *c,
 488                          struct mlx5e_rq_param *param,
 489                          struct mlx5e_rq *rq)
 490 {
 491         struct mlx5e_sq *sq = &c->icosq;
 492         u16 pi = sq->pc & sq->wq.sz_m1;
 493         int err;
 494
 495         err = mlx5e_create_rq(c, param, rq);
 496         if (err)
 497                 return err;
 498
 499         err = mlx5e_enable_rq(rq, param);
 500         if (err)
 501                 goto err_destroy_rq;
 502
 503         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 504         if (err)
 505                 goto err_disable_rq;
 506
 507         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 508
 509         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 510         sq->ico_wqe_info[pi].num_wqebbs = 1;
 511         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 512
 513         return 0;
 514
 515 err_disable_rq:
 516         mlx5e_disable_rq(rq);
 517 err_destroy_rq:
 518         mlx5e_destroy_rq(rq);
 519
 520         return err;
 521 }
 522
 523 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 524 {
 525         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 526         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 527
 528         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 529         while (!mlx5_wq_ll_is_empty(&rq->wq))
 530                 msleep(20);
 531
 532         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 533         napi_synchronize(&rq->channel->napi);
 534
 535         mlx5e_disable_rq(rq);
 536         mlx5e_destroy_rq(rq);
 537 }
 538
 539 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 540 {
 541         kfree(sq->wqe_info);
 542         kfree(sq->dma_fifo);
 543         kfree(sq->skb);
 544 }
 545
 546 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 547 {
 548         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 549         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 550
 551         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 552         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 553                                     numa);
 554         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 555                                     numa);
 556
 557         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 558                 mlx5e_free_sq_db(sq);
 559                 return -ENOMEM;
 560         }
 561
 562         sq->dma_fifo_mask = df_sz - 1;
 563
 564         return 0;
 565 }
 566
 567 static int mlx5e_create_sq(struct mlx5e_channel *c,
 568                            int tc,
 569                            struct mlx5e_sq_param *param,
 570                            struct mlx5e_sq *sq)
 571 {
 572         struct mlx5e_priv *priv = c->priv;
 573         struct mlx5_core_dev *mdev = priv->mdev;
 574
 575         void *sqc = param->sqc;
 576         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 577         int err;
 578
 579         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 580         if (err)
 581                 return err;
 582
 583         param->wq.db_numa_node = cpu_to_node(c->cpu);
 584
 585         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 586                                  &sq->wq_ctrl);
 587         if (err)
 588                 goto err_unmap_free_uar;
 589
 590         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 591         if (sq->uar.bf_map) {
 592                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 593                 sq->uar_map = sq->uar.bf_map;
 594         } else {
 595                 sq->uar_map = sq->uar.map;
 596         }
 597         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 598         sq->max_inline  = param->max_inline;
 599
 600         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 601         if (err)
 602                 goto err_sq_wq_destroy;
 603
 604         if (param->icosq) {
 605                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 606
 607                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 608                                                 wq_sz,
 609                                                 GFP_KERNEL,
 610                                                 cpu_to_node(c->cpu));
 611                 if (!sq->ico_wqe_info) {
 612                         err = -ENOMEM;
 613                         goto err_free_sq_db;
 614                 }
 615         } else {
 616                 int txq_ix;
 617
 618                 txq_ix = c->ix + tc * priv->params.num_channels;
 619                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 620                 priv->txq_to_sq_map[txq_ix] = sq;
 621         }
 622
 623         sq->pdev      = c->pdev;
 624         sq->tstamp    = &priv->tstamp;
 625         sq->mkey_be   = c->mkey_be;
 626         sq->channel   = c;
 627         sq->tc        = tc;
 628         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 629         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 630
 631         return 0;
 632
 633 err_free_sq_db:
 634         mlx5e_free_sq_db(sq);
 635
 636 err_sq_wq_destroy:
 637         mlx5_wq_destroy(&sq->wq_ctrl);
 638
 639 err_unmap_free_uar:
 640         mlx5_unmap_free_uar(mdev, &sq->uar);
 641
 642         return err;
 643 }
 644
 645 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 646 {
 647         struct mlx5e_channel *c = sq->channel;
 648         struct mlx5e_priv *priv = c->priv;
 649
 650         kfree(sq->ico_wqe_info);
 651         mlx5e_free_sq_db(sq);
 652         mlx5_wq_destroy(&sq->wq_ctrl);
 653         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 654 }
 655
 656 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 657 {
 658         struct mlx5e_channel *c = sq->channel;
 659         struct mlx5e_priv *priv = c->priv;
 660         struct mlx5_core_dev *mdev = priv->mdev;
 661
 662         void *in;
 663         void *sqc;
 664         void *wq;
 665         int inlen;
 666         int err;
 667
 668         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 669                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 670         in = mlx5_vzalloc(inlen);
 671         if (!in)
 672                 return -ENOMEM;
 673
 674         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 675         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 676
 677         memcpy(sqc, param->sqc, sizeof(param->sqc));
 678
 679         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 680         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 681         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 682         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 683         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 684
 685         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 686         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 687         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 688                                           MLX5_ADAPTER_PAGE_SHIFT);
 689         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 690
 691         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 692                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 693
 694         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 695
 696         kvfree(in);
 697
 698         return err;
 699 }
 700
 701 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 702 {
 703         struct mlx5e_channel *c = sq->channel;
 704         struct mlx5e_priv *priv = c->priv;
 705         struct mlx5_core_dev *mdev = priv->mdev;
 706
 707         void *in;
 708         void *sqc;
 709         int inlen;
 710         int err;
 711
 712         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 713         in = mlx5_vzalloc(inlen);
 714         if (!in)
 715                 return -ENOMEM;
 716
 717         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 718
 719         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 720         MLX5_SET(sqc, sqc, state, next_state);
 721
 722         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 723
 724         kvfree(in);
 725
 726         return err;
 727 }
 728
 729 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 730 {
 731         struct mlx5e_channel *c = sq->channel;
 732         struct mlx5e_priv *priv = c->priv;
 733         struct mlx5_core_dev *mdev = priv->mdev;
 734
 735         mlx5_core_destroy_sq(mdev, sq->sqn);
 736 }
 737
 738 static int mlx5e_open_sq(struct mlx5e_channel *c,
 739                          int tc,
 740                          struct mlx5e_sq_param *param,
 741                          struct mlx5e_sq *sq)
 742 {
 743         int err;
 744
 745         err = mlx5e_create_sq(c, tc, param, sq);
 746         if (err)
 747                 return err;
 748
 749         err = mlx5e_enable_sq(sq, param);
 750         if (err)
 751                 goto err_destroy_sq;
 752
 753         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 754         if (err)
 755                 goto err_disable_sq;
 756
 757         if (sq->txq) {
 758                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 759                 netdev_tx_reset_queue(sq->txq);
 760                 netif_tx_start_queue(sq->txq);
 761         }
 762
 763         return 0;
 764
 765 err_disable_sq:
 766         mlx5e_disable_sq(sq);
 767 err_destroy_sq:
 768         mlx5e_destroy_sq(sq);
 769
 770         return err;
 771 }
 772
 773 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 774 {
 775         __netif_tx_lock_bh(txq);
 776         netif_tx_stop_queue(txq);
 777         __netif_tx_unlock_bh(txq);
 778 }
 779
 780 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 781 {
 782         if (sq->txq) {
 783                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 784                 /* prevent netif_tx_wake_queue */
 785                 napi_synchronize(&sq->channel->napi);
 786                 netif_tx_disable_queue(sq->txq);
 787
 788                 /* ensure hw is notified of all pending wqes */
 789                 if (mlx5e_sq_has_room_for(sq, 1))
 790                         mlx5e_send_nop(sq, true);
 791
 792                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 793         }
 794
 795         while (sq->cc != sq->pc) /* wait till sq is empty */
 796                 msleep(20);
 797
 798         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 799         napi_synchronize(&sq->channel->napi);
 800
 801         mlx5e_disable_sq(sq);
 802         mlx5e_destroy_sq(sq);
 803 }
 804
 805 static int mlx5e_create_cq(struct mlx5e_channel *c,
 806                            struct mlx5e_cq_param *param,
 807                            struct mlx5e_cq *cq)
 808 {
 809         struct mlx5e_priv *priv = c->priv;
 810         struct mlx5_core_dev *mdev = priv->mdev;
 811         struct mlx5_core_cq *mcq = &cq->mcq;
 812         int eqn_not_used;
 813         unsigned int irqn;
 814         int err;
 815         u32 i;
 816
 817         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 818         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 819         param->eq_ix   = c->ix;
 820
 821         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 822                                &cq->wq_ctrl);
 823         if (err)
 824                 return err;
 825
 826         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 827
 828         cq->napi        = &c->napi;
 829
 830         mcq->cqe_sz     = 64;
 831         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 832         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 833         *mcq->set_ci_db = 0;
 834         *mcq->arm_db    = 0;
 835         mcq->vector     = param->eq_ix;
 836         mcq->comp       = mlx5e_completion_event;
 837         mcq->event      = mlx5e_cq_error_event;
 838         mcq->irqn       = irqn;
 839         mcq->uar        = &priv->cq_uar;
 840
 841         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 842                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 843
 844                 cqe->op_own = 0xf1;
 845         }
 846
 847         cq->channel = c;
 848         cq->priv = priv;
 849
 850         return 0;
 851 }
 852
 853 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 854 {
 855         mlx5_wq_destroy(&cq->wq_ctrl);
 856 }
 857
 858 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 859 {
 860         struct mlx5e_priv *priv = cq->priv;
 861         struct mlx5_core_dev *mdev = priv->mdev;
 862         struct mlx5_core_cq *mcq = &cq->mcq;
 863
 864         void *in;
 865         void *cqc;
 866         int inlen;
 867         unsigned int irqn_not_used;
 868         int eqn;
 869         int err;
 870
 871         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 872                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 873         in = mlx5_vzalloc(inlen);
 874         if (!in)
 875                 return -ENOMEM;
 876
 877         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 878
 879         memcpy(cqc, param->cqc, sizeof(param->cqc));
 880
 881         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 882                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 883
 884         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 885
 886         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 887         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 888         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 889                                             MLX5_ADAPTER_PAGE_SHIFT);
 890         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 891
 892         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 893
 894         kvfree(in);
 895
 896         if (err)
 897                 return err;
 898
 899         mlx5e_cq_arm(cq);
 900
 901         return 0;
 902 }
 903
 904 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 905 {
 906         struct mlx5e_priv *priv = cq->priv;
 907         struct mlx5_core_dev *mdev = priv->mdev;
 908
 909         mlx5_core_destroy_cq(mdev, &cq->mcq);
 910 }
 911
 912 static int mlx5e_open_cq(struct mlx5e_channel *c,
 913                          struct mlx5e_cq_param *param,
 914                          struct mlx5e_cq *cq,
 915                          u16 moderation_usecs,
 916                          u16 moderation_frames)
 917 {
 918         int err;
 919         struct mlx5e_priv *priv = c->priv;
 920         struct mlx5_core_dev *mdev = priv->mdev;
 921
 922         err = mlx5e_create_cq(c, param, cq);
 923         if (err)
 924                 return err;
 925
 926         err = mlx5e_enable_cq(cq, param);
 927         if (err)
 928                 goto err_destroy_cq;
 929
 930         if (MLX5_CAP_GEN(mdev, cq_moderation))
 931                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 932                                                moderation_usecs,
 933                                                moderation_frames);
 934         return 0;
 935
 936 err_destroy_cq:
 937         mlx5e_destroy_cq(cq);
 938
 939         return err;
 940 }
 941
 942 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 943 {
 944         mlx5e_disable_cq(cq);
 945         mlx5e_destroy_cq(cq);
 946 }
 947
 948 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 949 {
 950         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 951 }
 952
 953 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 954                              struct mlx5e_channel_param *cparam)
 955 {
 956         struct mlx5e_priv *priv = c->priv;
 957         int err;
 958         int tc;
 959
 960         for (tc = 0; tc < c->num_tc; tc++) {
 961                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 962                                     priv->params.tx_cq_moderation_usec,
 963                                     priv->params.tx_cq_moderation_pkts);
 964                 if (err)
 965                         goto err_close_tx_cqs;
 966         }
 967
 968         return 0;
 969
 970 err_close_tx_cqs:
 971         for (tc--; tc >= 0; tc--)
 972                 mlx5e_close_cq(&c->sq[tc].cq);
 973
 974         return err;
 975 }
 976
 977 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 978 {
 979         int tc;
 980
 981         for (tc = 0; tc < c->num_tc; tc++)
 982                 mlx5e_close_cq(&c->sq[tc].cq);
 983 }
 984
 985 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 986                           struct mlx5e_channel_param *cparam)
 987 {
 988         int err;
 989         int tc;
 990
 991         for (tc = 0; tc < c->num_tc; tc++) {
 992                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 993                 if (err)
 994                         goto err_close_sqs;
 995         }
 996
 997         return 0;
 998
 999 err_close_sqs:
1000         for (tc--; tc >= 0; tc--)
1001                 mlx5e_close_sq(&c->sq[tc]);
1002
1003         return err;
1004 }
1005
1006 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1007 {
1008         int tc;
1009
1010         for (tc = 0; tc < c->num_tc; tc++)
1011                 mlx5e_close_sq(&c->sq[tc]);
1012 }
1013
1014 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1015 {
1016         int i;
1017
1018         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1019                 priv->channeltc_to_txq_map[ix][i] =
1020                         ix + i * priv->params.num_channels;
1021 }
1022
1023 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1024                               struct mlx5e_channel_param *cparam,
1025                               struct mlx5e_channel **cp)
1026 {
1027         struct net_device *netdev = priv->netdev;
1028         int cpu = mlx5e_get_cpu(priv, ix);
1029         struct mlx5e_channel *c;
1030         int err;
1031
1032         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1033         if (!c)
1034                 return -ENOMEM;
1035
1036         c->priv     = priv;
1037         c->ix       = ix;
1038         c->cpu      = cpu;
1039         c->pdev     = &priv->mdev->pdev->dev;
1040         c->netdev   = priv->netdev;
1041         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1042         c->num_tc   = priv->params.num_tc;
1043
1044         mlx5e_build_channeltc_to_txq_map(priv, ix);
1045
1046         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1047
1048         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1049         if (err)
1050                 goto err_napi_del;
1051
1052         err = mlx5e_open_tx_cqs(c, cparam);
1053         if (err)
1054                 goto err_close_icosq_cq;
1055
1056         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1057                             priv->params.rx_cq_moderation_usec,
1058                             priv->params.rx_cq_moderation_pkts);
1059         if (err)
1060                 goto err_close_tx_cqs;
1061
1062         napi_enable(&c->napi);
1063
1064         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1065         if (err)
1066                 goto err_disable_napi;
1067
1068         err = mlx5e_open_sqs(c, cparam);
1069         if (err)
1070                 goto err_close_icosq;
1071
1072         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1073         if (err)
1074                 goto err_close_sqs;
1075
1076         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1077         *cp = c;
1078
1079         return 0;
1080
1081 err_close_sqs:
1082         mlx5e_close_sqs(c);
1083
1084 err_close_icosq:
1085         mlx5e_close_sq(&c->icosq);
1086
1087 err_disable_napi:
1088         napi_disable(&c->napi);
1089         mlx5e_close_cq(&c->rq.cq);
1090
1091 err_close_tx_cqs:
1092         mlx5e_close_tx_cqs(c);
1093
1094 err_close_icosq_cq:
1095         mlx5e_close_cq(&c->icosq.cq);
1096
1097 err_napi_del:
1098         netif_napi_del(&c->napi);
1099         napi_hash_del(&c->napi);
1100         kfree(c);
1101
1102         return err;
1103 }
1104
1105 static void mlx5e_close_channel(struct mlx5e_channel *c)
1106 {
1107         mlx5e_close_rq(&c->rq);
1108         mlx5e_close_sqs(c);
1109         mlx5e_close_sq(&c->icosq);
1110         napi_disable(&c->napi);
1111         mlx5e_close_cq(&c->rq.cq);
1112         mlx5e_close_tx_cqs(c);
1113         mlx5e_close_cq(&c->icosq.cq);
1114         netif_napi_del(&c->napi);
1115
1116         napi_hash_del(&c->napi);
1117         synchronize_rcu();
1118
1119         kfree(c);
1120 }
1121
1122 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1123                                  struct mlx5e_rq_param *param)
1124 {
1125         void *rqc = param->rqc;
1126         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1127
1128         switch (priv->params.rq_wq_type) {
1129         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1130                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1131                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1132                 MLX5_SET(wq, wq, log_wqe_stride_size,
1133                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1134                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1135                 break;
1136         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1137                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1138         }
1139
1140         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1141         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1142         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1143         MLX5_SET(wq, wq, pd,               priv->pdn);
1144         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1145
1146         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1147         param->wq.linear = 1;
1148 }
1149
1150 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1151 {
1152         void *rqc = param->rqc;
1153         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1154
1155         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1156         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1157 }
1158
1159 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1160                                         struct mlx5e_sq_param *param)
1161 {
1162         void *sqc = param->sqc;
1163         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1164
1165         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1166         MLX5_SET(wq, wq, pd,            priv->pdn);
1167
1168         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1169 }
1170
1171 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1172                                  struct mlx5e_sq_param *param)
1173 {
1174         void *sqc = param->sqc;
1175         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1176
1177         mlx5e_build_sq_param_common(priv, param);
1178         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1179
1180         param->max_inline = priv->params.tx_max_inline;
1181 }
1182
1183 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1184                                         struct mlx5e_cq_param *param)
1185 {
1186         void *cqc = param->cqc;
1187
1188         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1189 }
1190
1191 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1192                                     struct mlx5e_cq_param *param)
1193 {
1194         void *cqc = param->cqc;
1195         u8 log_cq_size;
1196
1197         switch (priv->params.rq_wq_type) {
1198         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1199                 log_cq_size = priv->params.log_rq_size +
1200                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1201                 break;
1202         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1203                 log_cq_size = priv->params.log_rq_size;
1204         }
1205
1206         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1207
1208         mlx5e_build_common_cq_param(priv, param);
1209 }
1210
1211 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1212                                     struct mlx5e_cq_param *param)
1213 {
1214         void *cqc = param->cqc;
1215
1216         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1217
1218         mlx5e_build_common_cq_param(priv, param);
1219 }
1220
1221 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1222                                      struct mlx5e_cq_param *param,
1223                                      u8 log_wq_size)
1224 {
1225         void *cqc = param->cqc;
1226
1227         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1228
1229         mlx5e_build_common_cq_param(priv, param);
1230 }
1231
1232 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1233                                     struct mlx5e_sq_param *param,
1234                                     u8 log_wq_size)
1235 {
1236         void *sqc = param->sqc;
1237         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1238
1239         mlx5e_build_sq_param_common(priv, param);
1240
1241         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1242         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1243
1244         param->icosq = true;
1245 }
1246
1247 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1248                                       struct mlx5e_channel_param *cparam)
1249 {
1250         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1251
1252         memset(cparam, 0, sizeof(*cparam));
1253
1254         mlx5e_build_rq_param(priv, &cparam->rq);
1255         mlx5e_build_sq_param(priv, &cparam->sq);
1256         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1257         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1258         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1259         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1260 }
1261
1262 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1263 {
1264         struct mlx5e_channel_param cparam;
1265         int nch = priv->params.num_channels;
1266         int err = -ENOMEM;
1267         int i;
1268         int j;
1269
1270         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1271                                 GFP_KERNEL);
1272
1273         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1274                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1275
1276         if (!priv->channel || !priv->txq_to_sq_map)
1277                 goto err_free_txq_to_sq_map;
1278
1279         mlx5e_build_channel_param(priv, &cparam);
1280         for (i = 0; i < nch; i++) {
1281                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1282                 if (err)
1283                         goto err_close_channels;
1284         }
1285
1286         for (j = 0; j < nch; j++) {
1287                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1288                 if (err)
1289                         goto err_close_channels;
1290         }
1291
1292         return 0;
1293
1294 err_close_channels:
1295         for (i--; i >= 0; i--)
1296                 mlx5e_close_channel(priv->channel[i]);
1297
1298 err_free_txq_to_sq_map:
1299         kfree(priv->txq_to_sq_map);
1300         kfree(priv->channel);
1301
1302         return err;
1303 }
1304
1305 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1306 {
1307         int i;
1308
1309         for (i = 0; i < priv->params.num_channels; i++)
1310                 mlx5e_close_channel(priv->channel[i]);
1311
1312         kfree(priv->txq_to_sq_map);
1313         kfree(priv->channel);
1314 }
1315
1316 static int mlx5e_rx_hash_fn(int hfunc)
1317 {
1318         return (hfunc == ETH_RSS_HASH_TOP) ?
1319                MLX5_RX_HASH_FN_TOEPLITZ :
1320                MLX5_RX_HASH_FN_INVERTED_XOR8;
1321 }
1322
1323 static int mlx5e_bits_invert(unsigned long a, int size)
1324 {
1325         int inv = 0;
1326         int i;
1327
1328         for (i = 0; i < size; i++)
1329                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1330
1331         return inv;
1332 }
1333
1334 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1335 {
1336         int i;
1337
1338         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1339                 int ix = i;
1340
1341                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1342                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1343
1344                 ix = priv->params.indirection_rqt[ix];
1345                 MLX5_SET(rqtc, rqtc, rq_num[i],
1346                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1347                          priv->channel[ix]->rq.rqn :
1348                          priv->drop_rq.rqn);
1349         }
1350 }
1351
1352 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1353                                 enum mlx5e_rqt_ix rqt_ix)
1354 {
1355
1356         switch (rqt_ix) {
1357         case MLX5E_INDIRECTION_RQT:
1358                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1359
1360                 break;
1361
1362         default: /* MLX5E_SINGLE_RQ_RQT */
1363                 MLX5_SET(rqtc, rqtc, rq_num[0],
1364                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1365                          priv->channel[0]->rq.rqn :
1366                          priv->drop_rq.rqn);
1367
1368                 break;
1369         }
1370 }
1371
1372 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1373 {
1374         struct mlx5_core_dev *mdev = priv->mdev;
1375         u32 *in;
1376         void *rqtc;
1377         int inlen;
1378         int sz;
1379         int err;
1380
1381         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1382
1383         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1384         in = mlx5_vzalloc(inlen);
1385         if (!in)
1386                 return -ENOMEM;
1387
1388         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1389
1390         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1391         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1392
1393         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1394
1395         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1396
1397         kvfree(in);
1398
1399         return err;
1400 }
1401
1402 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1403 {
1404         struct mlx5_core_dev *mdev = priv->mdev;
1405         u32 *in;
1406         void *rqtc;
1407         int inlen;
1408         int sz;
1409         int err;
1410
1411         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1412
1413         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1414         in = mlx5_vzalloc(inlen);
1415         if (!in)
1416                 return -ENOMEM;
1417
1418         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1419
1420         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1421
1422         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1423
1424         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1425
1426         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1427
1428         kvfree(in);
1429
1430         return err;
1431 }
1432
1433 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1434 {
1435         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1436 }
1437
1438 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1439 {
1440         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1441         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1442 }
1443
1444 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1445 {
1446         if (!priv->params.lro_en)
1447                 return;
1448
1449 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1450
1451         MLX5_SET(tirc, tirc, lro_enable_mask,
1452                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1453                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1454         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1455                  (priv->params.lro_wqe_sz -
1456                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1457         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1458                  MLX5_CAP_ETH(priv->mdev,
1459                               lro_timer_supported_periods[2]));
1460 }
1461
1462 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1463 {
1464         MLX5_SET(tirc, tirc, rx_hash_fn,
1465                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1466         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1467                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1468                                              rx_hash_toeplitz_key);
1469                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1470                                                rx_hash_toeplitz_key);
1471
1472                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1473                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1474         }
1475 }
1476
1477 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1478 {
1479         struct mlx5_core_dev *mdev = priv->mdev;
1480
1481         void *in;
1482         void *tirc;
1483         int inlen;
1484         int err;
1485         int tt;
1486
1487         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1488         in = mlx5_vzalloc(inlen);
1489         if (!in)
1490                 return -ENOMEM;
1491
1492         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1493         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1494
1495         mlx5e_build_tir_ctx_lro(tirc, priv);
1496
1497         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1498                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1499                 if (err)
1500                         break;
1501         }
1502
1503         kvfree(in);
1504
1505         return err;
1506 }
1507
1508 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1509                                                   u32 tirn)
1510 {
1511         void *in;
1512         int inlen;
1513         int err;
1514
1515         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1516         in = mlx5_vzalloc(inlen);
1517         if (!in)
1518                 return -ENOMEM;
1519
1520         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1521
1522         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1523
1524         kvfree(in);
1525
1526         return err;
1527 }
1528
1529 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1530 {
1531         int err;
1532         int i;
1533
1534         for (i = 0; i < MLX5E_NUM_TT; i++) {
1535                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1536                                                              priv->tirn[i]);
1537                 if (err)
1538                         return err;
1539         }
1540
1541         return 0;
1542 }
1543
1544 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1545 {
1546         struct mlx5e_priv *priv = netdev_priv(netdev);
1547         struct mlx5_core_dev *mdev = priv->mdev;
1548         int hw_mtu;
1549         int err;
1550
1551         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1552         if (err)
1553                 return err;
1554
1555         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1556
1557         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1558                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1559                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1560
1561         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1562         return 0;
1563 }
1564
1565 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1566 {
1567         struct mlx5e_priv *priv = netdev_priv(netdev);
1568         int nch = priv->params.num_channels;
1569         int ntc = priv->params.num_tc;
1570         int tc;
1571
1572         netdev_reset_tc(netdev);
1573
1574         if (ntc == 1)
1575                 return;
1576
1577         netdev_set_num_tc(netdev, ntc);
1578
1579         for (tc = 0; tc < ntc; tc++)
1580                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1581 }
1582
1583 int mlx5e_open_locked(struct net_device *netdev)
1584 {
1585         struct mlx5e_priv *priv = netdev_priv(netdev);
1586         int num_txqs;
1587         int err;
1588
1589         set_bit(MLX5E_STATE_OPENED, &priv->state);
1590
1591         mlx5e_netdev_set_tcs(netdev);
1592
1593         num_txqs = priv->params.num_channels * priv->params.num_tc;
1594         netif_set_real_num_tx_queues(netdev, num_txqs);
1595         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1596
1597         err = mlx5e_set_dev_port_mtu(netdev);
1598         if (err)
1599                 goto err_clear_state_opened_flag;
1600
1601         err = mlx5e_open_channels(priv);
1602         if (err) {
1603                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1604                            __func__, err);
1605                 goto err_clear_state_opened_flag;
1606         }
1607
1608         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1609         if (err) {
1610                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1611                            __func__, err);
1612                 goto err_close_channels;
1613         }
1614
1615         mlx5e_redirect_rqts(priv);
1616         mlx5e_update_carrier(priv);
1617         mlx5e_timestamp_init(priv);
1618
1619         schedule_delayed_work(&priv->update_stats_work, 0);
1620
1621         return 0;
1622
1623 err_close_channels:
1624         mlx5e_close_channels(priv);
1625 err_clear_state_opened_flag:
1626         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1627         return err;
1628 }
1629
1630 static int mlx5e_open(struct net_device *netdev)
1631 {
1632         struct mlx5e_priv *priv = netdev_priv(netdev);
1633         int err;
1634
1635         mutex_lock(&priv->state_lock);
1636         err = mlx5e_open_locked(netdev);
1637         mutex_unlock(&priv->state_lock);
1638
1639         return err;
1640 }
1641
1642 int mlx5e_close_locked(struct net_device *netdev)
1643 {
1644         struct mlx5e_priv *priv = netdev_priv(netdev);
1645
1646         /* May already be CLOSED in case a previous configuration operation
1647          * (e.g RX/TX queue size change) that involves close&open failed.
1648          */
1649         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1650                 return 0;
1651
1652         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1653
1654         mlx5e_timestamp_cleanup(priv);
1655         netif_carrier_off(priv->netdev);
1656         mlx5e_redirect_rqts(priv);
1657         mlx5e_close_channels(priv);
1658
1659         return 0;
1660 }
1661
1662 static int mlx5e_close(struct net_device *netdev)
1663 {
1664         struct mlx5e_priv *priv = netdev_priv(netdev);
1665         int err;
1666
1667         mutex_lock(&priv->state_lock);
1668         err = mlx5e_close_locked(netdev);
1669         mutex_unlock(&priv->state_lock);
1670
1671         return err;
1672 }
1673
1674 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1675                                 struct mlx5e_rq *rq,
1676                                 struct mlx5e_rq_param *param)
1677 {
1678         struct mlx5_core_dev *mdev = priv->mdev;
1679         void *rqc = param->rqc;
1680         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1681         int err;
1682
1683         param->wq.db_numa_node = param->wq.buf_numa_node;
1684
1685         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1686                                 &rq->wq_ctrl);
1687         if (err)
1688                 return err;
1689
1690         rq->priv = priv;
1691
1692         return 0;
1693 }
1694
1695 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1696                                 struct mlx5e_cq *cq,
1697                                 struct mlx5e_cq_param *param)
1698 {
1699         struct mlx5_core_dev *mdev = priv->mdev;
1700         struct mlx5_core_cq *mcq = &cq->mcq;
1701         int eqn_not_used;
1702         unsigned int irqn;
1703         int err;
1704
1705         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1706                                &cq->wq_ctrl);
1707         if (err)
1708                 return err;
1709
1710         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1711
1712         mcq->cqe_sz     = 64;
1713         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1714         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1715         *mcq->set_ci_db = 0;
1716         *mcq->arm_db    = 0;
1717         mcq->vector     = param->eq_ix;
1718         mcq->comp       = mlx5e_completion_event;
1719         mcq->event      = mlx5e_cq_error_event;
1720         mcq->irqn       = irqn;
1721         mcq->uar        = &priv->cq_uar;
1722
1723         cq->priv = priv;
1724
1725         return 0;
1726 }
1727
1728 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1729 {
1730         struct mlx5e_cq_param cq_param;
1731         struct mlx5e_rq_param rq_param;
1732         struct mlx5e_rq *rq = &priv->drop_rq;
1733         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1734         int err;
1735
1736         memset(&cq_param, 0, sizeof(cq_param));
1737         memset(&rq_param, 0, sizeof(rq_param));
1738         mlx5e_build_drop_rq_param(&rq_param);
1739
1740         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1741         if (err)
1742                 return err;
1743
1744         err = mlx5e_enable_cq(cq, &cq_param);
1745         if (err)
1746                 goto err_destroy_cq;
1747
1748         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1749         if (err)
1750                 goto err_disable_cq;
1751
1752         err = mlx5e_enable_rq(rq, &rq_param);
1753         if (err)
1754                 goto err_destroy_rq;
1755
1756         return 0;
1757
1758 err_destroy_rq:
1759         mlx5e_destroy_rq(&priv->drop_rq);
1760
1761 err_disable_cq:
1762         mlx5e_disable_cq(&priv->drop_rq.cq);
1763
1764 err_destroy_cq:
1765         mlx5e_destroy_cq(&priv->drop_rq.cq);
1766
1767         return err;
1768 }
1769
1770 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1771 {
1772         mlx5e_disable_rq(&priv->drop_rq);
1773         mlx5e_destroy_rq(&priv->drop_rq);
1774         mlx5e_disable_cq(&priv->drop_rq.cq);
1775         mlx5e_destroy_cq(&priv->drop_rq.cq);
1776 }
1777
1778 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1779 {
1780         struct mlx5_core_dev *mdev = priv->mdev;
1781         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1782         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1783
1784         memset(in, 0, sizeof(in));
1785
1786         MLX5_SET(tisc, tisc, prio, tc << 1);
1787         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1788
1789         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1790 }
1791
1792 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1793 {
1794         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1795 }
1796
1797 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1798 {
1799         int err;
1800         int tc;
1801
1802         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1803                 err = mlx5e_create_tis(priv, tc);
1804                 if (err)
1805                         goto err_close_tises;
1806         }
1807
1808         return 0;
1809
1810 err_close_tises:
1811         for (tc--; tc >= 0; tc--)
1812                 mlx5e_destroy_tis(priv, tc);
1813
1814         return err;
1815 }
1816
1817 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1818 {
1819         int tc;
1820
1821         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1822                 mlx5e_destroy_tis(priv, tc);
1823 }
1824
1825 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1826 {
1827         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1828
1829         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1830
1831 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1832                                  MLX5_HASH_FIELD_SEL_DST_IP)
1833
1834 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1835                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1836                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1837                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1838
1839 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1840                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1841                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1842
1843         mlx5e_build_tir_ctx_lro(tirc, priv);
1844
1845         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1846
1847         switch (tt) {
1848         case MLX5E_TT_ANY:
1849                 MLX5_SET(tirc, tirc, indirect_table,
1850                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1851                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1852                 break;
1853         default:
1854                 MLX5_SET(tirc, tirc, indirect_table,
1855                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1856                 mlx5e_build_tir_ctx_hash(tirc, priv);
1857                 break;
1858         }
1859
1860         switch (tt) {
1861         case MLX5E_TT_IPV4_TCP:
1862                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1863                          MLX5_L3_PROT_TYPE_IPV4);
1864                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1865                          MLX5_L4_PROT_TYPE_TCP);
1866                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1867                          MLX5_HASH_IP_L4PORTS);
1868                 break;
1869
1870         case MLX5E_TT_IPV6_TCP:
1871                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1872                          MLX5_L3_PROT_TYPE_IPV6);
1873                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1874                          MLX5_L4_PROT_TYPE_TCP);
1875                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1876                          MLX5_HASH_IP_L4PORTS);
1877                 break;
1878
1879         case MLX5E_TT_IPV4_UDP:
1880                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1881                          MLX5_L3_PROT_TYPE_IPV4);
1882                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1883                          MLX5_L4_PROT_TYPE_UDP);
1884                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1885                          MLX5_HASH_IP_L4PORTS);
1886                 break;
1887
1888         case MLX5E_TT_IPV6_UDP:
1889                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1890                          MLX5_L3_PROT_TYPE_IPV6);
1891                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1892                          MLX5_L4_PROT_TYPE_UDP);
1893                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1894                          MLX5_HASH_IP_L4PORTS);
1895                 break;
1896
1897         case MLX5E_TT_IPV4_IPSEC_AH:
1898                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1899                          MLX5_L3_PROT_TYPE_IPV4);
1900                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1901                          MLX5_HASH_IP_IPSEC_SPI);
1902                 break;
1903
1904         case MLX5E_TT_IPV6_IPSEC_AH:
1905                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1906                          MLX5_L3_PROT_TYPE_IPV6);
1907                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1908                          MLX5_HASH_IP_IPSEC_SPI);
1909                 break;
1910
1911         case MLX5E_TT_IPV4_IPSEC_ESP:
1912                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1913                          MLX5_L3_PROT_TYPE_IPV4);
1914                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1915                          MLX5_HASH_IP_IPSEC_SPI);
1916                 break;
1917
1918         case MLX5E_TT_IPV6_IPSEC_ESP:
1919                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1920                          MLX5_L3_PROT_TYPE_IPV6);
1921                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1922                          MLX5_HASH_IP_IPSEC_SPI);
1923                 break;
1924
1925         case MLX5E_TT_IPV4:
1926                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1927                          MLX5_L3_PROT_TYPE_IPV4);
1928                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1929                          MLX5_HASH_IP);
1930                 break;
1931
1932         case MLX5E_TT_IPV6:
1933                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1934                          MLX5_L3_PROT_TYPE_IPV6);
1935                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1936                          MLX5_HASH_IP);
1937                 break;
1938         }
1939 }
1940
1941 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1942 {
1943         struct mlx5_core_dev *mdev = priv->mdev;
1944         u32 *in;
1945         void *tirc;
1946         int inlen;
1947         int err;
1948
1949         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1950         in = mlx5_vzalloc(inlen);
1951         if (!in)
1952                 return -ENOMEM;
1953
1954         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1955
1956         mlx5e_build_tir_ctx(priv, tirc, tt);
1957
1958         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1959
1960         kvfree(in);
1961
1962         return err;
1963 }
1964
1965 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1966 {
1967         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1968 }
1969
1970 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1971 {
1972         int err;
1973         int i;
1974
1975         for (i = 0; i < MLX5E_NUM_TT; i++) {
1976                 err = mlx5e_create_tir(priv, i);
1977                 if (err)
1978                         goto err_destroy_tirs;
1979         }
1980
1981         return 0;
1982
1983 err_destroy_tirs:
1984         for (i--; i >= 0; i--)
1985                 mlx5e_destroy_tir(priv, i);
1986
1987         return err;
1988 }
1989
1990 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1991 {
1992         int i;
1993
1994         for (i = 0; i < MLX5E_NUM_TT; i++)
1995                 mlx5e_destroy_tir(priv, i);
1996 }
1997
1998 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
1999 {
2000         int err = 0;
2001         int i;
2002
2003         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2004                 return 0;
2005
2006         for (i = 0; i < priv->params.num_channels; i++) {
2007                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2008                 if (err)
2009                         return err;
2010         }
2011
2012         return 0;
2013 }
2014
2015 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2016 {
2017         struct mlx5e_priv *priv = netdev_priv(netdev);
2018         bool was_opened;
2019         int err = 0;
2020
2021         if (tc && tc != MLX5E_MAX_NUM_TC)
2022                 return -EINVAL;
2023
2024         mutex_lock(&priv->state_lock);
2025
2026         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2027         if (was_opened)
2028                 mlx5e_close_locked(priv->netdev);
2029
2030         priv->params.num_tc = tc ? tc : 1;
2031
2032         if (was_opened)
2033                 err = mlx5e_open_locked(priv->netdev);
2034
2035         mutex_unlock(&priv->state_lock);
2036
2037         return err;
2038 }
2039
2040 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2041                               __be16 proto, struct tc_to_netdev *tc)
2042 {
2043         struct mlx5e_priv *priv = netdev_priv(dev);
2044
2045         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2046                 goto mqprio;
2047
2048         switch (tc->type) {
2049         case TC_SETUP_CLSFLOWER:
2050                 switch (tc->cls_flower->command) {
2051                 case TC_CLSFLOWER_REPLACE:
2052                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2053                 case TC_CLSFLOWER_DESTROY:
2054                         return mlx5e_delete_flower(priv, tc->cls_flower);
2055                 }
2056         default:
2057                 return -EOPNOTSUPP;
2058         }
2059
2060 mqprio:
2061         if (tc->type != TC_SETUP_MQPRIO)
2062                 return -EINVAL;
2063
2064         return mlx5e_setup_tc(dev, tc->tc);
2065 }
2066
2067 static struct rtnl_link_stats64 *
2068 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2069 {
2070         struct mlx5e_priv *priv = netdev_priv(dev);
2071         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2072         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2073         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2074
2075         stats->rx_packets = sstats->rx_packets;
2076         stats->rx_bytes   = sstats->rx_bytes;
2077         stats->tx_packets = sstats->tx_packets;
2078         stats->tx_bytes   = sstats->tx_bytes;
2079
2080         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2081         stats->tx_dropped = sstats->tx_queue_dropped;
2082
2083         stats->rx_length_errors =
2084                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2085                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2086                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2087         stats->rx_crc_errors =
2088                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2089         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2090         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2091         stats->tx_carrier_errors =
2092                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2093         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2094                            stats->rx_frame_errors;
2095         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2096
2097         /* vport multicast also counts packets that are dropped due to steering
2098          * or rx out of buffer
2099          */
2100         stats->multicast =
2101                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2102
2103         return stats;
2104 }
2105
2106 static void mlx5e_set_rx_mode(struct net_device *dev)
2107 {
2108         struct mlx5e_priv *priv = netdev_priv(dev);
2109
2110         schedule_work(&priv->set_rx_mode_work);
2111 }
2112
2113 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2114 {
2115         struct mlx5e_priv *priv = netdev_priv(netdev);
2116         struct sockaddr *saddr = addr;
2117
2118         if (!is_valid_ether_addr(saddr->sa_data))
2119                 return -EADDRNOTAVAIL;
2120
2121         netif_addr_lock_bh(netdev);
2122         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2123         netif_addr_unlock_bh(netdev);
2124
2125         schedule_work(&priv->set_rx_mode_work);
2126
2127         return 0;
2128 }
2129
2130 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2131         do {                                            \
2132                 if (enable)                             \
2133                         netdev->features |= feature;    \
2134                 else                                    \
2135                         netdev->features &= ~feature;   \
2136         } while (0)
2137
2138 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2139
2140 static int set_feature_lro(struct net_device *netdev, bool enable)
2141 {
2142         struct mlx5e_priv *priv = netdev_priv(netdev);
2143         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2144         int err;
2145
2146         mutex_lock(&priv->state_lock);
2147
2148         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2149                 mlx5e_close_locked(priv->netdev);
2150
2151         priv->params.lro_en = enable;
2152         err = mlx5e_modify_tirs_lro(priv);
2153         if (err) {
2154                 netdev_err(netdev, "lro modify failed, %d\n", err);
2155                 priv->params.lro_en = !enable;
2156         }
2157
2158         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2159                 mlx5e_open_locked(priv->netdev);
2160
2161         mutex_unlock(&priv->state_lock);
2162
2163         return err;
2164 }
2165
2166 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2167 {
2168         struct mlx5e_priv *priv = netdev_priv(netdev);
2169
2170         if (enable)
2171                 mlx5e_enable_vlan_filter(priv);
2172         else
2173                 mlx5e_disable_vlan_filter(priv);
2174
2175         return 0;
2176 }
2177
2178 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2179 {
2180         struct mlx5e_priv *priv = netdev_priv(netdev);
2181
2182         if (!enable && mlx5e_tc_num_filters(priv)) {
2183                 netdev_err(netdev,
2184                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2185                 return -EINVAL;
2186         }
2187
2188         return 0;
2189 }
2190
2191 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2192 {
2193         struct mlx5e_priv *priv = netdev_priv(netdev);
2194         struct mlx5_core_dev *mdev = priv->mdev;
2195
2196         return mlx5_set_port_fcs(mdev, !enable);
2197 }
2198
2199 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2200 {
2201         struct mlx5e_priv *priv = netdev_priv(netdev);
2202         int err;
2203
2204         mutex_lock(&priv->state_lock);
2205
2206         priv->params.vlan_strip_disable = !enable;
2207         err = mlx5e_modify_rqs_vsd(priv, !enable);
2208         if (err)
2209                 priv->params.vlan_strip_disable = enable;
2210
2211         mutex_unlock(&priv->state_lock);
2212
2213         return err;
2214 }
2215
2216 static int mlx5e_handle_feature(struct net_device *netdev,
2217                                 netdev_features_t wanted_features,
2218                                 netdev_features_t feature,
2219                                 mlx5e_feature_handler feature_handler)
2220 {
2221         netdev_features_t changes = wanted_features ^ netdev->features;
2222         bool enable = !!(wanted_features & feature);
2223         int err;
2224
2225         if (!(changes & feature))
2226                 return 0;
2227
2228         err = feature_handler(netdev, enable);
2229         if (err) {
2230                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2231                            enable ? "Enable" : "Disable", feature, err);
2232                 return err;
2233         }
2234
2235         MLX5E_SET_FEATURE(netdev, feature, enable);
2236         return 0;
2237 }
2238
2239 static int mlx5e_set_features(struct net_device *netdev,
2240                               netdev_features_t features)
2241 {
2242         int err;
2243
2244         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2245                                     set_feature_lro);
2246         err |= mlx5e_handle_feature(netdev, features,
2247                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2248                                     set_feature_vlan_filter);
2249         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2250                                     set_feature_tc_num_filters);
2251         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2252                                     set_feature_rx_all);
2253         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2254                                     set_feature_rx_vlan);
2255
2256         return err ? -EINVAL : 0;
2257 }
2258
2259 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2260 {
2261         struct mlx5e_priv *priv = netdev_priv(netdev);
2262         struct mlx5_core_dev *mdev = priv->mdev;
2263         bool was_opened;
2264         int max_mtu;
2265         int err = 0;
2266
2267         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2268
2269         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2270
2271         if (new_mtu > max_mtu) {
2272                 netdev_err(netdev,
2273                            "%s: Bad MTU (%d) > (%d) Max\n",
2274                            __func__, new_mtu, max_mtu);
2275                 return -EINVAL;
2276         }
2277
2278         mutex_lock(&priv->state_lock);
2279
2280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2281         if (was_opened)
2282                 mlx5e_close_locked(netdev);
2283
2284         netdev->mtu = new_mtu;
2285
2286         if (was_opened)
2287                 err = mlx5e_open_locked(netdev);
2288
2289         mutex_unlock(&priv->state_lock);
2290
2291         return err;
2292 }
2293
2294 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2295 {
2296         switch (cmd) {
2297         case SIOCSHWTSTAMP:
2298                 return mlx5e_hwstamp_set(dev, ifr);
2299         case SIOCGHWTSTAMP:
2300                 return mlx5e_hwstamp_get(dev, ifr);
2301         default:
2302                 return -EOPNOTSUPP;
2303         }
2304 }
2305
2306 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2307 {
2308         struct mlx5e_priv *priv = netdev_priv(dev);
2309         struct mlx5_core_dev *mdev = priv->mdev;
2310
2311         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2312 }
2313
2314 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2315 {
2316         struct mlx5e_priv *priv = netdev_priv(dev);
2317         struct mlx5_core_dev *mdev = priv->mdev;
2318
2319         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2320                                            vlan, qos);
2321 }
2322
2323 static int mlx5_vport_link2ifla(u8 esw_link)
2324 {
2325         switch (esw_link) {
2326         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2327                 return IFLA_VF_LINK_STATE_DISABLE;
2328         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2329                 return IFLA_VF_LINK_STATE_ENABLE;
2330         }
2331         return IFLA_VF_LINK_STATE_AUTO;
2332 }
2333
2334 static int mlx5_ifla_link2vport(u8 ifla_link)
2335 {
2336         switch (ifla_link) {
2337         case IFLA_VF_LINK_STATE_DISABLE:
2338                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2339         case IFLA_VF_LINK_STATE_ENABLE:
2340                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2341         }
2342         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2343 }
2344
2345 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2346                                    int link_state)
2347 {
2348         struct mlx5e_priv *priv = netdev_priv(dev);
2349         struct mlx5_core_dev *mdev = priv->mdev;
2350
2351         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2352                                             mlx5_ifla_link2vport(link_state));
2353 }
2354
2355 static int mlx5e_get_vf_config(struct net_device *dev,
2356                                int vf, struct ifla_vf_info *ivi)
2357 {
2358         struct mlx5e_priv *priv = netdev_priv(dev);
2359         struct mlx5_core_dev *mdev = priv->mdev;
2360         int err;
2361
2362         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2363         if (err)
2364                 return err;
2365         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2366         return 0;
2367 }
2368
2369 static int mlx5e_get_vf_stats(struct net_device *dev,
2370                               int vf, struct ifla_vf_stats *vf_stats)
2371 {
2372         struct mlx5e_priv *priv = netdev_priv(dev);
2373         struct mlx5_core_dev *mdev = priv->mdev;
2374
2375         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2376                                             vf_stats);
2377 }
2378
2379 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2380                                  sa_family_t sa_family, __be16 port)
2381 {
2382         struct mlx5e_priv *priv = netdev_priv(netdev);
2383
2384         if (!mlx5e_vxlan_allowed(priv->mdev))
2385                 return;
2386
2387         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2388 }
2389
2390 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2391                                  sa_family_t sa_family, __be16 port)
2392 {
2393         struct mlx5e_priv *priv = netdev_priv(netdev);
2394
2395         if (!mlx5e_vxlan_allowed(priv->mdev))
2396                 return;
2397
2398         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2399 }
2400
2401 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2402                                                     struct sk_buff *skb,
2403                                                     netdev_features_t features)
2404 {
2405         struct udphdr *udph;
2406         u16 proto;
2407         u16 port = 0;
2408
2409         switch (vlan_get_protocol(skb)) {
2410         case htons(ETH_P_IP):
2411                 proto = ip_hdr(skb)->protocol;
2412                 break;
2413         case htons(ETH_P_IPV6):
2414                 proto = ipv6_hdr(skb)->nexthdr;
2415                 break;
2416         default:
2417                 goto out;
2418         }
2419
2420         if (proto == IPPROTO_UDP) {
2421                 udph = udp_hdr(skb);
2422                 port = be16_to_cpu(udph->dest);
2423         }
2424
2425         /* Verify if UDP port is being offloaded by HW */
2426         if (port && mlx5e_vxlan_lookup_port(priv, port))
2427                 return features;
2428
2429 out:
2430         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2431         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2432 }
2433
2434 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2435                                               struct net_device *netdev,
2436                                               netdev_features_t features)
2437 {
2438         struct mlx5e_priv *priv = netdev_priv(netdev);
2439
2440         features = vlan_features_check(skb, features);
2441         features = vxlan_features_check(skb, features);
2442
2443         /* Validate if the tunneled packet is being offloaded by HW */
2444         if (skb->encapsulation &&
2445             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2446                 return mlx5e_vxlan_features_check(priv, skb, features);
2447
2448         return features;
2449 }
2450
2451 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2452         .ndo_open                = mlx5e_open,
2453         .ndo_stop                = mlx5e_close,
2454         .ndo_start_xmit          = mlx5e_xmit,
2455         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2456         .ndo_select_queue        = mlx5e_select_queue,
2457         .ndo_get_stats64         = mlx5e_get_stats,
2458         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2459         .ndo_set_mac_address     = mlx5e_set_mac,
2460         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2461         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2462         .ndo_set_features        = mlx5e_set_features,
2463         .ndo_change_mtu          = mlx5e_change_mtu,
2464         .ndo_do_ioctl            = mlx5e_ioctl,
2465 };
2466
2467 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2468         .ndo_open                = mlx5e_open,
2469         .ndo_stop                = mlx5e_close,
2470         .ndo_start_xmit          = mlx5e_xmit,
2471         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2472         .ndo_select_queue        = mlx5e_select_queue,
2473         .ndo_get_stats64         = mlx5e_get_stats,
2474         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2475         .ndo_set_mac_address     = mlx5e_set_mac,
2476         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2477         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2478         .ndo_set_features        = mlx5e_set_features,
2479         .ndo_change_mtu          = mlx5e_change_mtu,
2480         .ndo_do_ioctl            = mlx5e_ioctl,
2481         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2482         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2483         .ndo_features_check      = mlx5e_features_check,
2484         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2485         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2486         .ndo_get_vf_config       = mlx5e_get_vf_config,
2487         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2488         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2489 };
2490
2491 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2492 {
2493         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2494                 return -ENOTSUPP;
2495         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2496             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2497             !MLX5_CAP_ETH(mdev, csum_cap) ||
2498             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2499             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2500             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2501             MLX5_CAP_FLOWTABLE(mdev,
2502                                flow_table_properties_nic_receive.max_ft_level)
2503                                < 3) {
2504                 mlx5_core_warn(mdev,
2505                                "Not creating net device, some required device capabilities are missing\n");
2506                 return -ENOTSUPP;
2507         }
2508         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2509                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2510         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2511                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2512
2513         return 0;
2514 }
2515
2516 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2517 {
2518         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2519
2520         return bf_buf_size -
2521                sizeof(struct mlx5e_tx_wqe) +
2522                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2523 }
2524
2525 #ifdef CONFIG_MLX5_CORE_EN_DCB
2526 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2527 {
2528         int i;
2529
2530         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2531         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2532                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2533                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2534                 priv->params.ets.prio_tc[i] = i;
2535         }
2536
2537         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2538         priv->params.ets.prio_tc[0] = 1;
2539         priv->params.ets.prio_tc[1] = 0;
2540 }
2541 #endif
2542
2543 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2544                                    u32 *indirection_rqt, int len,
2545                                    int num_channels)
2546 {
2547         int node = mdev->priv.numa_node;
2548         int node_num_of_cores;
2549         int i;
2550
2551         if (node == -1)
2552                 node = first_online_node;
2553
2554         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2555
2556         if (node_num_of_cores)
2557                 num_channels = min_t(int, num_channels, node_num_of_cores);
2558
2559         for (i = 0; i < len; i++)
2560                 indirection_rqt[i] = i % num_channels;
2561 }
2562
2563 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2564 {
2565         return MLX5_CAP_GEN(mdev, striding_rq) &&
2566                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2567                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2568 }
2569
2570 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2571                                     struct net_device *netdev,
2572                                     int num_channels)
2573 {
2574         struct mlx5e_priv *priv = netdev_priv(netdev);
2575
2576         priv->params.log_sq_size           =
2577                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2578         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2579                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2580                 MLX5_WQ_TYPE_LINKED_LIST;
2581
2582         switch (priv->params.rq_wq_type) {
2583         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2584                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2585                 priv->params.lro_en = true;
2586                 break;
2587         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2588                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2589         }
2590
2591         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2592                                             BIT(priv->params.log_rq_size));
2593         priv->params.rx_cq_moderation_usec =
2594                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2595         priv->params.rx_cq_moderation_pkts =
2596                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2597         priv->params.tx_cq_moderation_usec =
2598                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2599         priv->params.tx_cq_moderation_pkts =
2600                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2601         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2602         priv->params.num_tc                = 1;
2603         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2604
2605         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2606                             sizeof(priv->params.toeplitz_hash_key));
2607
2608         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2609                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2610
2611         priv->params.lro_wqe_sz            =
2612                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2613
2614         priv->mdev                         = mdev;
2615         priv->netdev                       = netdev;
2616         priv->params.num_channels          = num_channels;
2617
2618 #ifdef CONFIG_MLX5_CORE_EN_DCB
2619         mlx5e_ets_init(priv);
2620 #endif
2621
2622         mutex_init(&priv->state_lock);
2623
2624         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2625         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2626         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2627 }
2628
2629 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2630 {
2631         struct mlx5e_priv *priv = netdev_priv(netdev);
2632
2633         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2634         if (is_zero_ether_addr(netdev->dev_addr) &&
2635             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2636                 eth_hw_addr_random(netdev);
2637                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2638         }
2639 }
2640
2641 static void mlx5e_build_netdev(struct net_device *netdev)
2642 {
2643         struct mlx5e_priv *priv = netdev_priv(netdev);
2644         struct mlx5_core_dev *mdev = priv->mdev;
2645         bool fcs_supported;
2646         bool fcs_enabled;
2647
2648         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2649
2650         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2651                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2652 #ifdef CONFIG_MLX5_CORE_EN_DCB
2653                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2654 #endif
2655         } else {
2656                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2657         }
2658
2659         netdev->watchdog_timeo    = 15 * HZ;
2660
2661         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2662
2663         netdev->vlan_features    |= NETIF_F_SG;
2664         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2665         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2666         netdev->vlan_features    |= NETIF_F_GRO;
2667         netdev->vlan_features    |= NETIF_F_TSO;
2668         netdev->vlan_features    |= NETIF_F_TSO6;
2669         netdev->vlan_features    |= NETIF_F_RXCSUM;
2670         netdev->vlan_features    |= NETIF_F_RXHASH;
2671
2672         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2673                 netdev->vlan_features    |= NETIF_F_LRO;
2674
2675         netdev->hw_features       = netdev->vlan_features;
2676         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2677         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2678         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2679
2680         if (mlx5e_vxlan_allowed(mdev)) {
2681                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2682                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2683                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2684                 netdev->hw_enc_features |= NETIF_F_TSO;
2685                 netdev->hw_enc_features |= NETIF_F_TSO6;
2686                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2687                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2688         }
2689
2690         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2691
2692         if (fcs_supported)
2693                 netdev->hw_features |= NETIF_F_RXALL;
2694
2695         netdev->features          = netdev->hw_features;
2696         if (!priv->params.lro_en)
2697                 netdev->features  &= ~NETIF_F_LRO;
2698
2699         if (fcs_enabled)
2700                 netdev->features  &= ~NETIF_F_RXALL;
2701
2702 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2703         if (FT_CAP(flow_modify_en) &&
2704             FT_CAP(modify_root) &&
2705             FT_CAP(identified_miss_table_mode) &&
2706             FT_CAP(flow_table_modify))
2707                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2708
2709         netdev->features         |= NETIF_F_HIGHDMA;
2710
2711         netdev->priv_flags       |= IFF_UNICAST_FLT;
2712
2713         mlx5e_set_netdev_dev_addr(netdev);
2714 }
2715
2716 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2717                              struct mlx5_core_mkey *mkey)
2718 {
2719         struct mlx5_core_dev *mdev = priv->mdev;
2720         struct mlx5_create_mkey_mbox_in *in;
2721         int err;
2722
2723         in = mlx5_vzalloc(sizeof(*in));
2724         if (!in)
2725                 return -ENOMEM;
2726
2727         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2728                         MLX5_PERM_LOCAL_READ  |
2729                         MLX5_ACCESS_MODE_PA;
2730         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2731         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2732
2733         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2734                                     NULL);
2735
2736         kvfree(in);
2737
2738         return err;
2739 }
2740
2741 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2742 {
2743         struct mlx5_core_dev *mdev = priv->mdev;
2744         int err;
2745
2746         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2747         if (err) {
2748                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2749                 priv->q_counter = 0;
2750         }
2751 }
2752
2753 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2754 {
2755         if (!priv->q_counter)
2756                 return;
2757
2758         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2759 }
2760
2761 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2762 {
2763         struct mlx5_core_dev *mdev = priv->mdev;
2764         struct mlx5_create_mkey_mbox_in *in;
2765         struct mlx5_mkey_seg *mkc;
2766         int inlen = sizeof(*in);
2767         u64 npages =
2768                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2769         int err;
2770
2771         in = mlx5_vzalloc(inlen);
2772         if (!in)
2773                 return -ENOMEM;
2774
2775         mkc = &in->seg;
2776         mkc->status = MLX5_MKEY_STATUS_FREE;
2777         mkc->flags = MLX5_PERM_UMR_EN |
2778                      MLX5_PERM_LOCAL_READ |
2779                      MLX5_PERM_LOCAL_WRITE |
2780                      MLX5_ACCESS_MODE_MTT;
2781
2782         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2783         mkc->flags_pd = cpu_to_be32(priv->pdn);
2784         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2785         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2786         mkc->log2_page_size = PAGE_SHIFT;
2787
2788         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2789                                     NULL, NULL);
2790
2791         kvfree(in);
2792
2793         return err;
2794 }
2795
2796 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2797 {
2798         struct net_device *netdev;
2799         struct mlx5e_priv *priv;
2800         int nch = mlx5e_get_max_num_channels(mdev);
2801         int err;
2802
2803         if (mlx5e_check_required_hca_cap(mdev))
2804                 return NULL;
2805
2806         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2807                                     nch * MLX5E_MAX_NUM_TC,
2808                                     nch);
2809         if (!netdev) {
2810                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2811                 return NULL;
2812         }
2813
2814         mlx5e_build_netdev_priv(mdev, netdev, nch);
2815         mlx5e_build_netdev(netdev);
2816
2817         netif_carrier_off(netdev);
2818
2819         priv = netdev_priv(netdev);
2820
2821         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2822         if (err) {
2823                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2824                 goto err_free_netdev;
2825         }
2826
2827         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2828         if (err) {
2829                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2830                 goto err_unmap_free_uar;
2831         }
2832
2833         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2834         if (err) {
2835                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2836                 goto err_dealloc_pd;
2837         }
2838
2839         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2840         if (err) {
2841                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2842                 goto err_dealloc_transport_domain;
2843         }
2844
2845         err = mlx5e_create_umr_mkey(priv);
2846         if (err) {
2847                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2848                 goto err_destroy_mkey;
2849         }
2850
2851         err = mlx5e_create_tises(priv);
2852         if (err) {
2853                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2854                 goto err_destroy_umr_mkey;
2855         }
2856
2857         err = mlx5e_open_drop_rq(priv);
2858         if (err) {
2859                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2860                 goto err_destroy_tises;
2861         }
2862
2863         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2864         if (err) {
2865                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2866                 goto err_close_drop_rq;
2867         }
2868
2869         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2870         if (err) {
2871                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2872                 goto err_destroy_rqt_indir;
2873         }
2874
2875         err = mlx5e_create_tirs(priv);
2876         if (err) {
2877                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2878                 goto err_destroy_rqt_single;
2879         }
2880
2881         err = mlx5e_create_flow_tables(priv);
2882         if (err) {
2883                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2884                 goto err_destroy_tirs;
2885         }
2886
2887         mlx5e_create_q_counter(priv);
2888
2889         mlx5e_init_eth_addr(priv);
2890
2891         mlx5e_vxlan_init(priv);
2892
2893         err = mlx5e_tc_init(priv);
2894         if (err)
2895                 goto err_dealloc_q_counters;
2896
2897 #ifdef CONFIG_MLX5_CORE_EN_DCB
2898         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2899 #endif
2900
2901         err = register_netdev(netdev);
2902         if (err) {
2903                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2904                 goto err_tc_cleanup;
2905         }
2906
2907         if (mlx5e_vxlan_allowed(mdev))
2908                 vxlan_get_rx_port(netdev);
2909
2910         mlx5e_enable_async_events(priv);
2911         schedule_work(&priv->set_rx_mode_work);
2912
2913         return priv;
2914
2915 err_tc_cleanup:
2916         mlx5e_tc_cleanup(priv);
2917
2918 err_dealloc_q_counters:
2919         mlx5e_destroy_q_counter(priv);
2920         mlx5e_destroy_flow_tables(priv);
2921
2922 err_destroy_tirs:
2923         mlx5e_destroy_tirs(priv);
2924
2925 err_destroy_rqt_single:
2926         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2927
2928 err_destroy_rqt_indir:
2929         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2930
2931 err_close_drop_rq:
2932         mlx5e_close_drop_rq(priv);
2933
2934 err_destroy_tises:
2935         mlx5e_destroy_tises(priv);
2936
2937 err_destroy_umr_mkey:
2938         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2939
2940 err_destroy_mkey:
2941         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2942
2943 err_dealloc_transport_domain:
2944         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2945
2946 err_dealloc_pd:
2947         mlx5_core_dealloc_pd(mdev, priv->pdn);
2948
2949 err_unmap_free_uar:
2950         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2951
2952 err_free_netdev:
2953         free_netdev(netdev);
2954
2955         return NULL;
2956 }
2957
2958 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2959 {
2960         struct mlx5e_priv *priv = vpriv;
2961         struct net_device *netdev = priv->netdev;
2962
2963         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2964
2965         schedule_work(&priv->set_rx_mode_work);
2966         mlx5e_disable_async_events(priv);
2967         flush_scheduled_work();
2968         unregister_netdev(netdev);
2969         mlx5e_tc_cleanup(priv);
2970         mlx5e_vxlan_cleanup(priv);
2971         mlx5e_destroy_q_counter(priv);
2972         mlx5e_destroy_flow_tables(priv);
2973         mlx5e_destroy_tirs(priv);
2974         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2975         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2976         mlx5e_close_drop_rq(priv);
2977         mlx5e_destroy_tises(priv);
2978         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
2979         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2980         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2981         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2982         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2983         free_netdev(netdev);
2984 }
2985
2986 static void *mlx5e_get_netdev(void *vpriv)
2987 {
2988         struct mlx5e_priv *priv = vpriv;
2989
2990         return priv->netdev;
2991 }
2992
2993 static struct mlx5_interface mlx5e_interface = {
2994         .add       = mlx5e_create_netdev,
2995         .remove    = mlx5e_destroy_netdev,
2996         .event     = mlx5e_async_event,
2997         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2998         .get_dev   = mlx5e_get_netdev,
2999 };
3000
3001 void mlx5e_init(void)
3002 {
3003         mlx5_register_interface(&mlx5e_interface);
3004 }
3005
3006 void mlx5e_cleanup(void)
3007 {
3008         mlx5_unregister_interface(&mlx5e_interface);
3009 }