drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param       wq;
  52 };
  53
  54 struct mlx5e_sq_param {
  55         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        max_inline;
  58         bool                       icosq;
  59 };
  60
  61 struct mlx5e_cq_param {
  62         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  63         struct mlx5_wq_param       wq;
  64         u16                        eq_ix;
  65 };
  66
  67 struct mlx5e_channel_param {
  68         struct mlx5e_rq_param      rq;
  69         struct mlx5e_sq_param      sq;
  70         struct mlx5e_sq_param      icosq;
  71         struct mlx5e_cq_param      rx_cq;
  72         struct mlx5e_cq_param      tx_cq;
  73         struct mlx5e_cq_param      icosq_cq;
  74 };
  75
  76 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  77 {
  78         struct mlx5_core_dev *mdev = priv->mdev;
  79         u8 port_state;
  80
  81         port_state = mlx5_query_vport_state(mdev,
  82                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  83
  84         if (port_state == VPORT_STATE_UP)
  85                 netif_carrier_on(priv->netdev);
  86         else
  87                 netif_carrier_off(priv->netdev);
  88 }
  89
  90 static void mlx5e_update_carrier_work(struct work_struct *work)
  91 {
  92         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  93                                                update_carrier_work);
  94
  95         mutex_lock(&priv->state_lock);
  96         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  97                 mlx5e_update_carrier(priv);
  98         mutex_unlock(&priv->state_lock);
  99 }
 100
 101 static void mlx5e_tx_timeout_work(struct work_struct *work)
 102 {
 103         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 104                                                tx_timeout_work);
 105         int err;
 106
 107         rtnl_lock();
 108         mutex_lock(&priv->state_lock);
 109         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 110                 goto unlock;
 111         mlx5e_close_locked(priv->netdev);
 112         err = mlx5e_open_locked(priv->netdev);
 113         if (err)
 114                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 115                            err);
 116 unlock:
 117         mutex_unlock(&priv->state_lock);
 118         rtnl_unlock();
 119 }
 120
 121 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 122 {
 123         struct mlx5e_sw_stats *s = &priv->stats.sw;
 124         struct mlx5e_rq_stats *rq_stats;
 125         struct mlx5e_sq_stats *sq_stats;
 126         u64 tx_offload_none = 0;
 127         int i, j;
 128
 129         memset(s, 0, sizeof(*s));
 130         for (i = 0; i < priv->params.num_channels; i++) {
 131                 rq_stats = &priv->channel[i]->rq.stats;
 132
 133                 s->rx_packets   += rq_stats->packets;
 134                 s->rx_bytes     += rq_stats->bytes;
 135                 s->rx_lro_packets += rq_stats->lro_packets;
 136                 s->rx_lro_bytes += rq_stats->lro_bytes;
 137                 s->rx_csum_none += rq_stats->csum_none;
 138                 s->rx_csum_complete += rq_stats->csum_complete;
 139                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 140                 s->rx_wqe_err   += rq_stats->wqe_err;
 141                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 142                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 143                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 144                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 145                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 146
 147                 for (j = 0; j < priv->params.num_tc; j++) {
 148                         sq_stats = &priv->channel[i]->sq[j].stats;
 149
 150                         s->tx_packets           += sq_stats->packets;
 151                         s->tx_bytes             += sq_stats->bytes;
 152                         s->tx_tso_packets       += sq_stats->tso_packets;
 153                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 154                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 155                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 156                         s->tx_queue_stopped     += sq_stats->stopped;
 157                         s->tx_queue_wake        += sq_stats->wake;
 158                         s->tx_queue_dropped     += sq_stats->dropped;
 159                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 160                         tx_offload_none         += sq_stats->csum_none;
 161                 }
 162         }
 163
 164         /* Update calculated offload counters */
 165         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 166         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 167
 168         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 169                                 priv->stats.pport.phy_counters,
 170                                 counter_set.phys_layer_cntrs.link_down_events);
 171 }
 172
 173 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 174 {
 175         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 176         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 177         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 178         struct mlx5_core_dev *mdev = priv->mdev;
 179
 180         memset(in, 0, sizeof(in));
 181
 182         MLX5_SET(query_vport_counter_in, in, opcode,
 183                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 184         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 185         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 186
 187         memset(out, 0, outlen);
 188
 189         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 190 }
 191
 192 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 193 {
 194         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 195         struct mlx5_core_dev *mdev = priv->mdev;
 196         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 197         int prio;
 198         void *out;
 199         u32 *in;
 200
 201         in = mlx5_vzalloc(sz);
 202         if (!in)
 203                 goto free_out;
 204
 205         MLX5_SET(ppcnt_reg, in, local_port, 1);
 206
 207         out = pstats->IEEE_802_3_counters;
 208         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 209         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 210
 211         out = pstats->RFC_2863_counters;
 212         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 213         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 214
 215         out = pstats->RFC_2819_counters;
 216         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 217         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 218
 219         out = pstats->phy_counters;
 220         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 221         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 222
 223         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 224         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 225                 out = pstats->per_prio_counters[prio];
 226                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 227                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 228                                      MLX5_REG_PPCNT, 0, 0);
 229         }
 230
 231 free_out:
 232         kvfree(in);
 233 }
 234
 235 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 236 {
 237         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 238
 239         if (!priv->q_counter)
 240                 return;
 241
 242         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 243                                       &qcnt->rx_out_of_buffer);
 244 }
 245
 246 void mlx5e_update_stats(struct mlx5e_priv *priv)
 247 {
 248         mlx5e_update_q_counter(priv);
 249         mlx5e_update_vport_counters(priv);
 250         mlx5e_update_pport_counters(priv);
 251         mlx5e_update_sw_counters(priv);
 252 }
 253
 254 static void mlx5e_update_stats_work(struct work_struct *work)
 255 {
 256         struct delayed_work *dwork = to_delayed_work(work);
 257         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 258                                                update_stats_work);
 259         mutex_lock(&priv->state_lock);
 260         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 261                 mlx5e_update_stats(priv);
 262                 queue_delayed_work(priv->wq, dwork,
 263                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 264         }
 265         mutex_unlock(&priv->state_lock);
 266 }
 267
 268 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 269                               enum mlx5_dev_event event, unsigned long param)
 270 {
 271         struct mlx5e_priv *priv = vpriv;
 272
 273         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 274                 return;
 275
 276         switch (event) {
 277         case MLX5_DEV_EVENT_PORT_UP:
 278         case MLX5_DEV_EVENT_PORT_DOWN:
 279                 queue_work(priv->wq, &priv->update_carrier_work);
 280                 break;
 281
 282         default:
 283                 break;
 284         }
 285 }
 286
 287 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 288 {
 289         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 290 }
 291
 292 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 293 {
 294         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 295         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 296 }
 297
 298 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 299 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 300
 301 static int mlx5e_create_rq(struct mlx5e_channel *c,
 302                            struct mlx5e_rq_param *param,
 303                            struct mlx5e_rq *rq)
 304 {
 305         struct mlx5e_priv *priv = c->priv;
 306         struct mlx5_core_dev *mdev = priv->mdev;
 307         void *rqc = param->rqc;
 308         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 309         u32 byte_count;
 310         int wq_sz;
 311         int err;
 312         int i;
 313
 314         param->wq.db_numa_node = cpu_to_node(c->cpu);
 315
 316         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 317                                 &rq->wq_ctrl);
 318         if (err)
 319                 return err;
 320
 321         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 322
 323         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 324
 325         switch (priv->params.rq_wq_type) {
 326         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 327                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 328                                             GFP_KERNEL, cpu_to_node(c->cpu));
 329                 if (!rq->wqe_info) {
 330                         err = -ENOMEM;
 331                         goto err_rq_wq_destroy;
 332                 }
 333                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 334                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 335                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 336
 337                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 338                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 339                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 340                 byte_count = rq->wqe_sz;
 341                 break;
 342         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 343                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 344                                        cpu_to_node(c->cpu));
 345                 if (!rq->skb) {
 346                         err = -ENOMEM;
 347                         goto err_rq_wq_destroy;
 348                 }
 349                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 350                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 351                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 352
 353                 rq->wqe_sz = (priv->params.lro_en) ?
 354                                 priv->params.lro_wqe_sz :
 355                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 356                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 357                 byte_count = rq->wqe_sz;
 358                 byte_count |= MLX5_HW_START_PADDING;
 359         }
 360
 361         for (i = 0; i < wq_sz; i++) {
 362                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 363
 364                 wqe->data.byte_count = cpu_to_be32(byte_count);
 365         }
 366
 367         rq->wq_type = priv->params.rq_wq_type;
 368         rq->pdev    = c->pdev;
 369         rq->netdev  = c->netdev;
 370         rq->tstamp  = &priv->tstamp;
 371         rq->channel = c;
 372         rq->ix      = c->ix;
 373         rq->priv    = c->priv;
 374         rq->mkey_be = c->mkey_be;
 375         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 376
 377         return 0;
 378
 379 err_rq_wq_destroy:
 380         mlx5_wq_destroy(&rq->wq_ctrl);
 381
 382         return err;
 383 }
 384
 385 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 386 {
 387         switch (rq->wq_type) {
 388         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 389                 kfree(rq->wqe_info);
 390                 break;
 391         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 392                 kfree(rq->skb);
 393         }
 394
 395         mlx5_wq_destroy(&rq->wq_ctrl);
 396 }
 397
 398 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 399 {
 400         struct mlx5e_priv *priv = rq->priv;
 401         struct mlx5_core_dev *mdev = priv->mdev;
 402
 403         void *in;
 404         void *rqc;
 405         void *wq;
 406         int inlen;
 407         int err;
 408
 409         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 410                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 411         in = mlx5_vzalloc(inlen);
 412         if (!in)
 413                 return -ENOMEM;
 414
 415         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 416         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 417
 418         memcpy(rqc, param->rqc, sizeof(param->rqc));
 419
 420         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 421         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 422         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 423         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 424         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 425                                                 MLX5_ADAPTER_PAGE_SHIFT);
 426         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 427
 428         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 429                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 430
 431         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 432
 433         kvfree(in);
 434
 435         return err;
 436 }
 437
 438 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 439                                  int next_state)
 440 {
 441         struct mlx5e_channel *c = rq->channel;
 442         struct mlx5e_priv *priv = c->priv;
 443         struct mlx5_core_dev *mdev = priv->mdev;
 444
 445         void *in;
 446         void *rqc;
 447         int inlen;
 448         int err;
 449
 450         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 451         in = mlx5_vzalloc(inlen);
 452         if (!in)
 453                 return -ENOMEM;
 454
 455         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 456
 457         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 458         MLX5_SET(rqc, rqc, state, next_state);
 459
 460         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 461
 462         kvfree(in);
 463
 464         return err;
 465 }
 466
 467 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 468 {
 469         struct mlx5e_channel *c = rq->channel;
 470         struct mlx5e_priv *priv = c->priv;
 471         struct mlx5_core_dev *mdev = priv->mdev;
 472
 473         void *in;
 474         void *rqc;
 475         int inlen;
 476         int err;
 477
 478         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 479         in = mlx5_vzalloc(inlen);
 480         if (!in)
 481                 return -ENOMEM;
 482
 483         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 484
 485         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 486         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 487         MLX5_SET(rqc, rqc, vsd, vsd);
 488         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 489
 490         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 491
 492         kvfree(in);
 493
 494         return err;
 495 }
 496
 497 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 498 {
 499         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 500 }
 501
 502 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 503 {
 504         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 505         struct mlx5e_channel *c = rq->channel;
 506         struct mlx5e_priv *priv = c->priv;
 507         struct mlx5_wq_ll *wq = &rq->wq;
 508
 509         while (time_before(jiffies, exp_time)) {
 510                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 511                         return 0;
 512
 513                 msleep(20);
 514         }
 515
 516         return -ETIMEDOUT;
 517 }
 518
 519 static int mlx5e_open_rq(struct mlx5e_channel *c,
 520                          struct mlx5e_rq_param *param,
 521                          struct mlx5e_rq *rq)
 522 {
 523         struct mlx5e_sq *sq = &c->icosq;
 524         u16 pi = sq->pc & sq->wq.sz_m1;
 525         int err;
 526
 527         err = mlx5e_create_rq(c, param, rq);
 528         if (err)
 529                 return err;
 530
 531         err = mlx5e_enable_rq(rq, param);
 532         if (err)
 533                 goto err_destroy_rq;
 534
 535         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 536         if (err)
 537                 goto err_disable_rq;
 538
 539         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 540
 541         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 542         sq->ico_wqe_info[pi].num_wqebbs = 1;
 543         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 544
 545         return 0;
 546
 547 err_disable_rq:
 548         mlx5e_disable_rq(rq);
 549 err_destroy_rq:
 550         mlx5e_destroy_rq(rq);
 551
 552         return err;
 553 }
 554
 555 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 556 {
 557         int tout = 0;
 558         int err;
 559
 560         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 561         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 562
 563         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 564         while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
 565                tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
 566                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 567
 568         if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
 569                 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 570
 571         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 572         napi_synchronize(&rq->channel->napi);
 573
 574         mlx5e_disable_rq(rq);
 575         mlx5e_free_rx_descs(rq);
 576         mlx5e_destroy_rq(rq);
 577 }
 578
 579 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 580 {
 581         kfree(sq->wqe_info);
 582         kfree(sq->dma_fifo);
 583         kfree(sq->skb);
 584 }
 585
 586 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 587 {
 588         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 589         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 590
 591         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 592         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 593                                     numa);
 594         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 595                                     numa);
 596
 597         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 598                 mlx5e_free_sq_db(sq);
 599                 return -ENOMEM;
 600         }
 601
 602         sq->dma_fifo_mask = df_sz - 1;
 603
 604         return 0;
 605 }
 606
 607 static int mlx5e_create_sq(struct mlx5e_channel *c,
 608                            int tc,
 609                            struct mlx5e_sq_param *param,
 610                            struct mlx5e_sq *sq)
 611 {
 612         struct mlx5e_priv *priv = c->priv;
 613         struct mlx5_core_dev *mdev = priv->mdev;
 614
 615         void *sqc = param->sqc;
 616         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 617         int err;
 618
 619         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 620         if (err)
 621                 return err;
 622
 623         param->wq.db_numa_node = cpu_to_node(c->cpu);
 624
 625         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 626                                  &sq->wq_ctrl);
 627         if (err)
 628                 goto err_unmap_free_uar;
 629
 630         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 631         if (sq->uar.bf_map) {
 632                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 633                 sq->uar_map = sq->uar.bf_map;
 634         } else {
 635                 sq->uar_map = sq->uar.map;
 636         }
 637         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 638         sq->max_inline  = param->max_inline;
 639
 640         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 641         if (err)
 642                 goto err_sq_wq_destroy;
 643
 644         if (param->icosq) {
 645                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 646
 647                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 648                                                 wq_sz,
 649                                                 GFP_KERNEL,
 650                                                 cpu_to_node(c->cpu));
 651                 if (!sq->ico_wqe_info) {
 652                         err = -ENOMEM;
 653                         goto err_free_sq_db;
 654                 }
 655         } else {
 656                 int txq_ix;
 657
 658                 txq_ix = c->ix + tc * priv->params.num_channels;
 659                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 660                 priv->txq_to_sq_map[txq_ix] = sq;
 661         }
 662
 663         sq->pdev      = c->pdev;
 664         sq->tstamp    = &priv->tstamp;
 665         sq->mkey_be   = c->mkey_be;
 666         sq->channel   = c;
 667         sq->tc        = tc;
 668         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 669         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 670
 671         return 0;
 672
 673 err_free_sq_db:
 674         mlx5e_free_sq_db(sq);
 675
 676 err_sq_wq_destroy:
 677         mlx5_wq_destroy(&sq->wq_ctrl);
 678
 679 err_unmap_free_uar:
 680         mlx5_unmap_free_uar(mdev, &sq->uar);
 681
 682         return err;
 683 }
 684
 685 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 686 {
 687         struct mlx5e_channel *c = sq->channel;
 688         struct mlx5e_priv *priv = c->priv;
 689
 690         kfree(sq->ico_wqe_info);
 691         mlx5e_free_sq_db(sq);
 692         mlx5_wq_destroy(&sq->wq_ctrl);
 693         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 694 }
 695
 696 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 697 {
 698         struct mlx5e_channel *c = sq->channel;
 699         struct mlx5e_priv *priv = c->priv;
 700         struct mlx5_core_dev *mdev = priv->mdev;
 701
 702         void *in;
 703         void *sqc;
 704         void *wq;
 705         int inlen;
 706         int err;
 707
 708         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 709                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 710         in = mlx5_vzalloc(inlen);
 711         if (!in)
 712                 return -ENOMEM;
 713
 714         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 715         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 716
 717         memcpy(sqc, param->sqc, sizeof(param->sqc));
 718
 719         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 720         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 721         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 722         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 723         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 724
 725         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 726         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 727         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 728                                           MLX5_ADAPTER_PAGE_SHIFT);
 729         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 730
 731         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 732                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 733
 734         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 735
 736         kvfree(in);
 737
 738         return err;
 739 }
 740
 741 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 742 {
 743         struct mlx5e_channel *c = sq->channel;
 744         struct mlx5e_priv *priv = c->priv;
 745         struct mlx5_core_dev *mdev = priv->mdev;
 746
 747         void *in;
 748         void *sqc;
 749         int inlen;
 750         int err;
 751
 752         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 753         in = mlx5_vzalloc(inlen);
 754         if (!in)
 755                 return -ENOMEM;
 756
 757         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 758
 759         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 760         MLX5_SET(sqc, sqc, state, next_state);
 761
 762         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 763
 764         kvfree(in);
 765
 766         return err;
 767 }
 768
 769 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 770 {
 771         struct mlx5e_channel *c = sq->channel;
 772         struct mlx5e_priv *priv = c->priv;
 773         struct mlx5_core_dev *mdev = priv->mdev;
 774
 775         mlx5_core_destroy_sq(mdev, sq->sqn);
 776 }
 777
 778 static int mlx5e_open_sq(struct mlx5e_channel *c,
 779                          int tc,
 780                          struct mlx5e_sq_param *param,
 781                          struct mlx5e_sq *sq)
 782 {
 783         int err;
 784
 785         err = mlx5e_create_sq(c, tc, param, sq);
 786         if (err)
 787                 return err;
 788
 789         err = mlx5e_enable_sq(sq, param);
 790         if (err)
 791                 goto err_destroy_sq;
 792
 793         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 794         if (err)
 795                 goto err_disable_sq;
 796
 797         if (sq->txq) {
 798                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 799                 netdev_tx_reset_queue(sq->txq);
 800                 netif_tx_start_queue(sq->txq);
 801         }
 802
 803         return 0;
 804
 805 err_disable_sq:
 806         mlx5e_disable_sq(sq);
 807 err_destroy_sq:
 808         mlx5e_destroy_sq(sq);
 809
 810         return err;
 811 }
 812
 813 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 814 {
 815         __netif_tx_lock_bh(txq);
 816         netif_tx_stop_queue(txq);
 817         __netif_tx_unlock_bh(txq);
 818 }
 819
 820 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 821 {
 822         int tout = 0;
 823         int err;
 824
 825         if (sq->txq) {
 826                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 827                 /* prevent netif_tx_wake_queue */
 828                 napi_synchronize(&sq->channel->napi);
 829                 netif_tx_disable_queue(sq->txq);
 830
 831                 /* ensure hw is notified of all pending wqes */
 832                 if (mlx5e_sq_has_room_for(sq, 1))
 833                         mlx5e_send_nop(sq, true);
 834
 835                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 836                                       MLX5_SQC_STATE_ERR);
 837                 if (err)
 838                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 839         }
 840
 841         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 842         while (sq->cc != sq->pc &&
 843                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 844                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 845                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 846                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 847         }
 848
 849         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 850         napi_synchronize(&sq->channel->napi);
 851
 852         mlx5e_free_tx_descs(sq);
 853         mlx5e_disable_sq(sq);
 854         mlx5e_destroy_sq(sq);
 855 }
 856
 857 static int mlx5e_create_cq(struct mlx5e_channel *c,
 858                            struct mlx5e_cq_param *param,
 859                            struct mlx5e_cq *cq)
 860 {
 861         struct mlx5e_priv *priv = c->priv;
 862         struct mlx5_core_dev *mdev = priv->mdev;
 863         struct mlx5_core_cq *mcq = &cq->mcq;
 864         int eqn_not_used;
 865         unsigned int irqn;
 866         int err;
 867         u32 i;
 868
 869         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 870         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 871         param->eq_ix   = c->ix;
 872
 873         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 874                                &cq->wq_ctrl);
 875         if (err)
 876                 return err;
 877
 878         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 879
 880         cq->napi        = &c->napi;
 881
 882         mcq->cqe_sz     = 64;
 883         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 884         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 885         *mcq->set_ci_db = 0;
 886         *mcq->arm_db    = 0;
 887         mcq->vector     = param->eq_ix;
 888         mcq->comp       = mlx5e_completion_event;
 889         mcq->event      = mlx5e_cq_error_event;
 890         mcq->irqn       = irqn;
 891         mcq->uar        = &priv->cq_uar;
 892
 893         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 894                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 895
 896                 cqe->op_own = 0xf1;
 897         }
 898
 899         cq->channel = c;
 900         cq->priv = priv;
 901
 902         return 0;
 903 }
 904
 905 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 906 {
 907         mlx5_wq_destroy(&cq->wq_ctrl);
 908 }
 909
 910 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 911 {
 912         struct mlx5e_priv *priv = cq->priv;
 913         struct mlx5_core_dev *mdev = priv->mdev;
 914         struct mlx5_core_cq *mcq = &cq->mcq;
 915
 916         void *in;
 917         void *cqc;
 918         int inlen;
 919         unsigned int irqn_not_used;
 920         int eqn;
 921         int err;
 922
 923         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 924                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 925         in = mlx5_vzalloc(inlen);
 926         if (!in)
 927                 return -ENOMEM;
 928
 929         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 930
 931         memcpy(cqc, param->cqc, sizeof(param->cqc));
 932
 933         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 934                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 935
 936         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 937
 938         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 939         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 940         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 941                                             MLX5_ADAPTER_PAGE_SHIFT);
 942         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 943
 944         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 945
 946         kvfree(in);
 947
 948         if (err)
 949                 return err;
 950
 951         mlx5e_cq_arm(cq);
 952
 953         return 0;
 954 }
 955
 956 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 957 {
 958         struct mlx5e_priv *priv = cq->priv;
 959         struct mlx5_core_dev *mdev = priv->mdev;
 960
 961         mlx5_core_destroy_cq(mdev, &cq->mcq);
 962 }
 963
 964 static int mlx5e_open_cq(struct mlx5e_channel *c,
 965                          struct mlx5e_cq_param *param,
 966                          struct mlx5e_cq *cq,
 967                          u16 moderation_usecs,
 968                          u16 moderation_frames)
 969 {
 970         int err;
 971         struct mlx5e_priv *priv = c->priv;
 972         struct mlx5_core_dev *mdev = priv->mdev;
 973
 974         err = mlx5e_create_cq(c, param, cq);
 975         if (err)
 976                 return err;
 977
 978         err = mlx5e_enable_cq(cq, param);
 979         if (err)
 980                 goto err_destroy_cq;
 981
 982         if (MLX5_CAP_GEN(mdev, cq_moderation))
 983                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 984                                                moderation_usecs,
 985                                                moderation_frames);
 986         return 0;
 987
 988 err_destroy_cq:
 989         mlx5e_destroy_cq(cq);
 990
 991         return err;
 992 }
 993
 994 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 995 {
 996         mlx5e_disable_cq(cq);
 997         mlx5e_destroy_cq(cq);
 998 }
 999
1000 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1001 {
1002         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1003 }
1004
1005 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1006                              struct mlx5e_channel_param *cparam)
1007 {
1008         struct mlx5e_priv *priv = c->priv;
1009         int err;
1010         int tc;
1011
1012         for (tc = 0; tc < c->num_tc; tc++) {
1013                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1014                                     priv->params.tx_cq_moderation_usec,
1015                                     priv->params.tx_cq_moderation_pkts);
1016                 if (err)
1017                         goto err_close_tx_cqs;
1018         }
1019
1020         return 0;
1021
1022 err_close_tx_cqs:
1023         for (tc--; tc >= 0; tc--)
1024                 mlx5e_close_cq(&c->sq[tc].cq);
1025
1026         return err;
1027 }
1028
1029 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1030 {
1031         int tc;
1032
1033         for (tc = 0; tc < c->num_tc; tc++)
1034                 mlx5e_close_cq(&c->sq[tc].cq);
1035 }
1036
1037 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1038                           struct mlx5e_channel_param *cparam)
1039 {
1040         int err;
1041         int tc;
1042
1043         for (tc = 0; tc < c->num_tc; tc++) {
1044                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1045                 if (err)
1046                         goto err_close_sqs;
1047         }
1048
1049         return 0;
1050
1051 err_close_sqs:
1052         for (tc--; tc >= 0; tc--)
1053                 mlx5e_close_sq(&c->sq[tc]);
1054
1055         return err;
1056 }
1057
1058 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1059 {
1060         int tc;
1061
1062         for (tc = 0; tc < c->num_tc; tc++)
1063                 mlx5e_close_sq(&c->sq[tc]);
1064 }
1065
1066 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1067 {
1068         int i;
1069
1070         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1071                 priv->channeltc_to_txq_map[ix][i] =
1072                         ix + i * priv->params.num_channels;
1073 }
1074
1075 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1076                               struct mlx5e_channel_param *cparam,
1077                               struct mlx5e_channel **cp)
1078 {
1079         struct net_device *netdev = priv->netdev;
1080         int cpu = mlx5e_get_cpu(priv, ix);
1081         struct mlx5e_channel *c;
1082         int err;
1083
1084         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1085         if (!c)
1086                 return -ENOMEM;
1087
1088         c->priv     = priv;
1089         c->ix       = ix;
1090         c->cpu      = cpu;
1091         c->pdev     = &priv->mdev->pdev->dev;
1092         c->netdev   = priv->netdev;
1093         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1094         c->num_tc   = priv->params.num_tc;
1095
1096         mlx5e_build_channeltc_to_txq_map(priv, ix);
1097
1098         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1099
1100         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1101         if (err)
1102                 goto err_napi_del;
1103
1104         err = mlx5e_open_tx_cqs(c, cparam);
1105         if (err)
1106                 goto err_close_icosq_cq;
1107
1108         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1109                             priv->params.rx_cq_moderation_usec,
1110                             priv->params.rx_cq_moderation_pkts);
1111         if (err)
1112                 goto err_close_tx_cqs;
1113
1114         napi_enable(&c->napi);
1115
1116         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1117         if (err)
1118                 goto err_disable_napi;
1119
1120         err = mlx5e_open_sqs(c, cparam);
1121         if (err)
1122                 goto err_close_icosq;
1123
1124         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1125         if (err)
1126                 goto err_close_sqs;
1127
1128         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1129         *cp = c;
1130
1131         return 0;
1132
1133 err_close_sqs:
1134         mlx5e_close_sqs(c);
1135
1136 err_close_icosq:
1137         mlx5e_close_sq(&c->icosq);
1138
1139 err_disable_napi:
1140         napi_disable(&c->napi);
1141         mlx5e_close_cq(&c->rq.cq);
1142
1143 err_close_tx_cqs:
1144         mlx5e_close_tx_cqs(c);
1145
1146 err_close_icosq_cq:
1147         mlx5e_close_cq(&c->icosq.cq);
1148
1149 err_napi_del:
1150         netif_napi_del(&c->napi);
1151         napi_hash_del(&c->napi);
1152         kfree(c);
1153
1154         return err;
1155 }
1156
1157 static void mlx5e_close_channel(struct mlx5e_channel *c)
1158 {
1159         mlx5e_close_rq(&c->rq);
1160         mlx5e_close_sqs(c);
1161         mlx5e_close_sq(&c->icosq);
1162         napi_disable(&c->napi);
1163         mlx5e_close_cq(&c->rq.cq);
1164         mlx5e_close_tx_cqs(c);
1165         mlx5e_close_cq(&c->icosq.cq);
1166         netif_napi_del(&c->napi);
1167
1168         napi_hash_del(&c->napi);
1169         synchronize_rcu();
1170
1171         kfree(c);
1172 }
1173
1174 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1175                                  struct mlx5e_rq_param *param)
1176 {
1177         void *rqc = param->rqc;
1178         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1179
1180         switch (priv->params.rq_wq_type) {
1181         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1182                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1183                          priv->params.mpwqe_log_num_strides - 9);
1184                 MLX5_SET(wq, wq, log_wqe_stride_size,
1185                          priv->params.mpwqe_log_stride_sz - 6);
1186                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1187                 break;
1188         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1189                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1190         }
1191
1192         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1193         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1194         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1195         MLX5_SET(wq, wq, pd,               priv->pdn);
1196         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1197
1198         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1199         param->wq.linear = 1;
1200 }
1201
1202 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1203 {
1204         void *rqc = param->rqc;
1205         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1206
1207         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1208         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1209 }
1210
1211 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1212                                         struct mlx5e_sq_param *param)
1213 {
1214         void *sqc = param->sqc;
1215         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1216
1217         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1218         MLX5_SET(wq, wq, pd,            priv->pdn);
1219
1220         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1221 }
1222
1223 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1224                                  struct mlx5e_sq_param *param)
1225 {
1226         void *sqc = param->sqc;
1227         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1228
1229         mlx5e_build_sq_param_common(priv, param);
1230         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1231
1232         param->max_inline = priv->params.tx_max_inline;
1233 }
1234
1235 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1236                                         struct mlx5e_cq_param *param)
1237 {
1238         void *cqc = param->cqc;
1239
1240         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1241 }
1242
1243 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1244                                     struct mlx5e_cq_param *param)
1245 {
1246         void *cqc = param->cqc;
1247         u8 log_cq_size;
1248
1249         switch (priv->params.rq_wq_type) {
1250         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1251                 log_cq_size = priv->params.log_rq_size +
1252                         priv->params.mpwqe_log_num_strides;
1253                 break;
1254         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1255                 log_cq_size = priv->params.log_rq_size;
1256         }
1257
1258         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1259         if (priv->params.rx_cqe_compress) {
1260                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1261                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1262         }
1263
1264         mlx5e_build_common_cq_param(priv, param);
1265 }
1266
1267 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1268                                     struct mlx5e_cq_param *param)
1269 {
1270         void *cqc = param->cqc;
1271
1272         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1273
1274         mlx5e_build_common_cq_param(priv, param);
1275 }
1276
1277 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1278                                      struct mlx5e_cq_param *param,
1279                                      u8 log_wq_size)
1280 {
1281         void *cqc = param->cqc;
1282
1283         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1284
1285         mlx5e_build_common_cq_param(priv, param);
1286 }
1287
1288 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1289                                     struct mlx5e_sq_param *param,
1290                                     u8 log_wq_size)
1291 {
1292         void *sqc = param->sqc;
1293         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1294
1295         mlx5e_build_sq_param_common(priv, param);
1296
1297         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1298         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1299
1300         param->icosq = true;
1301 }
1302
1303 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1304 {
1305         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1306
1307         mlx5e_build_rq_param(priv, &cparam->rq);
1308         mlx5e_build_sq_param(priv, &cparam->sq);
1309         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1310         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1311         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1312         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1313 }
1314
1315 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1316 {
1317         struct mlx5e_channel_param *cparam;
1318         int nch = priv->params.num_channels;
1319         int err = -ENOMEM;
1320         int i;
1321         int j;
1322
1323         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1324                                 GFP_KERNEL);
1325
1326         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1327                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1328
1329         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1330
1331         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1332                 goto err_free_txq_to_sq_map;
1333
1334         mlx5e_build_channel_param(priv, cparam);
1335
1336         for (i = 0; i < nch; i++) {
1337                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1338                 if (err)
1339                         goto err_close_channels;
1340         }
1341
1342         for (j = 0; j < nch; j++) {
1343                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1344                 if (err)
1345                         goto err_close_channels;
1346         }
1347
1348         kfree(cparam);
1349         return 0;
1350
1351 err_close_channels:
1352         for (i--; i >= 0; i--)
1353                 mlx5e_close_channel(priv->channel[i]);
1354
1355 err_free_txq_to_sq_map:
1356         kfree(priv->txq_to_sq_map);
1357         kfree(priv->channel);
1358         kfree(cparam);
1359
1360         return err;
1361 }
1362
1363 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1364 {
1365         int i;
1366
1367         for (i = 0; i < priv->params.num_channels; i++)
1368                 mlx5e_close_channel(priv->channel[i]);
1369
1370         kfree(priv->txq_to_sq_map);
1371         kfree(priv->channel);
1372 }
1373
1374 static int mlx5e_rx_hash_fn(int hfunc)
1375 {
1376         return (hfunc == ETH_RSS_HASH_TOP) ?
1377                MLX5_RX_HASH_FN_TOEPLITZ :
1378                MLX5_RX_HASH_FN_INVERTED_XOR8;
1379 }
1380
1381 static int mlx5e_bits_invert(unsigned long a, int size)
1382 {
1383         int inv = 0;
1384         int i;
1385
1386         for (i = 0; i < size; i++)
1387                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1388
1389         return inv;
1390 }
1391
1392 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1393 {
1394         int i;
1395
1396         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1397                 int ix = i;
1398                 u32 rqn;
1399
1400                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1401                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1402
1403                 ix = priv->params.indirection_rqt[ix];
1404                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1405                                 priv->channel[ix]->rq.rqn :
1406                                 priv->drop_rq.rqn;
1407                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1408         }
1409 }
1410
1411 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1412                                       int ix)
1413 {
1414         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1415                         priv->channel[ix]->rq.rqn :
1416                         priv->drop_rq.rqn;
1417
1418         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1419 }
1420
1421 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1422 {
1423         struct mlx5_core_dev *mdev = priv->mdev;
1424         void *rqtc;
1425         int inlen;
1426         int err;
1427         u32 *in;
1428
1429         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1430         in = mlx5_vzalloc(inlen);
1431         if (!in)
1432                 return -ENOMEM;
1433
1434         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1435
1436         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1437         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1438
1439         if (sz > 1) /* RSS */
1440                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1441         else
1442                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1443
1444         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1445
1446         kvfree(in);
1447         return err;
1448 }
1449
1450 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1451 {
1452         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1453 }
1454
1455 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1456 {
1457         int nch = mlx5e_get_max_num_channels(priv->mdev);
1458         u32 *rqtn;
1459         int err;
1460         int ix;
1461
1462         /* Indirect RQT */
1463         rqtn = &priv->indir_rqtn;
1464         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1465         if (err)
1466                 return err;
1467
1468         /* Direct RQTs */
1469         for (ix = 0; ix < nch; ix++) {
1470                 rqtn = &priv->direct_tir[ix].rqtn;
1471                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1472                 if (err)
1473                         goto err_destroy_rqts;
1474         }
1475
1476         return 0;
1477
1478 err_destroy_rqts:
1479         for (ix--; ix >= 0; ix--)
1480                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1481
1482         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1483
1484         return err;
1485 }
1486
1487 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1488 {
1489         int nch = mlx5e_get_max_num_channels(priv->mdev);
1490         int i;
1491
1492         for (i = 0; i < nch; i++)
1493                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1494
1495         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1496 }
1497
1498 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1499 {
1500         struct mlx5_core_dev *mdev = priv->mdev;
1501         void *rqtc;
1502         int inlen;
1503         u32 *in;
1504         int err;
1505
1506         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1507         in = mlx5_vzalloc(inlen);
1508         if (!in)
1509                 return -ENOMEM;
1510
1511         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1512
1513         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1514         if (sz > 1) /* RSS */
1515                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1516         else
1517                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1518
1519         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1520
1521         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1522
1523         kvfree(in);
1524
1525         return err;
1526 }
1527
1528 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1529 {
1530         u32 rqtn;
1531         int ix;
1532
1533         rqtn = priv->indir_rqtn;
1534         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1535         for (ix = 0; ix < priv->params.num_channels; ix++) {
1536                 rqtn = priv->direct_tir[ix].rqtn;
1537                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1538         }
1539 }
1540
1541 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1542 {
1543         if (!priv->params.lro_en)
1544                 return;
1545
1546 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1547
1548         MLX5_SET(tirc, tirc, lro_enable_mask,
1549                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1550                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1551         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1552                  (priv->params.lro_wqe_sz -
1553                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1554         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1555                  MLX5_CAP_ETH(priv->mdev,
1556                               lro_timer_supported_periods[2]));
1557 }
1558
1559 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1560 {
1561         MLX5_SET(tirc, tirc, rx_hash_fn,
1562                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1563         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1564                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1565                                              rx_hash_toeplitz_key);
1566                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1567                                                rx_hash_toeplitz_key);
1568
1569                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1570                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1571         }
1572 }
1573
1574 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1575 {
1576         struct mlx5_core_dev *mdev = priv->mdev;
1577
1578         void *in;
1579         void *tirc;
1580         int inlen;
1581         int err;
1582         int tt;
1583         int ix;
1584
1585         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1586         in = mlx5_vzalloc(inlen);
1587         if (!in)
1588                 return -ENOMEM;
1589
1590         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1591         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1592
1593         mlx5e_build_tir_ctx_lro(tirc, priv);
1594
1595         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1596                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1597                                            inlen);
1598                 if (err)
1599                         goto free_in;
1600         }
1601
1602         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1603                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1604                                            in, inlen);
1605                 if (err)
1606                         goto free_in;
1607         }
1608
1609 free_in:
1610         kvfree(in);
1611
1612         return err;
1613 }
1614
1615 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1616 {
1617         void *in;
1618         int inlen;
1619         int err;
1620         int i;
1621
1622         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1623         in = mlx5_vzalloc(inlen);
1624         if (!in)
1625                 return -ENOMEM;
1626
1627         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1628
1629         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1630                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1631                                            inlen);
1632                 if (err)
1633                         return err;
1634         }
1635
1636         for (i = 0; i < priv->params.num_channels; i++) {
1637                 err = mlx5_core_modify_tir(priv->mdev,
1638                                            priv->direct_tir[i].tirn, in,
1639                                            inlen);
1640                 if (err)
1641                         return err;
1642         }
1643
1644         kvfree(in);
1645
1646         return 0;
1647 }
1648
1649 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1650 {
1651         struct mlx5_core_dev *mdev = priv->mdev;
1652         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1653         int err;
1654
1655         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1656         if (err)
1657                 return err;
1658
1659         /* Update vport context MTU */
1660         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1661         return 0;
1662 }
1663
1664 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1665 {
1666         struct mlx5_core_dev *mdev = priv->mdev;
1667         u16 hw_mtu = 0;
1668         int err;
1669
1670         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1671         if (err || !hw_mtu) /* fallback to port oper mtu */
1672                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1673
1674         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1675 }
1676
1677 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1678 {
1679         struct mlx5e_priv *priv = netdev_priv(netdev);
1680         u16 mtu;
1681         int err;
1682
1683         err = mlx5e_set_mtu(priv, netdev->mtu);
1684         if (err)
1685                 return err;
1686
1687         mlx5e_query_mtu(priv, &mtu);
1688         if (mtu != netdev->mtu)
1689                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1690                             __func__, mtu, netdev->mtu);
1691
1692         netdev->mtu = mtu;
1693         return 0;
1694 }
1695
1696 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1697 {
1698         struct mlx5e_priv *priv = netdev_priv(netdev);
1699         int nch = priv->params.num_channels;
1700         int ntc = priv->params.num_tc;
1701         int tc;
1702
1703         netdev_reset_tc(netdev);
1704
1705         if (ntc == 1)
1706                 return;
1707
1708         netdev_set_num_tc(netdev, ntc);
1709
1710         /* Map netdev TCs to offset 0
1711          * We have our own UP to TXQ mapping for QoS
1712          */
1713         for (tc = 0; tc < ntc; tc++)
1714                 netdev_set_tc_queue(netdev, tc, nch, 0);
1715 }
1716
1717 int mlx5e_open_locked(struct net_device *netdev)
1718 {
1719         struct mlx5e_priv *priv = netdev_priv(netdev);
1720         int num_txqs;
1721         int err;
1722
1723         set_bit(MLX5E_STATE_OPENED, &priv->state);
1724
1725         mlx5e_netdev_set_tcs(netdev);
1726
1727         num_txqs = priv->params.num_channels * priv->params.num_tc;
1728         netif_set_real_num_tx_queues(netdev, num_txqs);
1729         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1730
1731         err = mlx5e_set_dev_port_mtu(netdev);
1732         if (err)
1733                 goto err_clear_state_opened_flag;
1734
1735         err = mlx5e_open_channels(priv);
1736         if (err) {
1737                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1738                            __func__, err);
1739                 goto err_clear_state_opened_flag;
1740         }
1741
1742         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1743         if (err) {
1744                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1745                            __func__, err);
1746                 goto err_close_channels;
1747         }
1748
1749         mlx5e_redirect_rqts(priv);
1750         mlx5e_update_carrier(priv);
1751         mlx5e_timestamp_init(priv);
1752 #ifdef CONFIG_RFS_ACCEL
1753         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1754 #endif
1755
1756         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1757
1758         return 0;
1759
1760 err_close_channels:
1761         mlx5e_close_channels(priv);
1762 err_clear_state_opened_flag:
1763         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1764         return err;
1765 }
1766
1767 static int mlx5e_open(struct net_device *netdev)
1768 {
1769         struct mlx5e_priv *priv = netdev_priv(netdev);
1770         int err;
1771
1772         mutex_lock(&priv->state_lock);
1773         err = mlx5e_open_locked(netdev);
1774         mutex_unlock(&priv->state_lock);
1775
1776         return err;
1777 }
1778
1779 int mlx5e_close_locked(struct net_device *netdev)
1780 {
1781         struct mlx5e_priv *priv = netdev_priv(netdev);
1782
1783         /* May already be CLOSED in case a previous configuration operation
1784          * (e.g RX/TX queue size change) that involves close&open failed.
1785          */
1786         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1787                 return 0;
1788
1789         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1790
1791         mlx5e_timestamp_cleanup(priv);
1792         netif_carrier_off(priv->netdev);
1793         mlx5e_redirect_rqts(priv);
1794         mlx5e_close_channels(priv);
1795
1796         return 0;
1797 }
1798
1799 static int mlx5e_close(struct net_device *netdev)
1800 {
1801         struct mlx5e_priv *priv = netdev_priv(netdev);
1802         int err;
1803
1804         mutex_lock(&priv->state_lock);
1805         err = mlx5e_close_locked(netdev);
1806         mutex_unlock(&priv->state_lock);
1807
1808         return err;
1809 }
1810
1811 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1812                                 struct mlx5e_rq *rq,
1813                                 struct mlx5e_rq_param *param)
1814 {
1815         struct mlx5_core_dev *mdev = priv->mdev;
1816         void *rqc = param->rqc;
1817         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1818         int err;
1819
1820         param->wq.db_numa_node = param->wq.buf_numa_node;
1821
1822         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1823                                 &rq->wq_ctrl);
1824         if (err)
1825                 return err;
1826
1827         rq->priv = priv;
1828
1829         return 0;
1830 }
1831
1832 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1833                                 struct mlx5e_cq *cq,
1834                                 struct mlx5e_cq_param *param)
1835 {
1836         struct mlx5_core_dev *mdev = priv->mdev;
1837         struct mlx5_core_cq *mcq = &cq->mcq;
1838         int eqn_not_used;
1839         unsigned int irqn;
1840         int err;
1841
1842         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1843                                &cq->wq_ctrl);
1844         if (err)
1845                 return err;
1846
1847         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1848
1849         mcq->cqe_sz     = 64;
1850         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1851         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1852         *mcq->set_ci_db = 0;
1853         *mcq->arm_db    = 0;
1854         mcq->vector     = param->eq_ix;
1855         mcq->comp       = mlx5e_completion_event;
1856         mcq->event      = mlx5e_cq_error_event;
1857         mcq->irqn       = irqn;
1858         mcq->uar        = &priv->cq_uar;
1859
1860         cq->priv = priv;
1861
1862         return 0;
1863 }
1864
1865 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1866 {
1867         struct mlx5e_cq_param cq_param;
1868         struct mlx5e_rq_param rq_param;
1869         struct mlx5e_rq *rq = &priv->drop_rq;
1870         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1871         int err;
1872
1873         memset(&cq_param, 0, sizeof(cq_param));
1874         memset(&rq_param, 0, sizeof(rq_param));
1875         mlx5e_build_drop_rq_param(&rq_param);
1876
1877         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1878         if (err)
1879                 return err;
1880
1881         err = mlx5e_enable_cq(cq, &cq_param);
1882         if (err)
1883                 goto err_destroy_cq;
1884
1885         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1886         if (err)
1887                 goto err_disable_cq;
1888
1889         err = mlx5e_enable_rq(rq, &rq_param);
1890         if (err)
1891                 goto err_destroy_rq;
1892
1893         return 0;
1894
1895 err_destroy_rq:
1896         mlx5e_destroy_rq(&priv->drop_rq);
1897
1898 err_disable_cq:
1899         mlx5e_disable_cq(&priv->drop_rq.cq);
1900
1901 err_destroy_cq:
1902         mlx5e_destroy_cq(&priv->drop_rq.cq);
1903
1904         return err;
1905 }
1906
1907 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1908 {
1909         mlx5e_disable_rq(&priv->drop_rq);
1910         mlx5e_destroy_rq(&priv->drop_rq);
1911         mlx5e_disable_cq(&priv->drop_rq.cq);
1912         mlx5e_destroy_cq(&priv->drop_rq.cq);
1913 }
1914
1915 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1916 {
1917         struct mlx5_core_dev *mdev = priv->mdev;
1918         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1919         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1920
1921         memset(in, 0, sizeof(in));
1922
1923         MLX5_SET(tisc, tisc, prio, tc << 1);
1924         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1925
1926         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1927 }
1928
1929 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1930 {
1931         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1932 }
1933
1934 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1935 {
1936         int err;
1937         int tc;
1938
1939         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1940                 err = mlx5e_create_tis(priv, tc);
1941                 if (err)
1942                         goto err_close_tises;
1943         }
1944
1945         return 0;
1946
1947 err_close_tises:
1948         for (tc--; tc >= 0; tc--)
1949                 mlx5e_destroy_tis(priv, tc);
1950
1951         return err;
1952 }
1953
1954 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1955 {
1956         int tc;
1957
1958         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1959                 mlx5e_destroy_tis(priv, tc);
1960 }
1961
1962 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1963                                       enum mlx5e_traffic_types tt)
1964 {
1965         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1966
1967         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1968
1969 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1970                                  MLX5_HASH_FIELD_SEL_DST_IP)
1971
1972 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1973                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1974                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1975                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1976
1977 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1978                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1979                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1980
1981         mlx5e_build_tir_ctx_lro(tirc, priv);
1982
1983         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1984         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1985         mlx5e_build_tir_ctx_hash(tirc, priv);
1986
1987         switch (tt) {
1988         case MLX5E_TT_IPV4_TCP:
1989                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1990                          MLX5_L3_PROT_TYPE_IPV4);
1991                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1992                          MLX5_L4_PROT_TYPE_TCP);
1993                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1994                          MLX5_HASH_IP_L4PORTS);
1995                 break;
1996
1997         case MLX5E_TT_IPV6_TCP:
1998                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1999                          MLX5_L3_PROT_TYPE_IPV6);
2000                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2001                          MLX5_L4_PROT_TYPE_TCP);
2002                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2003                          MLX5_HASH_IP_L4PORTS);
2004                 break;
2005
2006         case MLX5E_TT_IPV4_UDP:
2007                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2008                          MLX5_L3_PROT_TYPE_IPV4);
2009                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2010                          MLX5_L4_PROT_TYPE_UDP);
2011                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2012                          MLX5_HASH_IP_L4PORTS);
2013                 break;
2014
2015         case MLX5E_TT_IPV6_UDP:
2016                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2017                          MLX5_L3_PROT_TYPE_IPV6);
2018                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2019                          MLX5_L4_PROT_TYPE_UDP);
2020                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2021                          MLX5_HASH_IP_L4PORTS);
2022                 break;
2023
2024         case MLX5E_TT_IPV4_IPSEC_AH:
2025                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2026                          MLX5_L3_PROT_TYPE_IPV4);
2027                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2028                          MLX5_HASH_IP_IPSEC_SPI);
2029                 break;
2030
2031         case MLX5E_TT_IPV6_IPSEC_AH:
2032                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2033                          MLX5_L3_PROT_TYPE_IPV6);
2034                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035                          MLX5_HASH_IP_IPSEC_SPI);
2036                 break;
2037
2038         case MLX5E_TT_IPV4_IPSEC_ESP:
2039                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2040                          MLX5_L3_PROT_TYPE_IPV4);
2041                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2042                          MLX5_HASH_IP_IPSEC_SPI);
2043                 break;
2044
2045         case MLX5E_TT_IPV6_IPSEC_ESP:
2046                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2047                          MLX5_L3_PROT_TYPE_IPV6);
2048                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2049                          MLX5_HASH_IP_IPSEC_SPI);
2050                 break;
2051
2052         case MLX5E_TT_IPV4:
2053                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2054                          MLX5_L3_PROT_TYPE_IPV4);
2055                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2056                          MLX5_HASH_IP);
2057                 break;
2058
2059         case MLX5E_TT_IPV6:
2060                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2061                          MLX5_L3_PROT_TYPE_IPV6);
2062                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2063                          MLX5_HASH_IP);
2064                 break;
2065         default:
2066                 WARN_ONCE(true,
2067                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2068         }
2069 }
2070
2071 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2072                                        u32 rqtn)
2073 {
2074         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2075
2076         mlx5e_build_tir_ctx_lro(tirc, priv);
2077
2078         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2079         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2080         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2081 }
2082
2083 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2084 {
2085         int nch = mlx5e_get_max_num_channels(priv->mdev);
2086         void *tirc;
2087         int inlen;
2088         u32 *tirn;
2089         int err;
2090         u32 *in;
2091         int ix;
2092         int tt;
2093
2094         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2095         in = mlx5_vzalloc(inlen);
2096         if (!in)
2097                 return -ENOMEM;
2098
2099         /* indirect tirs */
2100         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2101                 memset(in, 0, inlen);
2102                 tirn = &priv->indir_tirn[tt];
2103                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2104                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2105                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2106                 if (err)
2107                         goto err_destroy_tirs;
2108         }
2109
2110         /* direct tirs */
2111         for (ix = 0; ix < nch; ix++) {
2112                 memset(in, 0, inlen);
2113                 tirn = &priv->direct_tir[ix].tirn;
2114                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2115                 mlx5e_build_direct_tir_ctx(priv, tirc,
2116                                            priv->direct_tir[ix].rqtn);
2117                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2118                 if (err)
2119                         goto err_destroy_ch_tirs;
2120         }
2121
2122         kvfree(in);
2123
2124         return 0;
2125
2126 err_destroy_ch_tirs:
2127         for (ix--; ix >= 0; ix--)
2128                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2129
2130 err_destroy_tirs:
2131         for (tt--; tt >= 0; tt--)
2132                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2133
2134         kvfree(in);
2135
2136         return err;
2137 }
2138
2139 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2140 {
2141         int nch = mlx5e_get_max_num_channels(priv->mdev);
2142         int i;
2143
2144         for (i = 0; i < nch; i++)
2145                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2146
2147         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2148                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2149 }
2150
2151 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2152 {
2153         int err = 0;
2154         int i;
2155
2156         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2157                 return 0;
2158
2159         for (i = 0; i < priv->params.num_channels; i++) {
2160                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2161                 if (err)
2162                         return err;
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2169 {
2170         struct mlx5e_priv *priv = netdev_priv(netdev);
2171         bool was_opened;
2172         int err = 0;
2173
2174         if (tc && tc != MLX5E_MAX_NUM_TC)
2175                 return -EINVAL;
2176
2177         mutex_lock(&priv->state_lock);
2178
2179         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2180         if (was_opened)
2181                 mlx5e_close_locked(priv->netdev);
2182
2183         priv->params.num_tc = tc ? tc : 1;
2184
2185         if (was_opened)
2186                 err = mlx5e_open_locked(priv->netdev);
2187
2188         mutex_unlock(&priv->state_lock);
2189
2190         return err;
2191 }
2192
2193 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2194                               __be16 proto, struct tc_to_netdev *tc)
2195 {
2196         struct mlx5e_priv *priv = netdev_priv(dev);
2197
2198         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2199                 goto mqprio;
2200
2201         switch (tc->type) {
2202         case TC_SETUP_CLSFLOWER:
2203                 switch (tc->cls_flower->command) {
2204                 case TC_CLSFLOWER_REPLACE:
2205                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2206                 case TC_CLSFLOWER_DESTROY:
2207                         return mlx5e_delete_flower(priv, tc->cls_flower);
2208                 case TC_CLSFLOWER_STATS:
2209                         return mlx5e_stats_flower(priv, tc->cls_flower);
2210                 }
2211         default:
2212                 return -EOPNOTSUPP;
2213         }
2214
2215 mqprio:
2216         if (tc->type != TC_SETUP_MQPRIO)
2217                 return -EINVAL;
2218
2219         return mlx5e_setup_tc(dev, tc->tc);
2220 }
2221
2222 static struct rtnl_link_stats64 *
2223 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2224 {
2225         struct mlx5e_priv *priv = netdev_priv(dev);
2226         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2227         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2228         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2229
2230         stats->rx_packets = sstats->rx_packets;
2231         stats->rx_bytes   = sstats->rx_bytes;
2232         stats->tx_packets = sstats->tx_packets;
2233         stats->tx_bytes   = sstats->tx_bytes;
2234
2235         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2236         stats->tx_dropped = sstats->tx_queue_dropped;
2237
2238         stats->rx_length_errors =
2239                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2240                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2241                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2242         stats->rx_crc_errors =
2243                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2244         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2245         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2246         stats->tx_carrier_errors =
2247                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2248         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2249                            stats->rx_frame_errors;
2250         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2251
2252         /* vport multicast also counts packets that are dropped due to steering
2253          * or rx out of buffer
2254          */
2255         stats->multicast =
2256                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2257
2258         return stats;
2259 }
2260
2261 static void mlx5e_set_rx_mode(struct net_device *dev)
2262 {
2263         struct mlx5e_priv *priv = netdev_priv(dev);
2264
2265         queue_work(priv->wq, &priv->set_rx_mode_work);
2266 }
2267
2268 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2269 {
2270         struct mlx5e_priv *priv = netdev_priv(netdev);
2271         struct sockaddr *saddr = addr;
2272
2273         if (!is_valid_ether_addr(saddr->sa_data))
2274                 return -EADDRNOTAVAIL;
2275
2276         netif_addr_lock_bh(netdev);
2277         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2278         netif_addr_unlock_bh(netdev);
2279
2280         queue_work(priv->wq, &priv->set_rx_mode_work);
2281
2282         return 0;
2283 }
2284
2285 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2286         do {                                            \
2287                 if (enable)                             \
2288                         netdev->features |= feature;    \
2289                 else                                    \
2290                         netdev->features &= ~feature;   \
2291         } while (0)
2292
2293 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2294
2295 static int set_feature_lro(struct net_device *netdev, bool enable)
2296 {
2297         struct mlx5e_priv *priv = netdev_priv(netdev);
2298         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2299         int err;
2300
2301         mutex_lock(&priv->state_lock);
2302
2303         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2304                 mlx5e_close_locked(priv->netdev);
2305
2306         priv->params.lro_en = enable;
2307         err = mlx5e_modify_tirs_lro(priv);
2308         if (err) {
2309                 netdev_err(netdev, "lro modify failed, %d\n", err);
2310                 priv->params.lro_en = !enable;
2311         }
2312
2313         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2314                 mlx5e_open_locked(priv->netdev);
2315
2316         mutex_unlock(&priv->state_lock);
2317
2318         return err;
2319 }
2320
2321 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2322 {
2323         struct mlx5e_priv *priv = netdev_priv(netdev);
2324
2325         if (enable)
2326                 mlx5e_enable_vlan_filter(priv);
2327         else
2328                 mlx5e_disable_vlan_filter(priv);
2329
2330         return 0;
2331 }
2332
2333 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2334 {
2335         struct mlx5e_priv *priv = netdev_priv(netdev);
2336
2337         if (!enable && mlx5e_tc_num_filters(priv)) {
2338                 netdev_err(netdev,
2339                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2340                 return -EINVAL;
2341         }
2342
2343         return 0;
2344 }
2345
2346 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2347 {
2348         struct mlx5e_priv *priv = netdev_priv(netdev);
2349         struct mlx5_core_dev *mdev = priv->mdev;
2350
2351         return mlx5_set_port_fcs(mdev, !enable);
2352 }
2353
2354 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2355 {
2356         struct mlx5e_priv *priv = netdev_priv(netdev);
2357         int err;
2358
2359         mutex_lock(&priv->state_lock);
2360
2361         priv->params.vlan_strip_disable = !enable;
2362         err = mlx5e_modify_rqs_vsd(priv, !enable);
2363         if (err)
2364                 priv->params.vlan_strip_disable = enable;
2365
2366         mutex_unlock(&priv->state_lock);
2367
2368         return err;
2369 }
2370
2371 #ifdef CONFIG_RFS_ACCEL
2372 static int set_feature_arfs(struct net_device *netdev, bool enable)
2373 {
2374         struct mlx5e_priv *priv = netdev_priv(netdev);
2375         int err;
2376
2377         if (enable)
2378                 err = mlx5e_arfs_enable(priv);
2379         else
2380                 err = mlx5e_arfs_disable(priv);
2381
2382         return err;
2383 }
2384 #endif
2385
2386 static int mlx5e_handle_feature(struct net_device *netdev,
2387                                 netdev_features_t wanted_features,
2388                                 netdev_features_t feature,
2389                                 mlx5e_feature_handler feature_handler)
2390 {
2391         netdev_features_t changes = wanted_features ^ netdev->features;
2392         bool enable = !!(wanted_features & feature);
2393         int err;
2394
2395         if (!(changes & feature))
2396                 return 0;
2397
2398         err = feature_handler(netdev, enable);
2399         if (err) {
2400                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2401                            enable ? "Enable" : "Disable", feature, err);
2402                 return err;
2403         }
2404
2405         MLX5E_SET_FEATURE(netdev, feature, enable);
2406         return 0;
2407 }
2408
2409 static int mlx5e_set_features(struct net_device *netdev,
2410                               netdev_features_t features)
2411 {
2412         int err;
2413
2414         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2415                                     set_feature_lro);
2416         err |= mlx5e_handle_feature(netdev, features,
2417                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2418                                     set_feature_vlan_filter);
2419         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2420                                     set_feature_tc_num_filters);
2421         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2422                                     set_feature_rx_all);
2423         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2424                                     set_feature_rx_vlan);
2425 #ifdef CONFIG_RFS_ACCEL
2426         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2427                                     set_feature_arfs);
2428 #endif
2429
2430         return err ? -EINVAL : 0;
2431 }
2432
2433 #define MXL5_HW_MIN_MTU 64
2434 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2435
2436 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2437 {
2438         struct mlx5e_priv *priv = netdev_priv(netdev);
2439         struct mlx5_core_dev *mdev = priv->mdev;
2440         bool was_opened;
2441         u16 max_mtu;
2442         u16 min_mtu;
2443         int err = 0;
2444
2445         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2446
2447         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2448         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2449
2450         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2451                 netdev_err(netdev,
2452                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2453                            __func__, new_mtu, min_mtu, max_mtu);
2454                 return -EINVAL;
2455         }
2456
2457         mutex_lock(&priv->state_lock);
2458
2459         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2460         if (was_opened)
2461                 mlx5e_close_locked(netdev);
2462
2463         netdev->mtu = new_mtu;
2464
2465         if (was_opened)
2466                 err = mlx5e_open_locked(netdev);
2467
2468         mutex_unlock(&priv->state_lock);
2469
2470         return err;
2471 }
2472
2473 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2474 {
2475         switch (cmd) {
2476         case SIOCSHWTSTAMP:
2477                 return mlx5e_hwstamp_set(dev, ifr);
2478         case SIOCGHWTSTAMP:
2479                 return mlx5e_hwstamp_get(dev, ifr);
2480         default:
2481                 return -EOPNOTSUPP;
2482         }
2483 }
2484
2485 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2486 {
2487         struct mlx5e_priv *priv = netdev_priv(dev);
2488         struct mlx5_core_dev *mdev = priv->mdev;
2489
2490         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2491 }
2492
2493 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2494 {
2495         struct mlx5e_priv *priv = netdev_priv(dev);
2496         struct mlx5_core_dev *mdev = priv->mdev;
2497
2498         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2499                                            vlan, qos);
2500 }
2501
2502 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2503 {
2504         struct mlx5e_priv *priv = netdev_priv(dev);
2505         struct mlx5_core_dev *mdev = priv->mdev;
2506
2507         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2508 }
2509
2510 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2511 {
2512         struct mlx5e_priv *priv = netdev_priv(dev);
2513         struct mlx5_core_dev *mdev = priv->mdev;
2514
2515         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2516 }
2517 static int mlx5_vport_link2ifla(u8 esw_link)
2518 {
2519         switch (esw_link) {
2520         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2521                 return IFLA_VF_LINK_STATE_DISABLE;
2522         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2523                 return IFLA_VF_LINK_STATE_ENABLE;
2524         }
2525         return IFLA_VF_LINK_STATE_AUTO;
2526 }
2527
2528 static int mlx5_ifla_link2vport(u8 ifla_link)
2529 {
2530         switch (ifla_link) {
2531         case IFLA_VF_LINK_STATE_DISABLE:
2532                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2533         case IFLA_VF_LINK_STATE_ENABLE:
2534                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2535         }
2536         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2537 }
2538
2539 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2540                                    int link_state)
2541 {
2542         struct mlx5e_priv *priv = netdev_priv(dev);
2543         struct mlx5_core_dev *mdev = priv->mdev;
2544
2545         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2546                                             mlx5_ifla_link2vport(link_state));
2547 }
2548
2549 static int mlx5e_get_vf_config(struct net_device *dev,
2550                                int vf, struct ifla_vf_info *ivi)
2551 {
2552         struct mlx5e_priv *priv = netdev_priv(dev);
2553         struct mlx5_core_dev *mdev = priv->mdev;
2554         int err;
2555
2556         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2557         if (err)
2558                 return err;
2559         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2560         return 0;
2561 }
2562
2563 static int mlx5e_get_vf_stats(struct net_device *dev,
2564                               int vf, struct ifla_vf_stats *vf_stats)
2565 {
2566         struct mlx5e_priv *priv = netdev_priv(dev);
2567         struct mlx5_core_dev *mdev = priv->mdev;
2568
2569         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2570                                             vf_stats);
2571 }
2572
2573 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2574                                  sa_family_t sa_family, __be16 port)
2575 {
2576         struct mlx5e_priv *priv = netdev_priv(netdev);
2577
2578         if (!mlx5e_vxlan_allowed(priv->mdev))
2579                 return;
2580
2581         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2582 }
2583
2584 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2585                                  sa_family_t sa_family, __be16 port)
2586 {
2587         struct mlx5e_priv *priv = netdev_priv(netdev);
2588
2589         if (!mlx5e_vxlan_allowed(priv->mdev))
2590                 return;
2591
2592         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2593 }
2594
2595 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2596                                                     struct sk_buff *skb,
2597                                                     netdev_features_t features)
2598 {
2599         struct udphdr *udph;
2600         u16 proto;
2601         u16 port = 0;
2602
2603         switch (vlan_get_protocol(skb)) {
2604         case htons(ETH_P_IP):
2605                 proto = ip_hdr(skb)->protocol;
2606                 break;
2607         case htons(ETH_P_IPV6):
2608                 proto = ipv6_hdr(skb)->nexthdr;
2609                 break;
2610         default:
2611                 goto out;
2612         }
2613
2614         if (proto == IPPROTO_UDP) {
2615                 udph = udp_hdr(skb);
2616                 port = be16_to_cpu(udph->dest);
2617         }
2618
2619         /* Verify if UDP port is being offloaded by HW */
2620         if (port && mlx5e_vxlan_lookup_port(priv, port))
2621                 return features;
2622
2623 out:
2624         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2625         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2626 }
2627
2628 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2629                                               struct net_device *netdev,
2630                                               netdev_features_t features)
2631 {
2632         struct mlx5e_priv *priv = netdev_priv(netdev);
2633
2634         features = vlan_features_check(skb, features);
2635         features = vxlan_features_check(skb, features);
2636
2637         /* Validate if the tunneled packet is being offloaded by HW */
2638         if (skb->encapsulation &&
2639             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2640                 return mlx5e_vxlan_features_check(priv, skb, features);
2641
2642         return features;
2643 }
2644
2645 static void mlx5e_tx_timeout(struct net_device *dev)
2646 {
2647         struct mlx5e_priv *priv = netdev_priv(dev);
2648         bool sched_work = false;
2649         int i;
2650
2651         netdev_err(dev, "TX timeout detected\n");
2652
2653         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2654                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2655
2656                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
2657                         continue;
2658                 sched_work = true;
2659                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2660                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2661                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2662         }
2663
2664         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2665                 schedule_work(&priv->tx_timeout_work);
2666 }
2667
2668 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2669         .ndo_open                = mlx5e_open,
2670         .ndo_stop                = mlx5e_close,
2671         .ndo_start_xmit          = mlx5e_xmit,
2672         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2673         .ndo_select_queue        = mlx5e_select_queue,
2674         .ndo_get_stats64         = mlx5e_get_stats,
2675         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2676         .ndo_set_mac_address     = mlx5e_set_mac,
2677         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2678         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2679         .ndo_set_features        = mlx5e_set_features,
2680         .ndo_change_mtu          = mlx5e_change_mtu,
2681         .ndo_do_ioctl            = mlx5e_ioctl,
2682 #ifdef CONFIG_RFS_ACCEL
2683         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2684 #endif
2685         .ndo_tx_timeout          = mlx5e_tx_timeout,
2686 };
2687
2688 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2689         .ndo_open                = mlx5e_open,
2690         .ndo_stop                = mlx5e_close,
2691         .ndo_start_xmit          = mlx5e_xmit,
2692         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2693         .ndo_select_queue        = mlx5e_select_queue,
2694         .ndo_get_stats64         = mlx5e_get_stats,
2695         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2696         .ndo_set_mac_address     = mlx5e_set_mac,
2697         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2698         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2699         .ndo_set_features        = mlx5e_set_features,
2700         .ndo_change_mtu          = mlx5e_change_mtu,
2701         .ndo_do_ioctl            = mlx5e_ioctl,
2702         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2703         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2704         .ndo_features_check      = mlx5e_features_check,
2705 #ifdef CONFIG_RFS_ACCEL
2706         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2707 #endif
2708         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2709         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2710         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2711         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2712         .ndo_get_vf_config       = mlx5e_get_vf_config,
2713         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2714         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2715         .ndo_tx_timeout          = mlx5e_tx_timeout,
2716 };
2717
2718 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2719 {
2720         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2721                 return -ENOTSUPP;
2722         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2723             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2724             !MLX5_CAP_ETH(mdev, csum_cap) ||
2725             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2726             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2727             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2728             MLX5_CAP_FLOWTABLE(mdev,
2729                                flow_table_properties_nic_receive.max_ft_level)
2730                                < 3) {
2731                 mlx5_core_warn(mdev,
2732                                "Not creating net device, some required device capabilities are missing\n");
2733                 return -ENOTSUPP;
2734         }
2735         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2736                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2737         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2738                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2739
2740         return 0;
2741 }
2742
2743 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2744 {
2745         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2746
2747         return bf_buf_size -
2748                sizeof(struct mlx5e_tx_wqe) +
2749                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2750 }
2751
2752 #ifdef CONFIG_MLX5_CORE_EN_DCB
2753 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2754 {
2755         int i;
2756
2757         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2758         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2759                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2760                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2761                 priv->params.ets.prio_tc[i] = i;
2762         }
2763
2764         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2765         priv->params.ets.prio_tc[0] = 1;
2766         priv->params.ets.prio_tc[1] = 0;
2767 }
2768 #endif
2769
2770 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2771                                    u32 *indirection_rqt, int len,
2772                                    int num_channels)
2773 {
2774         int node = mdev->priv.numa_node;
2775         int node_num_of_cores;
2776         int i;
2777
2778         if (node == -1)
2779                 node = first_online_node;
2780
2781         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2782
2783         if (node_num_of_cores)
2784                 num_channels = min_t(int, num_channels, node_num_of_cores);
2785
2786         for (i = 0; i < len; i++)
2787                 indirection_rqt[i] = i % num_channels;
2788 }
2789
2790 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2791 {
2792         return MLX5_CAP_GEN(mdev, striding_rq) &&
2793                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2794                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2795 }
2796
2797 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2798 {
2799         enum pcie_link_width width;
2800         enum pci_bus_speed speed;
2801         int err = 0;
2802
2803         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2804         if (err)
2805                 return err;
2806
2807         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2808                 return -EINVAL;
2809
2810         switch (speed) {
2811         case PCIE_SPEED_2_5GT:
2812                 *pci_bw = 2500 * width;
2813                 break;
2814         case PCIE_SPEED_5_0GT:
2815                 *pci_bw = 5000 * width;
2816                 break;
2817         case PCIE_SPEED_8_0GT:
2818                 *pci_bw = 8000 * width;
2819                 break;
2820         default:
2821                 return -EINVAL;
2822         }
2823
2824         return 0;
2825 }
2826
2827 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2828 {
2829         return (link_speed && pci_bw &&
2830                 (pci_bw < 40000) && (pci_bw < link_speed));
2831 }
2832
2833 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2834                                     struct net_device *netdev,
2835                                     int num_channels)
2836 {
2837         struct mlx5e_priv *priv = netdev_priv(netdev);
2838         u32 link_speed = 0;
2839         u32 pci_bw = 0;
2840
2841         priv->params.log_sq_size           =
2842                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2843         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2844                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2845                 MLX5_WQ_TYPE_LINKED_LIST;
2846
2847         /* set CQE compression */
2848         priv->params.rx_cqe_compress_admin = false;
2849         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2850             MLX5_CAP_GEN(mdev, vport_group_manager)) {
2851                 mlx5e_get_max_linkspeed(mdev, &link_speed);
2852                 mlx5e_get_pci_bw(mdev, &pci_bw);
2853                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2854                               link_speed, pci_bw);
2855                 priv->params.rx_cqe_compress_admin =
2856                         cqe_compress_heuristic(link_speed, pci_bw);
2857         }
2858
2859         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2860
2861         switch (priv->params.rq_wq_type) {
2862         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2863                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2864                 priv->params.mpwqe_log_stride_sz =
2865                         priv->params.rx_cqe_compress ?
2866                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2867                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
2868                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2869                         priv->params.mpwqe_log_stride_sz;
2870                 priv->params.lro_en = true;
2871                 break;
2872         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2873                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2874         }
2875
2876         mlx5_core_info(mdev,
2877                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2878                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2879                        BIT(priv->params.log_rq_size),
2880                        BIT(priv->params.mpwqe_log_stride_sz),
2881                        priv->params.rx_cqe_compress_admin);
2882
2883         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2884                                             BIT(priv->params.log_rq_size));
2885         priv->params.rx_cq_moderation_usec =
2886                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2887         priv->params.rx_cq_moderation_pkts =
2888                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2889         priv->params.tx_cq_moderation_usec =
2890                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2891         priv->params.tx_cq_moderation_pkts =
2892                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2893         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2894         priv->params.num_tc                = 1;
2895         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2896
2897         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2898                             sizeof(priv->params.toeplitz_hash_key));
2899
2900         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2901                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2902
2903         priv->params.lro_wqe_sz            =
2904                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2905
2906         priv->mdev                         = mdev;
2907         priv->netdev                       = netdev;
2908         priv->params.num_channels          = num_channels;
2909
2910 #ifdef CONFIG_MLX5_CORE_EN_DCB
2911         mlx5e_ets_init(priv);
2912 #endif
2913
2914         mutex_init(&priv->state_lock);
2915
2916         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2917         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2918         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
2919         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2920 }
2921
2922 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2923 {
2924         struct mlx5e_priv *priv = netdev_priv(netdev);
2925
2926         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2927         if (is_zero_ether_addr(netdev->dev_addr) &&
2928             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2929                 eth_hw_addr_random(netdev);
2930                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2931         }
2932 }
2933
2934 static void mlx5e_build_netdev(struct net_device *netdev)
2935 {
2936         struct mlx5e_priv *priv = netdev_priv(netdev);
2937         struct mlx5_core_dev *mdev = priv->mdev;
2938         bool fcs_supported;
2939         bool fcs_enabled;
2940
2941         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2942
2943         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2944                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2945 #ifdef CONFIG_MLX5_CORE_EN_DCB
2946                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2947 #endif
2948         } else {
2949                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2950         }
2951
2952         netdev->watchdog_timeo    = 15 * HZ;
2953
2954         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2955
2956         netdev->vlan_features    |= NETIF_F_SG;
2957         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2958         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2959         netdev->vlan_features    |= NETIF_F_GRO;
2960         netdev->vlan_features    |= NETIF_F_TSO;
2961         netdev->vlan_features    |= NETIF_F_TSO6;
2962         netdev->vlan_features    |= NETIF_F_RXCSUM;
2963         netdev->vlan_features    |= NETIF_F_RXHASH;
2964
2965         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2966                 netdev->vlan_features    |= NETIF_F_LRO;
2967
2968         netdev->hw_features       = netdev->vlan_features;
2969         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2970         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2971         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2972
2973         if (mlx5e_vxlan_allowed(mdev)) {
2974                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2975                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2976                                            NETIF_F_GSO_PARTIAL;
2977                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2978                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2979                 netdev->hw_enc_features |= NETIF_F_TSO;
2980                 netdev->hw_enc_features |= NETIF_F_TSO6;
2981                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2982                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2983                                            NETIF_F_GSO_PARTIAL;
2984                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2985         }
2986
2987         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2988
2989         if (fcs_supported)
2990                 netdev->hw_features |= NETIF_F_RXALL;
2991
2992         netdev->features          = netdev->hw_features;
2993         if (!priv->params.lro_en)
2994                 netdev->features  &= ~NETIF_F_LRO;
2995
2996         if (fcs_enabled)
2997                 netdev->features  &= ~NETIF_F_RXALL;
2998
2999 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3000         if (FT_CAP(flow_modify_en) &&
3001             FT_CAP(modify_root) &&
3002             FT_CAP(identified_miss_table_mode) &&
3003             FT_CAP(flow_table_modify)) {
3004                 netdev->hw_features      |= NETIF_F_HW_TC;
3005 #ifdef CONFIG_RFS_ACCEL
3006                 netdev->hw_features      |= NETIF_F_NTUPLE;
3007 #endif
3008         }
3009
3010         netdev->features         |= NETIF_F_HIGHDMA;
3011
3012         netdev->priv_flags       |= IFF_UNICAST_FLT;
3013
3014         mlx5e_set_netdev_dev_addr(netdev);
3015 }
3016
3017 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3018                              struct mlx5_core_mkey *mkey)
3019 {
3020         struct mlx5_core_dev *mdev = priv->mdev;
3021         struct mlx5_create_mkey_mbox_in *in;
3022         int err;
3023
3024         in = mlx5_vzalloc(sizeof(*in));
3025         if (!in)
3026                 return -ENOMEM;
3027
3028         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3029                         MLX5_PERM_LOCAL_READ  |
3030                         MLX5_ACCESS_MODE_PA;
3031         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3032         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3033
3034         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
3035                                     NULL);
3036
3037         kvfree(in);
3038
3039         return err;
3040 }
3041
3042 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3043 {
3044         struct mlx5_core_dev *mdev = priv->mdev;
3045         int err;
3046
3047         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3048         if (err) {
3049                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3050                 priv->q_counter = 0;
3051         }
3052 }
3053
3054 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3055 {
3056         if (!priv->q_counter)
3057                 return;
3058
3059         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3060 }
3061
3062 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3063 {
3064         struct mlx5_core_dev *mdev = priv->mdev;
3065         struct mlx5_create_mkey_mbox_in *in;
3066         struct mlx5_mkey_seg *mkc;
3067         int inlen = sizeof(*in);
3068         u64 npages =
3069                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3070         int err;
3071
3072         in = mlx5_vzalloc(inlen);
3073         if (!in)
3074                 return -ENOMEM;
3075
3076         mkc = &in->seg;
3077         mkc->status = MLX5_MKEY_STATUS_FREE;
3078         mkc->flags = MLX5_PERM_UMR_EN |
3079                      MLX5_PERM_LOCAL_READ |
3080                      MLX5_PERM_LOCAL_WRITE |
3081                      MLX5_ACCESS_MODE_MTT;
3082
3083         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3084         mkc->flags_pd = cpu_to_be32(priv->pdn);
3085         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3086         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3087         mkc->log2_page_size = PAGE_SHIFT;
3088
3089         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3090                                     NULL, NULL);
3091
3092         kvfree(in);
3093
3094         return err;
3095 }
3096
3097 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3098 {
3099         struct net_device *netdev;
3100         struct mlx5e_priv *priv;
3101         int nch = mlx5e_get_max_num_channels(mdev);
3102         int err;
3103
3104         if (mlx5e_check_required_hca_cap(mdev))
3105                 return NULL;
3106
3107         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3108                                     nch * MLX5E_MAX_NUM_TC,
3109                                     nch);
3110         if (!netdev) {
3111                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3112                 return NULL;
3113         }
3114
3115         mlx5e_build_netdev_priv(mdev, netdev, nch);
3116         mlx5e_build_netdev(netdev);
3117
3118         netif_carrier_off(netdev);
3119
3120         priv = netdev_priv(netdev);
3121
3122         priv->wq = create_singlethread_workqueue("mlx5e");
3123         if (!priv->wq)
3124                 goto err_free_netdev;
3125
3126         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3127         if (err) {
3128                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3129                 goto err_destroy_wq;
3130         }
3131
3132         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3133         if (err) {
3134                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3135                 goto err_unmap_free_uar;
3136         }
3137
3138         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3139         if (err) {
3140                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3141                 goto err_dealloc_pd;
3142         }
3143
3144         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3145         if (err) {
3146                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3147                 goto err_dealloc_transport_domain;
3148         }
3149
3150         err = mlx5e_create_umr_mkey(priv);
3151         if (err) {
3152                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3153                 goto err_destroy_mkey;
3154         }
3155
3156         err = mlx5e_create_tises(priv);
3157         if (err) {
3158                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3159                 goto err_destroy_umr_mkey;
3160         }
3161
3162         err = mlx5e_open_drop_rq(priv);
3163         if (err) {
3164                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3165                 goto err_destroy_tises;
3166         }
3167
3168         err = mlx5e_create_rqts(priv);
3169         if (err) {
3170                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3171                 goto err_close_drop_rq;
3172         }
3173
3174         err = mlx5e_create_tirs(priv);
3175         if (err) {
3176                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3177                 goto err_destroy_rqts;
3178         }
3179
3180         err = mlx5e_create_flow_steering(priv);
3181         if (err) {
3182                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3183                 goto err_destroy_tirs;
3184         }
3185
3186         mlx5e_create_q_counter(priv);
3187
3188         mlx5e_init_l2_addr(priv);
3189
3190         mlx5e_vxlan_init(priv);
3191
3192         err = mlx5e_tc_init(priv);
3193         if (err)
3194                 goto err_dealloc_q_counters;
3195
3196 #ifdef CONFIG_MLX5_CORE_EN_DCB
3197         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3198 #endif
3199
3200         err = register_netdev(netdev);
3201         if (err) {
3202                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3203                 goto err_tc_cleanup;
3204         }
3205
3206         if (mlx5e_vxlan_allowed(mdev)) {
3207                 rtnl_lock();
3208                 vxlan_get_rx_port(netdev);
3209                 rtnl_unlock();
3210         }
3211
3212         mlx5e_enable_async_events(priv);
3213         queue_work(priv->wq, &priv->set_rx_mode_work);
3214
3215         return priv;
3216
3217 err_tc_cleanup:
3218         mlx5e_tc_cleanup(priv);
3219
3220 err_dealloc_q_counters:
3221         mlx5e_destroy_q_counter(priv);
3222         mlx5e_destroy_flow_steering(priv);
3223
3224 err_destroy_tirs:
3225         mlx5e_destroy_tirs(priv);
3226
3227 err_destroy_rqts:
3228         mlx5e_destroy_rqts(priv);
3229
3230 err_close_drop_rq:
3231         mlx5e_close_drop_rq(priv);
3232
3233 err_destroy_tises:
3234         mlx5e_destroy_tises(priv);
3235
3236 err_destroy_umr_mkey:
3237         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3238
3239 err_destroy_mkey:
3240         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3241
3242 err_dealloc_transport_domain:
3243         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3244
3245 err_dealloc_pd:
3246         mlx5_core_dealloc_pd(mdev, priv->pdn);
3247
3248 err_unmap_free_uar:
3249         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3250
3251 err_destroy_wq:
3252         destroy_workqueue(priv->wq);
3253
3254 err_free_netdev:
3255         free_netdev(netdev);
3256
3257         return NULL;
3258 }
3259
3260 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3261 {
3262         struct mlx5e_priv *priv = vpriv;
3263         struct net_device *netdev = priv->netdev;
3264
3265         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3266
3267         queue_work(priv->wq, &priv->set_rx_mode_work);
3268         mlx5e_disable_async_events(priv);
3269         flush_workqueue(priv->wq);
3270         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3271                 netif_device_detach(netdev);
3272                 mlx5e_close(netdev);
3273         } else {
3274                 unregister_netdev(netdev);
3275         }
3276
3277         mlx5e_tc_cleanup(priv);
3278         mlx5e_vxlan_cleanup(priv);
3279         mlx5e_destroy_q_counter(priv);
3280         mlx5e_destroy_flow_steering(priv);
3281         mlx5e_destroy_tirs(priv);
3282         mlx5e_destroy_rqts(priv);
3283         mlx5e_close_drop_rq(priv);
3284         mlx5e_destroy_tises(priv);
3285         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3286         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3287         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3288         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3289         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3290         cancel_delayed_work_sync(&priv->update_stats_work);
3291         destroy_workqueue(priv->wq);
3292
3293         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3294                 free_netdev(netdev);
3295 }
3296
3297 static void *mlx5e_get_netdev(void *vpriv)
3298 {
3299         struct mlx5e_priv *priv = vpriv;
3300
3301         return priv->netdev;
3302 }
3303
3304 static struct mlx5_interface mlx5e_interface = {
3305         .add       = mlx5e_create_netdev,
3306         .remove    = mlx5e_destroy_netdev,
3307         .event     = mlx5e_async_event,
3308         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3309         .get_dev   = mlx5e_get_netdev,
3310 };
3311
3312 void mlx5e_init(void)
3313 {
3314         mlx5_register_interface(&mlx5e_interface);
3315 }
3316
3317 void mlx5e_cleanup(void)
3318 {
3319         mlx5_unregister_interface(&mlx5e_interface);
3320 }