drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5_core_dev *mdev = priv->mdev;
  97         struct mlx5e_pport_stats *s = &priv->stats.pport;
  98         u32 *in;
  99         u32 *out;
 100         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 101
 102         in  = mlx5_vzalloc(sz);
 103         out = mlx5_vzalloc(sz);
 104         if (!in || !out)
 105                 goto free_out;
 106
 107         MLX5_SET(ppcnt_reg, in, local_port, 1);
 108
 109         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 110         mlx5_core_access_reg(mdev, in, sz, out,
 111                              sz, MLX5_REG_PPCNT, 0, 0);
 112         memcpy(s->IEEE_802_3_counters,
 113                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 114                sizeof(s->IEEE_802_3_counters));
 115
 116         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 117         mlx5_core_access_reg(mdev, in, sz, out,
 118                              sz, MLX5_REG_PPCNT, 0, 0);
 119         memcpy(s->RFC_2863_counters,
 120                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 121                sizeof(s->RFC_2863_counters));
 122
 123         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 124         mlx5_core_access_reg(mdev, in, sz, out,
 125                              sz, MLX5_REG_PPCNT, 0, 0);
 126         memcpy(s->RFC_2819_counters,
 127                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 128                sizeof(s->RFC_2819_counters));
 129
 130 free_out:
 131         kvfree(in);
 132         kvfree(out);
 133 }
 134
 135 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 136 {
 137         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 138
 139         if (!priv->q_counter)
 140                 return;
 141
 142         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 143                                       &qcnt->rx_out_of_buffer);
 144 }
 145
 146 void mlx5e_update_stats(struct mlx5e_priv *priv)
 147 {
 148         struct mlx5_core_dev *mdev = priv->mdev;
 149         struct mlx5e_vport_stats *s = &priv->stats.vport;
 150         struct mlx5e_rq_stats *rq_stats;
 151         struct mlx5e_sq_stats *sq_stats;
 152         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 153         u32 *out;
 154         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 155         u64 tx_offload_none;
 156         int i, j;
 157
 158         out = mlx5_vzalloc(outlen);
 159         if (!out)
 160                 return;
 161
 162         /* Collect firts the SW counters and then HW for consistency */
 163         s->rx_packets           = 0;
 164         s->rx_bytes             = 0;
 165         s->tx_packets           = 0;
 166         s->tx_bytes             = 0;
 167         s->tso_packets          = 0;
 168         s->tso_bytes            = 0;
 169         s->tso_inner_packets    = 0;
 170         s->tso_inner_bytes      = 0;
 171         s->tx_queue_stopped     = 0;
 172         s->tx_queue_wake        = 0;
 173         s->tx_queue_dropped     = 0;
 174         s->tx_csum_inner        = 0;
 175         tx_offload_none         = 0;
 176         s->lro_packets          = 0;
 177         s->lro_bytes            = 0;
 178         s->rx_csum_none         = 0;
 179         s->rx_csum_sw           = 0;
 180         s->rx_wqe_err           = 0;
 181         s->rx_mpwqe_filler      = 0;
 182         for (i = 0; i < priv->params.num_channels; i++) {
 183                 rq_stats = &priv->channel[i]->rq.stats;
 184
 185                 s->rx_packets   += rq_stats->packets;
 186                 s->rx_bytes     += rq_stats->bytes;
 187                 s->lro_packets  += rq_stats->lro_packets;
 188                 s->lro_bytes    += rq_stats->lro_bytes;
 189                 s->rx_csum_none += rq_stats->csum_none;
 190                 s->rx_csum_sw   += rq_stats->csum_sw;
 191                 s->rx_wqe_err   += rq_stats->wqe_err;
 192                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 193
 194                 for (j = 0; j < priv->params.num_tc; j++) {
 195                         sq_stats = &priv->channel[i]->sq[j].stats;
 196
 197                         s->tx_packets           += sq_stats->packets;
 198                         s->tx_bytes             += sq_stats->bytes;
 199                         s->tso_packets          += sq_stats->tso_packets;
 200                         s->tso_bytes            += sq_stats->tso_bytes;
 201                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 202                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 203                         s->tx_queue_stopped     += sq_stats->stopped;
 204                         s->tx_queue_wake        += sq_stats->wake;
 205                         s->tx_queue_dropped     += sq_stats->dropped;
 206                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 207                         tx_offload_none         += sq_stats->csum_offload_none;
 208                 }
 209         }
 210
 211         /* HW counters */
 212         memset(in, 0, sizeof(in));
 213
 214         MLX5_SET(query_vport_counter_in, in, opcode,
 215                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 216         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 217         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 218
 219         memset(out, 0, outlen);
 220
 221         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 222                 goto free_out;
 223
 224 #define MLX5_GET_CTR(p, x) \
 225         MLX5_GET64(query_vport_counter_out, p, x)
 226
 227         s->rx_error_packets     =
 228                 MLX5_GET_CTR(out, received_errors.packets);
 229         s->rx_error_bytes       =
 230                 MLX5_GET_CTR(out, received_errors.octets);
 231         s->tx_error_packets     =
 232                 MLX5_GET_CTR(out, transmit_errors.packets);
 233         s->tx_error_bytes       =
 234                 MLX5_GET_CTR(out, transmit_errors.octets);
 235
 236         s->rx_unicast_packets   =
 237                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 238         s->rx_unicast_bytes     =
 239                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 240         s->tx_unicast_packets   =
 241                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 242         s->tx_unicast_bytes     =
 243                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 244
 245         s->rx_multicast_packets =
 246                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 247         s->rx_multicast_bytes   =
 248                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 249         s->tx_multicast_packets =
 250                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 251         s->tx_multicast_bytes   =
 252                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 253
 254         s->rx_broadcast_packets =
 255                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 256         s->rx_broadcast_bytes   =
 257                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 258         s->tx_broadcast_packets =
 259                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 260         s->tx_broadcast_bytes   =
 261                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 262
 263         /* Update calculated offload counters */
 264         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 265         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 266                                s->rx_csum_sw;
 267
 268         mlx5e_update_pport_counters(priv);
 269         mlx5e_update_q_counter(priv);
 270
 271 free_out:
 272         kvfree(out);
 273 }
 274
 275 static void mlx5e_update_stats_work(struct work_struct *work)
 276 {
 277         struct delayed_work *dwork = to_delayed_work(work);
 278         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 279                                                update_stats_work);
 280         mutex_lock(&priv->state_lock);
 281         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 282                 mlx5e_update_stats(priv);
 283                 schedule_delayed_work(dwork,
 284                                       msecs_to_jiffies(
 285                                               MLX5E_UPDATE_STATS_INTERVAL));
 286         }
 287         mutex_unlock(&priv->state_lock);
 288 }
 289
 290 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 291                               enum mlx5_dev_event event, unsigned long param)
 292 {
 293         struct mlx5e_priv *priv = vpriv;
 294
 295         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 296                 return;
 297
 298         switch (event) {
 299         case MLX5_DEV_EVENT_PORT_UP:
 300         case MLX5_DEV_EVENT_PORT_DOWN:
 301                 schedule_work(&priv->update_carrier_work);
 302                 break;
 303
 304         default:
 305                 break;
 306         }
 307 }
 308
 309 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 310 {
 311         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 312 }
 313
 314 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 315 {
 316         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 317         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 318 }
 319
 320 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 321 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 322
 323 static int mlx5e_create_rq(struct mlx5e_channel *c,
 324                            struct mlx5e_rq_param *param,
 325                            struct mlx5e_rq *rq)
 326 {
 327         struct mlx5e_priv *priv = c->priv;
 328         struct mlx5_core_dev *mdev = priv->mdev;
 329         void *rqc = param->rqc;
 330         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 331         u32 byte_count;
 332         int wq_sz;
 333         int err;
 334         int i;
 335
 336         param->wq.db_numa_node = cpu_to_node(c->cpu);
 337
 338         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 339                                 &rq->wq_ctrl);
 340         if (err)
 341                 return err;
 342
 343         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 344
 345         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 346
 347         switch (priv->params.rq_wq_type) {
 348         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 349                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 350                                             GFP_KERNEL, cpu_to_node(c->cpu));
 351                 if (!rq->wqe_info) {
 352                         err = -ENOMEM;
 353                         goto err_rq_wq_destroy;
 354                 }
 355                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 356                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 357
 358                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 359                 byte_count = rq->wqe_sz;
 360                 break;
 361         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 362                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 363                                        cpu_to_node(c->cpu));
 364                 if (!rq->skb) {
 365                         err = -ENOMEM;
 366                         goto err_rq_wq_destroy;
 367                 }
 368                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 369                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 370
 371                 rq->wqe_sz = (priv->params.lro_en) ?
 372                                 priv->params.lro_wqe_sz :
 373                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 374                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 375                 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 376                 byte_count |= MLX5_HW_START_PADDING;
 377         }
 378
 379         for (i = 0; i < wq_sz; i++) {
 380                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 381
 382                 wqe->data.lkey       = c->mkey_be;
 383                 wqe->data.byte_count = cpu_to_be32(byte_count);
 384         }
 385
 386         rq->wq_type = priv->params.rq_wq_type;
 387         rq->pdev    = c->pdev;
 388         rq->netdev  = c->netdev;
 389         rq->tstamp  = &priv->tstamp;
 390         rq->channel = c;
 391         rq->ix      = c->ix;
 392         rq->priv    = c->priv;
 393
 394         return 0;
 395
 396 err_rq_wq_destroy:
 397         mlx5_wq_destroy(&rq->wq_ctrl);
 398
 399         return err;
 400 }
 401
 402 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 403 {
 404         switch (rq->wq_type) {
 405         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 406                 kfree(rq->wqe_info);
 407                 break;
 408         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 409                 kfree(rq->skb);
 410         }
 411
 412         mlx5_wq_destroy(&rq->wq_ctrl);
 413 }
 414
 415 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 416 {
 417         struct mlx5e_priv *priv = rq->priv;
 418         struct mlx5_core_dev *mdev = priv->mdev;
 419
 420         void *in;
 421         void *rqc;
 422         void *wq;
 423         int inlen;
 424         int err;
 425
 426         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 427                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 428         in = mlx5_vzalloc(inlen);
 429         if (!in)
 430                 return -ENOMEM;
 431
 432         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 433         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 434
 435         memcpy(rqc, param->rqc, sizeof(param->rqc));
 436
 437         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 438         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 439         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 440         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 441                                                 MLX5_ADAPTER_PAGE_SHIFT);
 442         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 443
 444         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 445                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 446
 447         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 448
 449         kvfree(in);
 450
 451         return err;
 452 }
 453
 454 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 455 {
 456         struct mlx5e_channel *c = rq->channel;
 457         struct mlx5e_priv *priv = c->priv;
 458         struct mlx5_core_dev *mdev = priv->mdev;
 459
 460         void *in;
 461         void *rqc;
 462         int inlen;
 463         int err;
 464
 465         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 466         in = mlx5_vzalloc(inlen);
 467         if (!in)
 468                 return -ENOMEM;
 469
 470         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 471
 472         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 473         MLX5_SET(rqc, rqc, state, next_state);
 474
 475         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 476
 477         kvfree(in);
 478
 479         return err;
 480 }
 481
 482 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 483 {
 484         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 485 }
 486
 487 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 488 {
 489         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 490         struct mlx5e_channel *c = rq->channel;
 491         struct mlx5e_priv *priv = c->priv;
 492         struct mlx5_wq_ll *wq = &rq->wq;
 493
 494         while (time_before(jiffies, exp_time)) {
 495                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 496                         return 0;
 497
 498                 msleep(20);
 499         }
 500
 501         return -ETIMEDOUT;
 502 }
 503
 504 static int mlx5e_open_rq(struct mlx5e_channel *c,
 505                          struct mlx5e_rq_param *param,
 506                          struct mlx5e_rq *rq)
 507 {
 508         struct mlx5e_sq *sq = &c->icosq;
 509         u16 pi = sq->pc & sq->wq.sz_m1;
 510         int err;
 511
 512         err = mlx5e_create_rq(c, param, rq);
 513         if (err)
 514                 return err;
 515
 516         err = mlx5e_enable_rq(rq, param);
 517         if (err)
 518                 goto err_destroy_rq;
 519
 520         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 521         if (err)
 522                 goto err_disable_rq;
 523
 524         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 525
 526         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 527         sq->ico_wqe_info[pi].num_wqebbs = 1;
 528         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 529
 530         return 0;
 531
 532 err_disable_rq:
 533         mlx5e_disable_rq(rq);
 534 err_destroy_rq:
 535         mlx5e_destroy_rq(rq);
 536
 537         return err;
 538 }
 539
 540 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 541 {
 542         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 543         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 544
 545         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 546         while (!mlx5_wq_ll_is_empty(&rq->wq))
 547                 msleep(20);
 548
 549         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 550         napi_synchronize(&rq->channel->napi);
 551
 552         mlx5e_disable_rq(rq);
 553         mlx5e_destroy_rq(rq);
 554 }
 555
 556 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 557 {
 558         kfree(sq->wqe_info);
 559         kfree(sq->dma_fifo);
 560         kfree(sq->skb);
 561 }
 562
 563 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 564 {
 565         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 566         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 567
 568         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 569         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 570                                     numa);
 571         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 572                                     numa);
 573
 574         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 575                 mlx5e_free_sq_db(sq);
 576                 return -ENOMEM;
 577         }
 578
 579         sq->dma_fifo_mask = df_sz - 1;
 580
 581         return 0;
 582 }
 583
 584 static int mlx5e_create_sq(struct mlx5e_channel *c,
 585                            int tc,
 586                            struct mlx5e_sq_param *param,
 587                            struct mlx5e_sq *sq)
 588 {
 589         struct mlx5e_priv *priv = c->priv;
 590         struct mlx5_core_dev *mdev = priv->mdev;
 591
 592         void *sqc = param->sqc;
 593         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 594         int err;
 595
 596         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 597         if (err)
 598                 return err;
 599
 600         param->wq.db_numa_node = cpu_to_node(c->cpu);
 601
 602         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 603                                  &sq->wq_ctrl);
 604         if (err)
 605                 goto err_unmap_free_uar;
 606
 607         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 608         if (sq->uar.bf_map) {
 609                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 610                 sq->uar_map = sq->uar.bf_map;
 611         } else {
 612                 sq->uar_map = sq->uar.map;
 613         }
 614         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 615         sq->max_inline  = param->max_inline;
 616
 617         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 618         if (err)
 619                 goto err_sq_wq_destroy;
 620
 621         if (param->icosq) {
 622                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 623
 624                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 625                                                 wq_sz,
 626                                                 GFP_KERNEL,
 627                                                 cpu_to_node(c->cpu));
 628                 if (!sq->ico_wqe_info) {
 629                         err = -ENOMEM;
 630                         goto err_free_sq_db;
 631                 }
 632         } else {
 633                 int txq_ix;
 634
 635                 txq_ix = c->ix + tc * priv->params.num_channels;
 636                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 637                 priv->txq_to_sq_map[txq_ix] = sq;
 638         }
 639
 640         sq->pdev      = c->pdev;
 641         sq->tstamp    = &priv->tstamp;
 642         sq->mkey_be   = c->mkey_be;
 643         sq->channel   = c;
 644         sq->tc        = tc;
 645         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 646         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 647
 648         return 0;
 649
 650 err_free_sq_db:
 651         mlx5e_free_sq_db(sq);
 652
 653 err_sq_wq_destroy:
 654         mlx5_wq_destroy(&sq->wq_ctrl);
 655
 656 err_unmap_free_uar:
 657         mlx5_unmap_free_uar(mdev, &sq->uar);
 658
 659         return err;
 660 }
 661
 662 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 663 {
 664         struct mlx5e_channel *c = sq->channel;
 665         struct mlx5e_priv *priv = c->priv;
 666
 667         kfree(sq->ico_wqe_info);
 668         mlx5e_free_sq_db(sq);
 669         mlx5_wq_destroy(&sq->wq_ctrl);
 670         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 671 }
 672
 673 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 674 {
 675         struct mlx5e_channel *c = sq->channel;
 676         struct mlx5e_priv *priv = c->priv;
 677         struct mlx5_core_dev *mdev = priv->mdev;
 678
 679         void *in;
 680         void *sqc;
 681         void *wq;
 682         int inlen;
 683         int err;
 684
 685         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 686                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 687         in = mlx5_vzalloc(inlen);
 688         if (!in)
 689                 return -ENOMEM;
 690
 691         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 692         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 693
 694         memcpy(sqc, param->sqc, sizeof(param->sqc));
 695
 696         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 697         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 698         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 699         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 700         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 701
 702         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 703         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 704         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 705                                           MLX5_ADAPTER_PAGE_SHIFT);
 706         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 707
 708         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 709                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 710
 711         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 712
 713         kvfree(in);
 714
 715         return err;
 716 }
 717
 718 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 719 {
 720         struct mlx5e_channel *c = sq->channel;
 721         struct mlx5e_priv *priv = c->priv;
 722         struct mlx5_core_dev *mdev = priv->mdev;
 723
 724         void *in;
 725         void *sqc;
 726         int inlen;
 727         int err;
 728
 729         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 730         in = mlx5_vzalloc(inlen);
 731         if (!in)
 732                 return -ENOMEM;
 733
 734         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 735
 736         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 737         MLX5_SET(sqc, sqc, state, next_state);
 738
 739         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 740
 741         kvfree(in);
 742
 743         return err;
 744 }
 745
 746 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 747 {
 748         struct mlx5e_channel *c = sq->channel;
 749         struct mlx5e_priv *priv = c->priv;
 750         struct mlx5_core_dev *mdev = priv->mdev;
 751
 752         mlx5_core_destroy_sq(mdev, sq->sqn);
 753 }
 754
 755 static int mlx5e_open_sq(struct mlx5e_channel *c,
 756                          int tc,
 757                          struct mlx5e_sq_param *param,
 758                          struct mlx5e_sq *sq)
 759 {
 760         int err;
 761
 762         err = mlx5e_create_sq(c, tc, param, sq);
 763         if (err)
 764                 return err;
 765
 766         err = mlx5e_enable_sq(sq, param);
 767         if (err)
 768                 goto err_destroy_sq;
 769
 770         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 771         if (err)
 772                 goto err_disable_sq;
 773
 774         if (sq->txq) {
 775                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 776                 netdev_tx_reset_queue(sq->txq);
 777                 netif_tx_start_queue(sq->txq);
 778         }
 779
 780         return 0;
 781
 782 err_disable_sq:
 783         mlx5e_disable_sq(sq);
 784 err_destroy_sq:
 785         mlx5e_destroy_sq(sq);
 786
 787         return err;
 788 }
 789
 790 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 791 {
 792         __netif_tx_lock_bh(txq);
 793         netif_tx_stop_queue(txq);
 794         __netif_tx_unlock_bh(txq);
 795 }
 796
 797 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 798 {
 799         if (sq->txq) {
 800                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 801                 /* prevent netif_tx_wake_queue */
 802                 napi_synchronize(&sq->channel->napi);
 803                 netif_tx_disable_queue(sq->txq);
 804
 805                 /* ensure hw is notified of all pending wqes */
 806                 if (mlx5e_sq_has_room_for(sq, 1))
 807                         mlx5e_send_nop(sq, true);
 808
 809                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 810         }
 811
 812         while (sq->cc != sq->pc) /* wait till sq is empty */
 813                 msleep(20);
 814
 815         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 816         napi_synchronize(&sq->channel->napi);
 817
 818         mlx5e_disable_sq(sq);
 819         mlx5e_destroy_sq(sq);
 820 }
 821
 822 static int mlx5e_create_cq(struct mlx5e_channel *c,
 823                            struct mlx5e_cq_param *param,
 824                            struct mlx5e_cq *cq)
 825 {
 826         struct mlx5e_priv *priv = c->priv;
 827         struct mlx5_core_dev *mdev = priv->mdev;
 828         struct mlx5_core_cq *mcq = &cq->mcq;
 829         int eqn_not_used;
 830         unsigned int irqn;
 831         int err;
 832         u32 i;
 833
 834         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 835         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 836         param->eq_ix   = c->ix;
 837
 838         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 839                                &cq->wq_ctrl);
 840         if (err)
 841                 return err;
 842
 843         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 844
 845         cq->napi        = &c->napi;
 846
 847         mcq->cqe_sz     = 64;
 848         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 849         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 850         *mcq->set_ci_db = 0;
 851         *mcq->arm_db    = 0;
 852         mcq->vector     = param->eq_ix;
 853         mcq->comp       = mlx5e_completion_event;
 854         mcq->event      = mlx5e_cq_error_event;
 855         mcq->irqn       = irqn;
 856         mcq->uar        = &priv->cq_uar;
 857
 858         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 859                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 860
 861                 cqe->op_own = 0xf1;
 862         }
 863
 864         cq->channel = c;
 865         cq->priv = priv;
 866
 867         return 0;
 868 }
 869
 870 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 871 {
 872         mlx5_wq_destroy(&cq->wq_ctrl);
 873 }
 874
 875 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 876 {
 877         struct mlx5e_priv *priv = cq->priv;
 878         struct mlx5_core_dev *mdev = priv->mdev;
 879         struct mlx5_core_cq *mcq = &cq->mcq;
 880
 881         void *in;
 882         void *cqc;
 883         int inlen;
 884         unsigned int irqn_not_used;
 885         int eqn;
 886         int err;
 887
 888         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 889                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 890         in = mlx5_vzalloc(inlen);
 891         if (!in)
 892                 return -ENOMEM;
 893
 894         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 895
 896         memcpy(cqc, param->cqc, sizeof(param->cqc));
 897
 898         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 899                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 900
 901         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 902
 903         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 904         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 905         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 906                                             MLX5_ADAPTER_PAGE_SHIFT);
 907         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 908
 909         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 910
 911         kvfree(in);
 912
 913         if (err)
 914                 return err;
 915
 916         mlx5e_cq_arm(cq);
 917
 918         return 0;
 919 }
 920
 921 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 922 {
 923         struct mlx5e_priv *priv = cq->priv;
 924         struct mlx5_core_dev *mdev = priv->mdev;
 925
 926         mlx5_core_destroy_cq(mdev, &cq->mcq);
 927 }
 928
 929 static int mlx5e_open_cq(struct mlx5e_channel *c,
 930                          struct mlx5e_cq_param *param,
 931                          struct mlx5e_cq *cq,
 932                          u16 moderation_usecs,
 933                          u16 moderation_frames)
 934 {
 935         int err;
 936         struct mlx5e_priv *priv = c->priv;
 937         struct mlx5_core_dev *mdev = priv->mdev;
 938
 939         err = mlx5e_create_cq(c, param, cq);
 940         if (err)
 941                 return err;
 942
 943         err = mlx5e_enable_cq(cq, param);
 944         if (err)
 945                 goto err_destroy_cq;
 946
 947         if (MLX5_CAP_GEN(mdev, cq_moderation))
 948                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 949                                                moderation_usecs,
 950                                                moderation_frames);
 951         return 0;
 952
 953 err_destroy_cq:
 954         mlx5e_destroy_cq(cq);
 955
 956         return err;
 957 }
 958
 959 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 960 {
 961         mlx5e_disable_cq(cq);
 962         mlx5e_destroy_cq(cq);
 963 }
 964
 965 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 966 {
 967         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 968 }
 969
 970 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 971                              struct mlx5e_channel_param *cparam)
 972 {
 973         struct mlx5e_priv *priv = c->priv;
 974         int err;
 975         int tc;
 976
 977         for (tc = 0; tc < c->num_tc; tc++) {
 978                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 979                                     priv->params.tx_cq_moderation_usec,
 980                                     priv->params.tx_cq_moderation_pkts);
 981                 if (err)
 982                         goto err_close_tx_cqs;
 983         }
 984
 985         return 0;
 986
 987 err_close_tx_cqs:
 988         for (tc--; tc >= 0; tc--)
 989                 mlx5e_close_cq(&c->sq[tc].cq);
 990
 991         return err;
 992 }
 993
 994 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 995 {
 996         int tc;
 997
 998         for (tc = 0; tc < c->num_tc; tc++)
 999                 mlx5e_close_cq(&c->sq[tc].cq);
1000 }
1001
1002 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1003                           struct mlx5e_channel_param *cparam)
1004 {
1005         int err;
1006         int tc;
1007
1008         for (tc = 0; tc < c->num_tc; tc++) {
1009                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1010                 if (err)
1011                         goto err_close_sqs;
1012         }
1013
1014         return 0;
1015
1016 err_close_sqs:
1017         for (tc--; tc >= 0; tc--)
1018                 mlx5e_close_sq(&c->sq[tc]);
1019
1020         return err;
1021 }
1022
1023 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1024 {
1025         int tc;
1026
1027         for (tc = 0; tc < c->num_tc; tc++)
1028                 mlx5e_close_sq(&c->sq[tc]);
1029 }
1030
1031 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1032 {
1033         int i;
1034
1035         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1036                 priv->channeltc_to_txq_map[ix][i] =
1037                         ix + i * priv->params.num_channels;
1038 }
1039
1040 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1041                               struct mlx5e_channel_param *cparam,
1042                               struct mlx5e_channel **cp)
1043 {
1044         struct net_device *netdev = priv->netdev;
1045         int cpu = mlx5e_get_cpu(priv, ix);
1046         struct mlx5e_channel *c;
1047         int err;
1048
1049         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1050         if (!c)
1051                 return -ENOMEM;
1052
1053         c->priv     = priv;
1054         c->ix       = ix;
1055         c->cpu      = cpu;
1056         c->pdev     = &priv->mdev->pdev->dev;
1057         c->netdev   = priv->netdev;
1058         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1059         c->num_tc   = priv->params.num_tc;
1060
1061         mlx5e_build_channeltc_to_txq_map(priv, ix);
1062
1063         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1064
1065         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1066         if (err)
1067                 goto err_napi_del;
1068
1069         err = mlx5e_open_tx_cqs(c, cparam);
1070         if (err)
1071                 goto err_close_icosq_cq;
1072
1073         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1074                             priv->params.rx_cq_moderation_usec,
1075                             priv->params.rx_cq_moderation_pkts);
1076         if (err)
1077                 goto err_close_tx_cqs;
1078
1079         napi_enable(&c->napi);
1080
1081         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1082         if (err)
1083                 goto err_disable_napi;
1084
1085         err = mlx5e_open_sqs(c, cparam);
1086         if (err)
1087                 goto err_close_icosq;
1088
1089         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1090         if (err)
1091                 goto err_close_sqs;
1092
1093         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1094         *cp = c;
1095
1096         return 0;
1097
1098 err_close_sqs:
1099         mlx5e_close_sqs(c);
1100
1101 err_close_icosq:
1102         mlx5e_close_sq(&c->icosq);
1103
1104 err_disable_napi:
1105         napi_disable(&c->napi);
1106         mlx5e_close_cq(&c->rq.cq);
1107
1108 err_close_tx_cqs:
1109         mlx5e_close_tx_cqs(c);
1110
1111 err_close_icosq_cq:
1112         mlx5e_close_cq(&c->icosq.cq);
1113
1114 err_napi_del:
1115         netif_napi_del(&c->napi);
1116         napi_hash_del(&c->napi);
1117         kfree(c);
1118
1119         return err;
1120 }
1121
1122 static void mlx5e_close_channel(struct mlx5e_channel *c)
1123 {
1124         mlx5e_close_rq(&c->rq);
1125         mlx5e_close_sqs(c);
1126         mlx5e_close_sq(&c->icosq);
1127         napi_disable(&c->napi);
1128         mlx5e_close_cq(&c->rq.cq);
1129         mlx5e_close_tx_cqs(c);
1130         mlx5e_close_cq(&c->icosq.cq);
1131         netif_napi_del(&c->napi);
1132
1133         napi_hash_del(&c->napi);
1134         synchronize_rcu();
1135
1136         kfree(c);
1137 }
1138
1139 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1140                                  struct mlx5e_rq_param *param)
1141 {
1142         void *rqc = param->rqc;
1143         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1144
1145         switch (priv->params.rq_wq_type) {
1146         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1147                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1148                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1149                 MLX5_SET(wq, wq, log_wqe_stride_size,
1150                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1151                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1152                 break;
1153         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1154                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1155         }
1156
1157         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1158         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1159         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1160         MLX5_SET(wq, wq, pd,               priv->pdn);
1161         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1162
1163         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1164         param->wq.linear = 1;
1165 }
1166
1167 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1168 {
1169         void *rqc = param->rqc;
1170         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1171
1172         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1173         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1174 }
1175
1176 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1177                                         struct mlx5e_sq_param *param)
1178 {
1179         void *sqc = param->sqc;
1180         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1181
1182         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1183         MLX5_SET(wq, wq, pd,            priv->pdn);
1184
1185         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1186 }
1187
1188 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1189                                  struct mlx5e_sq_param *param)
1190 {
1191         void *sqc = param->sqc;
1192         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1193
1194         mlx5e_build_sq_param_common(priv, param);
1195         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1196
1197         param->max_inline = priv->params.tx_max_inline;
1198 }
1199
1200 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1201                                         struct mlx5e_cq_param *param)
1202 {
1203         void *cqc = param->cqc;
1204
1205         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1206 }
1207
1208 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1209                                     struct mlx5e_cq_param *param)
1210 {
1211         void *cqc = param->cqc;
1212         u8 log_cq_size;
1213
1214         switch (priv->params.rq_wq_type) {
1215         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1216                 log_cq_size = priv->params.log_rq_size +
1217                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1218                 break;
1219         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1220                 log_cq_size = priv->params.log_rq_size;
1221         }
1222
1223         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1224
1225         mlx5e_build_common_cq_param(priv, param);
1226 }
1227
1228 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1229                                     struct mlx5e_cq_param *param)
1230 {
1231         void *cqc = param->cqc;
1232
1233         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1234
1235         mlx5e_build_common_cq_param(priv, param);
1236 }
1237
1238 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1239                                      struct mlx5e_cq_param *param,
1240                                      u8 log_wq_size)
1241 {
1242         void *cqc = param->cqc;
1243
1244         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1245
1246         mlx5e_build_common_cq_param(priv, param);
1247 }
1248
1249 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1250                                     struct mlx5e_sq_param *param,
1251                                     u8 log_wq_size)
1252 {
1253         void *sqc = param->sqc;
1254         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1255
1256         mlx5e_build_sq_param_common(priv, param);
1257
1258         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1259
1260         param->icosq = true;
1261 }
1262
1263 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1264                                       struct mlx5e_channel_param *cparam)
1265 {
1266         u8 icosq_log_wq_sz = 0;
1267
1268         memset(cparam, 0, sizeof(*cparam));
1269
1270         mlx5e_build_rq_param(priv, &cparam->rq);
1271         mlx5e_build_sq_param(priv, &cparam->sq);
1272         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1273         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1274         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1275         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1276 }
1277
1278 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1279 {
1280         struct mlx5e_channel_param cparam;
1281         int nch = priv->params.num_channels;
1282         int err = -ENOMEM;
1283         int i;
1284         int j;
1285
1286         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1287                                 GFP_KERNEL);
1288
1289         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1290                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1291
1292         if (!priv->channel || !priv->txq_to_sq_map)
1293                 goto err_free_txq_to_sq_map;
1294
1295         mlx5e_build_channel_param(priv, &cparam);
1296         for (i = 0; i < nch; i++) {
1297                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1298                 if (err)
1299                         goto err_close_channels;
1300         }
1301
1302         for (j = 0; j < nch; j++) {
1303                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1304                 if (err)
1305                         goto err_close_channels;
1306         }
1307
1308         return 0;
1309
1310 err_close_channels:
1311         for (i--; i >= 0; i--)
1312                 mlx5e_close_channel(priv->channel[i]);
1313
1314 err_free_txq_to_sq_map:
1315         kfree(priv->txq_to_sq_map);
1316         kfree(priv->channel);
1317
1318         return err;
1319 }
1320
1321 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1322 {
1323         int i;
1324
1325         for (i = 0; i < priv->params.num_channels; i++)
1326                 mlx5e_close_channel(priv->channel[i]);
1327
1328         kfree(priv->txq_to_sq_map);
1329         kfree(priv->channel);
1330 }
1331
1332 static int mlx5e_rx_hash_fn(int hfunc)
1333 {
1334         return (hfunc == ETH_RSS_HASH_TOP) ?
1335                MLX5_RX_HASH_FN_TOEPLITZ :
1336                MLX5_RX_HASH_FN_INVERTED_XOR8;
1337 }
1338
1339 static int mlx5e_bits_invert(unsigned long a, int size)
1340 {
1341         int inv = 0;
1342         int i;
1343
1344         for (i = 0; i < size; i++)
1345                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1346
1347         return inv;
1348 }
1349
1350 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1351 {
1352         int i;
1353
1354         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1355                 int ix = i;
1356
1357                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1358                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1359
1360                 ix = priv->params.indirection_rqt[ix];
1361                 MLX5_SET(rqtc, rqtc, rq_num[i],
1362                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1363                          priv->channel[ix]->rq.rqn :
1364                          priv->drop_rq.rqn);
1365         }
1366 }
1367
1368 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1369                                 enum mlx5e_rqt_ix rqt_ix)
1370 {
1371
1372         switch (rqt_ix) {
1373         case MLX5E_INDIRECTION_RQT:
1374                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1375
1376                 break;
1377
1378         default: /* MLX5E_SINGLE_RQ_RQT */
1379                 MLX5_SET(rqtc, rqtc, rq_num[0],
1380                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1381                          priv->channel[0]->rq.rqn :
1382                          priv->drop_rq.rqn);
1383
1384                 break;
1385         }
1386 }
1387
1388 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1389 {
1390         struct mlx5_core_dev *mdev = priv->mdev;
1391         u32 *in;
1392         void *rqtc;
1393         int inlen;
1394         int sz;
1395         int err;
1396
1397         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1398
1399         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1400         in = mlx5_vzalloc(inlen);
1401         if (!in)
1402                 return -ENOMEM;
1403
1404         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1405
1406         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1407         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1408
1409         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1410
1411         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1412
1413         kvfree(in);
1414
1415         return err;
1416 }
1417
1418 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1419 {
1420         struct mlx5_core_dev *mdev = priv->mdev;
1421         u32 *in;
1422         void *rqtc;
1423         int inlen;
1424         int sz;
1425         int err;
1426
1427         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1428
1429         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1430         in = mlx5_vzalloc(inlen);
1431         if (!in)
1432                 return -ENOMEM;
1433
1434         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1435
1436         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1437
1438         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1439
1440         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1441
1442         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1443
1444         kvfree(in);
1445
1446         return err;
1447 }
1448
1449 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1450 {
1451         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1452 }
1453
1454 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1455 {
1456         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1457         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1458 }
1459
1460 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1461 {
1462         if (!priv->params.lro_en)
1463                 return;
1464
1465 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1466
1467         MLX5_SET(tirc, tirc, lro_enable_mask,
1468                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1469                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1470         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1471                  (priv->params.lro_wqe_sz -
1472                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1473         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1474                  MLX5_CAP_ETH(priv->mdev,
1475                               lro_timer_supported_periods[2]));
1476 }
1477
1478 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1479 {
1480         MLX5_SET(tirc, tirc, rx_hash_fn,
1481                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1482         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1483                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1484                                              rx_hash_toeplitz_key);
1485                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1486                                                rx_hash_toeplitz_key);
1487
1488                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1489                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1490         }
1491 }
1492
1493 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1494 {
1495         struct mlx5_core_dev *mdev = priv->mdev;
1496
1497         void *in;
1498         void *tirc;
1499         int inlen;
1500         int err;
1501         int tt;
1502
1503         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1504         in = mlx5_vzalloc(inlen);
1505         if (!in)
1506                 return -ENOMEM;
1507
1508         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1509         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1510
1511         mlx5e_build_tir_ctx_lro(tirc, priv);
1512
1513         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1514                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1515                 if (err)
1516                         break;
1517         }
1518
1519         kvfree(in);
1520
1521         return err;
1522 }
1523
1524 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1525                                                   u32 tirn)
1526 {
1527         void *in;
1528         int inlen;
1529         int err;
1530
1531         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1532         in = mlx5_vzalloc(inlen);
1533         if (!in)
1534                 return -ENOMEM;
1535
1536         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1537
1538         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1539
1540         kvfree(in);
1541
1542         return err;
1543 }
1544
1545 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1546 {
1547         int err;
1548         int i;
1549
1550         for (i = 0; i < MLX5E_NUM_TT; i++) {
1551                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1552                                                              priv->tirn[i]);
1553                 if (err)
1554                         return err;
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1561 {
1562         struct mlx5e_priv *priv = netdev_priv(netdev);
1563         struct mlx5_core_dev *mdev = priv->mdev;
1564         int hw_mtu;
1565         int err;
1566
1567         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1568         if (err)
1569                 return err;
1570
1571         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1572
1573         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1574                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1575                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1576
1577         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1578         return 0;
1579 }
1580
1581 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1582 {
1583         struct mlx5e_priv *priv = netdev_priv(netdev);
1584         int nch = priv->params.num_channels;
1585         int ntc = priv->params.num_tc;
1586         int tc;
1587
1588         netdev_reset_tc(netdev);
1589
1590         if (ntc == 1)
1591                 return;
1592
1593         netdev_set_num_tc(netdev, ntc);
1594
1595         for (tc = 0; tc < ntc; tc++)
1596                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1597 }
1598
1599 int mlx5e_open_locked(struct net_device *netdev)
1600 {
1601         struct mlx5e_priv *priv = netdev_priv(netdev);
1602         int num_txqs;
1603         int err;
1604
1605         set_bit(MLX5E_STATE_OPENED, &priv->state);
1606
1607         mlx5e_netdev_set_tcs(netdev);
1608
1609         num_txqs = priv->params.num_channels * priv->params.num_tc;
1610         netif_set_real_num_tx_queues(netdev, num_txqs);
1611         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1612
1613         err = mlx5e_set_dev_port_mtu(netdev);
1614         if (err)
1615                 goto err_clear_state_opened_flag;
1616
1617         err = mlx5e_open_channels(priv);
1618         if (err) {
1619                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1620                            __func__, err);
1621                 goto err_clear_state_opened_flag;
1622         }
1623
1624         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1625         if (err) {
1626                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1627                            __func__, err);
1628                 goto err_close_channels;
1629         }
1630
1631         mlx5e_redirect_rqts(priv);
1632         mlx5e_update_carrier(priv);
1633         mlx5e_timestamp_init(priv);
1634
1635         schedule_delayed_work(&priv->update_stats_work, 0);
1636
1637         return 0;
1638
1639 err_close_channels:
1640         mlx5e_close_channels(priv);
1641 err_clear_state_opened_flag:
1642         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1643         return err;
1644 }
1645
1646 static int mlx5e_open(struct net_device *netdev)
1647 {
1648         struct mlx5e_priv *priv = netdev_priv(netdev);
1649         int err;
1650
1651         mutex_lock(&priv->state_lock);
1652         err = mlx5e_open_locked(netdev);
1653         mutex_unlock(&priv->state_lock);
1654
1655         return err;
1656 }
1657
1658 int mlx5e_close_locked(struct net_device *netdev)
1659 {
1660         struct mlx5e_priv *priv = netdev_priv(netdev);
1661
1662         /* May already be CLOSED in case a previous configuration operation
1663          * (e.g RX/TX queue size change) that involves close&open failed.
1664          */
1665         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1666                 return 0;
1667
1668         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1669
1670         mlx5e_timestamp_cleanup(priv);
1671         netif_carrier_off(priv->netdev);
1672         mlx5e_redirect_rqts(priv);
1673         mlx5e_close_channels(priv);
1674
1675         return 0;
1676 }
1677
1678 static int mlx5e_close(struct net_device *netdev)
1679 {
1680         struct mlx5e_priv *priv = netdev_priv(netdev);
1681         int err;
1682
1683         mutex_lock(&priv->state_lock);
1684         err = mlx5e_close_locked(netdev);
1685         mutex_unlock(&priv->state_lock);
1686
1687         return err;
1688 }
1689
1690 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1691                                 struct mlx5e_rq *rq,
1692                                 struct mlx5e_rq_param *param)
1693 {
1694         struct mlx5_core_dev *mdev = priv->mdev;
1695         void *rqc = param->rqc;
1696         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1697         int err;
1698
1699         param->wq.db_numa_node = param->wq.buf_numa_node;
1700
1701         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1702                                 &rq->wq_ctrl);
1703         if (err)
1704                 return err;
1705
1706         rq->priv = priv;
1707
1708         return 0;
1709 }
1710
1711 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1712                                 struct mlx5e_cq *cq,
1713                                 struct mlx5e_cq_param *param)
1714 {
1715         struct mlx5_core_dev *mdev = priv->mdev;
1716         struct mlx5_core_cq *mcq = &cq->mcq;
1717         int eqn_not_used;
1718         unsigned int irqn;
1719         int err;
1720
1721         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1722                                &cq->wq_ctrl);
1723         if (err)
1724                 return err;
1725
1726         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1727
1728         mcq->cqe_sz     = 64;
1729         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1730         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1731         *mcq->set_ci_db = 0;
1732         *mcq->arm_db    = 0;
1733         mcq->vector     = param->eq_ix;
1734         mcq->comp       = mlx5e_completion_event;
1735         mcq->event      = mlx5e_cq_error_event;
1736         mcq->irqn       = irqn;
1737         mcq->uar        = &priv->cq_uar;
1738
1739         cq->priv = priv;
1740
1741         return 0;
1742 }
1743
1744 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1745 {
1746         struct mlx5e_cq_param cq_param;
1747         struct mlx5e_rq_param rq_param;
1748         struct mlx5e_rq *rq = &priv->drop_rq;
1749         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1750         int err;
1751
1752         memset(&cq_param, 0, sizeof(cq_param));
1753         memset(&rq_param, 0, sizeof(rq_param));
1754         mlx5e_build_drop_rq_param(&rq_param);
1755
1756         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1757         if (err)
1758                 return err;
1759
1760         err = mlx5e_enable_cq(cq, &cq_param);
1761         if (err)
1762                 goto err_destroy_cq;
1763
1764         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1765         if (err)
1766                 goto err_disable_cq;
1767
1768         err = mlx5e_enable_rq(rq, &rq_param);
1769         if (err)
1770                 goto err_destroy_rq;
1771
1772         return 0;
1773
1774 err_destroy_rq:
1775         mlx5e_destroy_rq(&priv->drop_rq);
1776
1777 err_disable_cq:
1778         mlx5e_disable_cq(&priv->drop_rq.cq);
1779
1780 err_destroy_cq:
1781         mlx5e_destroy_cq(&priv->drop_rq.cq);
1782
1783         return err;
1784 }
1785
1786 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1787 {
1788         mlx5e_disable_rq(&priv->drop_rq);
1789         mlx5e_destroy_rq(&priv->drop_rq);
1790         mlx5e_disable_cq(&priv->drop_rq.cq);
1791         mlx5e_destroy_cq(&priv->drop_rq.cq);
1792 }
1793
1794 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1795 {
1796         struct mlx5_core_dev *mdev = priv->mdev;
1797         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1798         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1799
1800         memset(in, 0, sizeof(in));
1801
1802         MLX5_SET(tisc, tisc, prio, tc << 1);
1803         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1804
1805         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1806 }
1807
1808 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1809 {
1810         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1811 }
1812
1813 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1814 {
1815         int err;
1816         int tc;
1817
1818         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1819                 err = mlx5e_create_tis(priv, tc);
1820                 if (err)
1821                         goto err_close_tises;
1822         }
1823
1824         return 0;
1825
1826 err_close_tises:
1827         for (tc--; tc >= 0; tc--)
1828                 mlx5e_destroy_tis(priv, tc);
1829
1830         return err;
1831 }
1832
1833 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1834 {
1835         int tc;
1836
1837         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1838                 mlx5e_destroy_tis(priv, tc);
1839 }
1840
1841 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1842 {
1843         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1844
1845         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1846
1847 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1848                                  MLX5_HASH_FIELD_SEL_DST_IP)
1849
1850 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1851                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1852                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1853                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1854
1855 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1856                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1857                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1858
1859         mlx5e_build_tir_ctx_lro(tirc, priv);
1860
1861         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1862
1863         switch (tt) {
1864         case MLX5E_TT_ANY:
1865                 MLX5_SET(tirc, tirc, indirect_table,
1866                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1867                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1868                 break;
1869         default:
1870                 MLX5_SET(tirc, tirc, indirect_table,
1871                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1872                 mlx5e_build_tir_ctx_hash(tirc, priv);
1873                 break;
1874         }
1875
1876         switch (tt) {
1877         case MLX5E_TT_IPV4_TCP:
1878                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1879                          MLX5_L3_PROT_TYPE_IPV4);
1880                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1881                          MLX5_L4_PROT_TYPE_TCP);
1882                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1883                          MLX5_HASH_IP_L4PORTS);
1884                 break;
1885
1886         case MLX5E_TT_IPV6_TCP:
1887                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1888                          MLX5_L3_PROT_TYPE_IPV6);
1889                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1890                          MLX5_L4_PROT_TYPE_TCP);
1891                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1892                          MLX5_HASH_IP_L4PORTS);
1893                 break;
1894
1895         case MLX5E_TT_IPV4_UDP:
1896                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1897                          MLX5_L3_PROT_TYPE_IPV4);
1898                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1899                          MLX5_L4_PROT_TYPE_UDP);
1900                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1901                          MLX5_HASH_IP_L4PORTS);
1902                 break;
1903
1904         case MLX5E_TT_IPV6_UDP:
1905                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1906                          MLX5_L3_PROT_TYPE_IPV6);
1907                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1908                          MLX5_L4_PROT_TYPE_UDP);
1909                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1910                          MLX5_HASH_IP_L4PORTS);
1911                 break;
1912
1913         case MLX5E_TT_IPV4_IPSEC_AH:
1914                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1915                          MLX5_L3_PROT_TYPE_IPV4);
1916                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1917                          MLX5_HASH_IP_IPSEC_SPI);
1918                 break;
1919
1920         case MLX5E_TT_IPV6_IPSEC_AH:
1921                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1922                          MLX5_L3_PROT_TYPE_IPV6);
1923                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1924                          MLX5_HASH_IP_IPSEC_SPI);
1925                 break;
1926
1927         case MLX5E_TT_IPV4_IPSEC_ESP:
1928                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1929                          MLX5_L3_PROT_TYPE_IPV4);
1930                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1931                          MLX5_HASH_IP_IPSEC_SPI);
1932                 break;
1933
1934         case MLX5E_TT_IPV6_IPSEC_ESP:
1935                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1936                          MLX5_L3_PROT_TYPE_IPV6);
1937                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1938                          MLX5_HASH_IP_IPSEC_SPI);
1939                 break;
1940
1941         case MLX5E_TT_IPV4:
1942                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1943                          MLX5_L3_PROT_TYPE_IPV4);
1944                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1945                          MLX5_HASH_IP);
1946                 break;
1947
1948         case MLX5E_TT_IPV6:
1949                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1950                          MLX5_L3_PROT_TYPE_IPV6);
1951                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1952                          MLX5_HASH_IP);
1953                 break;
1954         }
1955 }
1956
1957 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1958 {
1959         struct mlx5_core_dev *mdev = priv->mdev;
1960         u32 *in;
1961         void *tirc;
1962         int inlen;
1963         int err;
1964
1965         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1966         in = mlx5_vzalloc(inlen);
1967         if (!in)
1968                 return -ENOMEM;
1969
1970         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1971
1972         mlx5e_build_tir_ctx(priv, tirc, tt);
1973
1974         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1975
1976         kvfree(in);
1977
1978         return err;
1979 }
1980
1981 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1982 {
1983         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1984 }
1985
1986 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1987 {
1988         int err;
1989         int i;
1990
1991         for (i = 0; i < MLX5E_NUM_TT; i++) {
1992                 err = mlx5e_create_tir(priv, i);
1993                 if (err)
1994                         goto err_destroy_tirs;
1995         }
1996
1997         return 0;
1998
1999 err_destroy_tirs:
2000         for (i--; i >= 0; i--)
2001                 mlx5e_destroy_tir(priv, i);
2002
2003         return err;
2004 }
2005
2006 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2007 {
2008         int i;
2009
2010         for (i = 0; i < MLX5E_NUM_TT; i++)
2011                 mlx5e_destroy_tir(priv, i);
2012 }
2013
2014 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2015 {
2016         struct mlx5e_priv *priv = netdev_priv(netdev);
2017         bool was_opened;
2018         int err = 0;
2019
2020         if (tc && tc != MLX5E_MAX_NUM_TC)
2021                 return -EINVAL;
2022
2023         mutex_lock(&priv->state_lock);
2024
2025         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2026         if (was_opened)
2027                 mlx5e_close_locked(priv->netdev);
2028
2029         priv->params.num_tc = tc ? tc : 1;
2030
2031         if (was_opened)
2032                 err = mlx5e_open_locked(priv->netdev);
2033
2034         mutex_unlock(&priv->state_lock);
2035
2036         return err;
2037 }
2038
2039 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2040                               __be16 proto, struct tc_to_netdev *tc)
2041 {
2042         struct mlx5e_priv *priv = netdev_priv(dev);
2043
2044         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2045                 goto mqprio;
2046
2047         switch (tc->type) {
2048         case TC_SETUP_CLSFLOWER:
2049                 switch (tc->cls_flower->command) {
2050                 case TC_CLSFLOWER_REPLACE:
2051                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2052                 case TC_CLSFLOWER_DESTROY:
2053                         return mlx5e_delete_flower(priv, tc->cls_flower);
2054                 }
2055         default:
2056                 return -EOPNOTSUPP;
2057         }
2058
2059 mqprio:
2060         if (tc->type != TC_SETUP_MQPRIO)
2061                 return -EINVAL;
2062
2063         return mlx5e_setup_tc(dev, tc->tc);
2064 }
2065
2066 static struct rtnl_link_stats64 *
2067 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2068 {
2069         struct mlx5e_priv *priv = netdev_priv(dev);
2070         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2071
2072         stats->rx_packets = vstats->rx_packets;
2073         stats->rx_bytes   = vstats->rx_bytes;
2074         stats->tx_packets = vstats->tx_packets;
2075         stats->tx_bytes   = vstats->tx_bytes;
2076         stats->multicast  = vstats->rx_multicast_packets +
2077                             vstats->tx_multicast_packets;
2078         stats->tx_errors  = vstats->tx_error_packets;
2079         stats->rx_errors  = vstats->rx_error_packets;
2080         stats->tx_dropped = vstats->tx_queue_dropped;
2081         stats->rx_crc_errors = 0;
2082         stats->rx_length_errors = 0;
2083
2084         return stats;
2085 }
2086
2087 static void mlx5e_set_rx_mode(struct net_device *dev)
2088 {
2089         struct mlx5e_priv *priv = netdev_priv(dev);
2090
2091         schedule_work(&priv->set_rx_mode_work);
2092 }
2093
2094 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2095 {
2096         struct mlx5e_priv *priv = netdev_priv(netdev);
2097         struct sockaddr *saddr = addr;
2098
2099         if (!is_valid_ether_addr(saddr->sa_data))
2100                 return -EADDRNOTAVAIL;
2101
2102         netif_addr_lock_bh(netdev);
2103         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2104         netif_addr_unlock_bh(netdev);
2105
2106         schedule_work(&priv->set_rx_mode_work);
2107
2108         return 0;
2109 }
2110
2111 static int mlx5e_set_features(struct net_device *netdev,
2112                               netdev_features_t features)
2113 {
2114         struct mlx5e_priv *priv = netdev_priv(netdev);
2115         int err = 0;
2116         netdev_features_t changes = features ^ netdev->features;
2117
2118         mutex_lock(&priv->state_lock);
2119
2120         if (changes & NETIF_F_LRO) {
2121                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2122
2123                 if (was_opened && (priv->params.rq_wq_type ==
2124                                    MLX5_WQ_TYPE_LINKED_LIST))
2125                         mlx5e_close_locked(priv->netdev);
2126
2127                 priv->params.lro_en = !!(features & NETIF_F_LRO);
2128                 err = mlx5e_modify_tirs_lro(priv);
2129                 if (err)
2130                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2131                                        err);
2132
2133                 if (was_opened && (priv->params.rq_wq_type ==
2134                                    MLX5_WQ_TYPE_LINKED_LIST))
2135                         err = mlx5e_open_locked(priv->netdev);
2136         }
2137
2138         mutex_unlock(&priv->state_lock);
2139
2140         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2141                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2142                         mlx5e_enable_vlan_filter(priv);
2143                 else
2144                         mlx5e_disable_vlan_filter(priv);
2145         }
2146
2147         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2148             mlx5e_tc_num_filters(priv)) {
2149                 netdev_err(netdev,
2150                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2151                 return -EINVAL;
2152         }
2153
2154         return err;
2155 }
2156
2157 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2158 {
2159         struct mlx5e_priv *priv = netdev_priv(netdev);
2160         struct mlx5_core_dev *mdev = priv->mdev;
2161         bool was_opened;
2162         int max_mtu;
2163         int err = 0;
2164
2165         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2166
2167         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2168
2169         if (new_mtu > max_mtu) {
2170                 netdev_err(netdev,
2171                            "%s: Bad MTU (%d) > (%d) Max\n",
2172                            __func__, new_mtu, max_mtu);
2173                 return -EINVAL;
2174         }
2175
2176         mutex_lock(&priv->state_lock);
2177
2178         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2179         if (was_opened)
2180                 mlx5e_close_locked(netdev);
2181
2182         netdev->mtu = new_mtu;
2183
2184         if (was_opened)
2185                 err = mlx5e_open_locked(netdev);
2186
2187         mutex_unlock(&priv->state_lock);
2188
2189         return err;
2190 }
2191
2192 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2193 {
2194         switch (cmd) {
2195         case SIOCSHWTSTAMP:
2196                 return mlx5e_hwstamp_set(dev, ifr);
2197         case SIOCGHWTSTAMP:
2198                 return mlx5e_hwstamp_get(dev, ifr);
2199         default:
2200                 return -EOPNOTSUPP;
2201         }
2202 }
2203
2204 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2205 {
2206         struct mlx5e_priv *priv = netdev_priv(dev);
2207         struct mlx5_core_dev *mdev = priv->mdev;
2208
2209         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2210 }
2211
2212 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2213 {
2214         struct mlx5e_priv *priv = netdev_priv(dev);
2215         struct mlx5_core_dev *mdev = priv->mdev;
2216
2217         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2218                                            vlan, qos);
2219 }
2220
2221 static int mlx5_vport_link2ifla(u8 esw_link)
2222 {
2223         switch (esw_link) {
2224         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2225                 return IFLA_VF_LINK_STATE_DISABLE;
2226         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2227                 return IFLA_VF_LINK_STATE_ENABLE;
2228         }
2229         return IFLA_VF_LINK_STATE_AUTO;
2230 }
2231
2232 static int mlx5_ifla_link2vport(u8 ifla_link)
2233 {
2234         switch (ifla_link) {
2235         case IFLA_VF_LINK_STATE_DISABLE:
2236                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2237         case IFLA_VF_LINK_STATE_ENABLE:
2238                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2239         }
2240         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2241 }
2242
2243 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2244                                    int link_state)
2245 {
2246         struct mlx5e_priv *priv = netdev_priv(dev);
2247         struct mlx5_core_dev *mdev = priv->mdev;
2248
2249         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2250                                             mlx5_ifla_link2vport(link_state));
2251 }
2252
2253 static int mlx5e_get_vf_config(struct net_device *dev,
2254                                int vf, struct ifla_vf_info *ivi)
2255 {
2256         struct mlx5e_priv *priv = netdev_priv(dev);
2257         struct mlx5_core_dev *mdev = priv->mdev;
2258         int err;
2259
2260         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2261         if (err)
2262                 return err;
2263         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2264         return 0;
2265 }
2266
2267 static int mlx5e_get_vf_stats(struct net_device *dev,
2268                               int vf, struct ifla_vf_stats *vf_stats)
2269 {
2270         struct mlx5e_priv *priv = netdev_priv(dev);
2271         struct mlx5_core_dev *mdev = priv->mdev;
2272
2273         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2274                                             vf_stats);
2275 }
2276
2277 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2278                                  sa_family_t sa_family, __be16 port)
2279 {
2280         struct mlx5e_priv *priv = netdev_priv(netdev);
2281
2282         if (!mlx5e_vxlan_allowed(priv->mdev))
2283                 return;
2284
2285         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2286 }
2287
2288 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2289                                  sa_family_t sa_family, __be16 port)
2290 {
2291         struct mlx5e_priv *priv = netdev_priv(netdev);
2292
2293         if (!mlx5e_vxlan_allowed(priv->mdev))
2294                 return;
2295
2296         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2297 }
2298
2299 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2300                                                     struct sk_buff *skb,
2301                                                     netdev_features_t features)
2302 {
2303         struct udphdr *udph;
2304         u16 proto;
2305         u16 port = 0;
2306
2307         switch (vlan_get_protocol(skb)) {
2308         case htons(ETH_P_IP):
2309                 proto = ip_hdr(skb)->protocol;
2310                 break;
2311         case htons(ETH_P_IPV6):
2312                 proto = ipv6_hdr(skb)->nexthdr;
2313                 break;
2314         default:
2315                 goto out;
2316         }
2317
2318         if (proto == IPPROTO_UDP) {
2319                 udph = udp_hdr(skb);
2320                 port = be16_to_cpu(udph->dest);
2321         }
2322
2323         /* Verify if UDP port is being offloaded by HW */
2324         if (port && mlx5e_vxlan_lookup_port(priv, port))
2325                 return features;
2326
2327 out:
2328         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2329         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2330 }
2331
2332 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2333                                               struct net_device *netdev,
2334                                               netdev_features_t features)
2335 {
2336         struct mlx5e_priv *priv = netdev_priv(netdev);
2337
2338         features = vlan_features_check(skb, features);
2339         features = vxlan_features_check(skb, features);
2340
2341         /* Validate if the tunneled packet is being offloaded by HW */
2342         if (skb->encapsulation &&
2343             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2344                 return mlx5e_vxlan_features_check(priv, skb, features);
2345
2346         return features;
2347 }
2348
2349 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2350         .ndo_open                = mlx5e_open,
2351         .ndo_stop                = mlx5e_close,
2352         .ndo_start_xmit          = mlx5e_xmit,
2353         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2354         .ndo_select_queue        = mlx5e_select_queue,
2355         .ndo_get_stats64         = mlx5e_get_stats,
2356         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2357         .ndo_set_mac_address     = mlx5e_set_mac,
2358         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2359         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2360         .ndo_set_features        = mlx5e_set_features,
2361         .ndo_change_mtu          = mlx5e_change_mtu,
2362         .ndo_do_ioctl            = mlx5e_ioctl,
2363 };
2364
2365 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2366         .ndo_open                = mlx5e_open,
2367         .ndo_stop                = mlx5e_close,
2368         .ndo_start_xmit          = mlx5e_xmit,
2369         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2370         .ndo_select_queue        = mlx5e_select_queue,
2371         .ndo_get_stats64         = mlx5e_get_stats,
2372         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2373         .ndo_set_mac_address     = mlx5e_set_mac,
2374         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2375         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2376         .ndo_set_features        = mlx5e_set_features,
2377         .ndo_change_mtu          = mlx5e_change_mtu,
2378         .ndo_do_ioctl            = mlx5e_ioctl,
2379         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2380         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2381         .ndo_features_check      = mlx5e_features_check,
2382         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2383         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2384         .ndo_get_vf_config       = mlx5e_get_vf_config,
2385         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2386         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2387 };
2388
2389 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2390 {
2391         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2392                 return -ENOTSUPP;
2393         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2394             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2395             !MLX5_CAP_ETH(mdev, csum_cap) ||
2396             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2397             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2398             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2399             MLX5_CAP_FLOWTABLE(mdev,
2400                                flow_table_properties_nic_receive.max_ft_level)
2401                                < 3) {
2402                 mlx5_core_warn(mdev,
2403                                "Not creating net device, some required device capabilities are missing\n");
2404                 return -ENOTSUPP;
2405         }
2406         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2407                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2408         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2409                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2410
2411         return 0;
2412 }
2413
2414 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2415 {
2416         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2417
2418         return bf_buf_size -
2419                sizeof(struct mlx5e_tx_wqe) +
2420                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2421 }
2422
2423 #ifdef CONFIG_MLX5_CORE_EN_DCB
2424 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2425 {
2426         int i;
2427
2428         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2429         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2430                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2431                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2432                 priv->params.ets.prio_tc[i] = i;
2433         }
2434
2435         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2436         priv->params.ets.prio_tc[0] = 1;
2437         priv->params.ets.prio_tc[1] = 0;
2438 }
2439 #endif
2440
2441 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2442                                    u32 *indirection_rqt, int len,
2443                                    int num_channels)
2444 {
2445         int node = mdev->priv.numa_node;
2446         int node_num_of_cores;
2447         int i;
2448
2449         if (node == -1)
2450                 node = first_online_node;
2451
2452         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2453
2454         if (node_num_of_cores)
2455                 num_channels = min_t(int, num_channels, node_num_of_cores);
2456
2457         for (i = 0; i < len; i++)
2458                 indirection_rqt[i] = i % num_channels;
2459 }
2460
2461 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2462                                     struct net_device *netdev,
2463                                     int num_channels)
2464 {
2465         struct mlx5e_priv *priv = netdev_priv(netdev);
2466
2467         priv->params.log_sq_size           =
2468                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2469         priv->params.rq_wq_type = MLX5_CAP_GEN(mdev, striding_rq) ?
2470                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2471                 MLX5_WQ_TYPE_LINKED_LIST;
2472
2473         switch (priv->params.rq_wq_type) {
2474         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2475                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2476                 priv->params.lro_en = true;
2477                 break;
2478         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2479                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2480         }
2481
2482         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2483                                             BIT(priv->params.log_rq_size));
2484         priv->params.rx_cq_moderation_usec =
2485                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2486         priv->params.rx_cq_moderation_pkts =
2487                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2488         priv->params.tx_cq_moderation_usec =
2489                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2490         priv->params.tx_cq_moderation_pkts =
2491                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2492         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2493         priv->params.num_tc                = 1;
2494         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2495
2496         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2497                             sizeof(priv->params.toeplitz_hash_key));
2498
2499         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2500                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2501
2502         priv->params.lro_wqe_sz            =
2503                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2504
2505         priv->mdev                         = mdev;
2506         priv->netdev                       = netdev;
2507         priv->params.num_channels          = num_channels;
2508
2509 #ifdef CONFIG_MLX5_CORE_EN_DCB
2510         mlx5e_ets_init(priv);
2511 #endif
2512
2513         mutex_init(&priv->state_lock);
2514
2515         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2516         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2517         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2518 }
2519
2520 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2521 {
2522         struct mlx5e_priv *priv = netdev_priv(netdev);
2523
2524         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2525         if (is_zero_ether_addr(netdev->dev_addr) &&
2526             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2527                 eth_hw_addr_random(netdev);
2528                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2529         }
2530 }
2531
2532 static void mlx5e_build_netdev(struct net_device *netdev)
2533 {
2534         struct mlx5e_priv *priv = netdev_priv(netdev);
2535         struct mlx5_core_dev *mdev = priv->mdev;
2536
2537         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2538
2539         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2540                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2541 #ifdef CONFIG_MLX5_CORE_EN_DCB
2542                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2543 #endif
2544         } else {
2545                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2546         }
2547
2548         netdev->watchdog_timeo    = 15 * HZ;
2549
2550         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2551
2552         netdev->vlan_features    |= NETIF_F_SG;
2553         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2554         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2555         netdev->vlan_features    |= NETIF_F_GRO;
2556         netdev->vlan_features    |= NETIF_F_TSO;
2557         netdev->vlan_features    |= NETIF_F_TSO6;
2558         netdev->vlan_features    |= NETIF_F_RXCSUM;
2559         netdev->vlan_features    |= NETIF_F_RXHASH;
2560
2561         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2562                 netdev->vlan_features    |= NETIF_F_LRO;
2563
2564         netdev->hw_features       = netdev->vlan_features;
2565         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2566         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2567         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2568
2569         if (mlx5e_vxlan_allowed(mdev)) {
2570                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2571                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2572                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2573                 netdev->hw_enc_features |= NETIF_F_TSO;
2574                 netdev->hw_enc_features |= NETIF_F_TSO6;
2575                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2576                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2577         }
2578
2579         netdev->features          = netdev->hw_features;
2580         if (!priv->params.lro_en)
2581                 netdev->features  &= ~NETIF_F_LRO;
2582
2583 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2584         if (FT_CAP(flow_modify_en) &&
2585             FT_CAP(modify_root) &&
2586             FT_CAP(identified_miss_table_mode) &&
2587             FT_CAP(flow_table_modify))
2588                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2589
2590         netdev->features         |= NETIF_F_HIGHDMA;
2591
2592         netdev->priv_flags       |= IFF_UNICAST_FLT;
2593
2594         mlx5e_set_netdev_dev_addr(netdev);
2595 }
2596
2597 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2598                              struct mlx5_core_mkey *mkey)
2599 {
2600         struct mlx5_core_dev *mdev = priv->mdev;
2601         struct mlx5_create_mkey_mbox_in *in;
2602         int err;
2603
2604         in = mlx5_vzalloc(sizeof(*in));
2605         if (!in)
2606                 return -ENOMEM;
2607
2608         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2609                         MLX5_PERM_LOCAL_READ  |
2610                         MLX5_ACCESS_MODE_PA;
2611         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2612         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2613
2614         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2615                                     NULL);
2616
2617         kvfree(in);
2618
2619         return err;
2620 }
2621
2622 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2623 {
2624         struct mlx5_core_dev *mdev = priv->mdev;
2625         int err;
2626
2627         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2628         if (err) {
2629                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2630                 priv->q_counter = 0;
2631         }
2632 }
2633
2634 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2635 {
2636         if (!priv->q_counter)
2637                 return;
2638
2639         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2640 }
2641
2642 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2643 {
2644         struct net_device *netdev;
2645         struct mlx5e_priv *priv;
2646         int nch = mlx5e_get_max_num_channels(mdev);
2647         int err;
2648
2649         if (mlx5e_check_required_hca_cap(mdev))
2650                 return NULL;
2651
2652         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2653                                     nch * MLX5E_MAX_NUM_TC,
2654                                     nch);
2655         if (!netdev) {
2656                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2657                 return NULL;
2658         }
2659
2660         mlx5e_build_netdev_priv(mdev, netdev, nch);
2661         mlx5e_build_netdev(netdev);
2662
2663         netif_carrier_off(netdev);
2664
2665         priv = netdev_priv(netdev);
2666
2667         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2668         if (err) {
2669                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2670                 goto err_free_netdev;
2671         }
2672
2673         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2674         if (err) {
2675                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2676                 goto err_unmap_free_uar;
2677         }
2678
2679         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2680         if (err) {
2681                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2682                 goto err_dealloc_pd;
2683         }
2684
2685         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2686         if (err) {
2687                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2688                 goto err_dealloc_transport_domain;
2689         }
2690
2691         err = mlx5e_create_tises(priv);
2692         if (err) {
2693                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2694                 goto err_destroy_mkey;
2695         }
2696
2697         err = mlx5e_open_drop_rq(priv);
2698         if (err) {
2699                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2700                 goto err_destroy_tises;
2701         }
2702
2703         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2704         if (err) {
2705                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2706                 goto err_close_drop_rq;
2707         }
2708
2709         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2710         if (err) {
2711                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2712                 goto err_destroy_rqt_indir;
2713         }
2714
2715         err = mlx5e_create_tirs(priv);
2716         if (err) {
2717                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2718                 goto err_destroy_rqt_single;
2719         }
2720
2721         err = mlx5e_create_flow_tables(priv);
2722         if (err) {
2723                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2724                 goto err_destroy_tirs;
2725         }
2726
2727         mlx5e_create_q_counter(priv);
2728
2729         mlx5e_init_eth_addr(priv);
2730
2731         mlx5e_vxlan_init(priv);
2732
2733         err = mlx5e_tc_init(priv);
2734         if (err)
2735                 goto err_dealloc_q_counters;
2736
2737 #ifdef CONFIG_MLX5_CORE_EN_DCB
2738         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2739 #endif
2740
2741         err = register_netdev(netdev);
2742         if (err) {
2743                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2744                 goto err_tc_cleanup;
2745         }
2746
2747         if (mlx5e_vxlan_allowed(mdev))
2748                 vxlan_get_rx_port(netdev);
2749
2750         mlx5e_enable_async_events(priv);
2751         schedule_work(&priv->set_rx_mode_work);
2752
2753         return priv;
2754
2755 err_tc_cleanup:
2756         mlx5e_tc_cleanup(priv);
2757
2758 err_dealloc_q_counters:
2759         mlx5e_destroy_q_counter(priv);
2760         mlx5e_destroy_flow_tables(priv);
2761
2762 err_destroy_tirs:
2763         mlx5e_destroy_tirs(priv);
2764
2765 err_destroy_rqt_single:
2766         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2767
2768 err_destroy_rqt_indir:
2769         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2770
2771 err_close_drop_rq:
2772         mlx5e_close_drop_rq(priv);
2773
2774 err_destroy_tises:
2775         mlx5e_destroy_tises(priv);
2776
2777 err_destroy_mkey:
2778         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2779
2780 err_dealloc_transport_domain:
2781         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2782
2783 err_dealloc_pd:
2784         mlx5_core_dealloc_pd(mdev, priv->pdn);
2785
2786 err_unmap_free_uar:
2787         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2788
2789 err_free_netdev:
2790         free_netdev(netdev);
2791
2792         return NULL;
2793 }
2794
2795 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2796 {
2797         struct mlx5e_priv *priv = vpriv;
2798         struct net_device *netdev = priv->netdev;
2799
2800         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2801
2802         schedule_work(&priv->set_rx_mode_work);
2803         mlx5e_disable_async_events(priv);
2804         flush_scheduled_work();
2805         unregister_netdev(netdev);
2806         mlx5e_tc_cleanup(priv);
2807         mlx5e_vxlan_cleanup(priv);
2808         mlx5e_destroy_q_counter(priv);
2809         mlx5e_destroy_flow_tables(priv);
2810         mlx5e_destroy_tirs(priv);
2811         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2812         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2813         mlx5e_close_drop_rq(priv);
2814         mlx5e_destroy_tises(priv);
2815         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2816         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2817         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2818         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2819         free_netdev(netdev);
2820 }
2821
2822 static void *mlx5e_get_netdev(void *vpriv)
2823 {
2824         struct mlx5e_priv *priv = vpriv;
2825
2826         return priv->netdev;
2827 }
2828
2829 static struct mlx5_interface mlx5e_interface = {
2830         .add       = mlx5e_create_netdev,
2831         .remove    = mlx5e_destroy_netdev,
2832         .event     = mlx5e_async_event,
2833         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2834         .get_dev   = mlx5e_get_netdev,
2835 };
2836
2837 void mlx5e_init(void)
2838 {
2839         mlx5_register_interface(&mlx5e_interface);
2840 }
2841
2842 void mlx5e_cleanup(void)
2843 {
2844         mlx5_unregister_interface(&mlx5e_interface);
2845 }