drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/fs.h>
  34 #include <net/vxlan.h>
  35 #include "en.h"
  36 #include "eswitch.h"
  37 #include "vxlan.h"
  38
  39 struct mlx5e_rq_param {
  40         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  41         struct mlx5_wq_param       wq;
  42 };
  43
  44 struct mlx5e_sq_param {
  45         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  46         struct mlx5_wq_param       wq;
  47         u16                        max_inline;
  48 };
  49
  50 struct mlx5e_cq_param {
  51         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  52         struct mlx5_wq_param       wq;
  53         u16                        eq_ix;
  54 };
  55
  56 struct mlx5e_channel_param {
  57         struct mlx5e_rq_param      rq;
  58         struct mlx5e_sq_param      sq;
  59         struct mlx5e_cq_param      rx_cq;
  60         struct mlx5e_cq_param      tx_cq;
  61 };
  62
  63 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  64 {
  65         struct mlx5_core_dev *mdev = priv->mdev;
  66         u8 port_state;
  67
  68         port_state = mlx5_query_vport_state(mdev,
  69                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  70
  71         if (port_state == VPORT_STATE_UP)
  72                 netif_carrier_on(priv->netdev);
  73         else
  74                 netif_carrier_off(priv->netdev);
  75 }
  76
  77 static void mlx5e_update_carrier_work(struct work_struct *work)
  78 {
  79         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  80                                                update_carrier_work);
  81
  82         mutex_lock(&priv->state_lock);
  83         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  84                 mlx5e_update_carrier(priv);
  85         mutex_unlock(&priv->state_lock);
  86 }
  87
  88 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  89 {
  90         struct mlx5_core_dev *mdev = priv->mdev;
  91         struct mlx5e_pport_stats *s = &priv->stats.pport;
  92         u32 *in;
  93         u32 *out;
  94         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  95
  96         in  = mlx5_vzalloc(sz);
  97         out = mlx5_vzalloc(sz);
  98         if (!in || !out)
  99                 goto free_out;
 100
 101         MLX5_SET(ppcnt_reg, in, local_port, 1);
 102
 103         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 104         mlx5_core_access_reg(mdev, in, sz, out,
 105                              sz, MLX5_REG_PPCNT, 0, 0);
 106         memcpy(s->IEEE_802_3_counters,
 107                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 108                sizeof(s->IEEE_802_3_counters));
 109
 110         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 111         mlx5_core_access_reg(mdev, in, sz, out,
 112                              sz, MLX5_REG_PPCNT, 0, 0);
 113         memcpy(s->RFC_2863_counters,
 114                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 115                sizeof(s->RFC_2863_counters));
 116
 117         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 118         mlx5_core_access_reg(mdev, in, sz, out,
 119                              sz, MLX5_REG_PPCNT, 0, 0);
 120         memcpy(s->RFC_2819_counters,
 121                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 122                sizeof(s->RFC_2819_counters));
 123
 124 free_out:
 125         kvfree(in);
 126         kvfree(out);
 127 }
 128
 129 void mlx5e_update_stats(struct mlx5e_priv *priv)
 130 {
 131         struct mlx5_core_dev *mdev = priv->mdev;
 132         struct mlx5e_vport_stats *s = &priv->stats.vport;
 133         struct mlx5e_rq_stats *rq_stats;
 134         struct mlx5e_sq_stats *sq_stats;
 135         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 136         u32 *out;
 137         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 138         u64 tx_offload_none;
 139         int i, j;
 140
 141         out = mlx5_vzalloc(outlen);
 142         if (!out)
 143                 return;
 144
 145         /* Collect firts the SW counters and then HW for consistency */
 146         s->tso_packets          = 0;
 147         s->tso_bytes            = 0;
 148         s->tso_inner_packets    = 0;
 149         s->tso_inner_bytes      = 0;
 150         s->tx_queue_stopped     = 0;
 151         s->tx_queue_wake        = 0;
 152         s->tx_queue_dropped     = 0;
 153         s->tx_csum_inner        = 0;
 154         tx_offload_none         = 0;
 155         s->lro_packets          = 0;
 156         s->lro_bytes            = 0;
 157         s->rx_csum_none         = 0;
 158         s->rx_csum_sw           = 0;
 159         s->rx_wqe_err           = 0;
 160         for (i = 0; i < priv->params.num_channels; i++) {
 161                 rq_stats = &priv->channel[i]->rq.stats;
 162
 163                 s->lro_packets  += rq_stats->lro_packets;
 164                 s->lro_bytes    += rq_stats->lro_bytes;
 165                 s->rx_csum_none += rq_stats->csum_none;
 166                 s->rx_csum_sw   += rq_stats->csum_sw;
 167                 s->rx_wqe_err   += rq_stats->wqe_err;
 168
 169                 for (j = 0; j < priv->params.num_tc; j++) {
 170                         sq_stats = &priv->channel[i]->sq[j].stats;
 171
 172                         s->tso_packets          += sq_stats->tso_packets;
 173                         s->tso_bytes            += sq_stats->tso_bytes;
 174                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 175                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 176                         s->tx_queue_stopped     += sq_stats->stopped;
 177                         s->tx_queue_wake        += sq_stats->wake;
 178                         s->tx_queue_dropped     += sq_stats->dropped;
 179                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 180                         tx_offload_none         += sq_stats->csum_offload_none;
 181                 }
 182         }
 183
 184         /* HW counters */
 185         memset(in, 0, sizeof(in));
 186
 187         MLX5_SET(query_vport_counter_in, in, opcode,
 188                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 189         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 190         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 191
 192         memset(out, 0, outlen);
 193
 194         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 195                 goto free_out;
 196
 197 #define MLX5_GET_CTR(p, x) \
 198         MLX5_GET64(query_vport_counter_out, p, x)
 199
 200         s->rx_error_packets     =
 201                 MLX5_GET_CTR(out, received_errors.packets);
 202         s->rx_error_bytes       =
 203                 MLX5_GET_CTR(out, received_errors.octets);
 204         s->tx_error_packets     =
 205                 MLX5_GET_CTR(out, transmit_errors.packets);
 206         s->tx_error_bytes       =
 207                 MLX5_GET_CTR(out, transmit_errors.octets);
 208
 209         s->rx_unicast_packets   =
 210                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 211         s->rx_unicast_bytes     =
 212                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 213         s->tx_unicast_packets   =
 214                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 215         s->tx_unicast_bytes     =
 216                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 217
 218         s->rx_multicast_packets =
 219                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 220         s->rx_multicast_bytes   =
 221                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 222         s->tx_multicast_packets =
 223                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 224         s->tx_multicast_bytes   =
 225                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 226
 227         s->rx_broadcast_packets =
 228                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 229         s->rx_broadcast_bytes   =
 230                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 231         s->tx_broadcast_packets =
 232                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 233         s->tx_broadcast_bytes   =
 234                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 235
 236         s->rx_packets =
 237                 s->rx_unicast_packets +
 238                 s->rx_multicast_packets +
 239                 s->rx_broadcast_packets;
 240         s->rx_bytes =
 241                 s->rx_unicast_bytes +
 242                 s->rx_multicast_bytes +
 243                 s->rx_broadcast_bytes;
 244         s->tx_packets =
 245                 s->tx_unicast_packets +
 246                 s->tx_multicast_packets +
 247                 s->tx_broadcast_packets;
 248         s->tx_bytes =
 249                 s->tx_unicast_bytes +
 250                 s->tx_multicast_bytes +
 251                 s->tx_broadcast_bytes;
 252
 253         /* Update calculated offload counters */
 254         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 255         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 256                                s->rx_csum_sw;
 257
 258         mlx5e_update_pport_counters(priv);
 259 free_out:
 260         kvfree(out);
 261 }
 262
 263 static void mlx5e_update_stats_work(struct work_struct *work)
 264 {
 265         struct delayed_work *dwork = to_delayed_work(work);
 266         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 267                                                update_stats_work);
 268         mutex_lock(&priv->state_lock);
 269         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 270                 mlx5e_update_stats(priv);
 271                 schedule_delayed_work(dwork,
 272                                       msecs_to_jiffies(
 273                                               MLX5E_UPDATE_STATS_INTERVAL));
 274         }
 275         mutex_unlock(&priv->state_lock);
 276 }
 277
 278 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 279                                 enum mlx5_dev_event event)
 280 {
 281         switch (event) {
 282         case MLX5_DEV_EVENT_PORT_UP:
 283         case MLX5_DEV_EVENT_PORT_DOWN:
 284                 schedule_work(&priv->update_carrier_work);
 285                 break;
 286
 287         default:
 288                 break;
 289         }
 290 }
 291
 292 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 293                               enum mlx5_dev_event event, unsigned long param)
 294 {
 295         struct mlx5e_priv *priv = vpriv;
 296
 297         spin_lock(&priv->async_events_spinlock);
 298         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 299                 __mlx5e_async_event(priv, event);
 300         spin_unlock(&priv->async_events_spinlock);
 301 }
 302
 303 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 304 {
 305         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 306 }
 307
 308 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 309 {
 310         spin_lock_irq(&priv->async_events_spinlock);
 311         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 312         spin_unlock_irq(&priv->async_events_spinlock);
 313 }
 314
 315 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 316 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 317
 318 static int mlx5e_create_rq(struct mlx5e_channel *c,
 319                            struct mlx5e_rq_param *param,
 320                            struct mlx5e_rq *rq)
 321 {
 322         struct mlx5e_priv *priv = c->priv;
 323         struct mlx5_core_dev *mdev = priv->mdev;
 324         void *rqc = param->rqc;
 325         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 326         int wq_sz;
 327         int err;
 328         int i;
 329
 330         param->wq.db_numa_node = cpu_to_node(c->cpu);
 331
 332         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 333                                 &rq->wq_ctrl);
 334         if (err)
 335                 return err;
 336
 337         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 338
 339         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 340         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 341                                cpu_to_node(c->cpu));
 342         if (!rq->skb) {
 343                 err = -ENOMEM;
 344                 goto err_rq_wq_destroy;
 345         }
 346
 347         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 348                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 349         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 350
 351         for (i = 0; i < wq_sz; i++) {
 352                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 353                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 354
 355                 wqe->data.lkey       = c->mkey_be;
 356                 wqe->data.byte_count =
 357                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 358         }
 359
 360         rq->pdev    = c->pdev;
 361         rq->netdev  = c->netdev;
 362         rq->tstamp  = &priv->tstamp;
 363         rq->channel = c;
 364         rq->ix      = c->ix;
 365         rq->priv    = c->priv;
 366
 367         return 0;
 368
 369 err_rq_wq_destroy:
 370         mlx5_wq_destroy(&rq->wq_ctrl);
 371
 372         return err;
 373 }
 374
 375 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 376 {
 377         kfree(rq->skb);
 378         mlx5_wq_destroy(&rq->wq_ctrl);
 379 }
 380
 381 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 382 {
 383         struct mlx5e_priv *priv = rq->priv;
 384         struct mlx5_core_dev *mdev = priv->mdev;
 385
 386         void *in;
 387         void *rqc;
 388         void *wq;
 389         int inlen;
 390         int err;
 391
 392         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 393                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 394         in = mlx5_vzalloc(inlen);
 395         if (!in)
 396                 return -ENOMEM;
 397
 398         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 399         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 400
 401         memcpy(rqc, param->rqc, sizeof(param->rqc));
 402
 403         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 404         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 405         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 406         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 407                                                 MLX5_ADAPTER_PAGE_SHIFT);
 408         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 409
 410         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 411                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 412
 413         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 414
 415         kvfree(in);
 416
 417         return err;
 418 }
 419
 420 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 421 {
 422         struct mlx5e_channel *c = rq->channel;
 423         struct mlx5e_priv *priv = c->priv;
 424         struct mlx5_core_dev *mdev = priv->mdev;
 425
 426         void *in;
 427         void *rqc;
 428         int inlen;
 429         int err;
 430
 431         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 432         in = mlx5_vzalloc(inlen);
 433         if (!in)
 434                 return -ENOMEM;
 435
 436         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 437
 438         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 439         MLX5_SET(rqc, rqc, state, next_state);
 440
 441         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 442
 443         kvfree(in);
 444
 445         return err;
 446 }
 447
 448 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 449 {
 450         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 451 }
 452
 453 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 454 {
 455         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 456         struct mlx5e_channel *c = rq->channel;
 457         struct mlx5e_priv *priv = c->priv;
 458         struct mlx5_wq_ll *wq = &rq->wq;
 459
 460         while (time_before(jiffies, exp_time)) {
 461                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 462                         return 0;
 463
 464                 msleep(20);
 465         }
 466
 467         return -ETIMEDOUT;
 468 }
 469
 470 static int mlx5e_open_rq(struct mlx5e_channel *c,
 471                          struct mlx5e_rq_param *param,
 472                          struct mlx5e_rq *rq)
 473 {
 474         int err;
 475
 476         err = mlx5e_create_rq(c, param, rq);
 477         if (err)
 478                 return err;
 479
 480         err = mlx5e_enable_rq(rq, param);
 481         if (err)
 482                 goto err_destroy_rq;
 483
 484         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 485         if (err)
 486                 goto err_disable_rq;
 487
 488         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 489         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 490
 491         return 0;
 492
 493 err_disable_rq:
 494         mlx5e_disable_rq(rq);
 495 err_destroy_rq:
 496         mlx5e_destroy_rq(rq);
 497
 498         return err;
 499 }
 500
 501 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 502 {
 503         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 504         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 505
 506         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 507         while (!mlx5_wq_ll_is_empty(&rq->wq))
 508                 msleep(20);
 509
 510         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 511         napi_synchronize(&rq->channel->napi);
 512
 513         mlx5e_disable_rq(rq);
 514         mlx5e_destroy_rq(rq);
 515 }
 516
 517 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 518 {
 519         kfree(sq->wqe_info);
 520         kfree(sq->dma_fifo);
 521         kfree(sq->skb);
 522 }
 523
 524 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 525 {
 526         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 527         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 528
 529         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 530         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 531                                     numa);
 532         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 533                                     numa);
 534
 535         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 536                 mlx5e_free_sq_db(sq);
 537                 return -ENOMEM;
 538         }
 539
 540         sq->dma_fifo_mask = df_sz - 1;
 541
 542         return 0;
 543 }
 544
 545 static int mlx5e_create_sq(struct mlx5e_channel *c,
 546                            int tc,
 547                            struct mlx5e_sq_param *param,
 548                            struct mlx5e_sq *sq)
 549 {
 550         struct mlx5e_priv *priv = c->priv;
 551         struct mlx5_core_dev *mdev = priv->mdev;
 552
 553         void *sqc = param->sqc;
 554         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 555         int txq_ix;
 556         int err;
 557
 558         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 559         if (err)
 560                 return err;
 561
 562         param->wq.db_numa_node = cpu_to_node(c->cpu);
 563
 564         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 565                                  &sq->wq_ctrl);
 566         if (err)
 567                 goto err_unmap_free_uar;
 568
 569         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 570         sq->uar_map     = sq->uar.map;
 571         sq->uar_bf_map  = sq->uar.bf_map;
 572         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 573         sq->max_inline  = param->max_inline;
 574
 575         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 576         if (err)
 577                 goto err_sq_wq_destroy;
 578
 579         txq_ix = c->ix + tc * priv->params.num_channels;
 580         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 581
 582         sq->pdev      = c->pdev;
 583         sq->tstamp    = &priv->tstamp;
 584         sq->mkey_be   = c->mkey_be;
 585         sq->channel   = c;
 586         sq->tc        = tc;
 587         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 588         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 589         priv->txq_to_sq_map[txq_ix] = sq;
 590
 591         return 0;
 592
 593 err_sq_wq_destroy:
 594         mlx5_wq_destroy(&sq->wq_ctrl);
 595
 596 err_unmap_free_uar:
 597         mlx5_unmap_free_uar(mdev, &sq->uar);
 598
 599         return err;
 600 }
 601
 602 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 603 {
 604         struct mlx5e_channel *c = sq->channel;
 605         struct mlx5e_priv *priv = c->priv;
 606
 607         mlx5e_free_sq_db(sq);
 608         mlx5_wq_destroy(&sq->wq_ctrl);
 609         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 610 }
 611
 612 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 613 {
 614         struct mlx5e_channel *c = sq->channel;
 615         struct mlx5e_priv *priv = c->priv;
 616         struct mlx5_core_dev *mdev = priv->mdev;
 617
 618         void *in;
 619         void *sqc;
 620         void *wq;
 621         int inlen;
 622         int err;
 623
 624         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 625                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 626         in = mlx5_vzalloc(inlen);
 627         if (!in)
 628                 return -ENOMEM;
 629
 630         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 631         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 632
 633         memcpy(sqc, param->sqc, sizeof(param->sqc));
 634
 635         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 636         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 637         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 638         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 639         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 640
 641         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 642         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 643         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 644                                           MLX5_ADAPTER_PAGE_SHIFT);
 645         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 646
 647         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 648                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 649
 650         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 651
 652         kvfree(in);
 653
 654         return err;
 655 }
 656
 657 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 658 {
 659         struct mlx5e_channel *c = sq->channel;
 660         struct mlx5e_priv *priv = c->priv;
 661         struct mlx5_core_dev *mdev = priv->mdev;
 662
 663         void *in;
 664         void *sqc;
 665         int inlen;
 666         int err;
 667
 668         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 669         in = mlx5_vzalloc(inlen);
 670         if (!in)
 671                 return -ENOMEM;
 672
 673         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 674
 675         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 676         MLX5_SET(sqc, sqc, state, next_state);
 677
 678         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 679
 680         kvfree(in);
 681
 682         return err;
 683 }
 684
 685 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 686 {
 687         struct mlx5e_channel *c = sq->channel;
 688         struct mlx5e_priv *priv = c->priv;
 689         struct mlx5_core_dev *mdev = priv->mdev;
 690
 691         mlx5_core_destroy_sq(mdev, sq->sqn);
 692 }
 693
 694 static int mlx5e_open_sq(struct mlx5e_channel *c,
 695                          int tc,
 696                          struct mlx5e_sq_param *param,
 697                          struct mlx5e_sq *sq)
 698 {
 699         int err;
 700
 701         err = mlx5e_create_sq(c, tc, param, sq);
 702         if (err)
 703                 return err;
 704
 705         err = mlx5e_enable_sq(sq, param);
 706         if (err)
 707                 goto err_destroy_sq;
 708
 709         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 710         if (err)
 711                 goto err_disable_sq;
 712
 713         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 714         netdev_tx_reset_queue(sq->txq);
 715         netif_tx_start_queue(sq->txq);
 716
 717         return 0;
 718
 719 err_disable_sq:
 720         mlx5e_disable_sq(sq);
 721 err_destroy_sq:
 722         mlx5e_destroy_sq(sq);
 723
 724         return err;
 725 }
 726
 727 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 728 {
 729         __netif_tx_lock_bh(txq);
 730         netif_tx_stop_queue(txq);
 731         __netif_tx_unlock_bh(txq);
 732 }
 733
 734 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 735 {
 736         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 737         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 738         netif_tx_disable_queue(sq->txq);
 739
 740         /* ensure hw is notified of all pending wqes */
 741         if (mlx5e_sq_has_room_for(sq, 1))
 742                 mlx5e_send_nop(sq, true);
 743
 744         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 745         while (sq->cc != sq->pc) /* wait till sq is empty */
 746                 msleep(20);
 747
 748         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 749         napi_synchronize(&sq->channel->napi);
 750
 751         mlx5e_disable_sq(sq);
 752         mlx5e_destroy_sq(sq);
 753 }
 754
 755 static int mlx5e_create_cq(struct mlx5e_channel *c,
 756                            struct mlx5e_cq_param *param,
 757                            struct mlx5e_cq *cq)
 758 {
 759         struct mlx5e_priv *priv = c->priv;
 760         struct mlx5_core_dev *mdev = priv->mdev;
 761         struct mlx5_core_cq *mcq = &cq->mcq;
 762         int eqn_not_used;
 763         unsigned int irqn;
 764         int err;
 765         u32 i;
 766
 767         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 768         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 769         param->eq_ix   = c->ix;
 770
 771         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 772                                &cq->wq_ctrl);
 773         if (err)
 774                 return err;
 775
 776         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 777
 778         cq->napi        = &c->napi;
 779
 780         mcq->cqe_sz     = 64;
 781         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 782         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 783         *mcq->set_ci_db = 0;
 784         *mcq->arm_db    = 0;
 785         mcq->vector     = param->eq_ix;
 786         mcq->comp       = mlx5e_completion_event;
 787         mcq->event      = mlx5e_cq_error_event;
 788         mcq->irqn       = irqn;
 789         mcq->uar        = &priv->cq_uar;
 790
 791         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 792                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 793
 794                 cqe->op_own = 0xf1;
 795         }
 796
 797         cq->channel = c;
 798         cq->priv = priv;
 799
 800         return 0;
 801 }
 802
 803 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 804 {
 805         mlx5_wq_destroy(&cq->wq_ctrl);
 806 }
 807
 808 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 809 {
 810         struct mlx5e_priv *priv = cq->priv;
 811         struct mlx5_core_dev *mdev = priv->mdev;
 812         struct mlx5_core_cq *mcq = &cq->mcq;
 813
 814         void *in;
 815         void *cqc;
 816         int inlen;
 817         unsigned int irqn_not_used;
 818         int eqn;
 819         int err;
 820
 821         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 822                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 823         in = mlx5_vzalloc(inlen);
 824         if (!in)
 825                 return -ENOMEM;
 826
 827         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 828
 829         memcpy(cqc, param->cqc, sizeof(param->cqc));
 830
 831         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 832                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 833
 834         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 835
 836         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 837         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 838         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 839                                             MLX5_ADAPTER_PAGE_SHIFT);
 840         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 841
 842         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 843
 844         kvfree(in);
 845
 846         if (err)
 847                 return err;
 848
 849         mlx5e_cq_arm(cq);
 850
 851         return 0;
 852 }
 853
 854 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 855 {
 856         struct mlx5e_priv *priv = cq->priv;
 857         struct mlx5_core_dev *mdev = priv->mdev;
 858
 859         mlx5_core_destroy_cq(mdev, &cq->mcq);
 860 }
 861
 862 static int mlx5e_open_cq(struct mlx5e_channel *c,
 863                          struct mlx5e_cq_param *param,
 864                          struct mlx5e_cq *cq,
 865                          u16 moderation_usecs,
 866                          u16 moderation_frames)
 867 {
 868         int err;
 869         struct mlx5e_priv *priv = c->priv;
 870         struct mlx5_core_dev *mdev = priv->mdev;
 871
 872         err = mlx5e_create_cq(c, param, cq);
 873         if (err)
 874                 return err;
 875
 876         err = mlx5e_enable_cq(cq, param);
 877         if (err)
 878                 goto err_destroy_cq;
 879
 880         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 881                                              moderation_usecs,
 882                                              moderation_frames);
 883         if (err)
 884                 goto err_destroy_cq;
 885
 886         return 0;
 887
 888 err_destroy_cq:
 889         mlx5e_destroy_cq(cq);
 890
 891         return err;
 892 }
 893
 894 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 895 {
 896         mlx5e_disable_cq(cq);
 897         mlx5e_destroy_cq(cq);
 898 }
 899
 900 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 901 {
 902         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 903 }
 904
 905 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 906                              struct mlx5e_channel_param *cparam)
 907 {
 908         struct mlx5e_priv *priv = c->priv;
 909         int err;
 910         int tc;
 911
 912         for (tc = 0; tc < c->num_tc; tc++) {
 913                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 914                                     priv->params.tx_cq_moderation_usec,
 915                                     priv->params.tx_cq_moderation_pkts);
 916                 if (err)
 917                         goto err_close_tx_cqs;
 918         }
 919
 920         return 0;
 921
 922 err_close_tx_cqs:
 923         for (tc--; tc >= 0; tc--)
 924                 mlx5e_close_cq(&c->sq[tc].cq);
 925
 926         return err;
 927 }
 928
 929 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 930 {
 931         int tc;
 932
 933         for (tc = 0; tc < c->num_tc; tc++)
 934                 mlx5e_close_cq(&c->sq[tc].cq);
 935 }
 936
 937 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 938                           struct mlx5e_channel_param *cparam)
 939 {
 940         int err;
 941         int tc;
 942
 943         for (tc = 0; tc < c->num_tc; tc++) {
 944                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 945                 if (err)
 946                         goto err_close_sqs;
 947         }
 948
 949         return 0;
 950
 951 err_close_sqs:
 952         for (tc--; tc >= 0; tc--)
 953                 mlx5e_close_sq(&c->sq[tc]);
 954
 955         return err;
 956 }
 957
 958 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 959 {
 960         int tc;
 961
 962         for (tc = 0; tc < c->num_tc; tc++)
 963                 mlx5e_close_sq(&c->sq[tc]);
 964 }
 965
 966 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 967 {
 968         int i;
 969
 970         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 971                 priv->channeltc_to_txq_map[ix][i] =
 972                         ix + i * priv->params.num_channels;
 973 }
 974
 975 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 976                               struct mlx5e_channel_param *cparam,
 977                               struct mlx5e_channel **cp)
 978 {
 979         struct net_device *netdev = priv->netdev;
 980         int cpu = mlx5e_get_cpu(priv, ix);
 981         struct mlx5e_channel *c;
 982         int err;
 983
 984         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 985         if (!c)
 986                 return -ENOMEM;
 987
 988         c->priv     = priv;
 989         c->ix       = ix;
 990         c->cpu      = cpu;
 991         c->pdev     = &priv->mdev->pdev->dev;
 992         c->netdev   = priv->netdev;
 993         c->mkey_be  = cpu_to_be32(priv->mr.key);
 994         c->num_tc   = priv->params.num_tc;
 995
 996         mlx5e_build_channeltc_to_txq_map(priv, ix);
 997
 998         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 999
1000         err = mlx5e_open_tx_cqs(c, cparam);
1001         if (err)
1002                 goto err_napi_del;
1003
1004         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1005                             priv->params.rx_cq_moderation_usec,
1006                             priv->params.rx_cq_moderation_pkts);
1007         if (err)
1008                 goto err_close_tx_cqs;
1009
1010         napi_enable(&c->napi);
1011
1012         err = mlx5e_open_sqs(c, cparam);
1013         if (err)
1014                 goto err_disable_napi;
1015
1016         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1017         if (err)
1018                 goto err_close_sqs;
1019
1020         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1021         *cp = c;
1022
1023         return 0;
1024
1025 err_close_sqs:
1026         mlx5e_close_sqs(c);
1027
1028 err_disable_napi:
1029         napi_disable(&c->napi);
1030         mlx5e_close_cq(&c->rq.cq);
1031
1032 err_close_tx_cqs:
1033         mlx5e_close_tx_cqs(c);
1034
1035 err_napi_del:
1036         netif_napi_del(&c->napi);
1037         napi_hash_del(&c->napi);
1038         kfree(c);
1039
1040         return err;
1041 }
1042
1043 static void mlx5e_close_channel(struct mlx5e_channel *c)
1044 {
1045         mlx5e_close_rq(&c->rq);
1046         mlx5e_close_sqs(c);
1047         napi_disable(&c->napi);
1048         mlx5e_close_cq(&c->rq.cq);
1049         mlx5e_close_tx_cqs(c);
1050         netif_napi_del(&c->napi);
1051
1052         napi_hash_del(&c->napi);
1053         synchronize_rcu();
1054
1055         kfree(c);
1056 }
1057
1058 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1059                                  struct mlx5e_rq_param *param)
1060 {
1061         void *rqc = param->rqc;
1062         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1063
1064         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1065         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1066         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1067         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1068         MLX5_SET(wq, wq, pd,               priv->pdn);
1069
1070         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1071         param->wq.linear = 1;
1072 }
1073
1074 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1075                                  struct mlx5e_sq_param *param)
1076 {
1077         void *sqc = param->sqc;
1078         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1079
1080         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1081         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1082         MLX5_SET(wq, wq, pd,            priv->pdn);
1083
1084         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1085         param->max_inline = priv->params.tx_max_inline;
1086 }
1087
1088 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1089                                         struct mlx5e_cq_param *param)
1090 {
1091         void *cqc = param->cqc;
1092
1093         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1094 }
1095
1096 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1097                                     struct mlx5e_cq_param *param)
1098 {
1099         void *cqc = param->cqc;
1100
1101         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1102
1103         mlx5e_build_common_cq_param(priv, param);
1104 }
1105
1106 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1107                                     struct mlx5e_cq_param *param)
1108 {
1109         void *cqc = param->cqc;
1110
1111         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1112
1113         mlx5e_build_common_cq_param(priv, param);
1114 }
1115
1116 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1117                                       struct mlx5e_channel_param *cparam)
1118 {
1119         memset(cparam, 0, sizeof(*cparam));
1120
1121         mlx5e_build_rq_param(priv, &cparam->rq);
1122         mlx5e_build_sq_param(priv, &cparam->sq);
1123         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1124         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1125 }
1126
1127 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1128 {
1129         struct mlx5e_channel_param cparam;
1130         int nch = priv->params.num_channels;
1131         int err = -ENOMEM;
1132         int i;
1133         int j;
1134
1135         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1136                                 GFP_KERNEL);
1137
1138         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1139                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1140
1141         if (!priv->channel || !priv->txq_to_sq_map)
1142                 goto err_free_txq_to_sq_map;
1143
1144         mlx5e_build_channel_param(priv, &cparam);
1145         for (i = 0; i < nch; i++) {
1146                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1147                 if (err)
1148                         goto err_close_channels;
1149         }
1150
1151         for (j = 0; j < nch; j++) {
1152                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1153                 if (err)
1154                         goto err_close_channels;
1155         }
1156
1157         return 0;
1158
1159 err_close_channels:
1160         for (i--; i >= 0; i--)
1161                 mlx5e_close_channel(priv->channel[i]);
1162
1163 err_free_txq_to_sq_map:
1164         kfree(priv->txq_to_sq_map);
1165         kfree(priv->channel);
1166
1167         return err;
1168 }
1169
1170 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1171 {
1172         int i;
1173
1174         for (i = 0; i < priv->params.num_channels; i++)
1175                 mlx5e_close_channel(priv->channel[i]);
1176
1177         kfree(priv->txq_to_sq_map);
1178         kfree(priv->channel);
1179 }
1180
1181 static int mlx5e_rx_hash_fn(int hfunc)
1182 {
1183         return (hfunc == ETH_RSS_HASH_TOP) ?
1184                MLX5_RX_HASH_FN_TOEPLITZ :
1185                MLX5_RX_HASH_FN_INVERTED_XOR8;
1186 }
1187
1188 static int mlx5e_bits_invert(unsigned long a, int size)
1189 {
1190         int inv = 0;
1191         int i;
1192
1193         for (i = 0; i < size; i++)
1194                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1195
1196         return inv;
1197 }
1198
1199 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1200 {
1201         int i;
1202
1203         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1204                 int ix = i;
1205
1206                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1207                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1208
1209                 ix = priv->params.indirection_rqt[ix];
1210                 ix = ix % priv->params.num_channels;
1211                 MLX5_SET(rqtc, rqtc, rq_num[i],
1212                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1213                          priv->channel[ix]->rq.rqn :
1214                          priv->drop_rq.rqn);
1215         }
1216 }
1217
1218 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1219                                 enum mlx5e_rqt_ix rqt_ix)
1220 {
1221
1222         switch (rqt_ix) {
1223         case MLX5E_INDIRECTION_RQT:
1224                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1225
1226                 break;
1227
1228         default: /* MLX5E_SINGLE_RQ_RQT */
1229                 MLX5_SET(rqtc, rqtc, rq_num[0],
1230                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1231                          priv->channel[0]->rq.rqn :
1232                          priv->drop_rq.rqn);
1233
1234                 break;
1235         }
1236 }
1237
1238 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1239 {
1240         struct mlx5_core_dev *mdev = priv->mdev;
1241         u32 *in;
1242         void *rqtc;
1243         int inlen;
1244         int sz;
1245         int err;
1246
1247         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1248
1249         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1250         in = mlx5_vzalloc(inlen);
1251         if (!in)
1252                 return -ENOMEM;
1253
1254         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1255
1256         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1257         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1258
1259         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1260
1261         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1262
1263         kvfree(in);
1264
1265         return err;
1266 }
1267
1268 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1269 {
1270         struct mlx5_core_dev *mdev = priv->mdev;
1271         u32 *in;
1272         void *rqtc;
1273         int inlen;
1274         int sz;
1275         int err;
1276
1277         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1278
1279         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1280         in = mlx5_vzalloc(inlen);
1281         if (!in)
1282                 return -ENOMEM;
1283
1284         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1285
1286         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1287
1288         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1289
1290         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1291
1292         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1293
1294         kvfree(in);
1295
1296         return err;
1297 }
1298
1299 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1300 {
1301         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1302 }
1303
1304 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1305 {
1306         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1307         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1308 }
1309
1310 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1311 {
1312         if (!priv->params.lro_en)
1313                 return;
1314
1315 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1316
1317         MLX5_SET(tirc, tirc, lro_enable_mask,
1318                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1319                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1320         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1321                  (priv->params.lro_wqe_sz -
1322                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1323         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1324                  MLX5_CAP_ETH(priv->mdev,
1325                               lro_timer_supported_periods[2]));
1326 }
1327
1328 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1329 {
1330         struct mlx5_core_dev *mdev = priv->mdev;
1331
1332         void *in;
1333         void *tirc;
1334         int inlen;
1335         int err;
1336
1337         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1338         in = mlx5_vzalloc(inlen);
1339         if (!in)
1340                 return -ENOMEM;
1341
1342         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1343         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1344
1345         mlx5e_build_tir_ctx_lro(tirc, priv);
1346
1347         err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1348
1349         kvfree(in);
1350
1351         return err;
1352 }
1353
1354 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1355                                                   u32 tirn)
1356 {
1357         void *in;
1358         int inlen;
1359         int err;
1360
1361         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1362         in = mlx5_vzalloc(inlen);
1363         if (!in)
1364                 return -ENOMEM;
1365
1366         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1367
1368         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1369
1370         kvfree(in);
1371
1372         return err;
1373 }
1374
1375 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1376 {
1377         int err;
1378         int i;
1379
1380         for (i = 0; i < MLX5E_NUM_TT; i++) {
1381                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1382                                                              priv->tirn[i]);
1383                 if (err)
1384                         return err;
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1391 {
1392         struct mlx5e_priv *priv = netdev_priv(netdev);
1393         struct mlx5_core_dev *mdev = priv->mdev;
1394         int hw_mtu;
1395         int err;
1396
1397         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1398         if (err)
1399                 return err;
1400
1401         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1402
1403         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1404                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1405                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1406
1407         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1408         return 0;
1409 }
1410
1411 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1412 {
1413         struct mlx5e_priv *priv = netdev_priv(netdev);
1414         int nch = priv->params.num_channels;
1415         int ntc = priv->params.num_tc;
1416         int tc;
1417
1418         netdev_reset_tc(netdev);
1419
1420         if (ntc == 1)
1421                 return;
1422
1423         netdev_set_num_tc(netdev, ntc);
1424
1425         for (tc = 0; tc < ntc; tc++)
1426                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1427 }
1428
1429 int mlx5e_open_locked(struct net_device *netdev)
1430 {
1431         struct mlx5e_priv *priv = netdev_priv(netdev);
1432         int num_txqs;
1433         int err;
1434
1435         set_bit(MLX5E_STATE_OPENED, &priv->state);
1436
1437         mlx5e_netdev_set_tcs(netdev);
1438
1439         num_txqs = priv->params.num_channels * priv->params.num_tc;
1440         netif_set_real_num_tx_queues(netdev, num_txqs);
1441         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1442
1443         err = mlx5e_set_dev_port_mtu(netdev);
1444         if (err)
1445                 goto err_clear_state_opened_flag;
1446
1447         err = mlx5e_open_channels(priv);
1448         if (err) {
1449                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1450                            __func__, err);
1451                 goto err_clear_state_opened_flag;
1452         }
1453
1454         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1455         if (err) {
1456                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1457                            __func__, err);
1458                 goto err_close_channels;
1459         }
1460
1461         mlx5e_update_carrier(priv);
1462         mlx5e_redirect_rqts(priv);
1463         mlx5e_timestamp_init(priv);
1464
1465         schedule_delayed_work(&priv->update_stats_work, 0);
1466
1467         return 0;
1468
1469 err_close_channels:
1470         mlx5e_close_channels(priv);
1471 err_clear_state_opened_flag:
1472         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1473         return err;
1474 }
1475
1476 static int mlx5e_open(struct net_device *netdev)
1477 {
1478         struct mlx5e_priv *priv = netdev_priv(netdev);
1479         int err;
1480
1481         mutex_lock(&priv->state_lock);
1482         err = mlx5e_open_locked(netdev);
1483         mutex_unlock(&priv->state_lock);
1484
1485         return err;
1486 }
1487
1488 int mlx5e_close_locked(struct net_device *netdev)
1489 {
1490         struct mlx5e_priv *priv = netdev_priv(netdev);
1491
1492         /* May already be CLOSED in case a previous configuration operation
1493          * (e.g RX/TX queue size change) that involves close&open failed.
1494          */
1495         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1496                 return 0;
1497
1498         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1499
1500         mlx5e_timestamp_cleanup(priv);
1501         mlx5e_redirect_rqts(priv);
1502         netif_carrier_off(priv->netdev);
1503         mlx5e_close_channels(priv);
1504
1505         return 0;
1506 }
1507
1508 static int mlx5e_close(struct net_device *netdev)
1509 {
1510         struct mlx5e_priv *priv = netdev_priv(netdev);
1511         int err;
1512
1513         mutex_lock(&priv->state_lock);
1514         err = mlx5e_close_locked(netdev);
1515         mutex_unlock(&priv->state_lock);
1516
1517         return err;
1518 }
1519
1520 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1521                                 struct mlx5e_rq *rq,
1522                                 struct mlx5e_rq_param *param)
1523 {
1524         struct mlx5_core_dev *mdev = priv->mdev;
1525         void *rqc = param->rqc;
1526         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1527         int err;
1528
1529         param->wq.db_numa_node = param->wq.buf_numa_node;
1530
1531         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1532                                 &rq->wq_ctrl);
1533         if (err)
1534                 return err;
1535
1536         rq->priv = priv;
1537
1538         return 0;
1539 }
1540
1541 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1542                                 struct mlx5e_cq *cq,
1543                                 struct mlx5e_cq_param *param)
1544 {
1545         struct mlx5_core_dev *mdev = priv->mdev;
1546         struct mlx5_core_cq *mcq = &cq->mcq;
1547         int eqn_not_used;
1548         unsigned int irqn;
1549         int err;
1550
1551         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1552                                &cq->wq_ctrl);
1553         if (err)
1554                 return err;
1555
1556         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1557
1558         mcq->cqe_sz     = 64;
1559         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1560         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1561         *mcq->set_ci_db = 0;
1562         *mcq->arm_db    = 0;
1563         mcq->vector     = param->eq_ix;
1564         mcq->comp       = mlx5e_completion_event;
1565         mcq->event      = mlx5e_cq_error_event;
1566         mcq->irqn       = irqn;
1567         mcq->uar        = &priv->cq_uar;
1568
1569         cq->priv = priv;
1570
1571         return 0;
1572 }
1573
1574 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1575 {
1576         struct mlx5e_cq_param cq_param;
1577         struct mlx5e_rq_param rq_param;
1578         struct mlx5e_rq *rq = &priv->drop_rq;
1579         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1580         int err;
1581
1582         memset(&cq_param, 0, sizeof(cq_param));
1583         memset(&rq_param, 0, sizeof(rq_param));
1584         mlx5e_build_rx_cq_param(priv, &cq_param);
1585         mlx5e_build_rq_param(priv, &rq_param);
1586
1587         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1588         if (err)
1589                 return err;
1590
1591         err = mlx5e_enable_cq(cq, &cq_param);
1592         if (err)
1593                 goto err_destroy_cq;
1594
1595         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1596         if (err)
1597                 goto err_disable_cq;
1598
1599         err = mlx5e_enable_rq(rq, &rq_param);
1600         if (err)
1601                 goto err_destroy_rq;
1602
1603         return 0;
1604
1605 err_destroy_rq:
1606         mlx5e_destroy_rq(&priv->drop_rq);
1607
1608 err_disable_cq:
1609         mlx5e_disable_cq(&priv->drop_rq.cq);
1610
1611 err_destroy_cq:
1612         mlx5e_destroy_cq(&priv->drop_rq.cq);
1613
1614         return err;
1615 }
1616
1617 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1618 {
1619         mlx5e_disable_rq(&priv->drop_rq);
1620         mlx5e_destroy_rq(&priv->drop_rq);
1621         mlx5e_disable_cq(&priv->drop_rq.cq);
1622         mlx5e_destroy_cq(&priv->drop_rq.cq);
1623 }
1624
1625 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1626 {
1627         struct mlx5_core_dev *mdev = priv->mdev;
1628         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1629         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1630
1631         memset(in, 0, sizeof(in));
1632
1633         MLX5_SET(tisc, tisc, prio, tc << 1);
1634         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1635
1636         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1637 }
1638
1639 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1640 {
1641         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1642 }
1643
1644 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1645 {
1646         int err;
1647         int tc;
1648
1649         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1650                 err = mlx5e_create_tis(priv, tc);
1651                 if (err)
1652                         goto err_close_tises;
1653         }
1654
1655         return 0;
1656
1657 err_close_tises:
1658         for (tc--; tc >= 0; tc--)
1659                 mlx5e_destroy_tis(priv, tc);
1660
1661         return err;
1662 }
1663
1664 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1665 {
1666         int tc;
1667
1668         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1669                 mlx5e_destroy_tis(priv, tc);
1670 }
1671
1672 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1673 {
1674         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1675
1676         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1677
1678 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1679                                  MLX5_HASH_FIELD_SEL_DST_IP)
1680
1681 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1682                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1683                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1684                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1685
1686 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1687                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1688                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1689
1690         mlx5e_build_tir_ctx_lro(tirc, priv);
1691
1692         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1693
1694         switch (tt) {
1695         case MLX5E_TT_ANY:
1696                 MLX5_SET(tirc, tirc, indirect_table,
1697                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1698                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1699                 break;
1700         default:
1701                 MLX5_SET(tirc, tirc, indirect_table,
1702                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1703                 MLX5_SET(tirc, tirc, rx_hash_fn,
1704                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1705                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1706                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1707                                                      rx_hash_toeplitz_key);
1708                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1709                                                        rx_hash_toeplitz_key);
1710
1711                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1712                         memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1713                 }
1714                 break;
1715         }
1716
1717         switch (tt) {
1718         case MLX5E_TT_IPV4_TCP:
1719                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1720                          MLX5_L3_PROT_TYPE_IPV4);
1721                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1722                          MLX5_L4_PROT_TYPE_TCP);
1723                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1724                          MLX5_HASH_IP_L4PORTS);
1725                 break;
1726
1727         case MLX5E_TT_IPV6_TCP:
1728                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1729                          MLX5_L3_PROT_TYPE_IPV6);
1730                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1731                          MLX5_L4_PROT_TYPE_TCP);
1732                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1733                          MLX5_HASH_IP_L4PORTS);
1734                 break;
1735
1736         case MLX5E_TT_IPV4_UDP:
1737                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1738                          MLX5_L3_PROT_TYPE_IPV4);
1739                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1740                          MLX5_L4_PROT_TYPE_UDP);
1741                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1742                          MLX5_HASH_IP_L4PORTS);
1743                 break;
1744
1745         case MLX5E_TT_IPV6_UDP:
1746                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1747                          MLX5_L3_PROT_TYPE_IPV6);
1748                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1749                          MLX5_L4_PROT_TYPE_UDP);
1750                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1751                          MLX5_HASH_IP_L4PORTS);
1752                 break;
1753
1754         case MLX5E_TT_IPV4_IPSEC_AH:
1755                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1756                          MLX5_L3_PROT_TYPE_IPV4);
1757                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1758                          MLX5_HASH_IP_IPSEC_SPI);
1759                 break;
1760
1761         case MLX5E_TT_IPV6_IPSEC_AH:
1762                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1763                          MLX5_L3_PROT_TYPE_IPV6);
1764                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1765                          MLX5_HASH_IP_IPSEC_SPI);
1766                 break;
1767
1768         case MLX5E_TT_IPV4_IPSEC_ESP:
1769                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1770                          MLX5_L3_PROT_TYPE_IPV4);
1771                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1772                          MLX5_HASH_IP_IPSEC_SPI);
1773                 break;
1774
1775         case MLX5E_TT_IPV6_IPSEC_ESP:
1776                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1777                          MLX5_L3_PROT_TYPE_IPV6);
1778                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1779                          MLX5_HASH_IP_IPSEC_SPI);
1780                 break;
1781
1782         case MLX5E_TT_IPV4:
1783                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1784                          MLX5_L3_PROT_TYPE_IPV4);
1785                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1786                          MLX5_HASH_IP);
1787                 break;
1788
1789         case MLX5E_TT_IPV6:
1790                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1791                          MLX5_L3_PROT_TYPE_IPV6);
1792                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1793                          MLX5_HASH_IP);
1794                 break;
1795         }
1796 }
1797
1798 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1799 {
1800         struct mlx5_core_dev *mdev = priv->mdev;
1801         u32 *in;
1802         void *tirc;
1803         int inlen;
1804         int err;
1805
1806         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1807         in = mlx5_vzalloc(inlen);
1808         if (!in)
1809                 return -ENOMEM;
1810
1811         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1812
1813         mlx5e_build_tir_ctx(priv, tirc, tt);
1814
1815         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1816
1817         kvfree(in);
1818
1819         return err;
1820 }
1821
1822 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1823 {
1824         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1825 }
1826
1827 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1828 {
1829         int err;
1830         int i;
1831
1832         for (i = 0; i < MLX5E_NUM_TT; i++) {
1833                 err = mlx5e_create_tir(priv, i);
1834                 if (err)
1835                         goto err_destroy_tirs;
1836         }
1837
1838         return 0;
1839
1840 err_destroy_tirs:
1841         for (i--; i >= 0; i--)
1842                 mlx5e_destroy_tir(priv, i);
1843
1844         return err;
1845 }
1846
1847 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1848 {
1849         int i;
1850
1851         for (i = 0; i < MLX5E_NUM_TT; i++)
1852                 mlx5e_destroy_tir(priv, i);
1853 }
1854
1855 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1856 {
1857         struct mlx5e_priv *priv = netdev_priv(netdev);
1858         bool was_opened;
1859         int err = 0;
1860
1861         if (tc && tc != MLX5E_MAX_NUM_TC)
1862                 return -EINVAL;
1863
1864         mutex_lock(&priv->state_lock);
1865
1866         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1867         if (was_opened)
1868                 mlx5e_close_locked(priv->netdev);
1869
1870         priv->params.num_tc = tc ? tc : 1;
1871
1872         if (was_opened)
1873                 err = mlx5e_open_locked(priv->netdev);
1874
1875         mutex_unlock(&priv->state_lock);
1876
1877         return err;
1878 }
1879
1880 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1881                               __be16 proto, struct tc_to_netdev *tc)
1882 {
1883         if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1884                 return -EINVAL;
1885
1886         return mlx5e_setup_tc(dev, tc->tc);
1887 }
1888
1889 static struct rtnl_link_stats64 *
1890 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1891 {
1892         struct mlx5e_priv *priv = netdev_priv(dev);
1893         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1894
1895         stats->rx_packets = vstats->rx_packets;
1896         stats->rx_bytes   = vstats->rx_bytes;
1897         stats->tx_packets = vstats->tx_packets;
1898         stats->tx_bytes   = vstats->tx_bytes;
1899         stats->multicast  = vstats->rx_multicast_packets +
1900                             vstats->tx_multicast_packets;
1901         stats->tx_errors  = vstats->tx_error_packets;
1902         stats->rx_errors  = vstats->rx_error_packets;
1903         stats->tx_dropped = vstats->tx_queue_dropped;
1904         stats->rx_crc_errors = 0;
1905         stats->rx_length_errors = 0;
1906
1907         return stats;
1908 }
1909
1910 static void mlx5e_set_rx_mode(struct net_device *dev)
1911 {
1912         struct mlx5e_priv *priv = netdev_priv(dev);
1913
1914         schedule_work(&priv->set_rx_mode_work);
1915 }
1916
1917 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1918 {
1919         struct mlx5e_priv *priv = netdev_priv(netdev);
1920         struct sockaddr *saddr = addr;
1921
1922         if (!is_valid_ether_addr(saddr->sa_data))
1923                 return -EADDRNOTAVAIL;
1924
1925         netif_addr_lock_bh(netdev);
1926         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1927         netif_addr_unlock_bh(netdev);
1928
1929         schedule_work(&priv->set_rx_mode_work);
1930
1931         return 0;
1932 }
1933
1934 static int mlx5e_set_features(struct net_device *netdev,
1935                               netdev_features_t features)
1936 {
1937         struct mlx5e_priv *priv = netdev_priv(netdev);
1938         int err = 0;
1939         netdev_features_t changes = features ^ netdev->features;
1940
1941         mutex_lock(&priv->state_lock);
1942
1943         if (changes & NETIF_F_LRO) {
1944                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1945
1946                 if (was_opened)
1947                         mlx5e_close_locked(priv->netdev);
1948
1949                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1950                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1951                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1952
1953                 if (was_opened)
1954                         err = mlx5e_open_locked(priv->netdev);
1955         }
1956
1957         mutex_unlock(&priv->state_lock);
1958
1959         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1960                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1961                         mlx5e_enable_vlan_filter(priv);
1962                 else
1963                         mlx5e_disable_vlan_filter(priv);
1964         }
1965
1966         return err;
1967 }
1968
1969 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1970 {
1971         struct mlx5e_priv *priv = netdev_priv(netdev);
1972         struct mlx5_core_dev *mdev = priv->mdev;
1973         bool was_opened;
1974         int max_mtu;
1975         int err = 0;
1976
1977         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1978
1979         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1980
1981         if (new_mtu > max_mtu) {
1982                 netdev_err(netdev,
1983                            "%s: Bad MTU (%d) > (%d) Max\n",
1984                            __func__, new_mtu, max_mtu);
1985                 return -EINVAL;
1986         }
1987
1988         mutex_lock(&priv->state_lock);
1989
1990         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1991         if (was_opened)
1992                 mlx5e_close_locked(netdev);
1993
1994         netdev->mtu = new_mtu;
1995
1996         if (was_opened)
1997                 err = mlx5e_open_locked(netdev);
1998
1999         mutex_unlock(&priv->state_lock);
2000
2001         return err;
2002 }
2003
2004 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2005 {
2006         switch (cmd) {
2007         case SIOCSHWTSTAMP:
2008                 return mlx5e_hwstamp_set(dev, ifr);
2009         case SIOCGHWTSTAMP:
2010                 return mlx5e_hwstamp_get(dev, ifr);
2011         default:
2012                 return -EOPNOTSUPP;
2013         }
2014 }
2015
2016 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2017 {
2018         struct mlx5e_priv *priv = netdev_priv(dev);
2019         struct mlx5_core_dev *mdev = priv->mdev;
2020
2021         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2022 }
2023
2024 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2025 {
2026         struct mlx5e_priv *priv = netdev_priv(dev);
2027         struct mlx5_core_dev *mdev = priv->mdev;
2028
2029         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2030                                            vlan, qos);
2031 }
2032
2033 static int mlx5_vport_link2ifla(u8 esw_link)
2034 {
2035         switch (esw_link) {
2036         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2037                 return IFLA_VF_LINK_STATE_DISABLE;
2038         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2039                 return IFLA_VF_LINK_STATE_ENABLE;
2040         }
2041         return IFLA_VF_LINK_STATE_AUTO;
2042 }
2043
2044 static int mlx5_ifla_link2vport(u8 ifla_link)
2045 {
2046         switch (ifla_link) {
2047         case IFLA_VF_LINK_STATE_DISABLE:
2048                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2049         case IFLA_VF_LINK_STATE_ENABLE:
2050                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2051         }
2052         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2053 }
2054
2055 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2056                                    int link_state)
2057 {
2058         struct mlx5e_priv *priv = netdev_priv(dev);
2059         struct mlx5_core_dev *mdev = priv->mdev;
2060
2061         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2062                                             mlx5_ifla_link2vport(link_state));
2063 }
2064
2065 static int mlx5e_get_vf_config(struct net_device *dev,
2066                                int vf, struct ifla_vf_info *ivi)
2067 {
2068         struct mlx5e_priv *priv = netdev_priv(dev);
2069         struct mlx5_core_dev *mdev = priv->mdev;
2070         int err;
2071
2072         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2073         if (err)
2074                 return err;
2075         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2076         return 0;
2077 }
2078
2079 static int mlx5e_get_vf_stats(struct net_device *dev,
2080                               int vf, struct ifla_vf_stats *vf_stats)
2081 {
2082         struct mlx5e_priv *priv = netdev_priv(dev);
2083         struct mlx5_core_dev *mdev = priv->mdev;
2084
2085         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2086                                             vf_stats);
2087 }
2088
2089 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2090                                  sa_family_t sa_family, __be16 port)
2091 {
2092         struct mlx5e_priv *priv = netdev_priv(netdev);
2093
2094         if (!mlx5e_vxlan_allowed(priv->mdev))
2095                 return;
2096
2097         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2098 }
2099
2100 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2101                                  sa_family_t sa_family, __be16 port)
2102 {
2103         struct mlx5e_priv *priv = netdev_priv(netdev);
2104
2105         if (!mlx5e_vxlan_allowed(priv->mdev))
2106                 return;
2107
2108         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2109 }
2110
2111 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2112                                                     struct sk_buff *skb,
2113                                                     netdev_features_t features)
2114 {
2115         struct udphdr *udph;
2116         u16 proto;
2117         u16 port = 0;
2118
2119         switch (vlan_get_protocol(skb)) {
2120         case htons(ETH_P_IP):
2121                 proto = ip_hdr(skb)->protocol;
2122                 break;
2123         case htons(ETH_P_IPV6):
2124                 proto = ipv6_hdr(skb)->nexthdr;
2125                 break;
2126         default:
2127                 goto out;
2128         }
2129
2130         if (proto == IPPROTO_UDP) {
2131                 udph = udp_hdr(skb);
2132                 port = be16_to_cpu(udph->dest);
2133         }
2134
2135         /* Verify if UDP port is being offloaded by HW */
2136         if (port && mlx5e_vxlan_lookup_port(priv, port))
2137                 return features;
2138
2139 out:
2140         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2141         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2142 }
2143
2144 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2145                                               struct net_device *netdev,
2146                                               netdev_features_t features)
2147 {
2148         struct mlx5e_priv *priv = netdev_priv(netdev);
2149
2150         features = vlan_features_check(skb, features);
2151         features = vxlan_features_check(skb, features);
2152
2153         /* Validate if the tunneled packet is being offloaded by HW */
2154         if (skb->encapsulation &&
2155             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2156                 return mlx5e_vxlan_features_check(priv, skb, features);
2157
2158         return features;
2159 }
2160
2161 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2162         .ndo_open                = mlx5e_open,
2163         .ndo_stop                = mlx5e_close,
2164         .ndo_start_xmit          = mlx5e_xmit,
2165         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2166         .ndo_select_queue        = mlx5e_select_queue,
2167         .ndo_get_stats64         = mlx5e_get_stats,
2168         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2169         .ndo_set_mac_address     = mlx5e_set_mac,
2170         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2171         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2172         .ndo_set_features        = mlx5e_set_features,
2173         .ndo_change_mtu          = mlx5e_change_mtu,
2174         .ndo_do_ioctl            = mlx5e_ioctl,
2175 };
2176
2177 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2178         .ndo_open                = mlx5e_open,
2179         .ndo_stop                = mlx5e_close,
2180         .ndo_start_xmit          = mlx5e_xmit,
2181         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2182         .ndo_select_queue        = mlx5e_select_queue,
2183         .ndo_get_stats64         = mlx5e_get_stats,
2184         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2185         .ndo_set_mac_address     = mlx5e_set_mac,
2186         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2187         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2188         .ndo_set_features        = mlx5e_set_features,
2189         .ndo_change_mtu          = mlx5e_change_mtu,
2190         .ndo_do_ioctl            = mlx5e_ioctl,
2191         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2192         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2193         .ndo_features_check      = mlx5e_features_check,
2194         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2195         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2196         .ndo_get_vf_config       = mlx5e_get_vf_config,
2197         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2198         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2199 };
2200
2201 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2202 {
2203         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2204                 return -ENOTSUPP;
2205         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2206             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2207             !MLX5_CAP_ETH(mdev, csum_cap) ||
2208             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2209             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2210             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2211             MLX5_CAP_FLOWTABLE(mdev,
2212                                flow_table_properties_nic_receive.max_ft_level)
2213                                < 3) {
2214                 mlx5_core_warn(mdev,
2215                                "Not creating net device, some required device capabilities are missing\n");
2216                 return -ENOTSUPP;
2217         }
2218         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2219                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2220
2221         return 0;
2222 }
2223
2224 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2225 {
2226         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2227
2228         return bf_buf_size -
2229                sizeof(struct mlx5e_tx_wqe) +
2230                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2231 }
2232
2233 #ifdef CONFIG_MLX5_CORE_EN_DCB
2234 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2235 {
2236         int i;
2237
2238         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2239         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2240                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2241                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2242                 priv->params.ets.prio_tc[i] = i;
2243         }
2244
2245         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2246         priv->params.ets.prio_tc[0] = 1;
2247         priv->params.ets.prio_tc[1] = 0;
2248 }
2249 #endif
2250
2251 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2252                                     struct net_device *netdev,
2253                                     int num_channels)
2254 {
2255         struct mlx5e_priv *priv = netdev_priv(netdev);
2256         int i;
2257
2258         priv->params.log_sq_size           =
2259                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2260         priv->params.log_rq_size           =
2261                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2262         priv->params.rx_cq_moderation_usec =
2263                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2264         priv->params.rx_cq_moderation_pkts =
2265                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2266         priv->params.tx_cq_moderation_usec =
2267                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2268         priv->params.tx_cq_moderation_pkts =
2269                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2270         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2271         priv->params.min_rx_wqes           =
2272                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2273         priv->params.num_tc                = 1;
2274         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2275
2276         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2277                             sizeof(priv->params.toeplitz_hash_key));
2278
2279         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2280                 priv->params.indirection_rqt[i] = i % num_channels;
2281
2282         priv->params.lro_wqe_sz            =
2283                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2284
2285         priv->mdev                         = mdev;
2286         priv->netdev                       = netdev;
2287         priv->params.num_channels          = num_channels;
2288
2289 #ifdef CONFIG_MLX5_CORE_EN_DCB
2290         mlx5e_ets_init(priv);
2291 #endif
2292
2293         spin_lock_init(&priv->async_events_spinlock);
2294         mutex_init(&priv->state_lock);
2295
2296         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2297         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2298         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2299 }
2300
2301 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2302 {
2303         struct mlx5e_priv *priv = netdev_priv(netdev);
2304
2305         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2306         if (is_zero_ether_addr(netdev->dev_addr) &&
2307             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2308                 eth_hw_addr_random(netdev);
2309                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2310         }
2311 }
2312
2313 static void mlx5e_build_netdev(struct net_device *netdev)
2314 {
2315         struct mlx5e_priv *priv = netdev_priv(netdev);
2316         struct mlx5_core_dev *mdev = priv->mdev;
2317
2318         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2319
2320         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2321                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2322 #ifdef CONFIG_MLX5_CORE_EN_DCB
2323                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2324 #endif
2325         } else {
2326                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2327         }
2328
2329         netdev->watchdog_timeo    = 15 * HZ;
2330
2331         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2332
2333         netdev->vlan_features    |= NETIF_F_SG;
2334         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2335         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2336         netdev->vlan_features    |= NETIF_F_GRO;
2337         netdev->vlan_features    |= NETIF_F_TSO;
2338         netdev->vlan_features    |= NETIF_F_TSO6;
2339         netdev->vlan_features    |= NETIF_F_RXCSUM;
2340         netdev->vlan_features    |= NETIF_F_RXHASH;
2341
2342         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2343                 netdev->vlan_features    |= NETIF_F_LRO;
2344
2345         netdev->hw_features       = netdev->vlan_features;
2346         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2347         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2348         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2349
2350         if (mlx5e_vxlan_allowed(mdev)) {
2351                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2352                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2353                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2354                 netdev->hw_enc_features |= NETIF_F_TSO;
2355                 netdev->hw_enc_features |= NETIF_F_TSO6;
2356                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2357                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2358         }
2359
2360         netdev->features          = netdev->hw_features;
2361         if (!priv->params.lro_en)
2362                 netdev->features  &= ~NETIF_F_LRO;
2363
2364         netdev->features         |= NETIF_F_HIGHDMA;
2365
2366         netdev->priv_flags       |= IFF_UNICAST_FLT;
2367
2368         mlx5e_set_netdev_dev_addr(netdev);
2369 }
2370
2371 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2372                              struct mlx5_core_mr *mr)
2373 {
2374         struct mlx5_core_dev *mdev = priv->mdev;
2375         struct mlx5_create_mkey_mbox_in *in;
2376         int err;
2377
2378         in = mlx5_vzalloc(sizeof(*in));
2379         if (!in)
2380                 return -ENOMEM;
2381
2382         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2383                         MLX5_PERM_LOCAL_READ  |
2384                         MLX5_ACCESS_MODE_PA;
2385         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2386         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2387
2388         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2389                                     NULL);
2390
2391         kvfree(in);
2392
2393         return err;
2394 }
2395
2396 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2397 {
2398         struct net_device *netdev;
2399         struct mlx5e_priv *priv;
2400         int nch = mlx5e_get_max_num_channels(mdev);
2401         int err;
2402
2403         if (mlx5e_check_required_hca_cap(mdev))
2404                 return NULL;
2405
2406         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2407                                     nch * MLX5E_MAX_NUM_TC,
2408                                     nch);
2409         if (!netdev) {
2410                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2411                 return NULL;
2412         }
2413
2414         mlx5e_build_netdev_priv(mdev, netdev, nch);
2415         mlx5e_build_netdev(netdev);
2416
2417         netif_carrier_off(netdev);
2418
2419         priv = netdev_priv(netdev);
2420
2421         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2422         if (err) {
2423                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2424                 goto err_free_netdev;
2425         }
2426
2427         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2428         if (err) {
2429                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2430                 goto err_unmap_free_uar;
2431         }
2432
2433         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2434         if (err) {
2435                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2436                 goto err_dealloc_pd;
2437         }
2438
2439         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2440         if (err) {
2441                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2442                 goto err_dealloc_transport_domain;
2443         }
2444
2445         err = mlx5e_create_tises(priv);
2446         if (err) {
2447                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2448                 goto err_destroy_mkey;
2449         }
2450
2451         err = mlx5e_open_drop_rq(priv);
2452         if (err) {
2453                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2454                 goto err_destroy_tises;
2455         }
2456
2457         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2458         if (err) {
2459                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2460                 goto err_close_drop_rq;
2461         }
2462
2463         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2464         if (err) {
2465                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2466                 goto err_destroy_rqt_indir;
2467         }
2468
2469         err = mlx5e_create_tirs(priv);
2470         if (err) {
2471                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2472                 goto err_destroy_rqt_single;
2473         }
2474
2475         err = mlx5e_create_flow_tables(priv);
2476         if (err) {
2477                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2478                 goto err_destroy_tirs;
2479         }
2480
2481         mlx5e_init_eth_addr(priv);
2482
2483         mlx5e_vxlan_init(priv);
2484
2485 #ifdef CONFIG_MLX5_CORE_EN_DCB
2486         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2487 #endif
2488
2489         err = register_netdev(netdev);
2490         if (err) {
2491                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2492                 goto err_destroy_flow_tables;
2493         }
2494
2495         if (mlx5e_vxlan_allowed(mdev))
2496                 vxlan_get_rx_port(netdev);
2497
2498         mlx5e_enable_async_events(priv);
2499         schedule_work(&priv->set_rx_mode_work);
2500
2501         return priv;
2502
2503 err_destroy_flow_tables:
2504         mlx5e_destroy_flow_tables(priv);
2505
2506 err_destroy_tirs:
2507         mlx5e_destroy_tirs(priv);
2508
2509 err_destroy_rqt_single:
2510         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2511
2512 err_destroy_rqt_indir:
2513         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2514
2515 err_close_drop_rq:
2516         mlx5e_close_drop_rq(priv);
2517
2518 err_destroy_tises:
2519         mlx5e_destroy_tises(priv);
2520
2521 err_destroy_mkey:
2522         mlx5_core_destroy_mkey(mdev, &priv->mr);
2523
2524 err_dealloc_transport_domain:
2525         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2526
2527 err_dealloc_pd:
2528         mlx5_core_dealloc_pd(mdev, priv->pdn);
2529
2530 err_unmap_free_uar:
2531         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2532
2533 err_free_netdev:
2534         free_netdev(netdev);
2535
2536         return NULL;
2537 }
2538
2539 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2540 {
2541         struct mlx5e_priv *priv = vpriv;
2542         struct net_device *netdev = priv->netdev;
2543
2544         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2545
2546         schedule_work(&priv->set_rx_mode_work);
2547         mlx5e_disable_async_events(priv);
2548         flush_scheduled_work();
2549         unregister_netdev(netdev);
2550         mlx5e_vxlan_cleanup(priv);
2551         mlx5e_destroy_flow_tables(priv);
2552         mlx5e_destroy_tirs(priv);
2553         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2554         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2555         mlx5e_close_drop_rq(priv);
2556         mlx5e_destroy_tises(priv);
2557         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2558         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2559         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2560         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2561         free_netdev(netdev);
2562 }
2563
2564 static void *mlx5e_get_netdev(void *vpriv)
2565 {
2566         struct mlx5e_priv *priv = vpriv;
2567
2568         return priv->netdev;
2569 }
2570
2571 static struct mlx5_interface mlx5e_interface = {
2572         .add       = mlx5e_create_netdev,
2573         .remove    = mlx5e_destroy_netdev,
2574         .event     = mlx5e_async_event,
2575         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2576         .get_dev   = mlx5e_get_netdev,
2577 };
2578
2579 void mlx5e_init(void)
2580 {
2581         mlx5_register_interface(&mlx5e_interface);
2582 }
2583
2584 void mlx5e_cleanup(void)
2585 {
2586         mlx5_unregister_interface(&mlx5e_interface);
2587 }