drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/ip.h>
  34 #include <linux/ipv6.h>
  35 #include <linux/tcp.h>
  36 #include <net/busy_poll.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39
  40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
  41 {
  42         return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
  43 }
  44
  45 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
  46 {
  47         struct sk_buff *skb;
  48         dma_addr_t dma_addr;
  49
  50         skb = netdev_alloc_skb(rq->netdev, rq->wqe_sz);
  51         if (unlikely(!skb))
  52                 return -ENOMEM;
  53
  54         dma_addr = dma_map_single(rq->pdev,
  55                                   /* hw start padding */
  56                                   skb->data,
  57                                   /* hw end padding */
  58                                   rq->wqe_sz,
  59                                   DMA_FROM_DEVICE);
  60
  61         if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
  62                 goto err_free_skb;
  63
  64         skb_reserve(skb, MLX5E_NET_IP_ALIGN);
  65
  66         *((dma_addr_t *)skb->cb) = dma_addr;
  67         wqe->data.addr = cpu_to_be64(dma_addr + MLX5E_NET_IP_ALIGN);
  68         wqe->data.lkey = rq->mkey_be;
  69
  70         rq->skb[ix] = skb;
  71
  72         return 0;
  73
  74 err_free_skb:
  75         dev_kfree_skb(skb);
  76
  77         return -ENOMEM;
  78 }
  79
  80 static inline void
  81 mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev,
  82                                 struct mlx5e_mpw_info *wi,
  83                                 u32 wqe_offset, u32 len)
  84 {
  85         dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset,
  86                                 len, DMA_FROM_DEVICE);
  87 }
  88
  89 static inline void
  90 mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev,
  91                                     struct mlx5e_mpw_info *wi,
  92                                     u32 wqe_offset, u32 len)
  93 {
  94         /* No dma pre sync for fragmented MPWQE */
  95 }
  96
  97 static inline void
  98 mlx5e_add_skb_frag_linear_mpwqe(struct device *pdev,
  99                                 struct sk_buff *skb,
 100                                 struct mlx5e_mpw_info *wi,
 101                                 u32 page_idx, u32 frag_offset,
 102                                 u32 len)
 103 {
 104         unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE);
 105
 106         wi->skbs_frags[page_idx]++;
 107         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 108                         &wi->dma_info.page[page_idx], frag_offset,
 109                         len, truesize);
 110 }
 111
 112 static inline void
 113 mlx5e_add_skb_frag_fragmented_mpwqe(struct device *pdev,
 114                                     struct sk_buff *skb,
 115                                     struct mlx5e_mpw_info *wi,
 116                                     u32 page_idx, u32 frag_offset,
 117                                     u32 len)
 118 {
 119         unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE);
 120
 121         dma_sync_single_for_cpu(pdev,
 122                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 123                                 len, DMA_FROM_DEVICE);
 124         wi->skbs_frags[page_idx]++;
 125         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 126                         wi->umr.dma_info[page_idx].page, frag_offset,
 127                         len, truesize);
 128 }
 129
 130 static inline void
 131 mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev,
 132                                    struct sk_buff *skb,
 133                                    struct mlx5e_mpw_info *wi,
 134                                    u32 page_idx, u32 offset,
 135                                    u32 headlen)
 136 {
 137         struct page *page = &wi->dma_info.page[page_idx];
 138
 139         skb_copy_to_linear_data(skb, page_address(page) + offset,
 140                                 ALIGN(headlen, sizeof(long)));
 141 }
 142
 143 static inline void
 144 mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev,
 145                                        struct sk_buff *skb,
 146                                        struct mlx5e_mpw_info *wi,
 147                                        u32 page_idx, u32 offset,
 148                                        u32 headlen)
 149 {
 150         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 151         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 152         unsigned int len;
 153
 154          /* Aligning len to sizeof(long) optimizes memcpy performance */
 155         len = ALIGN(headlen_pg, sizeof(long));
 156         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 157                                 DMA_FROM_DEVICE);
 158         skb_copy_to_linear_data_offset(skb, 0,
 159                                        page_address(dma_info->page) + offset,
 160                                        len);
 161 #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE)
 162         if (unlikely(offset + headlen > PAGE_SIZE)) {
 163                 dma_info++;
 164                 headlen_pg = len;
 165                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 166                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 167                                         DMA_FROM_DEVICE);
 168                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 169                                                page_address(dma_info->page),
 170                                                len);
 171         }
 172 #endif
 173 }
 174
 175 static u16 mlx5e_get_wqe_mtt_offset(u16 rq_ix, u16 wqe_ix)
 176 {
 177         return rq_ix * MLX5_CHANNEL_MAX_NUM_MTTS +
 178                 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 179 }
 180
 181 static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 182                                 struct mlx5e_sq *sq,
 183                                 struct mlx5e_umr_wqe *wqe,
 184                                 u16 ix)
 185 {
 186         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 187         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 188         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 189         struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
 190         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 191         u16 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix);
 192
 193         memset(wqe, 0, sizeof(*wqe));
 194         cseg->opmod_idx_opcode =
 195                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 196                             MLX5_OPCODE_UMR);
 197         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 198                                       ds_cnt);
 199         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 200         cseg->imm       = rq->umr_mkey_be;
 201
 202         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 203         ucseg->klm_octowords =
 204                 cpu_to_be16(mlx5e_get_mtt_octw(MLX5_MPWRQ_PAGES_PER_WQE));
 205         ucseg->bsf_octowords =
 206                 cpu_to_be16(mlx5e_get_mtt_octw(umr_wqe_mtt_offset));
 207         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 208
 209         dseg->lkey = sq->mkey_be;
 210         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 211 }
 212
 213 static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 214 {
 215         struct mlx5e_sq *sq = &rq->channel->icosq;
 216         struct mlx5_wq_cyc *wq = &sq->wq;
 217         struct mlx5e_umr_wqe *wqe;
 218         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 219         u16 pi;
 220
 221         /* fill sq edge with nops to avoid wqe wrap around */
 222         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 223                 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
 224                 sq->ico_wqe_info[pi].num_wqebbs = 1;
 225                 mlx5e_send_nop(sq, true);
 226         }
 227
 228         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 229         mlx5e_build_umr_wqe(rq, sq, wqe, ix);
 230         sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
 231         sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
 232         sq->pc += num_wqebbs;
 233         mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
 234 }
 235
 236 static inline int mlx5e_get_wqe_mtt_sz(void)
 237 {
 238         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 239          * To avoid copying garbage after the mtt array, we allocate
 240          * a little more.
 241          */
 242         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 243                      MLX5_UMR_MTT_ALIGNMENT);
 244 }
 245
 246 static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq,
 247                                     struct mlx5e_mpw_info *wi,
 248                                     int i)
 249 {
 250         struct page *page;
 251
 252         page = dev_alloc_page();
 253         if (unlikely(!page))
 254                 return -ENOMEM;
 255
 256         wi->umr.dma_info[i].page = page;
 257         wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
 258                                                 PCI_DMA_FROMDEVICE);
 259         if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) {
 260                 put_page(page);
 261                 return -ENOMEM;
 262         }
 263         wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR);
 264
 265         return 0;
 266 }
 267
 268 static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
 269                                            struct mlx5e_rx_wqe *wqe,
 270                                            u16 ix)
 271 {
 272         struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
 273         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 274         u32 dma_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix) << PAGE_SHIFT;
 275         int i;
 276
 277         wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) *
 278                                    MLX5_MPWRQ_PAGES_PER_WQE,
 279                                    GFP_ATOMIC);
 280         if (unlikely(!wi->umr.dma_info))
 281                 goto err_out;
 282
 283         /* We allocate more than mtt_sz as we will align the pointer */
 284         wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1,
 285                                        GFP_ATOMIC);
 286         if (unlikely(!wi->umr.mtt_no_align))
 287                 goto err_free_umr;
 288
 289         wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN);
 290         wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz,
 291                                           PCI_DMA_TODEVICE);
 292         if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr)))
 293                 goto err_free_mtt;
 294
 295         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 296                 if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i)))
 297                         goto err_unmap;
 298                 atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE,
 299                            &wi->umr.dma_info[i].page->_count);
 300                 wi->skbs_frags[i] = 0;
 301         }
 302
 303         wi->consumed_strides = 0;
 304         wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe;
 305         wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe;
 306         wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe;
 307         wi->free_wqe     = mlx5e_free_rx_fragmented_mpwqe;
 308         wqe->data.lkey = rq->umr_mkey_be;
 309         wqe->data.addr = cpu_to_be64(dma_offset);
 310
 311         return 0;
 312
 313 err_unmap:
 314         while (--i >= 0) {
 315                 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
 316                                PCI_DMA_FROMDEVICE);
 317                 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE,
 318                            &wi->umr.dma_info[i].page->_count);
 319                 put_page(wi->umr.dma_info[i].page);
 320         }
 321         dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
 322
 323 err_free_mtt:
 324         kfree(wi->umr.mtt_no_align);
 325
 326 err_free_umr:
 327         kfree(wi->umr.dma_info);
 328
 329 err_out:
 330         return -ENOMEM;
 331 }
 332
 333 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
 334                                     struct mlx5e_mpw_info *wi)
 335 {
 336         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 337         int i;
 338
 339         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 340                 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
 341                                PCI_DMA_FROMDEVICE);
 342                 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i],
 343                            &wi->umr.dma_info[i].page->_count);
 344                 put_page(wi->umr.dma_info[i].page);
 345         }
 346         dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
 347         kfree(wi->umr.mtt_no_align);
 348         kfree(wi->umr.dma_info);
 349 }
 350
 351 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq)
 352 {
 353         struct mlx5_wq_ll *wq = &rq->wq;
 354         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 355
 356         clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
 357         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 358         rq->stats.mpwqe_frag++;
 359
 360         /* ensure wqes are visible to device before updating doorbell record */
 361         dma_wmb();
 362
 363         mlx5_wq_ll_update_db_record(wq);
 364 }
 365
 366 static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq,
 367                                        struct mlx5e_rx_wqe *wqe,
 368                                        u16 ix)
 369 {
 370         struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
 371         gfp_t gfp_mask;
 372         int i;
 373
 374         gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC;
 375         wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask,
 376                                              MLX5_MPWRQ_WQE_PAGE_ORDER);
 377         if (unlikely(!wi->dma_info.page))
 378                 return -ENOMEM;
 379
 380         wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0,
 381                                          rq->wqe_sz, PCI_DMA_FROMDEVICE);
 382         if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) {
 383                 put_page(wi->dma_info.page);
 384                 return -ENOMEM;
 385         }
 386
 387         /* We split the high-order page into order-0 ones and manage their
 388          * reference counter to minimize the memory held by small skb fragments
 389          */
 390         split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER);
 391         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 392                 atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE,
 393                            &wi->dma_info.page[i]._count);
 394                 wi->skbs_frags[i] = 0;
 395         }
 396
 397         wi->consumed_strides = 0;
 398         wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe;
 399         wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe;
 400         wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe;
 401         wi->free_wqe     = mlx5e_free_rx_linear_mpwqe;
 402         wqe->data.lkey = rq->mkey_be;
 403         wqe->data.addr = cpu_to_be64(wi->dma_info.addr);
 404
 405         return 0;
 406 }
 407
 408 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
 409                                 struct mlx5e_mpw_info *wi)
 410 {
 411         int i;
 412
 413         dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz,
 414                        PCI_DMA_FROMDEVICE);
 415         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 416                 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i],
 417                            &wi->dma_info.page[i]._count);
 418                 put_page(&wi->dma_info.page[i]);
 419         }
 420 }
 421
 422 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 423 {
 424         int err;
 425
 426         err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix);
 427         if (unlikely(err)) {
 428                 err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix);
 429                 if (unlikely(err))
 430                         return err;
 431                 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
 432                 mlx5e_post_umr_wqe(rq, ix);
 433                 return -EBUSY;
 434         }
 435
 436         return 0;
 437 }
 438
 439 #define RQ_CANNOT_POST(rq) \
 440                 (!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) || \
 441                  test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 442
 443 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 444 {
 445         struct mlx5_wq_ll *wq = &rq->wq;
 446
 447         if (unlikely(RQ_CANNOT_POST(rq)))
 448                 return false;
 449
 450         while (!mlx5_wq_ll_is_full(wq)) {
 451                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 452
 453                 if (unlikely(rq->alloc_wqe(rq, wqe, wq->head)))
 454                         break;
 455
 456                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 457         }
 458
 459         /* ensure wqes are visible to device before updating doorbell record */
 460         dma_wmb();
 461
 462         mlx5_wq_ll_update_db_record(wq);
 463
 464         return !mlx5_wq_ll_is_full(wq);
 465 }
 466
 467 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 468                                  u32 cqe_bcnt)
 469 {
 470         struct ethhdr   *eth    = (struct ethhdr *)(skb->data);
 471         struct iphdr    *ipv4   = (struct iphdr *)(skb->data + ETH_HLEN);
 472         struct ipv6hdr  *ipv6   = (struct ipv6hdr *)(skb->data + ETH_HLEN);
 473         struct tcphdr   *tcp;
 474
 475         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 476         int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA  == l4_hdr_type) ||
 477                        (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
 478
 479         u16 tot_len = cqe_bcnt - ETH_HLEN;
 480
 481         if (eth->h_proto == htons(ETH_P_IP)) {
 482                 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
 483                                         sizeof(struct iphdr));
 484                 ipv6 = NULL;
 485                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 486         } else {
 487                 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
 488                                         sizeof(struct ipv6hdr));
 489                 ipv4 = NULL;
 490                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 491         }
 492
 493         if (get_cqe_lro_tcppsh(cqe))
 494                 tcp->psh                = 1;
 495
 496         if (tcp_ack) {
 497                 tcp->ack                = 1;
 498                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 499                 tcp->window             = cqe->lro_tcp_win;
 500         }
 501
 502         if (ipv4) {
 503                 ipv4->ttl               = cqe->lro_min_ttl;
 504                 ipv4->tot_len           = cpu_to_be16(tot_len);
 505                 ipv4->check             = 0;
 506                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 507                                                        ipv4->ihl);
 508         } else {
 509                 ipv6->hop_limit         = cqe->lro_min_ttl;
 510                 ipv6->payload_len       = cpu_to_be16(tot_len -
 511                                                       sizeof(struct ipv6hdr));
 512         }
 513 }
 514
 515 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 516                                       struct sk_buff *skb)
 517 {
 518         u8 cht = cqe->rss_hash_type;
 519         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 520                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 521                                             PKT_HASH_TYPE_NONE;
 522         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 523 }
 524
 525 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
 526 {
 527         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 528
 529         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 530 }
 531
 532 static inline void mlx5e_handle_csum(struct net_device *netdev,
 533                                      struct mlx5_cqe64 *cqe,
 534                                      struct mlx5e_rq *rq,
 535                                      struct sk_buff *skb,
 536                                      bool   lro)
 537 {
 538         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 539                 goto csum_none;
 540
 541         if (lro) {
 542                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 543         } else if (likely(is_first_ethertype_ip(skb))) {
 544                 skb->ip_summed = CHECKSUM_COMPLETE;
 545                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 546                 rq->stats.csum_sw++;
 547         } else {
 548                 goto csum_none;
 549         }
 550
 551         return;
 552
 553 csum_none:
 554         skb->ip_summed = CHECKSUM_NONE;
 555         rq->stats.csum_none++;
 556 }
 557
 558 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 559                                       u32 cqe_bcnt,
 560                                       struct mlx5e_rq *rq,
 561                                       struct sk_buff *skb)
 562 {
 563         struct net_device *netdev = rq->netdev;
 564         struct mlx5e_tstamp *tstamp = rq->tstamp;
 565         int lro_num_seg;
 566
 567         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 568         if (lro_num_seg > 1) {
 569                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 570                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 571                 rq->stats.lro_packets++;
 572                 rq->stats.lro_bytes += cqe_bcnt;
 573         }
 574
 575         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
 576                 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
 577
 578         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 579
 580         skb->protocol = eth_type_trans(skb, netdev);
 581
 582         skb_record_rx_queue(skb, rq->ix);
 583
 584         if (likely(netdev->features & NETIF_F_RXHASH))
 585                 mlx5e_skb_set_hash(cqe, skb);
 586
 587         if (cqe_has_vlan(cqe))
 588                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 589                                        be16_to_cpu(cqe->vlan_info));
 590
 591         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 592 }
 593
 594 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 595                                          struct mlx5_cqe64 *cqe,
 596                                          u32 cqe_bcnt,
 597                                          struct sk_buff *skb)
 598 {
 599         rq->stats.packets++;
 600         rq->stats.bytes += cqe_bcnt;
 601         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 602         napi_gro_receive(rq->cq.napi, skb);
 603 }
 604
 605 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 606 {
 607         struct mlx5e_rx_wqe *wqe;
 608         struct sk_buff *skb;
 609         __be16 wqe_counter_be;
 610         u16 wqe_counter;
 611         u32 cqe_bcnt;
 612
 613         wqe_counter_be = cqe->wqe_counter;
 614         wqe_counter    = be16_to_cpu(wqe_counter_be);
 615         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 616         skb            = rq->skb[wqe_counter];
 617         prefetch(skb->data);
 618         rq->skb[wqe_counter] = NULL;
 619
 620         dma_unmap_single(rq->pdev,
 621                          *((dma_addr_t *)skb->cb),
 622                          rq->wqe_sz,
 623                          DMA_FROM_DEVICE);
 624
 625         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 626                 rq->stats.wqe_err++;
 627                 dev_kfree_skb(skb);
 628                 goto wq_ll_pop;
 629         }
 630
 631         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
 632         skb_put(skb, cqe_bcnt);
 633
 634         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 635
 636 wq_ll_pop:
 637         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 638                        &wqe->next.next_wqe_index);
 639 }
 640
 641 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
 642                                            struct mlx5_cqe64 *cqe,
 643                                            struct mlx5e_mpw_info *wi,
 644                                            u32 cqe_bcnt,
 645                                            struct sk_buff *skb)
 646 {
 647         u32 consumed_bytes = ALIGN(cqe_bcnt, MLX5_MPWRQ_STRIDE_SIZE);
 648         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
 649         u32 wqe_offset     = stride_ix * MLX5_MPWRQ_STRIDE_SIZE;
 650         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
 651         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
 652         u32 head_page_idx  = page_idx;
 653         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
 654         u32 frag_offset    = head_offset + headlen;
 655         u16 byte_cnt       = cqe_bcnt - headlen;
 656
 657 #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE)
 658         if (unlikely(frag_offset >= PAGE_SIZE)) {
 659                 page_idx++;
 660                 frag_offset -= PAGE_SIZE;
 661         }
 662 #endif
 663         wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes);
 664
 665         while (byte_cnt) {
 666                 u32 pg_consumed_bytes =
 667                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
 668
 669                 wi->add_skb_frag(rq->pdev, skb, wi, page_idx, frag_offset,
 670                                  pg_consumed_bytes);
 671                 byte_cnt -= pg_consumed_bytes;
 672                 frag_offset = 0;
 673                 page_idx++;
 674         }
 675         /* copy header */
 676         wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset,
 677                             headlen);
 678         /* skb linear part was allocated with headlen and aligned to long */
 679         skb->tail += headlen;
 680         skb->len  += headlen;
 681 }
 682
 683 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 684 {
 685         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
 686         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
 687         struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
 688         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
 689         struct sk_buff *skb;
 690         u16 cqe_bcnt;
 691
 692         wi->consumed_strides += cstrides;
 693
 694         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 695                 rq->stats.wqe_err++;
 696                 goto mpwrq_cqe_out;
 697         }
 698
 699         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
 700                 rq->stats.mpwqe_filler++;
 701                 goto mpwrq_cqe_out;
 702         }
 703
 704         skb = netdev_alloc_skb(rq->netdev,
 705                                ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
 706                                      sizeof(long)));
 707         if (unlikely(!skb))
 708                 goto mpwrq_cqe_out;
 709
 710         prefetch(skb->data);
 711         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
 712
 713         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
 714         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 715
 716 mpwrq_cqe_out:
 717         if (likely(wi->consumed_strides < MLX5_MPWRQ_NUM_STRIDES))
 718                 return;
 719
 720         wi->free_wqe(rq, wi);
 721         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
 722 }
 723
 724 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
 725 {
 726         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
 727         int work_done;
 728
 729         for (work_done = 0; work_done < budget; work_done++) {
 730                 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
 731
 732                 if (!cqe)
 733                         break;
 734
 735                 mlx5_cqwq_pop(&cq->wq);
 736
 737                 rq->handle_rx_cqe(rq, cqe);
 738         }
 739
 740         mlx5_cqwq_update_db_record(&cq->wq);
 741
 742         /* ensure cq space is freed before enabling more cqes */
 743         wmb();
 744
 745         return work_done;
 746 }