2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/busy_poll.h>
40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
45 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
50 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz);
54 dma_addr = dma_map_single(rq->pdev,
55 /* hw start padding */
61 if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
64 *((dma_addr_t *)skb->cb) = dma_addr;
65 wqe->data.addr = cpu_to_be64(dma_addr);
66 wqe->data.lkey = rq->mkey_be;
79 mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev,
80 struct mlx5e_mpw_info *wi,
81 u32 wqe_offset, u32 len)
83 dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset,
84 len, DMA_FROM_DEVICE);
88 mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev,
89 struct mlx5e_mpw_info *wi,
90 u32 wqe_offset, u32 len)
92 /* No dma pre sync for fragmented MPWQE */
96 mlx5e_add_skb_frag_linear_mpwqe(struct device *pdev,
98 struct mlx5e_mpw_info *wi,
99 u32 page_idx, u32 frag_offset,
102 unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE);
104 wi->skbs_frags[page_idx]++;
105 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
106 &wi->dma_info.page[page_idx], frag_offset,
111 mlx5e_add_skb_frag_fragmented_mpwqe(struct device *pdev,
113 struct mlx5e_mpw_info *wi,
114 u32 page_idx, u32 frag_offset,
117 unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE);
119 dma_sync_single_for_cpu(pdev,
120 wi->umr.dma_info[page_idx].addr + frag_offset,
121 len, DMA_FROM_DEVICE);
122 wi->skbs_frags[page_idx]++;
123 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
124 wi->umr.dma_info[page_idx].page, frag_offset,
129 mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev,
131 struct mlx5e_mpw_info *wi,
132 u32 page_idx, u32 offset,
135 struct page *page = &wi->dma_info.page[page_idx];
137 skb_copy_to_linear_data(skb, page_address(page) + offset,
138 ALIGN(headlen, sizeof(long)));
142 mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev,
144 struct mlx5e_mpw_info *wi,
145 u32 page_idx, u32 offset,
148 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
149 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
152 /* Aligning len to sizeof(long) optimizes memcpy performance */
153 len = ALIGN(headlen_pg, sizeof(long));
154 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
156 skb_copy_to_linear_data_offset(skb, 0,
157 page_address(dma_info->page) + offset,
159 #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE)
160 if (unlikely(offset + headlen > PAGE_SIZE)) {
163 len = ALIGN(headlen - headlen_pg, sizeof(long));
164 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
166 skb_copy_to_linear_data_offset(skb, headlen_pg,
167 page_address(dma_info->page),
173 static u16 mlx5e_get_wqe_mtt_offset(u16 rq_ix, u16 wqe_ix)
175 return rq_ix * MLX5_CHANNEL_MAX_NUM_MTTS +
176 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
179 static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
181 struct mlx5e_umr_wqe *wqe,
184 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
185 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
186 struct mlx5_wqe_data_seg *dseg = &wqe->data;
187 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
188 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
189 u16 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix);
191 memset(wqe, 0, sizeof(*wqe));
192 cseg->opmod_idx_opcode =
193 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
195 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
197 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
198 cseg->imm = rq->umr_mkey_be;
200 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
201 ucseg->klm_octowords =
202 cpu_to_be16(mlx5e_get_mtt_octw(MLX5_MPWRQ_PAGES_PER_WQE));
203 ucseg->bsf_octowords =
204 cpu_to_be16(mlx5e_get_mtt_octw(umr_wqe_mtt_offset));
205 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
207 dseg->lkey = sq->mkey_be;
208 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
211 static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
213 struct mlx5e_sq *sq = &rq->channel->icosq;
214 struct mlx5_wq_cyc *wq = &sq->wq;
215 struct mlx5e_umr_wqe *wqe;
216 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
219 /* fill sq edge with nops to avoid wqe wrap around */
220 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
221 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
222 sq->ico_wqe_info[pi].num_wqebbs = 1;
223 mlx5e_send_nop(sq, true);
226 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
227 mlx5e_build_umr_wqe(rq, sq, wqe, ix);
228 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
229 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
230 sq->pc += num_wqebbs;
231 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
234 static inline int mlx5e_get_wqe_mtt_sz(void)
236 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
237 * To avoid copying garbage after the mtt array, we allocate
240 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
241 MLX5_UMR_MTT_ALIGNMENT);
244 static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq,
245 struct mlx5e_mpw_info *wi,
250 page = dev_alloc_page();
254 wi->umr.dma_info[i].page = page;
255 wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
257 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) {
261 wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR);
266 static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
267 struct mlx5e_rx_wqe *wqe,
270 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
271 int mtt_sz = mlx5e_get_wqe_mtt_sz();
272 u32 dma_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix) << PAGE_SHIFT;
275 wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) *
276 MLX5_MPWRQ_PAGES_PER_WQE,
278 if (unlikely(!wi->umr.dma_info))
281 /* We allocate more than mtt_sz as we will align the pointer */
282 wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1,
284 if (unlikely(!wi->umr.mtt_no_align))
287 wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN);
288 wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz,
290 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr)))
293 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
294 if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i)))
296 atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE,
297 &wi->umr.dma_info[i].page->_count);
298 wi->skbs_frags[i] = 0;
301 wi->consumed_strides = 0;
302 wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe;
303 wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe;
304 wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe;
305 wi->free_wqe = mlx5e_free_rx_fragmented_mpwqe;
306 wqe->data.lkey = rq->umr_mkey_be;
307 wqe->data.addr = cpu_to_be64(dma_offset);
313 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
315 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE,
316 &wi->umr.dma_info[i].page->_count);
317 put_page(wi->umr.dma_info[i].page);
319 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
322 kfree(wi->umr.mtt_no_align);
325 kfree(wi->umr.dma_info);
331 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
332 struct mlx5e_mpw_info *wi)
334 int mtt_sz = mlx5e_get_wqe_mtt_sz();
337 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
338 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
340 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i],
341 &wi->umr.dma_info[i].page->_count);
342 put_page(wi->umr.dma_info[i].page);
344 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
345 kfree(wi->umr.mtt_no_align);
346 kfree(wi->umr.dma_info);
349 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq)
351 struct mlx5_wq_ll *wq = &rq->wq;
352 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
354 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
355 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
356 rq->stats.mpwqe_frag++;
358 /* ensure wqes are visible to device before updating doorbell record */
361 mlx5_wq_ll_update_db_record(wq);
364 static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq,
365 struct mlx5e_rx_wqe *wqe,
368 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
372 gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC;
373 wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask,
374 MLX5_MPWRQ_WQE_PAGE_ORDER);
375 if (unlikely(!wi->dma_info.page))
378 wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0,
379 rq->wqe_sz, PCI_DMA_FROMDEVICE);
380 if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) {
381 put_page(wi->dma_info.page);
385 /* We split the high-order page into order-0 ones and manage their
386 * reference counter to minimize the memory held by small skb fragments
388 split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER);
389 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
390 atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE,
391 &wi->dma_info.page[i]._count);
392 wi->skbs_frags[i] = 0;
395 wi->consumed_strides = 0;
396 wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe;
397 wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe;
398 wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe;
399 wi->free_wqe = mlx5e_free_rx_linear_mpwqe;
400 wqe->data.lkey = rq->mkey_be;
401 wqe->data.addr = cpu_to_be64(wi->dma_info.addr);
406 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
407 struct mlx5e_mpw_info *wi)
411 dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz,
413 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
414 atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i],
415 &wi->dma_info.page[i]._count);
416 put_page(&wi->dma_info.page[i]);
420 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
424 err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix);
426 err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix);
429 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
430 mlx5e_post_umr_wqe(rq, ix);
437 #define RQ_CANNOT_POST(rq) \
438 (!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) || \
439 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
441 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
443 struct mlx5_wq_ll *wq = &rq->wq;
445 if (unlikely(RQ_CANNOT_POST(rq)))
448 while (!mlx5_wq_ll_is_full(wq)) {
449 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
452 err = rq->alloc_wqe(rq, wqe, wq->head);
455 rq->stats.buff_alloc_err++;
459 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
462 /* ensure wqes are visible to device before updating doorbell record */
465 mlx5_wq_ll_update_db_record(wq);
467 return !mlx5_wq_ll_is_full(wq);
470 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
473 struct ethhdr *eth = (struct ethhdr *)(skb->data);
474 struct iphdr *ipv4 = (struct iphdr *)(skb->data + ETH_HLEN);
475 struct ipv6hdr *ipv6 = (struct ipv6hdr *)(skb->data + ETH_HLEN);
478 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
479 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
480 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
482 u16 tot_len = cqe_bcnt - ETH_HLEN;
484 if (eth->h_proto == htons(ETH_P_IP)) {
485 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
486 sizeof(struct iphdr));
488 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
490 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
491 sizeof(struct ipv6hdr));
493 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
496 if (get_cqe_lro_tcppsh(cqe))
501 tcp->ack_seq = cqe->lro_ack_seq_num;
502 tcp->window = cqe->lro_tcp_win;
506 ipv4->ttl = cqe->lro_min_ttl;
507 ipv4->tot_len = cpu_to_be16(tot_len);
509 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
512 ipv6->hop_limit = cqe->lro_min_ttl;
513 ipv6->payload_len = cpu_to_be16(tot_len -
514 sizeof(struct ipv6hdr));
518 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
521 u8 cht = cqe->rss_hash_type;
522 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
523 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
525 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
528 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
530 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
532 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
535 static inline void mlx5e_handle_csum(struct net_device *netdev,
536 struct mlx5_cqe64 *cqe,
541 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
545 skb->ip_summed = CHECKSUM_UNNECESSARY;
549 if (is_first_ethertype_ip(skb)) {
550 skb->ip_summed = CHECKSUM_COMPLETE;
551 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
556 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
557 (cqe->hds_ip_ext & CQE_L4_OK))) {
558 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 if (cqe_is_tunneled(cqe)) {
561 skb->encapsulation = 1;
562 rq->stats.csum_inner++;
567 skb->ip_summed = CHECKSUM_NONE;
568 rq->stats.csum_none++;
571 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
576 struct net_device *netdev = rq->netdev;
577 struct mlx5e_tstamp *tstamp = rq->tstamp;
580 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
581 if (lro_num_seg > 1) {
582 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
583 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
584 rq->stats.lro_packets++;
585 rq->stats.lro_bytes += cqe_bcnt;
588 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
589 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
591 skb_record_rx_queue(skb, rq->ix);
593 if (likely(netdev->features & NETIF_F_RXHASH))
594 mlx5e_skb_set_hash(cqe, skb);
596 if (cqe_has_vlan(cqe))
597 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
598 be16_to_cpu(cqe->vlan_info));
600 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
602 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
603 skb->protocol = eth_type_trans(skb, netdev);
606 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
607 struct mlx5_cqe64 *cqe,
612 rq->stats.bytes += cqe_bcnt;
613 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
614 napi_gro_receive(rq->cq.napi, skb);
617 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
619 struct mlx5e_rx_wqe *wqe;
621 __be16 wqe_counter_be;
625 wqe_counter_be = cqe->wqe_counter;
626 wqe_counter = be16_to_cpu(wqe_counter_be);
627 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
628 skb = rq->skb[wqe_counter];
630 rq->skb[wqe_counter] = NULL;
632 dma_unmap_single(rq->pdev,
633 *((dma_addr_t *)skb->cb),
637 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
643 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
644 skb_put(skb, cqe_bcnt);
646 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
649 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
650 &wqe->next.next_wqe_index);
653 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
654 struct mlx5_cqe64 *cqe,
655 struct mlx5e_mpw_info *wi,
659 u32 consumed_bytes = ALIGN(cqe_bcnt, MLX5_MPWRQ_STRIDE_SIZE);
660 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
661 u32 wqe_offset = stride_ix * MLX5_MPWRQ_STRIDE_SIZE;
662 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
663 u32 page_idx = wqe_offset >> PAGE_SHIFT;
664 u32 head_page_idx = page_idx;
665 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
666 u32 frag_offset = head_offset + headlen;
667 u16 byte_cnt = cqe_bcnt - headlen;
669 #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE)
670 if (unlikely(frag_offset >= PAGE_SIZE)) {
672 frag_offset -= PAGE_SIZE;
675 wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes);
678 u32 pg_consumed_bytes =
679 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
681 wi->add_skb_frag(rq->pdev, skb, wi, page_idx, frag_offset,
683 byte_cnt -= pg_consumed_bytes;
688 wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset,
690 /* skb linear part was allocated with headlen and aligned to long */
691 skb->tail += headlen;
695 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
697 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
698 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
699 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
700 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
704 wi->consumed_strides += cstrides;
706 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
711 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
712 rq->stats.mpwqe_filler++;
716 skb = napi_alloc_skb(rq->cq.napi,
717 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
719 if (unlikely(!skb)) {
720 rq->stats.buff_alloc_err++;
725 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
727 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
728 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
731 if (likely(wi->consumed_strides < MLX5_MPWRQ_NUM_STRIDES))
734 wi->free_wqe(rq, wi);
735 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
738 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
740 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
743 for (work_done = 0; work_done < budget; work_done++) {
744 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
749 mlx5_cqwq_pop(&cq->wq);
751 rq->handle_rx_cqe(rq, cqe);
754 mlx5_cqwq_update_db_record(&cq->wq);
756 /* ensure cq space is freed before enabling more cqes */