2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
37 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
38 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
41 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
43 struct mlx5_wq_cyc *wq = &sq->wq;
45 u16 pi = sq->pc & wq->sz_m1;
46 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
48 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
50 memset(cseg, 0, sizeof(*cseg));
52 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
53 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | 0x01);
59 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
60 mlx5e_tx_notify_hw(sq, wqe);
64 static void mlx5e_dma_pop_last_pushed(struct mlx5e_sq *sq, dma_addr_t *addr,
68 *addr = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr;
69 *size = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size;
72 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, struct sk_buff *skb)
78 for (i = 0; i < MLX5E_TX_SKB_CB(skb)->num_dma; i++) {
79 mlx5e_dma_pop_last_pushed(sq, &addr, &size);
80 dma_unmap_single(sq->pdev, addr, size, DMA_TO_DEVICE);
84 static inline void mlx5e_dma_push(struct mlx5e_sq *sq, dma_addr_t addr,
87 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
88 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
92 static inline void mlx5e_dma_get(struct mlx5e_sq *sq, u32 i, dma_addr_t *addr,
95 *addr = sq->dma_fifo[i & sq->dma_fifo_mask].addr;
96 *size = sq->dma_fifo[i & sq->dma_fifo_mask].size;
99 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
100 void *accel_priv, select_queue_fallback_t fallback)
102 struct mlx5e_priv *priv = netdev_priv(dev);
103 int channel_ix = fallback(dev, skb);
104 int up = skb_vlan_tag_present(skb) ?
105 skb->vlan_tci >> VLAN_PRIO_SHIFT :
106 priv->default_vlan_prio;
107 int tc = netdev_get_prio_tc_map(dev, up);
109 return priv->channel[channel_ix]->tc_to_txq_map[tc];
112 static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
115 #define MLX5E_MIN_INLINE 16 /* eth header with vlan (w/o next ethertype) */
116 return MLX5E_MIN_INLINE;
119 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
121 struct mlx5_wq_cyc *wq = &sq->wq;
123 u16 pi = sq->pc & wq->sz_m1;
124 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
126 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
127 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
128 struct mlx5_wqe_data_seg *dseg;
130 u8 opcode = MLX5_OPCODE_SEND;
131 dma_addr_t dma_addr = 0;
137 memset(wqe, 0, sizeof(*wqe));
139 if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
140 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
142 sq->stats.csum_offload_none++;
144 if (skb_is_gso(skb)) {
148 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
149 opcode = MLX5_OPCODE_LSO;
150 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
151 payload_len = skb->len - ihs;
152 num_pkts = (payload_len / skb_shinfo(skb)->gso_size) +
153 !!(payload_len % skb_shinfo(skb)->gso_size);
154 MLX5E_TX_SKB_CB(skb)->num_bytes = skb->len +
155 (num_pkts - 1) * ihs;
156 sq->stats.tso_packets++;
157 sq->stats.tso_bytes += payload_len;
159 ihs = mlx5e_get_inline_hdr_size(sq, skb);
160 MLX5E_TX_SKB_CB(skb)->num_bytes = max_t(unsigned int, skb->len,
164 skb_copy_from_linear_data(skb, eseg->inline_hdr_start, ihs);
165 skb_pull_inline(skb, ihs);
167 eseg->inline_hdr_sz = cpu_to_be16(ihs);
169 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
170 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
172 dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
174 MLX5E_TX_SKB_CB(skb)->num_dma = 0;
176 headlen = skb_headlen(skb);
178 dma_addr = dma_map_single(sq->pdev, skb->data, headlen,
180 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
181 goto dma_unmap_wqe_err;
183 dseg->addr = cpu_to_be64(dma_addr);
184 dseg->lkey = sq->mkey_be;
185 dseg->byte_count = cpu_to_be32(headlen);
187 mlx5e_dma_push(sq, dma_addr, headlen);
188 MLX5E_TX_SKB_CB(skb)->num_dma++;
193 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
194 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
195 int fsz = skb_frag_size(frag);
197 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
199 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
200 goto dma_unmap_wqe_err;
202 dseg->addr = cpu_to_be64(dma_addr);
203 dseg->lkey = sq->mkey_be;
204 dseg->byte_count = cpu_to_be32(fsz);
206 mlx5e_dma_push(sq, dma_addr, fsz);
207 MLX5E_TX_SKB_CB(skb)->num_dma++;
212 ds_cnt += MLX5E_TX_SKB_CB(skb)->num_dma;
214 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
215 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
216 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
220 MLX5E_TX_SKB_CB(skb)->num_wqebbs = DIV_ROUND_UP(ds_cnt,
221 MLX5_SEND_WQEBB_NUM_DS);
222 sq->pc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
224 netdev_tx_sent_queue(sq->txq, MLX5E_TX_SKB_CB(skb)->num_bytes);
226 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
227 netif_tx_stop_queue(sq->txq);
231 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
232 mlx5e_tx_notify_hw(sq, wqe);
234 /* fill sq edge with nops to avoid wqe wrap around */
235 while ((sq->pc & wq->sz_m1) > sq->edge)
236 mlx5e_send_nop(sq, false);
243 mlx5e_dma_unmap_wqe_err(sq, skb);
245 dev_kfree_skb_any(skb);
250 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
252 struct mlx5e_priv *priv = netdev_priv(dev);
253 struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
255 return mlx5e_sq_xmit(sq, skb);
258 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
267 /* avoid accessing cq (dma coherent memory) if not needed */
268 if (!test_and_clear_bit(MLX5E_CQ_HAS_CQES, &cq->flags))
276 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
277 * otherwise a cq overrun may occur
281 /* avoid dirtying sq cache line every cqe */
282 dma_fifo_cc = sq->dma_fifo_cc;
284 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
285 struct mlx5_cqe64 *cqe;
290 cqe = mlx5e_get_cqe(cq);
294 ci = sqcc & sq->wq.sz_m1;
297 if (unlikely(!skb)) { /* nop */
303 for (j = 0; j < MLX5E_TX_SKB_CB(skb)->num_dma; j++) {
307 mlx5e_dma_get(sq, dma_fifo_cc, &addr, &size);
309 dma_unmap_single(sq->pdev, addr, size, DMA_TO_DEVICE);
313 nbytes += MLX5E_TX_SKB_CB(skb)->num_bytes;
314 sqcc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
320 mlx5_cqwq_update_db_record(&cq->wq);
322 /* ensure cq space is freed before enabling more cqes */
325 sq->dma_fifo_cc = dma_fifo_cc;
328 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
330 if (netif_tx_queue_stopped(sq->txq) &&
331 mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
332 likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
333 netif_tx_wake_queue(sq->txq);
336 if (i == MLX5E_TX_CQ_POLL_BUDGET) {
337 set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);