2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
37 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
38 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
41 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
43 struct mlx5_wq_cyc *wq = &sq->wq;
45 u16 pi = sq->pc & wq->sz_m1;
46 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
48 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
50 memset(cseg, 0, sizeof(*cseg));
52 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
53 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | 0x01);
59 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
60 mlx5e_tx_notify_hw(sq, wqe, 0);
64 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
65 struct mlx5e_sq_dma *dma)
68 case MLX5E_DMA_MAP_SINGLE:
69 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
71 case MLX5E_DMA_MAP_PAGE:
72 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
75 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
79 static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
82 enum mlx5e_dma_map_type map_type)
84 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
85 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
86 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
90 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i)
92 return &sq->dma_fifo[i & sq->dma_fifo_mask];
95 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
99 for (i = 0; i < num_dma; i++) {
100 struct mlx5e_sq_dma *last_pushed_dma =
101 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
103 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
107 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
108 void *accel_priv, select_queue_fallback_t fallback)
110 struct mlx5e_priv *priv = netdev_priv(dev);
111 int channel_ix = fallback(dev, skb);
112 int up = (netdev_get_num_tc(dev) && skb_vlan_tag_present(skb)) ?
113 skb->vlan_tci >> VLAN_PRIO_SHIFT : 0;
115 return priv->channeltc_to_txq_map[channel_ix][up];
118 static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
119 struct sk_buff *skb, bool bf)
121 /* Some NIC TX decisions, e.g loopback, are based on the packet
122 * headers and occur before the data gather.
123 * Therefore these headers must be copied into the WQE
125 #define MLX5E_MIN_INLINE ETH_HLEN
128 u16 ihs = skb_headlen(skb);
130 if (skb_vlan_tag_present(skb))
133 if (ihs <= sq->max_inline)
134 return skb_headlen(skb);
137 return MLX5E_MIN_INLINE;
140 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
141 unsigned int *skb_len,
148 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
149 unsigned char **skb_data,
150 unsigned int *skb_len)
152 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
153 int cpy1_sz = 2 * ETH_ALEN;
154 int cpy2_sz = ihs - cpy1_sz;
156 memcpy(vhdr, *skb_data, cpy1_sz);
157 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
158 vhdr->h_vlan_proto = skb->vlan_proto;
159 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
160 memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
161 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
164 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
166 struct mlx5_wq_cyc *wq = &sq->wq;
168 u16 pi = sq->pc & wq->sz_m1;
169 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
170 struct mlx5e_tx_wqe_info *wi = &sq->wqe_info[pi];
172 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
173 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
174 struct mlx5_wqe_data_seg *dseg;
176 unsigned char *skb_data = skb->data;
177 unsigned int skb_len = skb->len;
178 u8 opcode = MLX5_OPCODE_SEND;
179 dma_addr_t dma_addr = 0;
180 unsigned int num_bytes;
187 memset(wqe, 0, sizeof(*wqe));
189 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
190 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
191 if (skb->encapsulation) {
192 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
193 MLX5_ETH_WQE_L4_INNER_CSUM;
194 sq->stats.csum_offload_inner++;
196 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
199 sq->stats.csum_offload_none++;
201 if (sq->cc != sq->prev_cc) {
202 sq->prev_cc = sq->cc;
203 sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
206 if (skb_is_gso(skb)) {
207 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
208 opcode = MLX5_OPCODE_LSO;
210 if (skb->encapsulation) {
211 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
212 sq->stats.tso_inner_packets++;
213 sq->stats.tso_inner_bytes += skb->len - ihs;
215 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
216 sq->stats.tso_packets++;
217 sq->stats.tso_bytes += skb->len - ihs;
220 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
222 bf = sq->bf_budget &&
224 !skb_shinfo(skb)->nr_frags;
225 ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
226 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
229 wi->num_bytes = num_bytes;
231 if (skb_vlan_tag_present(skb)) {
232 mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
236 memcpy(eseg->inline_hdr_start, skb_data, ihs);
237 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
240 eseg->inline_hdr_sz = cpu_to_be16(ihs);
242 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
243 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
245 dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
249 headlen = skb_len - skb->data_len;
251 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
253 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
254 goto dma_unmap_wqe_err;
256 dseg->addr = cpu_to_be64(dma_addr);
257 dseg->lkey = sq->mkey_be;
258 dseg->byte_count = cpu_to_be32(headlen);
260 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
267 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
268 int fsz = skb_frag_size(frag);
270 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
272 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
273 goto dma_unmap_wqe_err;
275 dseg->addr = cpu_to_be64(dma_addr);
276 dseg->lkey = sq->mkey_be;
277 dseg->byte_count = cpu_to_be32(fsz);
279 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
285 ds_cnt += wi->num_dma;
287 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
288 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
292 wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
293 sq->pc += wi->num_wqebbs;
295 netdev_tx_sent_queue(sq->txq, wi->num_bytes);
297 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
298 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
300 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
301 netif_tx_stop_queue(sq->txq);
305 if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
308 if (bf && test_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state))
309 bf_sz = wi->num_wqebbs << 3;
311 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
312 mlx5e_tx_notify_hw(sq, wqe, bf_sz);
315 /* fill sq edge with nops to avoid wqe wrap around */
316 while ((sq->pc & wq->sz_m1) > sq->edge)
317 mlx5e_send_nop(sq, false);
319 sq->bf_budget = bf ? sq->bf_budget - 1 : 0;
322 sq->stats.bytes += num_bytes;
327 mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
329 dev_kfree_skb_any(skb);
334 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
336 struct mlx5e_priv *priv = netdev_priv(dev);
337 struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
339 return mlx5e_sq_xmit(sq, skb);
342 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
351 sq = container_of(cq, struct mlx5e_sq, cq);
356 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
357 * otherwise a cq overrun may occur
361 /* avoid dirtying sq cache line every cqe */
362 dma_fifo_cc = sq->dma_fifo_cc;
364 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
365 struct mlx5_cqe64 *cqe;
369 cqe = mlx5e_get_cqe(cq);
373 mlx5_cqwq_pop(&cq->wq);
375 wqe_counter = be16_to_cpu(cqe->wqe_counter);
378 struct mlx5e_tx_wqe_info *wi;
383 last_wqe = (sqcc == wqe_counter);
385 ci = sqcc & sq->wq.sz_m1;
387 wi = &sq->wqe_info[ci];
389 if (unlikely(!skb)) { /* nop */
395 if (unlikely(skb_shinfo(skb)->tx_flags &
397 struct skb_shared_hwtstamps hwts = {};
399 mlx5e_fill_hwstamp(sq->tstamp,
400 get_cqe_ts(cqe), &hwts);
401 skb_tstamp_tx(skb, &hwts);
404 for (j = 0; j < wi->num_dma; j++) {
405 struct mlx5e_sq_dma *dma =
406 mlx5e_dma_get(sq, dma_fifo_cc++);
408 mlx5e_tx_dma_unmap(sq->pdev, dma);
412 nbytes += wi->num_bytes;
413 sqcc += wi->num_wqebbs;
414 napi_consume_skb(skb, napi_budget);
418 mlx5_cqwq_update_db_record(&cq->wq);
420 /* ensure cq space is freed before enabling more cqes */
423 sq->dma_fifo_cc = dma_fifo_cc;
426 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
428 if (netif_tx_queue_stopped(sq->txq) &&
429 mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
430 likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
431 netif_tx_wake_queue(sq->txq);
435 return (i == MLX5E_TX_CQ_POLL_BUDGET);