2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the names of the copyright holders nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * Alternatively, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") version 2 as published by the Free
23 * Software Foundation.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
41 #include <linux/string.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
48 struct mlxsw_reg_info {
53 #define MLXSW_REG(type) (&mlxsw_reg_##type)
54 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
55 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
57 /* SGCR - Switch General Configuration Register
58 * --------------------------------------------
59 * This register is used for configuration of the switch capabilities.
61 #define MLXSW_REG_SGCR_ID 0x2000
62 #define MLXSW_REG_SGCR_LEN 0x10
64 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
65 .id = MLXSW_REG_SGCR_ID,
66 .len = MLXSW_REG_SGCR_LEN,
70 * Link Local Broadcast (Default=0)
71 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
72 * packets and ignore the IGMP snooping entries.
75 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
77 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
79 MLXSW_REG_ZERO(sgcr, payload);
80 mlxsw_reg_sgcr_llb_set(payload, !!llb);
83 /* SPAD - Switch Physical Address Register
84 * ---------------------------------------
85 * The SPAD register configures the switch physical MAC address.
87 #define MLXSW_REG_SPAD_ID 0x2002
88 #define MLXSW_REG_SPAD_LEN 0x10
90 static const struct mlxsw_reg_info mlxsw_reg_spad = {
91 .id = MLXSW_REG_SPAD_ID,
92 .len = MLXSW_REG_SPAD_LEN,
96 * Base MAC address for the switch partitions.
97 * Per switch partition MAC address is equal to:
101 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
103 /* SMID - Switch Multicast ID
104 * --------------------------
105 * The MID record maps from a MID (Multicast ID), which is a unique identifier
106 * of the multicast group within the stacking domain, into a list of local
107 * ports into which the packet is replicated.
109 #define MLXSW_REG_SMID_ID 0x2007
110 #define MLXSW_REG_SMID_LEN 0x240
112 static const struct mlxsw_reg_info mlxsw_reg_smid = {
113 .id = MLXSW_REG_SMID_ID,
114 .len = MLXSW_REG_SMID_LEN,
118 * Switch partition ID.
121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
124 * Multicast identifier - global identifier that represents the multicast group
125 * across all devices.
128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
131 * Local port memebership (1 bit per port).
134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
136 /* reg_smid_port_mask
137 * Local port mask (1 bit per port).
140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
152 /* SSPR - Switch System Port Record Register
153 * -----------------------------------------
154 * Configures the system port to local port mapping.
156 #define MLXSW_REG_SSPR_ID 0x2008
157 #define MLXSW_REG_SSPR_LEN 0x8
159 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
160 .id = MLXSW_REG_SSPR_ID,
161 .len = MLXSW_REG_SSPR_LEN,
165 * Master - if set, then the record describes the master system port.
166 * This is needed in case a local port is mapped into several system ports
167 * (for multipathing). That number will be reported as the source system
168 * port when packets are forwarded to the CPU. Only one master port is allowed
171 * Note: Must be set for Spectrum.
174 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
176 /* reg_sspr_local_port
181 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
184 * Virtual port within the physical port.
185 * Should be set to 0 when virtual ports are not enabled on the port.
189 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
191 /* reg_sspr_system_port
192 * Unique identifier within the stacking domain that represents all the ports
193 * that are available in the system (external ports).
195 * Currently, only single-ASIC configurations are supported, so we default to
196 * 1:1 mapping between system ports and local ports.
199 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
201 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
203 MLXSW_REG_ZERO(sspr, payload);
204 mlxsw_reg_sspr_m_set(payload, 1);
205 mlxsw_reg_sspr_local_port_set(payload, local_port);
206 mlxsw_reg_sspr_sub_port_set(payload, 0);
207 mlxsw_reg_sspr_system_port_set(payload, local_port);
210 /* SFDAT - Switch Filtering Database Aging Time
211 * --------------------------------------------
212 * Controls the Switch aging time. Aging time is able to be set per Switch
215 #define MLXSW_REG_SFDAT_ID 0x2009
216 #define MLXSW_REG_SFDAT_LEN 0x8
218 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
219 .id = MLXSW_REG_SFDAT_ID,
220 .len = MLXSW_REG_SFDAT_LEN,
224 * Switch partition ID.
227 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
229 /* reg_sfdat_age_time
230 * Aging time in seconds
232 * Max - 1,000,000 seconds
233 * Default is 300 seconds.
236 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
238 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
240 MLXSW_REG_ZERO(sfdat, payload);
241 mlxsw_reg_sfdat_swid_set(payload, 0);
242 mlxsw_reg_sfdat_age_time_set(payload, age_time);
245 /* SFD - Switch Filtering Database
246 * -------------------------------
247 * The following register defines the access to the filtering database.
248 * The register supports querying, adding, removing and modifying the database.
249 * The access is optimized for bulk updates in which case more than one
250 * FDB record is present in the same command.
252 #define MLXSW_REG_SFD_ID 0x200A
253 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
254 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
255 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
256 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
257 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
259 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
260 .id = MLXSW_REG_SFD_ID,
261 .len = MLXSW_REG_SFD_LEN,
265 * Switch partition ID for queries. Reserved on Write.
268 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
270 enum mlxsw_reg_sfd_op {
271 /* Dump entire FDB a (process according to record_locator) */
272 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
273 /* Query records by {MAC, VID/FID} value */
274 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
275 /* Query and clear activity. Query records by {MAC, VID/FID} value */
276 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
277 /* Test. Response indicates if each of the records could be
280 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
281 /* Add/modify. Aged-out records cannot be added. This command removes
282 * the learning notification of the {MAC, VID/FID}. Response includes
283 * the entries that were added to the FDB.
285 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
286 /* Remove record by {MAC, VID/FID}. This command also removes
287 * the learning notification and aged-out notifications
288 * of the {MAC, VID/FID}. The response provides current (pre-removal)
289 * entries as non-aged-out.
291 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
292 /* Remove learned notification by {MAC, VID/FID}. The response provides
293 * the removed learning notification.
295 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
302 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
304 /* reg_sfd_record_locator
305 * Used for querying the FDB. Use record_locator=0 to initiate the
306 * query. When a record is returned, a new record_locator is
307 * returned to be used in the subsequent query.
308 * Reserved for database update.
311 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
314 * Request: Number of records to read/add/modify/remove
315 * Response: Number of records read/added/replaced/removed
316 * See above description for more details.
320 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
322 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
325 MLXSW_REG_ZERO(sfd, payload);
326 mlxsw_reg_sfd_op_set(payload, op);
327 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
331 * Switch partition ID.
334 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
335 MLXSW_REG_SFD_REC_LEN, 0x00, false);
337 enum mlxsw_reg_sfd_rec_type {
338 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
339 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
340 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x00, false);
350 enum mlxsw_reg_sfd_rec_policy {
351 /* Replacement disabled, aging disabled. */
352 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
353 /* (mlag remote): Replacement enabled, aging disabled,
354 * learning notification enabled on this port.
356 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
357 /* (ingress device): Replacement enabled, aging enabled. */
358 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
361 /* reg_sfd_rec_policy
365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
369 * Activity. Set for new static entries. Set for static entries if a frame SMAC
370 * lookup hits on the entry.
371 * To clear the a bit, use "query and clear activity" op.
374 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
375 MLXSW_REG_SFD_REC_LEN, 0x00, false);
381 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
382 MLXSW_REG_SFD_REC_LEN, 0x02);
384 enum mlxsw_reg_sfd_rec_action {
386 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
387 /* forward and trap, trap_id is FDB_TRAP */
388 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
389 /* trap and do not forward, trap_id is FDB_TRAP */
390 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
391 /* forward to IP router */
392 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
393 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
396 /* reg_sfd_rec_action
397 * Action to apply on the packet.
398 * Note: Dynamic entries can only be configured with NOP action.
401 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
402 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
404 /* reg_sfd_uc_sub_port
405 * VEPA channel on local port.
406 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
407 * VEPA is not enabled.
410 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
411 MLXSW_REG_SFD_REC_LEN, 0x08, false);
413 /* reg_sfd_uc_fid_vid
414 * Filtering ID or VLAN ID
415 * For SwitchX and SwitchX-2:
416 * - Dynamic entries (policy 2,3) use FID
417 * - Static entries (policy 0) use VID
418 * - When independent learning is configured, VID=FID
419 * For Spectrum: use FID for both Dynamic and Static entries.
420 * VID should not be used.
423 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
424 MLXSW_REG_SFD_REC_LEN, 0x08, false);
426 /* reg_sfd_uc_system_port
427 * Unique port identifier for the final destination of the packet.
430 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
431 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
433 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
434 enum mlxsw_reg_sfd_rec_type rec_type,
436 enum mlxsw_reg_sfd_rec_action action)
438 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
440 if (rec_index >= num_rec)
441 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
442 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
443 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
444 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
445 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
448 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
449 enum mlxsw_reg_sfd_rec_policy policy,
450 const char *mac, u16 fid_vid,
451 enum mlxsw_reg_sfd_rec_action action,
454 mlxsw_reg_sfd_rec_pack(payload, rec_index,
455 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
457 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
458 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
459 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
462 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
463 char *mac, u16 *p_fid_vid,
466 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
467 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
468 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
471 /* reg_sfd_uc_lag_sub_port
473 * Must be 0 if multichannel VEPA is not enabled.
476 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
477 MLXSW_REG_SFD_REC_LEN, 0x08, false);
479 /* reg_sfd_uc_lag_fid_vid
480 * Filtering ID or VLAN ID
481 * For SwitchX and SwitchX-2:
482 * - Dynamic entries (policy 2,3) use FID
483 * - Static entries (policy 0) use VID
484 * - When independent learning is configured, VID=FID
485 * For Spectrum: use FID for both Dynamic and Static entries.
486 * VID should not be used.
489 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
490 MLXSW_REG_SFD_REC_LEN, 0x08, false);
492 /* reg_sfd_uc_lag_lag_vid
493 * Indicates VID in case of vFIDs. Reserved for FIDs.
496 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
497 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
499 /* reg_sfd_uc_lag_lag_id
500 * LAG Identifier - pointer into the LAG descriptor table.
503 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
504 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
507 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
508 enum mlxsw_reg_sfd_rec_policy policy,
509 const char *mac, u16 fid_vid,
510 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
513 mlxsw_reg_sfd_rec_pack(payload, rec_index,
514 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
516 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
517 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
518 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
519 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
520 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
523 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
524 char *mac, u16 *p_vid,
527 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
528 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
529 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
534 * Multicast port group index - index into the port group table.
535 * Value 0x1FFF indicates the pgi should point to the MID entry.
536 * For Spectrum this value must be set to 0x1FFF
539 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
540 MLXSW_REG_SFD_REC_LEN, 0x08, false);
542 /* reg_sfd_mc_fid_vid
544 * Filtering ID or VLAN ID
547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x08, false);
552 * Multicast identifier - global identifier that represents the multicast
553 * group across all devices.
556 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
557 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
560 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
561 const char *mac, u16 fid_vid,
562 enum mlxsw_reg_sfd_rec_action action, u16 mid)
564 mlxsw_reg_sfd_rec_pack(payload, rec_index,
565 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
566 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
567 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
568 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
571 /* SFN - Switch FDB Notification Register
572 * -------------------------------------------
573 * The switch provides notifications on newly learned FDB entries and
574 * aged out entries. The notifications can be polled by software.
576 #define MLXSW_REG_SFN_ID 0x200B
577 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
578 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
579 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
580 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
581 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
583 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
584 .id = MLXSW_REG_SFN_ID,
585 .len = MLXSW_REG_SFN_LEN,
589 * Switch partition ID.
592 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
595 * Forces the current session to end.
598 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
601 * Request: Number of learned notifications and aged-out notification
603 * Response: Number of notification records returned (must be smaller
604 * than or equal to the value requested)
608 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
610 static inline void mlxsw_reg_sfn_pack(char *payload)
612 MLXSW_REG_ZERO(sfn, payload);
613 mlxsw_reg_sfn_swid_set(payload, 0);
614 mlxsw_reg_sfn_end_set(payload, 1);
615 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
619 * Switch partition ID.
622 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
623 MLXSW_REG_SFN_REC_LEN, 0x00, false);
625 enum mlxsw_reg_sfn_rec_type {
626 /* MAC addresses learned on a regular port. */
627 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
628 /* MAC addresses learned on a LAG port. */
629 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
630 /* Aged-out MAC address on a regular port. */
631 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
632 /* Aged-out MAC address on a LAG port. */
633 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
637 * Notification record type.
640 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
641 MLXSW_REG_SFN_REC_LEN, 0x00, false);
647 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
648 MLXSW_REG_SFN_REC_LEN, 0x02);
650 /* reg_sfn_mac_sub_port
651 * VEPA channel on the local port.
652 * 0 if multichannel VEPA is not enabled.
655 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
656 MLXSW_REG_SFN_REC_LEN, 0x08, false);
659 * Filtering identifier.
662 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
663 MLXSW_REG_SFN_REC_LEN, 0x08, false);
665 /* reg_sfn_mac_system_port
666 * Unique port identifier for the final destination of the packet.
669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
670 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
672 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
673 char *mac, u16 *p_vid,
676 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
677 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
678 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
681 /* reg_sfn_mac_lag_lag_id
682 * LAG ID (pointer into the LAG descriptor table).
685 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
686 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
688 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
689 char *mac, u16 *p_vid,
692 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
693 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
694 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
697 /* SPMS - Switch Port MSTP/RSTP State Register
698 * -------------------------------------------
699 * Configures the spanning tree state of a physical port.
701 #define MLXSW_REG_SPMS_ID 0x200D
702 #define MLXSW_REG_SPMS_LEN 0x404
704 static const struct mlxsw_reg_info mlxsw_reg_spms = {
705 .id = MLXSW_REG_SPMS_ID,
706 .len = MLXSW_REG_SPMS_LEN,
709 /* reg_spms_local_port
713 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
715 enum mlxsw_reg_spms_state {
716 MLXSW_REG_SPMS_STATE_NO_CHANGE,
717 MLXSW_REG_SPMS_STATE_DISCARDING,
718 MLXSW_REG_SPMS_STATE_LEARNING,
719 MLXSW_REG_SPMS_STATE_FORWARDING,
723 * Spanning tree state of each VLAN ID (VID) of the local port.
724 * 0 - Do not change spanning tree state (used only when writing).
725 * 1 - Discarding. No learning or forwarding to/from this port (default).
726 * 2 - Learning. Port is learning, but not forwarding.
727 * 3 - Forwarding. Port is learning and forwarding.
730 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
732 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
734 MLXSW_REG_ZERO(spms, payload);
735 mlxsw_reg_spms_local_port_set(payload, local_port);
738 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
739 enum mlxsw_reg_spms_state state)
741 mlxsw_reg_spms_state_set(payload, vid, state);
744 /* SPVID - Switch Port VID
745 * -----------------------
746 * The switch port VID configures the default VID for a port.
748 #define MLXSW_REG_SPVID_ID 0x200E
749 #define MLXSW_REG_SPVID_LEN 0x08
751 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
752 .id = MLXSW_REG_SPVID_ID,
753 .len = MLXSW_REG_SPVID_LEN,
756 /* reg_spvid_local_port
760 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
762 /* reg_spvid_sub_port
763 * Virtual port within the physical port.
764 * Should be set to 0 when virtual ports are not enabled on the port.
767 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
773 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
775 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
777 MLXSW_REG_ZERO(spvid, payload);
778 mlxsw_reg_spvid_local_port_set(payload, local_port);
779 mlxsw_reg_spvid_pvid_set(payload, pvid);
782 /* SPVM - Switch Port VLAN Membership
783 * ----------------------------------
784 * The Switch Port VLAN Membership register configures the VLAN membership
785 * of a port in a VLAN denoted by VID. VLAN membership is managed per
786 * virtual port. The register can be used to add and remove VID(s) from a port.
788 #define MLXSW_REG_SPVM_ID 0x200F
789 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
790 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
791 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
792 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
793 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
795 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
796 .id = MLXSW_REG_SPVM_ID,
797 .len = MLXSW_REG_SPVM_LEN,
801 * Priority tagged. If this bit is set, packets forwarded to the port with
802 * untagged VLAN membership (u bit is set) will be tagged with priority tag
806 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
809 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
810 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
813 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
815 /* reg_spvm_local_port
819 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
822 * Virtual port within the physical port.
823 * Should be set to 0 when virtual ports are not enabled on the port.
826 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
829 * Number of records to update. Each record contains: i, e, u, vid.
832 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
835 * Ingress membership in VLAN ID.
838 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
839 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
840 MLXSW_REG_SPVM_REC_LEN, 0, false);
843 * Egress membership in VLAN ID.
846 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
847 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
848 MLXSW_REG_SPVM_REC_LEN, 0, false);
851 * Untagged - port is an untagged member - egress transmission uses untagged
855 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
856 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
857 MLXSW_REG_SPVM_REC_LEN, 0, false);
860 * Egress membership in VLAN ID.
863 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
864 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
865 MLXSW_REG_SPVM_REC_LEN, 0, false);
867 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
868 u16 vid_begin, u16 vid_end,
869 bool is_member, bool untagged)
871 int size = vid_end - vid_begin + 1;
874 MLXSW_REG_ZERO(spvm, payload);
875 mlxsw_reg_spvm_local_port_set(payload, local_port);
876 mlxsw_reg_spvm_num_rec_set(payload, size);
878 for (i = 0; i < size; i++) {
879 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
880 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
881 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
882 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
886 /* SPAFT - Switch Port Acceptable Frame Types
887 * ------------------------------------------
888 * The Switch Port Acceptable Frame Types register configures the frame
889 * admittance of the port.
891 #define MLXSW_REG_SPAFT_ID 0x2010
892 #define MLXSW_REG_SPAFT_LEN 0x08
894 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
895 .id = MLXSW_REG_SPAFT_ID,
896 .len = MLXSW_REG_SPAFT_LEN,
899 /* reg_spaft_local_port
903 * Note: CPU port is not supported (all tag types are allowed).
905 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
907 /* reg_spaft_sub_port
908 * Virtual port within the physical port.
909 * Should be set to 0 when virtual ports are not enabled on the port.
912 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
914 /* reg_spaft_allow_untagged
915 * When set, untagged frames on the ingress are allowed (default).
918 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
920 /* reg_spaft_allow_prio_tagged
921 * When set, priority tagged frames on the ingress are allowed (default).
924 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
926 /* reg_spaft_allow_tagged
927 * When set, tagged frames on the ingress are allowed (default).
930 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
932 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
935 MLXSW_REG_ZERO(spaft, payload);
936 mlxsw_reg_spaft_local_port_set(payload, local_port);
937 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
938 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
939 mlxsw_reg_spaft_allow_tagged_set(payload, true);
942 /* SFGC - Switch Flooding Group Configuration
943 * ------------------------------------------
944 * The following register controls the association of flooding tables and MIDs
945 * to packet types used for flooding.
947 #define MLXSW_REG_SFGC_ID 0x2011
948 #define MLXSW_REG_SFGC_LEN 0x10
950 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
951 .id = MLXSW_REG_SFGC_ID,
952 .len = MLXSW_REG_SFGC_LEN,
955 enum mlxsw_reg_sfgc_type {
956 MLXSW_REG_SFGC_TYPE_BROADCAST,
957 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
958 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
959 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
960 MLXSW_REG_SFGC_TYPE_RESERVED,
961 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
962 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
963 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
964 MLXSW_REG_SFGC_TYPE_MAX,
968 * The traffic type to reach the flooding table.
971 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
973 enum mlxsw_reg_sfgc_bridge_type {
974 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
975 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
978 /* reg_sfgc_bridge_type
981 * Note: SwitchX-2 only supports 802.1Q mode.
983 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
985 enum mlxsw_flood_table_type {
986 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
987 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
988 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
989 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
990 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
993 /* reg_sfgc_table_type
994 * See mlxsw_flood_table_type
997 * Note: FID offset and FID types are not supported in SwitchX-2.
999 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1001 /* reg_sfgc_flood_table
1002 * Flooding table index to associate with the specific type on the specific
1006 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1009 * The multicast ID for the swid. Not supported for Spectrum
1012 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1014 /* reg_sfgc_counter_set_type
1015 * Counter Set Type for flow counters.
1018 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1020 /* reg_sfgc_counter_index
1021 * Counter Index for flow counters.
1024 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1027 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1028 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1029 enum mlxsw_flood_table_type table_type,
1030 unsigned int flood_table)
1032 MLXSW_REG_ZERO(sfgc, payload);
1033 mlxsw_reg_sfgc_type_set(payload, type);
1034 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1035 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1036 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1037 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1040 /* SFTR - Switch Flooding Table Register
1041 * -------------------------------------
1042 * The switch flooding table is used for flooding packet replication. The table
1043 * defines a bit mask of ports for packet replication.
1045 #define MLXSW_REG_SFTR_ID 0x2012
1046 #define MLXSW_REG_SFTR_LEN 0x420
1048 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1049 .id = MLXSW_REG_SFTR_ID,
1050 .len = MLXSW_REG_SFTR_LEN,
1054 * Switch partition ID with which to associate the port.
1057 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1059 /* reg_sftr_flood_table
1060 * Flooding table index to associate with the specific type on the specific
1064 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1067 * Index. Used as an index into the Flooding Table in case the table is
1068 * configured to use VID / FID or FID Offset.
1071 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1073 /* reg_sftr_table_type
1074 * See mlxsw_flood_table_type
1077 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1080 * Range of entries to update
1083 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1086 * Local port membership (1 bit per port).
1089 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1091 /* reg_sftr_cpu_port_mask
1092 * CPU port mask (1 bit per port).
1095 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1097 static inline void mlxsw_reg_sftr_pack(char *payload,
1098 unsigned int flood_table,
1100 enum mlxsw_flood_table_type table_type,
1101 unsigned int range, u8 port, bool set)
1103 MLXSW_REG_ZERO(sftr, payload);
1104 mlxsw_reg_sftr_swid_set(payload, 0);
1105 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1106 mlxsw_reg_sftr_index_set(payload, index);
1107 mlxsw_reg_sftr_table_type_set(payload, table_type);
1108 mlxsw_reg_sftr_range_set(payload, range);
1109 mlxsw_reg_sftr_port_set(payload, port, set);
1110 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1113 /* SFDF - Switch Filtering DB Flush
1114 * --------------------------------
1115 * The switch filtering DB flush register is used to flush the FDB.
1116 * Note that FDB notifications are flushed as well.
1118 #define MLXSW_REG_SFDF_ID 0x2013
1119 #define MLXSW_REG_SFDF_LEN 0x14
1121 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1122 .id = MLXSW_REG_SFDF_ID,
1123 .len = MLXSW_REG_SFDF_LEN,
1127 * Switch partition ID.
1130 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1132 enum mlxsw_reg_sfdf_flush_type {
1133 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1134 MLXSW_REG_SFDF_FLUSH_PER_FID,
1135 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1136 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1137 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1138 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1141 /* reg_sfdf_flush_type
1143 * 0 - All SWID dynamic entries are flushed.
1144 * 1 - All FID dynamic entries are flushed.
1145 * 2 - All dynamic entries pointing to port are flushed.
1146 * 3 - All FID dynamic entries pointing to port are flushed.
1147 * 4 - All dynamic entries pointing to LAG are flushed.
1148 * 5 - All FID dynamic entries pointing to LAG are flushed.
1151 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1153 /* reg_sfdf_flush_static
1155 * 0 - Flush only dynamic entries.
1156 * 1 - Flush both dynamic and static entries.
1159 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1161 static inline void mlxsw_reg_sfdf_pack(char *payload,
1162 enum mlxsw_reg_sfdf_flush_type type)
1164 MLXSW_REG_ZERO(sfdf, payload);
1165 mlxsw_reg_sfdf_flush_type_set(payload, type);
1166 mlxsw_reg_sfdf_flush_static_set(payload, true);
1173 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1175 /* reg_sfdf_system_port
1179 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1181 /* reg_sfdf_port_fid_system_port
1182 * Port to flush, pointed to by FID.
1185 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1191 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1193 /* reg_sfdf_lag_fid_lag_id
1194 * LAG ID to flush, pointed to by FID.
1197 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1199 /* SLDR - Switch LAG Descriptor Register
1200 * -----------------------------------------
1201 * The switch LAG descriptor register is populated by LAG descriptors.
1202 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1205 #define MLXSW_REG_SLDR_ID 0x2014
1206 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1208 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1209 .id = MLXSW_REG_SLDR_ID,
1210 .len = MLXSW_REG_SLDR_LEN,
1213 enum mlxsw_reg_sldr_op {
1214 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1215 MLXSW_REG_SLDR_OP_LAG_CREATE,
1216 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1217 /* Ports that appear in the list have the Distributor enabled */
1218 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1219 /* Removes ports from the disributor list */
1220 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1227 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1230 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1233 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1235 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1237 MLXSW_REG_ZERO(sldr, payload);
1238 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1239 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1242 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1244 MLXSW_REG_ZERO(sldr, payload);
1245 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1246 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1249 /* reg_sldr_num_ports
1250 * The number of member ports of the LAG.
1251 * Reserved for Create / Destroy operations
1252 * For Add / Remove operations - indicates the number of ports in the list.
1255 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1257 /* reg_sldr_system_port
1261 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1263 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1266 MLXSW_REG_ZERO(sldr, payload);
1267 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1268 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1269 mlxsw_reg_sldr_num_ports_set(payload, 1);
1270 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1273 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1276 MLXSW_REG_ZERO(sldr, payload);
1277 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1278 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1279 mlxsw_reg_sldr_num_ports_set(payload, 1);
1280 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1283 /* SLCR - Switch LAG Configuration 2 Register
1284 * -------------------------------------------
1285 * The Switch LAG Configuration register is used for configuring the
1286 * LAG properties of the switch.
1288 #define MLXSW_REG_SLCR_ID 0x2015
1289 #define MLXSW_REG_SLCR_LEN 0x10
1291 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1292 .id = MLXSW_REG_SLCR_ID,
1293 .len = MLXSW_REG_SLCR_LEN,
1296 enum mlxsw_reg_slcr_pp {
1297 /* Global Configuration (for all ports) */
1298 MLXSW_REG_SLCR_PP_GLOBAL,
1299 /* Per port configuration, based on local_port field */
1300 MLXSW_REG_SLCR_PP_PER_PORT,
1304 * Per Port Configuration
1305 * Note: Reading at Global mode results in reading port 1 configuration.
1308 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1310 /* reg_slcr_local_port
1312 * Supported from CPU port
1313 * Not supported from router port
1314 * Reserved when pp = Global Configuration
1317 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1319 enum mlxsw_reg_slcr_type {
1320 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1321 MLXSW_REG_SLCR_TYPE_XOR,
1322 MLXSW_REG_SLCR_TYPE_RANDOM,
1329 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1332 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1333 /* SMAC - for IPv4 and IPv6 packets */
1334 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1335 /* SMAC - for non-IP packets */
1336 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1337 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1338 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1339 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1340 /* DMAC - for IPv4 and IPv6 packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1342 /* DMAC - for non-IP packets */
1343 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1344 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1345 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1347 /* Ethertype - for IPv4 and IPv6 packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1349 /* Ethertype - for non-IP packets */
1350 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1351 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1352 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1354 /* VLAN ID - for IPv4 and IPv6 packets */
1355 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1356 /* VLAN ID - for non-IP packets */
1357 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1358 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1359 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1360 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1361 /* Source IP address (can be IPv4 or IPv6) */
1362 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1363 /* Destination IP address (can be IPv4 or IPv6) */
1364 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1365 /* TCP/UDP source port */
1366 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1367 /* TCP/UDP destination port*/
1368 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1369 /* IPv4 Protocol/IPv6 Next Header */
1370 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1371 /* IPv6 Flow label */
1372 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1373 /* SID - FCoE source ID */
1374 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1375 /* DID - FCoE destination ID */
1376 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1377 /* OXID - FCoE originator exchange ID */
1378 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1379 /* Destination QP number - for RoCE packets */
1380 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1382 /* reg_slcr_lag_hash
1383 * LAG hashing configuration. This is a bitmask, in which each set
1384 * bit includes the corresponding item in the LAG hash calculation.
1385 * The default lag_hash contains SMAC, DMAC, VLANID and
1386 * Ethertype (for all packet types).
1389 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1391 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1393 MLXSW_REG_ZERO(slcr, payload);
1394 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1395 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1396 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1399 /* SLCOR - Switch LAG Collector Register
1400 * -------------------------------------
1401 * The Switch LAG Collector register controls the Local Port membership
1402 * in a LAG and enablement of the collector.
1404 #define MLXSW_REG_SLCOR_ID 0x2016
1405 #define MLXSW_REG_SLCOR_LEN 0x10
1407 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1408 .id = MLXSW_REG_SLCOR_ID,
1409 .len = MLXSW_REG_SLCOR_LEN,
1412 enum mlxsw_reg_slcor_col {
1413 /* Port is added with collector disabled */
1414 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1415 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1416 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1417 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1421 * Collector configuration
1424 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1426 /* reg_slcor_local_port
1428 * Not supported for CPU port
1431 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1434 * LAG Identifier. Index into the LAG descriptor table.
1437 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1439 /* reg_slcor_port_index
1440 * Port index in the LAG list. Only valid on Add Port to LAG col.
1441 * Valid range is from 0 to cap_max_lag_members-1
1444 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1446 static inline void mlxsw_reg_slcor_pack(char *payload,
1447 u8 local_port, u16 lag_id,
1448 enum mlxsw_reg_slcor_col col)
1450 MLXSW_REG_ZERO(slcor, payload);
1451 mlxsw_reg_slcor_col_set(payload, col);
1452 mlxsw_reg_slcor_local_port_set(payload, local_port);
1453 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1456 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1457 u8 local_port, u16 lag_id,
1460 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1461 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1462 mlxsw_reg_slcor_port_index_set(payload, port_index);
1465 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1472 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1479 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1480 u8 local_port, u16 lag_id)
1482 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1483 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1486 /* SPMLR - Switch Port MAC Learning Register
1487 * -----------------------------------------
1488 * Controls the Switch MAC learning policy per port.
1490 #define MLXSW_REG_SPMLR_ID 0x2018
1491 #define MLXSW_REG_SPMLR_LEN 0x8
1493 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1494 .id = MLXSW_REG_SPMLR_ID,
1495 .len = MLXSW_REG_SPMLR_LEN,
1498 /* reg_spmlr_local_port
1499 * Local port number.
1502 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1504 /* reg_spmlr_sub_port
1505 * Virtual port within the physical port.
1506 * Should be set to 0 when virtual ports are not enabled on the port.
1509 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1511 enum mlxsw_reg_spmlr_learn_mode {
1512 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1513 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1514 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1517 /* reg_spmlr_learn_mode
1518 * Learning mode on the port.
1519 * 0 - Learning disabled.
1520 * 2 - Learning enabled.
1521 * 3 - Security mode.
1523 * In security mode the switch does not learn MACs on the port, but uses the
1524 * SMAC to see if it exists on another ingress port. If so, the packet is
1525 * classified as a bad packet and is discarded unless the software registers
1526 * to receive port security error packets usign HPKT.
1528 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1530 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1531 enum mlxsw_reg_spmlr_learn_mode mode)
1533 MLXSW_REG_ZERO(spmlr, payload);
1534 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1535 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1536 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1539 /* SVFA - Switch VID to FID Allocation Register
1540 * --------------------------------------------
1541 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1542 * virtualized ports.
1544 #define MLXSW_REG_SVFA_ID 0x201C
1545 #define MLXSW_REG_SVFA_LEN 0x10
1547 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1548 .id = MLXSW_REG_SVFA_ID,
1549 .len = MLXSW_REG_SVFA_LEN,
1553 * Switch partition ID.
1556 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1558 /* reg_svfa_local_port
1559 * Local port number.
1562 * Note: Reserved for 802.1Q FIDs.
1564 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1566 enum mlxsw_reg_svfa_mt {
1567 MLXSW_REG_SVFA_MT_VID_TO_FID,
1568 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1571 /* reg_svfa_mapping_table
1574 * 1 - {Port, VID} to FID
1577 * Note: Reserved for SwitchX-2.
1579 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1586 * Note: Reserved for SwitchX-2.
1588 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1594 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1600 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1602 /* reg_svfa_counter_set_type
1603 * Counter set type for flow counters.
1606 * Note: Reserved for SwitchX-2.
1608 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1610 /* reg_svfa_counter_index
1611 * Counter index for flow counters.
1614 * Note: Reserved for SwitchX-2.
1616 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1618 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1619 enum mlxsw_reg_svfa_mt mt, bool valid,
1622 MLXSW_REG_ZERO(svfa, payload);
1623 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1624 mlxsw_reg_svfa_swid_set(payload, 0);
1625 mlxsw_reg_svfa_local_port_set(payload, local_port);
1626 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1627 mlxsw_reg_svfa_v_set(payload, valid);
1628 mlxsw_reg_svfa_fid_set(payload, fid);
1629 mlxsw_reg_svfa_vid_set(payload, vid);
1632 /* SVPE - Switch Virtual-Port Enabling Register
1633 * --------------------------------------------
1634 * Enables port virtualization.
1636 #define MLXSW_REG_SVPE_ID 0x201E
1637 #define MLXSW_REG_SVPE_LEN 0x4
1639 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1640 .id = MLXSW_REG_SVPE_ID,
1641 .len = MLXSW_REG_SVPE_LEN,
1644 /* reg_svpe_local_port
1648 * Note: CPU port is not supported (uses VLAN mode only).
1650 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1653 * Virtual port enable.
1654 * 0 - Disable, VLAN mode (VID to FID).
1655 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1658 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1660 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1663 MLXSW_REG_ZERO(svpe, payload);
1664 mlxsw_reg_svpe_local_port_set(payload, local_port);
1665 mlxsw_reg_svpe_vp_en_set(payload, enable);
1668 /* SFMR - Switch FID Management Register
1669 * -------------------------------------
1670 * Creates and configures FIDs.
1672 #define MLXSW_REG_SFMR_ID 0x201F
1673 #define MLXSW_REG_SFMR_LEN 0x18
1675 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1676 .id = MLXSW_REG_SFMR_ID,
1677 .len = MLXSW_REG_SFMR_LEN,
1680 enum mlxsw_reg_sfmr_op {
1681 MLXSW_REG_SFMR_OP_CREATE_FID,
1682 MLXSW_REG_SFMR_OP_DESTROY_FID,
1687 * 0 - Create or edit FID.
1691 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1697 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1699 /* reg_sfmr_fid_offset
1701 * Used to point into the flooding table selected by SFGC register if
1702 * the table is of type FID-Offset. Otherwise, this field is reserved.
1705 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1708 * Valid Tunnel Flood Pointer.
1709 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1712 * Note: Reserved for 802.1Q FIDs.
1714 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1716 /* reg_sfmr_nve_tunnel_flood_ptr
1717 * Underlay Flooding and BC Pointer.
1718 * Used as a pointer to the first entry of the group based link lists of
1719 * flooding or BC entries (for NVE tunnels).
1722 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1726 * If not set, then vni is reserved.
1729 * Note: Reserved for 802.1Q FIDs.
1731 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1734 * Virtual Network Identifier.
1737 * Note: A given VNI can only be assigned to one FID.
1739 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1741 static inline void mlxsw_reg_sfmr_pack(char *payload,
1742 enum mlxsw_reg_sfmr_op op, u16 fid,
1745 MLXSW_REG_ZERO(sfmr, payload);
1746 mlxsw_reg_sfmr_op_set(payload, op);
1747 mlxsw_reg_sfmr_fid_set(payload, fid);
1748 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1749 mlxsw_reg_sfmr_vtfp_set(payload, false);
1750 mlxsw_reg_sfmr_vv_set(payload, false);
1753 /* SPVMLR - Switch Port VLAN MAC Learning Register
1754 * -----------------------------------------------
1755 * Controls the switch MAC learning policy per {Port, VID}.
1757 #define MLXSW_REG_SPVMLR_ID 0x2020
1758 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1759 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1760 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1761 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1762 MLXSW_REG_SPVMLR_REC_LEN * \
1763 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1765 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1766 .id = MLXSW_REG_SPVMLR_ID,
1767 .len = MLXSW_REG_SPVMLR_LEN,
1770 /* reg_spvmlr_local_port
1771 * Local ingress port.
1774 * Note: CPU port is not supported.
1776 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1778 /* reg_spvmlr_num_rec
1779 * Number of records to update.
1782 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1784 /* reg_spvmlr_rec_learn_enable
1785 * 0 - Disable learning for {Port, VID}.
1786 * 1 - Enable learning for {Port, VID}.
1789 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1790 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1792 /* reg_spvmlr_rec_vid
1793 * VLAN ID to be added/removed from port or for querying.
1796 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1797 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1799 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1800 u16 vid_begin, u16 vid_end,
1803 int num_rec = vid_end - vid_begin + 1;
1806 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1808 MLXSW_REG_ZERO(spvmlr, payload);
1809 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1810 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1812 for (i = 0; i < num_rec; i++) {
1813 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1814 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1818 /* QTCT - QoS Switch Traffic Class Table
1819 * -------------------------------------
1820 * Configures the mapping between the packet switch priority and the
1821 * traffic class on the transmit port.
1823 #define MLXSW_REG_QTCT_ID 0x400A
1824 #define MLXSW_REG_QTCT_LEN 0x08
1826 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1827 .id = MLXSW_REG_QTCT_ID,
1828 .len = MLXSW_REG_QTCT_LEN,
1831 /* reg_qtct_local_port
1832 * Local port number.
1835 * Note: CPU port is not supported.
1837 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1839 /* reg_qtct_sub_port
1840 * Virtual port within the physical port.
1841 * Should be set to 0 when virtual ports are not enabled on the port.
1844 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1846 /* reg_qtct_switch_prio
1850 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1855 * switch_prio 0 : tclass 1
1856 * switch_prio 1 : tclass 0
1857 * switch_prio i : tclass i, for i > 1
1860 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1862 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1863 u8 switch_prio, u8 tclass)
1865 MLXSW_REG_ZERO(qtct, payload);
1866 mlxsw_reg_qtct_local_port_set(payload, local_port);
1867 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1868 mlxsw_reg_qtct_tclass_set(payload, tclass);
1871 /* QEEC - QoS ETS Element Configuration Register
1872 * ---------------------------------------------
1873 * Configures the ETS elements.
1875 #define MLXSW_REG_QEEC_ID 0x400D
1876 #define MLXSW_REG_QEEC_LEN 0x1C
1878 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1879 .id = MLXSW_REG_QEEC_ID,
1880 .len = MLXSW_REG_QEEC_LEN,
1883 /* reg_qeec_local_port
1884 * Local port number.
1887 * Note: CPU port is supported.
1889 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1891 enum mlxsw_reg_qeec_hr {
1892 MLXSW_REG_QEEC_HIERARCY_PORT,
1893 MLXSW_REG_QEEC_HIERARCY_GROUP,
1894 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1895 MLXSW_REG_QEEC_HIERARCY_TC,
1898 /* reg_qeec_element_hierarchy
1905 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1907 /* reg_qeec_element_index
1908 * The index of the element in the hierarchy.
1911 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1913 /* reg_qeec_next_element_index
1914 * The index of the next (lower) element in the hierarchy.
1917 * Note: Reserved for element_hierarchy 0.
1919 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1922 MLXSW_REG_QEEC_BYTES_MODE,
1923 MLXSW_REG_QEEC_PACKETS_MODE,
1927 * Packets or bytes mode.
1932 * Note: Used for max shaper configuration. For Spectrum, packets mode
1933 * is supported only for traffic classes of CPU port.
1935 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1938 * Max shaper configuration enable. Enables configuration of the max
1939 * shaper on this ETS element.
1944 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1946 /* A large max rate will disable the max shaper. */
1947 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1949 /* reg_qeec_max_shaper_rate
1950 * Max shaper information rate.
1951 * For CPU port, can only be configured for port hierarchy.
1952 * When in bytes mode, value is specified in units of 1000bps.
1955 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1958 * DWRR configuration enable. Enables configuration of the dwrr and
1964 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1967 * Transmission selection algorithm to use on the link going down from
1969 * 0 - Strict priority
1973 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1975 /* reg_qeec_dwrr_weight
1976 * DWRR weight on the link going down from the ETS element. The
1977 * percentage of bandwidth guaranteed to an ETS element within
1978 * its hierarchy. The sum of all weights across all ETS elements
1979 * within one hierarchy should be equal to 100. Reserved when
1980 * transmission selection algorithm is strict priority.
1983 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1985 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1986 enum mlxsw_reg_qeec_hr hr, u8 index,
1989 MLXSW_REG_ZERO(qeec, payload);
1990 mlxsw_reg_qeec_local_port_set(payload, local_port);
1991 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1992 mlxsw_reg_qeec_element_index_set(payload, index);
1993 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1996 /* PMLP - Ports Module to Local Port Register
1997 * ------------------------------------------
1998 * Configures the assignment of modules to local ports.
2000 #define MLXSW_REG_PMLP_ID 0x5002
2001 #define MLXSW_REG_PMLP_LEN 0x40
2003 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
2004 .id = MLXSW_REG_PMLP_ID,
2005 .len = MLXSW_REG_PMLP_LEN,
2009 * 0 - Tx value is used for both Tx and Rx.
2010 * 1 - Rx value is taken from a separte field.
2013 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2015 /* reg_pmlp_local_port
2016 * Local port number.
2019 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2022 * 0 - Unmap local port.
2023 * 1 - Lane 0 is used.
2024 * 2 - Lanes 0 and 1 are used.
2025 * 4 - Lanes 0, 1, 2 and 3 are used.
2028 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2034 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2037 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2040 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2043 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2047 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2049 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2051 MLXSW_REG_ZERO(pmlp, payload);
2052 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2055 /* PMTU - Port MTU Register
2056 * ------------------------
2057 * Configures and reports the port MTU.
2059 #define MLXSW_REG_PMTU_ID 0x5003
2060 #define MLXSW_REG_PMTU_LEN 0x10
2062 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2063 .id = MLXSW_REG_PMTU_ID,
2064 .len = MLXSW_REG_PMTU_LEN,
2067 /* reg_pmtu_local_port
2068 * Local port number.
2071 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2075 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2076 * reported, otherwise the minimum between the max_mtu of the different
2077 * types is reported.
2080 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2082 /* reg_pmtu_admin_mtu
2083 * MTU value to set port to. Must be smaller or equal to max_mtu.
2084 * Note: If port type is Infiniband, then port must be disabled, when its
2088 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2090 /* reg_pmtu_oper_mtu
2091 * The actual MTU configured on the port. Packets exceeding this size
2093 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2094 * oper_mtu might be smaller than admin_mtu.
2097 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2099 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2102 MLXSW_REG_ZERO(pmtu, payload);
2103 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2104 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2105 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2106 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2109 /* PTYS - Port Type and Speed Register
2110 * -----------------------------------
2111 * Configures and reports the port speed type.
2113 * Note: When set while the link is up, the changes will not take effect
2114 * until the port transitions from down to up state.
2116 #define MLXSW_REG_PTYS_ID 0x5004
2117 #define MLXSW_REG_PTYS_LEN 0x40
2119 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2120 .id = MLXSW_REG_PTYS_ID,
2121 .len = MLXSW_REG_PTYS_LEN,
2124 /* reg_ptys_local_port
2125 * Local port number.
2128 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2130 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2132 /* reg_ptys_proto_mask
2133 * Protocol mask. Indicates which protocol is used.
2135 * 1 - Fibre Channel.
2139 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2142 MLXSW_REG_PTYS_AN_STATUS_NA,
2143 MLXSW_REG_PTYS_AN_STATUS_OK,
2144 MLXSW_REG_PTYS_AN_STATUS_FAIL,
2147 /* reg_ptys_an_status
2148 * Autonegotiation status.
2151 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
2153 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2160 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2161 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2162 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2163 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2164 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2165 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2166 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2167 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
2168 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2169 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2170 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2171 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2172 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2173 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2174 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2175 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2176 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2177 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2178 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2179 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2180 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2182 /* reg_ptys_eth_proto_cap
2183 * Ethernet port supported speeds and protocols.
2186 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2188 /* reg_ptys_eth_proto_admin
2189 * Speed and protocol to set port to.
2192 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2194 /* reg_ptys_eth_proto_oper
2195 * The current speed and protocol configured for the port.
2198 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2200 /* reg_ptys_eth_proto_lp_advertise
2201 * The protocols that were advertised by the link partner during
2205 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
2207 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2210 MLXSW_REG_ZERO(ptys, payload);
2211 mlxsw_reg_ptys_local_port_set(payload, local_port);
2212 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2213 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2216 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2217 u32 *p_eth_proto_adm,
2218 u32 *p_eth_proto_oper)
2220 if (p_eth_proto_cap)
2221 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2222 if (p_eth_proto_adm)
2223 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2224 if (p_eth_proto_oper)
2225 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2228 /* PPAD - Port Physical Address Register
2229 * -------------------------------------
2230 * The PPAD register configures the per port physical MAC address.
2232 #define MLXSW_REG_PPAD_ID 0x5005
2233 #define MLXSW_REG_PPAD_LEN 0x10
2235 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2236 .id = MLXSW_REG_PPAD_ID,
2237 .len = MLXSW_REG_PPAD_LEN,
2240 /* reg_ppad_single_base_mac
2241 * 0: base_mac, local port should be 0 and mac[7:0] is
2242 * reserved. HW will set incremental
2243 * 1: single_mac - mac of the local_port
2246 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2248 /* reg_ppad_local_port
2249 * port number, if single_base_mac = 0 then local_port is reserved
2252 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2255 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2256 * If single_base_mac = 1 - the per port MAC address
2259 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2261 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2264 MLXSW_REG_ZERO(ppad, payload);
2265 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2266 mlxsw_reg_ppad_local_port_set(payload, local_port);
2269 /* PAOS - Ports Administrative and Operational Status Register
2270 * -----------------------------------------------------------
2271 * Configures and retrieves per port administrative and operational status.
2273 #define MLXSW_REG_PAOS_ID 0x5006
2274 #define MLXSW_REG_PAOS_LEN 0x10
2276 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2277 .id = MLXSW_REG_PAOS_ID,
2278 .len = MLXSW_REG_PAOS_LEN,
2282 * Switch partition ID with which to associate the port.
2283 * Note: while external ports uses unique local port numbers (and thus swid is
2284 * redundant), router ports use the same local port number where swid is the
2285 * only indication for the relevant port.
2288 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2290 /* reg_paos_local_port
2291 * Local port number.
2294 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2296 /* reg_paos_admin_status
2297 * Port administrative state (the desired state of the port):
2300 * 3 - Up once. This means that in case of link failure, the port won't go
2301 * into polling mode, but will wait to be re-enabled by software.
2302 * 4 - Disabled by system. Can only be set by hardware.
2305 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2307 /* reg_paos_oper_status
2308 * Port operational state (the current state):
2311 * 3 - Down by port failure. This means that the device will not let the
2312 * port up again until explicitly specified by software.
2315 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2318 * Admin state update enabled.
2321 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2324 * Event update enable. If this bit is set, event generation will be
2325 * updated based on the e field.
2328 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2331 * Event generation on operational state change:
2332 * 0 - Do not generate event.
2333 * 1 - Generate Event.
2334 * 2 - Generate Single Event.
2337 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2339 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2340 enum mlxsw_port_admin_status status)
2342 MLXSW_REG_ZERO(paos, payload);
2343 mlxsw_reg_paos_swid_set(payload, 0);
2344 mlxsw_reg_paos_local_port_set(payload, local_port);
2345 mlxsw_reg_paos_admin_status_set(payload, status);
2346 mlxsw_reg_paos_oper_status_set(payload, 0);
2347 mlxsw_reg_paos_ase_set(payload, 1);
2348 mlxsw_reg_paos_ee_set(payload, 1);
2349 mlxsw_reg_paos_e_set(payload, 1);
2352 /* PFCC - Ports Flow Control Configuration Register
2353 * ------------------------------------------------
2354 * Configures and retrieves the per port flow control configuration.
2356 #define MLXSW_REG_PFCC_ID 0x5007
2357 #define MLXSW_REG_PFCC_LEN 0x20
2359 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2360 .id = MLXSW_REG_PFCC_ID,
2361 .len = MLXSW_REG_PFCC_LEN,
2364 /* reg_pfcc_local_port
2365 * Local port number.
2368 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2371 * Port number access type. Determines the way local_port is interpreted:
2372 * 0 - Local port number.
2373 * 1 - IB / label port number.
2376 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2379 * Send to higher layers capabilities:
2380 * 0 - No capability of sending Pause and PFC frames to higher layers.
2381 * 1 - Device has capability of sending Pause and PFC frames to higher
2385 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2388 * Send to higher layers operation:
2389 * 0 - Pause and PFC frames are handled by the port (default).
2390 * 1 - Pause and PFC frames are handled by the port and also sent to
2391 * higher layers. Only valid if shl_cap = 1.
2394 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2397 * Pause policy auto negotiation.
2398 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2399 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2400 * based on the auto-negotiation resolution.
2403 * Note: The auto-negotiation advertisement is set according to pptx and
2404 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2406 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2408 /* reg_pfcc_prio_mask_tx
2409 * Bit per priority indicating if Tx flow control policy should be
2410 * updated based on bit pfctx.
2413 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2415 /* reg_pfcc_prio_mask_rx
2416 * Bit per priority indicating if Rx flow control policy should be
2417 * updated based on bit pfcrx.
2420 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2423 * Admin Pause policy on Tx.
2424 * 0 - Never generate Pause frames (default).
2425 * 1 - Generate Pause frames according to Rx buffer threshold.
2428 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2431 * Active (operational) Pause policy on Tx.
2432 * 0 - Never generate Pause frames.
2433 * 1 - Generate Pause frames according to Rx buffer threshold.
2436 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2439 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2440 * 0 - Never generate priority Pause frames on the specified priority
2442 * 1 - Generate priority Pause frames according to Rx buffer threshold on
2443 * the specified priority.
2446 * Note: pfctx and pptx must be mutually exclusive.
2448 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2451 * Admin Pause policy on Rx.
2452 * 0 - Ignore received Pause frames (default).
2453 * 1 - Respect received Pause frames.
2456 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2459 * Active (operational) Pause policy on Rx.
2460 * 0 - Ignore received Pause frames.
2461 * 1 - Respect received Pause frames.
2464 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2467 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2468 * 0 - Ignore incoming priority Pause frames on the specified priority
2470 * 1 - Respect incoming priority Pause frames on the specified priority.
2473 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2475 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2477 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2479 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2480 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2481 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2482 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2485 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2487 MLXSW_REG_ZERO(pfcc, payload);
2488 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2491 /* PPCNT - Ports Performance Counters Register
2492 * -------------------------------------------
2493 * The PPCNT register retrieves per port performance counters.
2495 #define MLXSW_REG_PPCNT_ID 0x5008
2496 #define MLXSW_REG_PPCNT_LEN 0x100
2498 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2499 .id = MLXSW_REG_PPCNT_ID,
2500 .len = MLXSW_REG_PPCNT_LEN,
2504 * For HCA: must be always 0.
2505 * Switch partition ID to associate port with.
2506 * Switch partitions are numbered from 0 to 7 inclusively.
2507 * Switch partition 254 indicates stacking ports.
2508 * Switch partition 255 indicates all switch partitions.
2509 * Only valid on Set() operation with local_port=255.
2512 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2514 /* reg_ppcnt_local_port
2515 * Local port number.
2516 * 255 indicates all ports on the device, and is only allowed
2517 * for Set() operation.
2520 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2523 * Port number access type:
2524 * 0 - Local port number
2525 * 1 - IB port number
2528 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2530 enum mlxsw_reg_ppcnt_grp {
2531 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2532 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2533 MLXSW_REG_PPCNT_TC_CNT = 0x11,
2537 * Performance counter group.
2538 * Group 63 indicates all groups. Only valid on Set() operation with
2540 * 0x0: IEEE 802.3 Counters
2541 * 0x1: RFC 2863 Counters
2542 * 0x2: RFC 2819 Counters
2543 * 0x3: RFC 3635 Counters
2544 * 0x5: Ethernet Extended Counters
2545 * 0x8: Link Level Retransmission Counters
2546 * 0x10: Per Priority Counters
2547 * 0x11: Per Traffic Class Counters
2548 * 0x12: Physical Layer Counters
2551 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2554 * Clear counters. Setting the clr bit will reset the counter value
2555 * for all counters in the counter group. This bit can be set
2556 * for both Set() and Get() operation.
2559 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2561 /* reg_ppcnt_prio_tc
2562 * Priority for counter set that support per priority, valid values: 0-7.
2563 * Traffic class for counter set that support per traffic class,
2564 * valid values: 0- cap_max_tclass-1 .
2565 * For HCA: cap_max_tclass is always 8.
2566 * Otherwise must be 0.
2569 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2571 /* Ethernet IEEE 802.3 Counter Group */
2573 /* reg_ppcnt_a_frames_transmitted_ok
2576 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2577 0x08 + 0x00, 0, 64);
2579 /* reg_ppcnt_a_frames_received_ok
2582 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2583 0x08 + 0x08, 0, 64);
2585 /* reg_ppcnt_a_frame_check_sequence_errors
2588 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2589 0x08 + 0x10, 0, 64);
2591 /* reg_ppcnt_a_alignment_errors
2594 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2595 0x08 + 0x18, 0, 64);
2597 /* reg_ppcnt_a_octets_transmitted_ok
2600 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2601 0x08 + 0x20, 0, 64);
2603 /* reg_ppcnt_a_octets_received_ok
2606 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2607 0x08 + 0x28, 0, 64);
2609 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2612 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2613 0x08 + 0x30, 0, 64);
2615 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2618 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2619 0x08 + 0x38, 0, 64);
2621 /* reg_ppcnt_a_multicast_frames_received_ok
2624 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2625 0x08 + 0x40, 0, 64);
2627 /* reg_ppcnt_a_broadcast_frames_received_ok
2630 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2631 0x08 + 0x48, 0, 64);
2633 /* reg_ppcnt_a_in_range_length_errors
2636 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2637 0x08 + 0x50, 0, 64);
2639 /* reg_ppcnt_a_out_of_range_length_field
2642 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2643 0x08 + 0x58, 0, 64);
2645 /* reg_ppcnt_a_frame_too_long_errors
2648 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2649 0x08 + 0x60, 0, 64);
2651 /* reg_ppcnt_a_symbol_error_during_carrier
2654 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2655 0x08 + 0x68, 0, 64);
2657 /* reg_ppcnt_a_mac_control_frames_transmitted
2660 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2661 0x08 + 0x70, 0, 64);
2663 /* reg_ppcnt_a_mac_control_frames_received
2666 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2667 0x08 + 0x78, 0, 64);
2669 /* reg_ppcnt_a_unsupported_opcodes_received
2672 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2673 0x08 + 0x80, 0, 64);
2675 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2678 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2679 0x08 + 0x88, 0, 64);
2681 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2684 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2685 0x08 + 0x90, 0, 64);
2687 /* Ethernet Per Priority Group Counters */
2689 /* reg_ppcnt_rx_octets
2692 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2694 /* reg_ppcnt_rx_frames
2697 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2699 /* reg_ppcnt_tx_octets
2702 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2704 /* reg_ppcnt_tx_frames
2707 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2709 /* reg_ppcnt_rx_pause
2712 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2714 /* reg_ppcnt_rx_pause_duration
2717 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2719 /* reg_ppcnt_tx_pause
2722 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2724 /* reg_ppcnt_tx_pause_duration
2727 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2729 /* reg_ppcnt_rx_pause_transition
2732 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2734 /* Ethernet Per Traffic Group Counters */
2736 /* reg_ppcnt_tc_transmit_queue
2737 * Contains the transmit queue depth in cells of traffic class
2738 * selected by prio_tc and the port selected by local_port.
2739 * The field cannot be cleared.
2742 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2744 /* reg_ppcnt_tc_no_buffer_discard_uc
2745 * The number of unicast packets dropped due to lack of shared
2749 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2751 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2752 enum mlxsw_reg_ppcnt_grp grp,
2755 MLXSW_REG_ZERO(ppcnt, payload);
2756 mlxsw_reg_ppcnt_swid_set(payload, 0);
2757 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2758 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2759 mlxsw_reg_ppcnt_grp_set(payload, grp);
2760 mlxsw_reg_ppcnt_clr_set(payload, 0);
2761 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2764 /* PPTB - Port Prio To Buffer Register
2765 * -----------------------------------
2766 * Configures the switch priority to buffer table.
2768 #define MLXSW_REG_PPTB_ID 0x500B
2769 #define MLXSW_REG_PPTB_LEN 0x10
2771 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2772 .id = MLXSW_REG_PPTB_ID,
2773 .len = MLXSW_REG_PPTB_LEN,
2777 MLXSW_REG_PPTB_MM_UM,
2778 MLXSW_REG_PPTB_MM_UNICAST,
2779 MLXSW_REG_PPTB_MM_MULTICAST,
2784 * 0 - Map both unicast and multicast packets to the same buffer.
2785 * 1 - Map only unicast packets.
2786 * 2 - Map only multicast packets.
2789 * Note: SwitchX-2 only supports the first option.
2791 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2793 /* reg_pptb_local_port
2794 * Local port number.
2797 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2800 * Enables the update of the untagged_buf field.
2803 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2806 * Enables the update of the prio_to_buff field.
2807 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2810 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2812 /* reg_pptb_prio_to_buff
2813 * Mapping of switch priority <i> to one of the allocated receive port
2817 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2820 * Enables the update of the prio_to_buff field.
2821 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2824 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2826 /* reg_pptb_untagged_buff
2827 * Mapping of untagged frames to one of the allocated receive port buffers.
2830 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2831 * Spectrum, as it maps untagged packets based on the default switch priority.
2833 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2835 /* reg_pptb_prio_to_buff_msb
2836 * Mapping of switch priority <i+8> to one of the allocated receive port
2840 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2842 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2844 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2846 MLXSW_REG_ZERO(pptb, payload);
2847 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2848 mlxsw_reg_pptb_local_port_set(payload, local_port);
2849 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2850 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2853 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2856 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2857 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
2860 /* PBMC - Port Buffer Management Control Register
2861 * ----------------------------------------------
2862 * The PBMC register configures and retrieves the port packet buffer
2863 * allocation for different Prios, and the Pause threshold management.
2865 #define MLXSW_REG_PBMC_ID 0x500C
2866 #define MLXSW_REG_PBMC_LEN 0x6C
2868 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2869 .id = MLXSW_REG_PBMC_ID,
2870 .len = MLXSW_REG_PBMC_LEN,
2873 /* reg_pbmc_local_port
2874 * Local port number.
2877 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2879 /* reg_pbmc_xoff_timer_value
2880 * When device generates a pause frame, it uses this value as the pause
2881 * timer (time for the peer port to pause in quota-512 bit time).
2884 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2886 /* reg_pbmc_xoff_refresh
2887 * The time before a new pause frame should be sent to refresh the pause RW
2888 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2892 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2894 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2896 /* reg_pbmc_buf_lossy
2897 * The field indicates if the buffer is lossy.
2902 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2904 /* reg_pbmc_buf_epsb
2905 * Eligible for Port Shared buffer.
2906 * If epsb is set, packets assigned to buffer are allowed to insert the port
2908 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2911 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2913 /* reg_pbmc_buf_size
2914 * The part of the packet buffer array is allocated for the specific buffer.
2915 * Units are represented in cells.
2918 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2920 /* reg_pbmc_buf_xoff_threshold
2921 * Once the amount of data in the buffer goes above this value, device
2922 * starts sending PFC frames for all priorities associated with the
2923 * buffer. Units are represented in cells. Reserved in case of lossy
2927 * Note: In Spectrum, reserved for buffer[9].
2929 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2932 /* reg_pbmc_buf_xon_threshold
2933 * When the amount of data in the buffer goes below this value, device
2934 * stops sending PFC frames for the priorities associated with the
2935 * buffer. Units are represented in cells. Reserved in case of lossy
2939 * Note: In Spectrum, reserved for buffer[9].
2941 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2944 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2945 u16 xoff_timer_value, u16 xoff_refresh)
2947 MLXSW_REG_ZERO(pbmc, payload);
2948 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2949 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2950 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2953 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2957 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2958 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2959 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2962 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2963 int buf_index, u16 size,
2966 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2967 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2968 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2969 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2970 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2973 /* PSPA - Port Switch Partition Allocation
2974 * ---------------------------------------
2975 * Controls the association of a port with a switch partition and enables
2976 * configuring ports as stacking ports.
2978 #define MLXSW_REG_PSPA_ID 0x500D
2979 #define MLXSW_REG_PSPA_LEN 0x8
2981 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2982 .id = MLXSW_REG_PSPA_ID,
2983 .len = MLXSW_REG_PSPA_LEN,
2987 * Switch partition ID.
2990 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2992 /* reg_pspa_local_port
2993 * Local port number.
2996 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2998 /* reg_pspa_sub_port
2999 * Virtual port within the local port. Set to 0 when virtual ports are
3000 * disabled on the local port.
3003 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
3005 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
3007 MLXSW_REG_ZERO(pspa, payload);
3008 mlxsw_reg_pspa_swid_set(payload, swid);
3009 mlxsw_reg_pspa_local_port_set(payload, local_port);
3010 mlxsw_reg_pspa_sub_port_set(payload, 0);
3013 /* HTGT - Host Trap Group Table
3014 * ----------------------------
3015 * Configures the properties for forwarding to CPU.
3017 #define MLXSW_REG_HTGT_ID 0x7002
3018 #define MLXSW_REG_HTGT_LEN 0x100
3020 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
3021 .id = MLXSW_REG_HTGT_ID,
3022 .len = MLXSW_REG_HTGT_LEN,
3026 * Switch partition ID.
3029 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3031 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
3037 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3039 enum mlxsw_reg_htgt_trap_group {
3040 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3041 MLXSW_REG_HTGT_TRAP_GROUP_RX,
3042 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3045 /* reg_htgt_trap_group
3046 * Trap group number. User defined number specifying which trap groups
3047 * should be forwarded to the CPU. The mapping between trap IDs and trap
3048 * groups is configured using HPKT register.
3051 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3054 MLXSW_REG_HTGT_POLICER_DISABLE,
3055 MLXSW_REG_HTGT_POLICER_ENABLE,
3059 * Enable policer ID specified using 'pid' field.
3062 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3065 * Policer ID for the trap group.
3068 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3070 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3072 /* reg_htgt_mirror_action
3073 * Mirror action to use.
3075 * 1 - Trap to CPU and mirror to a mirroring agent.
3076 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3079 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3081 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3083 /* reg_htgt_mirroring_agent
3087 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3089 /* reg_htgt_priority
3090 * Trap group priority.
3091 * In case a packet matches multiple classification rules, the packet will
3092 * only be trapped once, based on the trap ID associated with the group (via
3093 * register HPKT) with the highest priority.
3094 * Supported values are 0-7, with 7 represnting the highest priority.
3097 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3098 * by the 'trap_group' field.
3100 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3102 /* reg_htgt_local_path_cpu_tclass
3103 * CPU ingress traffic class for the trap group.
3106 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3108 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3109 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
3110 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
3112 /* reg_htgt_local_path_rdq
3113 * Receive descriptor queue (RDQ) to use for the trap group.
3116 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3118 static inline void mlxsw_reg_htgt_pack(char *payload,
3119 enum mlxsw_reg_htgt_trap_group group)
3123 MLXSW_REG_ZERO(htgt, payload);
3125 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3126 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3127 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3129 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3131 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3133 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3135 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3138 mlxsw_reg_htgt_swid_set(payload, swid);
3139 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3140 mlxsw_reg_htgt_trap_group_set(payload, group);
3141 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3142 mlxsw_reg_htgt_pid_set(payload, 0);
3143 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3144 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3145 mlxsw_reg_htgt_priority_set(payload, 0);
3146 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3147 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3150 /* HPKT - Host Packet Trap
3151 * -----------------------
3152 * Configures trap IDs inside trap groups.
3154 #define MLXSW_REG_HPKT_ID 0x7003
3155 #define MLXSW_REG_HPKT_LEN 0x10
3157 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3158 .id = MLXSW_REG_HPKT_ID,
3159 .len = MLXSW_REG_HPKT_LEN,
3163 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3164 MLXSW_REG_HPKT_ACK_REQUIRED,
3168 * Require acknowledgements from the host for events.
3169 * If set, then the device will wait for the event it sent to be acknowledged
3170 * by the host. This option is only relevant for event trap IDs.
3173 * Note: Currently not supported by firmware.
3175 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3177 enum mlxsw_reg_hpkt_action {
3178 MLXSW_REG_HPKT_ACTION_FORWARD,
3179 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3180 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3181 MLXSW_REG_HPKT_ACTION_DISCARD,
3182 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3183 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3187 * Action to perform on packet when trapped.
3188 * 0 - No action. Forward to CPU based on switching rules.
3189 * 1 - Trap to CPU (CPU receives sole copy).
3190 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3192 * 4 - Soft discard (allow other traps to act on the packet).
3193 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3196 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3197 * addressed to the CPU.
3199 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3201 /* reg_hpkt_trap_group
3202 * Trap group to associate the trap with.
3205 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3211 * Note: A trap ID can only be associated with a single trap group. The device
3212 * will associate the trap ID with the last trap group configured.
3214 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3217 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3218 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3219 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3223 * Configure dedicated buffer resources for control packets.
3224 * 0 - Keep factory defaults.
3225 * 1 - Do not use control buffer for this trap ID.
3226 * 2 - Use control buffer for this trap ID.
3229 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3231 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3233 enum mlxsw_reg_htgt_trap_group trap_group;
3235 MLXSW_REG_ZERO(hpkt, payload);
3236 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3237 mlxsw_reg_hpkt_action_set(payload, action);
3239 case MLXSW_TRAP_ID_ETHEMAD:
3240 case MLXSW_TRAP_ID_PUDE:
3241 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3244 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3247 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3248 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3249 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3252 /* RGCR - Router General Configuration Register
3253 * --------------------------------------------
3254 * The register is used for setting up the router configuration.
3256 #define MLXSW_REG_RGCR_ID 0x8001
3257 #define MLXSW_REG_RGCR_LEN 0x28
3259 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3260 .id = MLXSW_REG_RGCR_ID,
3261 .len = MLXSW_REG_RGCR_LEN,
3265 * IPv4 router enable.
3268 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3271 * IPv6 router enable.
3274 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3276 /* reg_rgcr_max_router_interfaces
3277 * Defines the maximum number of active router interfaces for all virtual
3281 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3284 * Update switch priority and packet color.
3285 * 0 - Preserve the value of Switch Priority and packet color.
3286 * 1 - Recalculate the value of Switch Priority and packet color.
3289 * Note: Not supported by SwitchX and SwitchX-2.
3291 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3294 * Indicates how to handle the pcp_rewrite_en value:
3295 * 0 - Preserve the value of pcp_rewrite_en.
3296 * 2 - Disable PCP rewrite.
3297 * 3 - Enable PCP rewrite.
3300 * Note: Not supported by SwitchX and SwitchX-2.
3302 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3304 /* reg_rgcr_activity_dis
3306 * 0 - Activity will be set when an entry is hit (default).
3307 * 1 - Activity will not be set when an entry is hit.
3309 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3311 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3313 * Bits 2:7 are reserved.
3316 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3318 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3320 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3322 MLXSW_REG_ZERO(rgcr, payload);
3323 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3326 /* RITR - Router Interface Table Register
3327 * --------------------------------------
3328 * The register is used to configure the router interface table.
3330 #define MLXSW_REG_RITR_ID 0x8002
3331 #define MLXSW_REG_RITR_LEN 0x40
3333 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3334 .id = MLXSW_REG_RITR_ID,
3335 .len = MLXSW_REG_RITR_LEN,
3339 * Enables routing on the router interface.
3342 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3345 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3349 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3352 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3356 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3358 enum mlxsw_reg_ritr_if_type {
3359 MLXSW_REG_RITR_VLAN_IF,
3360 MLXSW_REG_RITR_FID_IF,
3361 MLXSW_REG_RITR_SP_IF,
3365 * Router interface type.
3366 * 0 - VLAN interface.
3367 * 1 - FID interface.
3368 * 2 - Sub-port interface.
3371 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3374 MLXSW_REG_RITR_RIF_CREATE,
3375 MLXSW_REG_RITR_RIF_DEL,
3380 * 0 - Create or edit RIF.
3382 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3383 * is not supported. An interface must be deleted and re-created in order
3384 * to update properties.
3387 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3390 * Router interface index. A pointer to the Router Interface Table.
3393 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3396 * IPv4 Forwarding Enable.
3397 * Enables routing of IPv4 traffic on the router interface. When disabled,
3398 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3399 * Not supported in SwitchX-2.
3402 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3405 * IPv6 Forwarding Enable.
3406 * Enables routing of IPv6 traffic on the router interface. When disabled,
3407 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3408 * Not supported in SwitchX-2.
3411 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3414 * Loop-back filter enable for unicast packets.
3415 * If the flag is set then loop-back filter for unicast packets is
3416 * implemented on the RIF. Multicast packets are always subject to
3417 * loop-back filtering.
3420 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
3422 /* reg_ritr_virtual_router
3423 * Virtual router ID associated with the router interface.
3426 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3429 * Router interface MTU.
3432 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3435 * Switch partition ID.
3438 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3441 * Router interface MAC address.
3442 * In Spectrum, all MAC addresses must have the same 38 MSBits.
3445 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3447 /* VLAN Interface */
3449 /* reg_ritr_vlan_if_vid
3453 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3457 /* reg_ritr_fid_if_fid
3458 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3459 * the vFID range are supported.
3462 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3464 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3465 enum mlxsw_reg_ritr_if_type rif_type,
3468 if (rif_type == MLXSW_REG_RITR_FID_IF)
3469 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3471 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3474 /* Sub-port Interface */
3476 /* reg_ritr_sp_if_lag
3477 * LAG indication. When this bit is set the system_port field holds the
3481 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3483 /* reg_ritr_sp_system_port
3484 * Port unique indentifier. When lag bit is set, this field holds the
3485 * lag_id in bits 0:9.
3488 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3490 /* reg_ritr_sp_if_vid
3494 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3496 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3498 MLXSW_REG_ZERO(ritr, payload);
3499 mlxsw_reg_ritr_rif_set(payload, rif);
3502 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3503 u16 system_port, u16 vid)
3505 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3506 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3507 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3510 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3511 enum mlxsw_reg_ritr_if_type type,
3512 u16 rif, u16 mtu, const char *mac)
3514 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3516 MLXSW_REG_ZERO(ritr, payload);
3517 mlxsw_reg_ritr_enable_set(payload, enable);
3518 mlxsw_reg_ritr_ipv4_set(payload, 1);
3519 mlxsw_reg_ritr_type_set(payload, type);
3520 mlxsw_reg_ritr_op_set(payload, op);
3521 mlxsw_reg_ritr_rif_set(payload, rif);
3522 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3523 mlxsw_reg_ritr_lb_en_set(payload, 1);
3524 mlxsw_reg_ritr_mtu_set(payload, mtu);
3525 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3528 /* RATR - Router Adjacency Table Register
3529 * --------------------------------------
3530 * The RATR register is used to configure the Router Adjacency (next-hop)
3533 #define MLXSW_REG_RATR_ID 0x8008
3534 #define MLXSW_REG_RATR_LEN 0x2C
3536 static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3537 .id = MLXSW_REG_RATR_ID,
3538 .len = MLXSW_REG_RATR_LEN,
3541 enum mlxsw_reg_ratr_op {
3543 MLXSW_REG_RATR_OP_QUERY_READ = 0,
3544 /* Read and clear activity */
3545 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3546 /* Write Adjacency entry */
3547 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3548 /* Write Adjacency entry only if the activity is cleared.
3549 * The write may not succeed if the activity is set. There is not
3550 * direct feedback if the write has succeeded or not, however
3551 * the get will reveal the actual entry (SW can compare the get
3552 * response to the set command).
3554 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3558 * Note that Write operation may also be used for updating
3559 * counter_set_type and counter_index. In this case all other
3560 * fields must not be updated.
3563 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3566 * Valid bit. Indicates if the adjacency entry is valid.
3567 * Note: the device may need some time before reusing an invalidated
3568 * entry. During this time the entry can not be reused. It is
3569 * recommended to use another entry before reusing an invalidated
3570 * entry (e.g. software can put it at the end of the list for
3571 * reusing). Trying to access an invalidated entry not yet cleared
3572 * by the device results with failure indicating "Try Again" status.
3573 * When valid is '0' then egress_router_interface,trap_action,
3574 * adjacency_parameters and counters are reserved
3577 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3580 * Activity. Set for new entries. Set if a packet lookup has hit on
3581 * the specific entry. To clear the a bit, use "clear activity".
3584 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3586 /* reg_ratr_adjacency_index_low
3587 * Bits 15:0 of index into the adjacency table.
3588 * For SwitchX and SwitchX-2, the adjacency table is linear and
3589 * used for adjacency entries only.
3590 * For Spectrum, the index is to the KVD linear.
3593 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3595 /* reg_ratr_egress_router_interface
3596 * Range is 0 .. cap_max_router_interfaces - 1
3599 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3601 enum mlxsw_reg_ratr_trap_action {
3602 MLXSW_REG_RATR_TRAP_ACTION_NOP,
3603 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3604 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3605 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3606 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3609 /* reg_ratr_trap_action
3610 * see mlxsw_reg_ratr_trap_action
3613 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3615 enum mlxsw_reg_ratr_trap_id {
3616 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3617 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3620 /* reg_ratr_adjacency_index_high
3621 * Bits 23:16 of the adjacency_index.
3624 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3627 * Trap ID to be reported to CPU.
3628 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
3629 * For trap_action of NOP, MIRROR and DISCARD_ERROR
3632 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3634 /* reg_ratr_eth_destination_mac
3635 * MAC address of the destination next-hop.
3638 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3641 mlxsw_reg_ratr_pack(char *payload,
3642 enum mlxsw_reg_ratr_op op, bool valid,
3643 u32 adjacency_index, u16 egress_rif)
3645 MLXSW_REG_ZERO(ratr, payload);
3646 mlxsw_reg_ratr_op_set(payload, op);
3647 mlxsw_reg_ratr_v_set(payload, valid);
3648 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3649 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3650 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3653 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3654 const char *dest_mac)
3656 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3659 /* RALTA - Router Algorithmic LPM Tree Allocation Register
3660 * -------------------------------------------------------
3661 * RALTA is used to allocate the LPM trees of the SHSPM method.
3663 #define MLXSW_REG_RALTA_ID 0x8010
3664 #define MLXSW_REG_RALTA_LEN 0x04
3666 static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3667 .id = MLXSW_REG_RALTA_ID,
3668 .len = MLXSW_REG_RALTA_LEN,
3672 * opcode (valid for Write, must be 0 on Read)
3673 * 0 - allocate a tree
3674 * 1 - deallocate a tree
3677 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3679 enum mlxsw_reg_ralxx_protocol {
3680 MLXSW_REG_RALXX_PROTOCOL_IPV4,
3681 MLXSW_REG_RALXX_PROTOCOL_IPV6,
3684 /* reg_ralta_protocol
3686 * Deallocation opcode: Reserved.
3689 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3691 /* reg_ralta_tree_id
3692 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3693 * the tree identifier (managed by software).
3694 * Note that tree_id 0 is allocated for a default-route tree.
3697 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3699 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3700 enum mlxsw_reg_ralxx_protocol protocol,
3703 MLXSW_REG_ZERO(ralta, payload);
3704 mlxsw_reg_ralta_op_set(payload, !alloc);
3705 mlxsw_reg_ralta_protocol_set(payload, protocol);
3706 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3709 /* RALST - Router Algorithmic LPM Structure Tree Register
3710 * ------------------------------------------------------
3711 * RALST is used to set and query the structure of an LPM tree.
3712 * The structure of the tree must be sorted as a sorted binary tree, while
3713 * each node is a bin that is tagged as the length of the prefixes the lookup
3714 * will refer to. Therefore, bin X refers to a set of entries with prefixes
3715 * of X bits to match with the destination address. The bin 0 indicates
3716 * the default action, when there is no match of any prefix.
3718 #define MLXSW_REG_RALST_ID 0x8011
3719 #define MLXSW_REG_RALST_LEN 0x104
3721 static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3722 .id = MLXSW_REG_RALST_ID,
3723 .len = MLXSW_REG_RALST_LEN,
3726 /* reg_ralst_root_bin
3727 * The bin number of the root bin.
3728 * 0<root_bin=<(length of IP address)
3729 * For a default-route tree configure 0xff
3732 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3734 /* reg_ralst_tree_id
3735 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3738 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3740 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3741 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
3742 #define MLXSW_REG_RALST_BIN_COUNT 128
3744 /* reg_ralst_left_child_bin
3745 * Holding the children of the bin according to the stored tree's structure.
3746 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3747 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3750 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3752 /* reg_ralst_right_child_bin
3753 * Holding the children of the bin according to the stored tree's structure.
3754 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3755 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3758 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3761 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3763 MLXSW_REG_ZERO(ralst, payload);
3765 /* Initialize all bins to have no left or right child */
3766 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3767 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3769 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3770 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3773 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3777 int bin_index = bin_number - 1;
3779 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3780 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3784 /* RALTB - Router Algorithmic LPM Tree Binding Register
3785 * ----------------------------------------------------
3786 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
3788 #define MLXSW_REG_RALTB_ID 0x8012
3789 #define MLXSW_REG_RALTB_LEN 0x04
3791 static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3792 .id = MLXSW_REG_RALTB_ID,
3793 .len = MLXSW_REG_RALTB_LEN,
3796 /* reg_raltb_virtual_router
3798 * Range is 0..cap_max_virtual_routers-1
3801 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3803 /* reg_raltb_protocol
3807 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3809 /* reg_raltb_tree_id
3810 * Tree to be used for the {virtual_router, protocol}
3811 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3812 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
3815 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3817 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3818 enum mlxsw_reg_ralxx_protocol protocol,
3821 MLXSW_REG_ZERO(raltb, payload);
3822 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3823 mlxsw_reg_raltb_protocol_set(payload, protocol);
3824 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3827 /* RALUE - Router Algorithmic LPM Unicast Entry Register
3828 * -----------------------------------------------------
3829 * RALUE is used to configure and query LPM entries that serve
3830 * the Unicast protocols.
3832 #define MLXSW_REG_RALUE_ID 0x8013
3833 #define MLXSW_REG_RALUE_LEN 0x38
3835 static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3836 .id = MLXSW_REG_RALUE_ID,
3837 .len = MLXSW_REG_RALUE_LEN,
3840 /* reg_ralue_protocol
3844 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3846 enum mlxsw_reg_ralue_op {
3847 /* Read operation. If entry doesn't exist, the operation fails. */
3848 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3849 /* Clear on read operation. Used to read entry and
3850 * clear Activity bit.
3852 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3853 /* Write operation. Used to write a new entry to the table. All RW
3854 * fields are written for new entry. Activity bit is set
3857 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3858 /* Update operation. Used to update an existing route entry and
3859 * only update the RW fields that are detailed in the field
3860 * op_u_mask. If entry doesn't exist, the operation fails.
3862 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3863 /* Clear activity. The Activity bit (the field a) is cleared
3866 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3867 /* Delete operation. Used to delete an existing entry. If entry
3868 * doesn't exist, the operation fails.
3870 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3877 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3880 * Activity. Set for new entries. Set if a packet lookup has hit on the
3881 * specific entry, only if the entry is a route. To clear the a bit, use
3882 * "clear activity" op.
3883 * Enabled by activity_dis in RGCR
3886 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3888 /* reg_ralue_virtual_router
3890 * Range is 0..cap_max_virtual_routers-1
3893 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3895 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
3896 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
3897 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
3899 /* reg_ralue_op_u_mask
3900 * opcode update mask.
3901 * On read operation, this field is reserved.
3902 * This field is valid for update opcode, otherwise - reserved.
3903 * This field is a bitmask of the fields that should be updated.
3906 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3908 /* reg_ralue_prefix_len
3909 * Number of bits in the prefix of the LPM route.
3910 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
3911 * two entries in the physical HW table.
3914 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3917 * The prefix of the route or of the marker that the object of the LPM
3918 * is compared with. The most significant bits of the dip are the prefix.
3919 * The list significant bits must be '0' if the prefix_len is smaller
3920 * than 128 for IPv6 or smaller than 32 for IPv4.
3921 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
3924 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3926 enum mlxsw_reg_ralue_entry_type {
3927 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3928 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3929 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3932 /* reg_ralue_entry_type
3934 * Note - for Marker entries, the action_type and action fields are reserved.
3937 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3939 /* reg_ralue_bmp_len
3940 * The best match prefix length in the case that there is no match for
3942 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
3943 * Note for any update operation with entry_type modification this
3944 * field must be set.
3947 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3949 enum mlxsw_reg_ralue_action_type {
3950 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3951 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3952 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3955 /* reg_ralue_action_type
3957 * Indicates how the IP address is connected.
3958 * It can be connected to a local subnet through local_erif or can be
3959 * on a remote subnet connected through a next-hop router,
3960 * or transmitted to the CPU.
3961 * Reserved when entry_type = MARKER_ENTRY
3964 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3966 enum mlxsw_reg_ralue_trap_action {
3967 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3968 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3969 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3970 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3971 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3974 /* reg_ralue_trap_action
3976 * For IP2ME action, only NOP and MIRROR are possible.
3979 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3981 /* reg_ralue_trap_id
3982 * Trap ID to be reported to CPU.
3983 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
3984 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
3987 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3989 /* reg_ralue_adjacency_index
3990 * Points to the first entry of the group-based ECMP.
3991 * Only relevant in case of REMOTE action.
3994 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3996 /* reg_ralue_ecmp_size
3997 * Amount of sequential entries starting
3998 * from the adjacency_index (the number of ECMPs).
3999 * The valid range is 1-64, 512, 1024, 2048 and 4096.
4000 * Reserved when trap_action is TRAP or DISCARD_ERROR.
4001 * Only relevant in case of REMOTE action.
4004 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
4006 /* reg_ralue_local_erif
4007 * Egress Router Interface.
4008 * Only relevant in case of LOCAL action.
4011 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
4014 * Valid bit for the tunnel_ptr field.
4015 * If valid = 0 then trap to CPU as IP2ME trap ID.
4016 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
4017 * decapsulation then tunnel decapsulation is done.
4018 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
4019 * decapsulation then trap as IP2ME trap ID.
4020 * Only relevant in case of IP2ME action.
4023 MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
4025 /* reg_ralue_tunnel_ptr
4026 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
4027 * For Spectrum, pointer to KVD Linear.
4028 * Only relevant in case of IP2ME action.
4031 MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
4033 static inline void mlxsw_reg_ralue_pack(char *payload,
4034 enum mlxsw_reg_ralxx_protocol protocol,
4035 enum mlxsw_reg_ralue_op op,
4036 u16 virtual_router, u8 prefix_len)
4038 MLXSW_REG_ZERO(ralue, payload);
4039 mlxsw_reg_ralue_protocol_set(payload, protocol);
4040 mlxsw_reg_ralue_op_set(payload, op);
4041 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4042 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4043 mlxsw_reg_ralue_entry_type_set(payload,
4044 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4045 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4048 static inline void mlxsw_reg_ralue_pack4(char *payload,
4049 enum mlxsw_reg_ralxx_protocol protocol,
4050 enum mlxsw_reg_ralue_op op,
4051 u16 virtual_router, u8 prefix_len,
4054 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4055 mlxsw_reg_ralue_dip4_set(payload, dip);
4059 mlxsw_reg_ralue_act_remote_pack(char *payload,
4060 enum mlxsw_reg_ralue_trap_action trap_action,
4061 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4063 mlxsw_reg_ralue_action_type_set(payload,
4064 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4065 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4066 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4067 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4068 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4072 mlxsw_reg_ralue_act_local_pack(char *payload,
4073 enum mlxsw_reg_ralue_trap_action trap_action,
4074 u16 trap_id, u16 local_erif)
4076 mlxsw_reg_ralue_action_type_set(payload,
4077 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4078 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4079 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4080 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4084 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4086 mlxsw_reg_ralue_action_type_set(payload,
4087 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4090 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
4091 * ----------------------------------------------------------
4092 * The RAUHT register is used to configure and query the Unicast Host table in
4093 * devices that implement the Algorithmic LPM.
4095 #define MLXSW_REG_RAUHT_ID 0x8014
4096 #define MLXSW_REG_RAUHT_LEN 0x74
4098 static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4099 .id = MLXSW_REG_RAUHT_ID,
4100 .len = MLXSW_REG_RAUHT_LEN,
4103 enum mlxsw_reg_rauht_type {
4104 MLXSW_REG_RAUHT_TYPE_IPV4,
4105 MLXSW_REG_RAUHT_TYPE_IPV6,
4111 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4113 enum mlxsw_reg_rauht_op {
4114 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4115 /* Read operation */
4116 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4117 /* Clear on read operation. Used to read entry and clear
4120 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4121 /* Add. Used to write a new entry to the table. All R/W fields are
4122 * relevant for new entry. Activity bit is set for new entries.
4124 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4125 /* Update action. Used to update an existing route entry and
4126 * only update the following fields:
4127 * trap_action, trap_id, mac, counter_set_type, counter_index
4129 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4130 /* Clear activity. A bit is cleared for the entry. */
4131 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4133 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4134 /* Delete all host entries on a RIF. In this command, dip
4135 * field is reserved.
4142 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4145 * Activity. Set for new entries. Set if a packet lookup has hit on
4146 * the specific entry.
4147 * To clear the a bit, use "clear activity" op.
4148 * Enabled by activity_dis in RGCR
4151 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4157 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4160 * Destination address.
4163 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4165 enum mlxsw_reg_rauht_trap_action {
4166 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4167 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4168 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4169 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4170 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4173 /* reg_rauht_trap_action
4176 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4178 enum mlxsw_reg_rauht_trap_id {
4179 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4180 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4183 /* reg_rauht_trap_id
4184 * Trap ID to be reported to CPU.
4185 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4186 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
4187 * trap_id is reserved.
4190 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4192 /* reg_rauht_counter_set_type
4193 * Counter set type for flow counters
4196 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4198 /* reg_rauht_counter_index
4199 * Counter index for flow counters
4202 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4208 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4210 static inline void mlxsw_reg_rauht_pack(char *payload,
4211 enum mlxsw_reg_rauht_op op, u16 rif,
4214 MLXSW_REG_ZERO(rauht, payload);
4215 mlxsw_reg_rauht_op_set(payload, op);
4216 mlxsw_reg_rauht_rif_set(payload, rif);
4217 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4220 static inline void mlxsw_reg_rauht_pack4(char *payload,
4221 enum mlxsw_reg_rauht_op op, u16 rif,
4222 const char *mac, u32 dip)
4224 mlxsw_reg_rauht_pack(payload, op, rif, mac);
4225 mlxsw_reg_rauht_dip4_set(payload, dip);
4228 /* RALEU - Router Algorithmic LPM ECMP Update Register
4229 * ---------------------------------------------------
4230 * The register enables updating the ECMP section in the action for multiple
4231 * LPM Unicast entries in a single operation. The update is executed to
4232 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
4234 #define MLXSW_REG_RALEU_ID 0x8015
4235 #define MLXSW_REG_RALEU_LEN 0x28
4237 static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4238 .id = MLXSW_REG_RALEU_ID,
4239 .len = MLXSW_REG_RALEU_LEN,
4242 /* reg_raleu_protocol
4246 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4248 /* reg_raleu_virtual_router
4250 * Range is 0..cap_max_virtual_routers-1
4253 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4255 /* reg_raleu_adjacency_index
4256 * Adjacency Index used for matching on the existing entries.
4259 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4261 /* reg_raleu_ecmp_size
4262 * ECMP Size used for matching on the existing entries.
4265 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4267 /* reg_raleu_new_adjacency_index
4268 * New Adjacency Index.
4271 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4273 /* reg_raleu_new_ecmp_size
4277 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4279 static inline void mlxsw_reg_raleu_pack(char *payload,
4280 enum mlxsw_reg_ralxx_protocol protocol,
4282 u32 adjacency_index, u16 ecmp_size,
4283 u32 new_adjacency_index,
4286 MLXSW_REG_ZERO(raleu, payload);
4287 mlxsw_reg_raleu_protocol_set(payload, protocol);
4288 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4289 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4290 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4291 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4292 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4295 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
4296 * ----------------------------------------------------------------
4297 * The RAUHTD register allows dumping entries from the Router Unicast Host
4298 * Table. For a given session an entry is dumped no more than one time. The
4299 * first RAUHTD access after reset is a new session. A session ends when the
4300 * num_rec response is smaller than num_rec request or for IPv4 when the
4301 * num_entries is smaller than 4. The clear activity affect the current session
4302 * or the last session if a new session has not started.
4304 #define MLXSW_REG_RAUHTD_ID 0x8018
4305 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4306 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
4307 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4308 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4309 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4310 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4312 static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4313 .id = MLXSW_REG_RAUHTD_ID,
4314 .len = MLXSW_REG_RAUHTD_LEN,
4317 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4318 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4320 /* reg_rauhtd_filter_fields
4321 * if a bit is '0' then the relevant field is ignored and dump is done
4322 * regardless of the field value
4323 * Bit0 - filter by activity: entry_a
4324 * Bit3 - filter by entry rip: entry_rif
4327 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4329 enum mlxsw_reg_rauhtd_op {
4330 MLXSW_REG_RAUHTD_OP_DUMP,
4331 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4337 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4339 /* reg_rauhtd_num_rec
4340 * At request: number of records requested
4341 * At response: number of records dumped
4342 * For IPv4, each record has 4 entries at request and up to 4 entries
4344 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
4347 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4349 /* reg_rauhtd_entry_a
4350 * Dump only if activity has value of entry_a
4351 * Reserved if filter_fields bit0 is '0'
4354 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4356 enum mlxsw_reg_rauhtd_type {
4357 MLXSW_REG_RAUHTD_TYPE_IPV4,
4358 MLXSW_REG_RAUHTD_TYPE_IPV6,
4362 * Dump only if record type is:
4367 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4369 /* reg_rauhtd_entry_rif
4370 * Dump only if RIF has value of entry_rif
4371 * Reserved if filter_fields bit3 is '0'
4374 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4376 static inline void mlxsw_reg_rauhtd_pack(char *payload,
4377 enum mlxsw_reg_rauhtd_type type)
4379 MLXSW_REG_ZERO(rauhtd, payload);
4380 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4381 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4382 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4383 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4384 mlxsw_reg_rauhtd_type_set(payload, type);
4387 /* reg_rauhtd_ipv4_rec_num_entries
4388 * Number of valid entries in this record:
4390 * 1 - 2 valid entries
4391 * 2 - 3 valid entries
4392 * 3 - 4 valid entries
4395 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4396 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4397 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4399 /* reg_rauhtd_rec_type
4405 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4406 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4408 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4410 /* reg_rauhtd_ipv4_ent_a
4411 * Activity. Set for new entries. Set if a packet lookup has hit on the
4415 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4416 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4418 /* reg_rauhtd_ipv4_ent_rif
4422 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4423 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4425 /* reg_rauhtd_ipv4_ent_dip
4426 * Destination IPv4 address.
4429 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4430 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4432 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4433 int ent_index, u16 *p_rif,
4436 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4437 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4440 /* MFCR - Management Fan Control Register
4441 * --------------------------------------
4442 * This register controls the settings of the Fan Speed PWM mechanism.
4444 #define MLXSW_REG_MFCR_ID 0x9001
4445 #define MLXSW_REG_MFCR_LEN 0x08
4447 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4448 .id = MLXSW_REG_MFCR_ID,
4449 .len = MLXSW_REG_MFCR_LEN,
4452 enum mlxsw_reg_mfcr_pwm_frequency {
4453 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4454 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4455 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4456 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4457 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4458 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4459 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4460 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4463 /* reg_mfcr_pwm_frequency
4464 * Controls the frequency of the PWM signal.
4467 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4469 #define MLXSW_MFCR_TACHOS_MAX 10
4471 /* reg_mfcr_tacho_active
4472 * Indicates which of the tachometer is active (bit per tachometer).
4475 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4477 #define MLXSW_MFCR_PWMS_MAX 5
4479 /* reg_mfcr_pwm_active
4480 * Indicates which of the PWM control is active (bit per PWM).
4483 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4486 mlxsw_reg_mfcr_pack(char *payload,
4487 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4489 MLXSW_REG_ZERO(mfcr, payload);
4490 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4494 mlxsw_reg_mfcr_unpack(char *payload,
4495 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4496 u16 *p_tacho_active, u8 *p_pwm_active)
4498 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4499 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4500 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4503 /* MFSC - Management Fan Speed Control Register
4504 * --------------------------------------------
4505 * This register controls the settings of the Fan Speed PWM mechanism.
4507 #define MLXSW_REG_MFSC_ID 0x9002
4508 #define MLXSW_REG_MFSC_LEN 0x08
4510 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4511 .id = MLXSW_REG_MFSC_ID,
4512 .len = MLXSW_REG_MFSC_LEN,
4516 * Fan pwm to control / monitor.
4519 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4521 /* reg_mfsc_pwm_duty_cycle
4522 * Controls the duty cycle of the PWM. Value range from 0..255 to
4523 * represent duty cycle of 0%...100%.
4526 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4528 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4531 MLXSW_REG_ZERO(mfsc, payload);
4532 mlxsw_reg_mfsc_pwm_set(payload, pwm);
4533 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4536 /* MFSM - Management Fan Speed Measurement
4537 * ---------------------------------------
4538 * This register controls the settings of the Tacho measurements and
4539 * enables reading the Tachometer measurements.
4541 #define MLXSW_REG_MFSM_ID 0x9003
4542 #define MLXSW_REG_MFSM_LEN 0x08
4544 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4545 .id = MLXSW_REG_MFSM_ID,
4546 .len = MLXSW_REG_MFSM_LEN,
4550 * Fan tachometer index.
4553 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4556 * Fan speed (round per minute).
4559 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4561 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4563 MLXSW_REG_ZERO(mfsm, payload);
4564 mlxsw_reg_mfsm_tacho_set(payload, tacho);
4567 /* MTCAP - Management Temperature Capabilities
4568 * -------------------------------------------
4569 * This register exposes the capabilities of the device and
4570 * system temperature sensing.
4572 #define MLXSW_REG_MTCAP_ID 0x9009
4573 #define MLXSW_REG_MTCAP_LEN 0x08
4575 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4576 .id = MLXSW_REG_MTCAP_ID,
4577 .len = MLXSW_REG_MTCAP_LEN,
4580 /* reg_mtcap_sensor_count
4581 * Number of sensors supported by the device.
4582 * This includes the QSFP module sensors (if exists in the QSFP module).
4585 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4587 /* MTMP - Management Temperature
4588 * -----------------------------
4589 * This register controls the settings of the temperature measurements
4590 * and enables reading the temperature measurements. Note that temperature
4591 * is in 0.125 degrees Celsius.
4593 #define MLXSW_REG_MTMP_ID 0x900A
4594 #define MLXSW_REG_MTMP_LEN 0x20
4596 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4597 .id = MLXSW_REG_MTMP_ID,
4598 .len = MLXSW_REG_MTMP_LEN,
4601 /* reg_mtmp_sensor_index
4602 * Sensors index to access.
4603 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
4604 * (module 0 is mapped to sensor_index 64).
4607 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4609 /* Convert to milli degrees Celsius */
4610 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4612 /* reg_mtmp_temperature
4613 * Temperature reading from the sensor. Reading is in 0.125 Celsius
4617 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4620 * Max Temperature Enable - enables measuring the max temperature on a sensor.
4623 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4626 * Max Temperature Reset - clears the value of the max temperature register.
4629 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4631 /* reg_mtmp_max_temperature
4632 * The highest measured temperature from the sensor.
4633 * When the bit mte is cleared, the field max_temperature is reserved.
4636 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4638 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4640 /* reg_mtmp_sensor_name
4644 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4646 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4647 bool max_temp_enable,
4648 bool max_temp_reset)
4650 MLXSW_REG_ZERO(mtmp, payload);
4651 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4652 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4653 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4656 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4657 unsigned int *p_max_temp,
4663 temp = mlxsw_reg_mtmp_temperature_get(payload);
4664 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4667 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
4668 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4671 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4674 /* MPAT - Monitoring Port Analyzer Table
4675 * -------------------------------------
4676 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
4677 * For an enabled analyzer, all fields except e (enable) cannot be modified.
4679 #define MLXSW_REG_MPAT_ID 0x901A
4680 #define MLXSW_REG_MPAT_LEN 0x78
4682 static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4683 .id = MLXSW_REG_MPAT_ID,
4684 .len = MLXSW_REG_MPAT_LEN,
4691 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4693 /* reg_mpat_system_port
4694 * A unique port identifier for the final destination of the packet.
4697 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4700 * Enable. Indicating the Port Analyzer is enabled.
4703 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4706 * Quality Of Service Mode.
4707 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
4708 * PCP, DEI, DSCP or VL) are configured.
4709 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
4710 * same as in the original packet that has triggered the mirroring. For
4711 * SPAN also the pcp,dei are maintained.
4714 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4717 * Best effort mode. Indicates mirroring traffic should not cause packet
4718 * drop or back pressure, but will discard the mirrored packets. Mirrored
4719 * packets will be forwarded on a best effort manner.
4720 * 0: Do not discard mirrored packets
4721 * 1: Discard mirrored packets if causing congestion
4724 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4726 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4727 u16 system_port, bool e)
4729 MLXSW_REG_ZERO(mpat, payload);
4730 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4731 mlxsw_reg_mpat_system_port_set(payload, system_port);
4732 mlxsw_reg_mpat_e_set(payload, e);
4733 mlxsw_reg_mpat_qos_set(payload, 1);
4734 mlxsw_reg_mpat_be_set(payload, 1);
4737 /* MPAR - Monitoring Port Analyzer Register
4738 * ----------------------------------------
4739 * MPAR register is used to query and configure the port analyzer port mirroring
4742 #define MLXSW_REG_MPAR_ID 0x901B
4743 #define MLXSW_REG_MPAR_LEN 0x08
4745 static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4746 .id = MLXSW_REG_MPAR_ID,
4747 .len = MLXSW_REG_MPAR_LEN,
4750 /* reg_mpar_local_port
4751 * The local port to mirror the packets from.
4754 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4756 enum mlxsw_reg_mpar_i_e {
4757 MLXSW_REG_MPAR_TYPE_EGRESS,
4758 MLXSW_REG_MPAR_TYPE_INGRESS,
4765 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4769 * By default, port mirroring is disabled for all ports.
4772 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4778 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4780 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4781 enum mlxsw_reg_mpar_i_e i_e,
4782 bool enable, u8 pa_id)
4784 MLXSW_REG_ZERO(mpar, payload);
4785 mlxsw_reg_mpar_local_port_set(payload, local_port);
4786 mlxsw_reg_mpar_enable_set(payload, enable);
4787 mlxsw_reg_mpar_i_e_set(payload, i_e);
4788 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
4791 /* MLCR - Management LED Control Register
4792 * --------------------------------------
4793 * Controls the system LEDs.
4795 #define MLXSW_REG_MLCR_ID 0x902B
4796 #define MLXSW_REG_MLCR_LEN 0x0C
4798 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4799 .id = MLXSW_REG_MLCR_ID,
4800 .len = MLXSW_REG_MLCR_LEN,
4803 /* reg_mlcr_local_port
4804 * Local port number.
4807 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4809 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4811 /* reg_mlcr_beacon_duration
4812 * Duration of the beacon to be active, in seconds.
4813 * 0x0 - Will turn off the beacon.
4814 * 0xFFFF - Will turn on the beacon until explicitly turned off.
4817 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4819 /* reg_mlcr_beacon_remain
4820 * Remaining duration of the beacon, in seconds.
4821 * 0xFFFF indicates an infinite amount of time.
4824 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4826 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4829 MLXSW_REG_ZERO(mlcr, payload);
4830 mlxsw_reg_mlcr_local_port_set(payload, local_port);
4831 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4832 MLXSW_REG_MLCR_DURATION_MAX : 0);
4835 /* SBPR - Shared Buffer Pools Register
4836 * -----------------------------------
4837 * The SBPR configures and retrieves the shared buffer pools and configuration.
4839 #define MLXSW_REG_SBPR_ID 0xB001
4840 #define MLXSW_REG_SBPR_LEN 0x14
4842 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4843 .id = MLXSW_REG_SBPR_ID,
4844 .len = MLXSW_REG_SBPR_LEN,
4847 /* shared direstion enum for SBPR, SBCM, SBPM */
4848 enum mlxsw_reg_sbxx_dir {
4849 MLXSW_REG_SBXX_DIR_INGRESS,
4850 MLXSW_REG_SBXX_DIR_EGRESS,
4857 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4863 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4866 * Pool size in buffer cells.
4869 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4871 enum mlxsw_reg_sbpr_mode {
4872 MLXSW_REG_SBPR_MODE_STATIC,
4873 MLXSW_REG_SBPR_MODE_DYNAMIC,
4877 * Pool quota calculation mode.
4880 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4882 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
4883 enum mlxsw_reg_sbxx_dir dir,
4884 enum mlxsw_reg_sbpr_mode mode, u32 size)
4886 MLXSW_REG_ZERO(sbpr, payload);
4887 mlxsw_reg_sbpr_pool_set(payload, pool);
4888 mlxsw_reg_sbpr_dir_set(payload, dir);
4889 mlxsw_reg_sbpr_mode_set(payload, mode);
4890 mlxsw_reg_sbpr_size_set(payload, size);
4893 /* SBCM - Shared Buffer Class Management Register
4894 * ----------------------------------------------
4895 * The SBCM register configures and retrieves the shared buffer allocation
4896 * and configuration according to Port-PG, including the binding to pool
4897 * and definition of the associated quota.
4899 #define MLXSW_REG_SBCM_ID 0xB002
4900 #define MLXSW_REG_SBCM_LEN 0x28
4902 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4903 .id = MLXSW_REG_SBCM_ID,
4904 .len = MLXSW_REG_SBCM_LEN,
4907 /* reg_sbcm_local_port
4908 * Local port number.
4909 * For Ingress: excludes CPU port and Router port
4910 * For Egress: excludes IP Router
4913 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4916 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
4917 * For PG buffer: range is 0..cap_max_pg_buffers - 1
4918 * For traffic class: range is 0..cap_max_tclass - 1
4919 * Note that when traffic class is in MC aware mode then the traffic
4920 * classes which are MC aware cannot be configured.
4923 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4929 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4931 /* reg_sbcm_min_buff
4932 * Minimum buffer size for the limiter, in cells.
4935 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4937 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
4938 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4939 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4941 /* reg_sbcm_max_buff
4942 * When the pool associated to the port-pg/tclass is configured to
4943 * static, Maximum buffer size for the limiter configured in cells.
4944 * When the pool associated to the port-pg/tclass is configured to
4945 * dynamic, the max_buff holds the "alpha" parameter, supporting
4946 * the following values:
4948 * i: (1/128)*2^(i-1), for i=1..14
4952 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4955 * Association of the port-priority to a pool.
4958 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4960 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
4961 enum mlxsw_reg_sbxx_dir dir,
4962 u32 min_buff, u32 max_buff, u8 pool)
4964 MLXSW_REG_ZERO(sbcm, payload);
4965 mlxsw_reg_sbcm_local_port_set(payload, local_port);
4966 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4967 mlxsw_reg_sbcm_dir_set(payload, dir);
4968 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4969 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4970 mlxsw_reg_sbcm_pool_set(payload, pool);
4973 /* SBPM - Shared Buffer Port Management Register
4974 * ---------------------------------------------
4975 * The SBPM register configures and retrieves the shared buffer allocation
4976 * and configuration according to Port-Pool, including the definition
4977 * of the associated quota.
4979 #define MLXSW_REG_SBPM_ID 0xB003
4980 #define MLXSW_REG_SBPM_LEN 0x28
4982 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4983 .id = MLXSW_REG_SBPM_ID,
4984 .len = MLXSW_REG_SBPM_LEN,
4987 /* reg_sbpm_local_port
4988 * Local port number.
4989 * For Ingress: excludes CPU port and Router port
4990 * For Egress: excludes IP Router
4993 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4996 * The pool associated to quota counting on the local_port.
4999 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
5005 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
5007 /* reg_sbpm_buff_occupancy
5008 * Current buffer occupancy in cells.
5011 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
5014 * Clear Max Buffer Occupancy
5015 * When this bit is set, max_buff_occupancy field is cleared (and a
5016 * new max value is tracked from the time the clear was performed).
5019 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
5021 /* reg_sbpm_max_buff_occupancy
5022 * Maximum value of buffer occupancy in cells monitored. Cleared by
5023 * writing to the clr field.
5026 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
5028 /* reg_sbpm_min_buff
5029 * Minimum buffer size for the limiter, in cells.
5032 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
5034 /* reg_sbpm_max_buff
5035 * When the pool associated to the port-pg/tclass is configured to
5036 * static, Maximum buffer size for the limiter configured in cells.
5037 * When the pool associated to the port-pg/tclass is configured to
5038 * dynamic, the max_buff holds the "alpha" parameter, supporting
5039 * the following values:
5041 * i: (1/128)*2^(i-1), for i=1..14
5045 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5047 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
5048 enum mlxsw_reg_sbxx_dir dir, bool clr,
5049 u32 min_buff, u32 max_buff)
5051 MLXSW_REG_ZERO(sbpm, payload);
5052 mlxsw_reg_sbpm_local_port_set(payload, local_port);
5053 mlxsw_reg_sbpm_pool_set(payload, pool);
5054 mlxsw_reg_sbpm_dir_set(payload, dir);
5055 mlxsw_reg_sbpm_clr_set(payload, clr);
5056 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5057 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5060 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5061 u32 *p_max_buff_occupancy)
5063 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5064 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5067 /* SBMM - Shared Buffer Multicast Management Register
5068 * --------------------------------------------------
5069 * The SBMM register configures and retrieves the shared buffer allocation
5070 * and configuration for MC packets according to Switch-Priority, including
5071 * the binding to pool and definition of the associated quota.
5073 #define MLXSW_REG_SBMM_ID 0xB004
5074 #define MLXSW_REG_SBMM_LEN 0x28
5076 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5077 .id = MLXSW_REG_SBMM_ID,
5078 .len = MLXSW_REG_SBMM_LEN,
5085 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5087 /* reg_sbmm_min_buff
5088 * Minimum buffer size for the limiter, in cells.
5091 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5093 /* reg_sbmm_max_buff
5094 * When the pool associated to the port-pg/tclass is configured to
5095 * static, Maximum buffer size for the limiter configured in cells.
5096 * When the pool associated to the port-pg/tclass is configured to
5097 * dynamic, the max_buff holds the "alpha" parameter, supporting
5098 * the following values:
5100 * i: (1/128)*2^(i-1), for i=1..14
5104 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5107 * Association of the port-priority to a pool.
5110 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5112 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5113 u32 max_buff, u8 pool)
5115 MLXSW_REG_ZERO(sbmm, payload);
5116 mlxsw_reg_sbmm_prio_set(payload, prio);
5117 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5118 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5119 mlxsw_reg_sbmm_pool_set(payload, pool);
5122 /* SBSR - Shared Buffer Status Register
5123 * ------------------------------------
5124 * The SBSR register retrieves the shared buffer occupancy according to
5125 * Port-Pool. Note that this register enables reading a large amount of data.
5126 * It is the user's responsibility to limit the amount of data to ensure the
5127 * response can match the maximum transfer unit. In case the response exceeds
5128 * the maximum transport unit, it will be truncated with no special notice.
5130 #define MLXSW_REG_SBSR_ID 0xB005
5131 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
5132 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
5133 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5134 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
5135 MLXSW_REG_SBSR_REC_LEN * \
5136 MLXSW_REG_SBSR_REC_MAX_COUNT)
5138 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5139 .id = MLXSW_REG_SBSR_ID,
5140 .len = MLXSW_REG_SBSR_LEN,
5144 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
5145 * field is cleared (and a new max value is tracked from the time the clear
5149 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5151 /* reg_sbsr_ingress_port_mask
5152 * Bit vector for all ingress network ports.
5153 * Indicates which of the ports (for which the relevant bit is set)
5154 * are affected by the set operation. Configuration of any other port
5158 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5160 /* reg_sbsr_pg_buff_mask
5161 * Bit vector for all switch priority groups.
5162 * Indicates which of the priorities (for which the relevant bit is set)
5163 * are affected by the set operation. Configuration of any other priority
5165 * Range is 0..cap_max_pg_buffers - 1
5168 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5170 /* reg_sbsr_egress_port_mask
5171 * Bit vector for all egress network ports.
5172 * Indicates which of the ports (for which the relevant bit is set)
5173 * are affected by the set operation. Configuration of any other port
5177 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5179 /* reg_sbsr_tclass_mask
5180 * Bit vector for all traffic classes.
5181 * Indicates which of the traffic classes (for which the relevant bit is
5182 * set) are affected by the set operation. Configuration of any other
5183 * traffic class does not change.
5184 * Range is 0..cap_max_tclass - 1
5187 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5189 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5191 MLXSW_REG_ZERO(sbsr, payload);
5192 mlxsw_reg_sbsr_clr_set(payload, clr);
5195 /* reg_sbsr_rec_buff_occupancy
5196 * Current buffer occupancy in cells.
5199 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5200 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5202 /* reg_sbsr_rec_max_buff_occupancy
5203 * Maximum value of buffer occupancy in cells monitored. Cleared by
5204 * writing to the clr field.
5207 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5208 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5210 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5211 u32 *p_buff_occupancy,
5212 u32 *p_max_buff_occupancy)
5215 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5216 *p_max_buff_occupancy =
5217 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5220 /* SBIB - Shared Buffer Internal Buffer Register
5221 * ---------------------------------------------
5222 * The SBIB register configures per port buffers for internal use. The internal
5223 * buffers consume memory on the port buffers (note that the port buffers are
5224 * used also by PBMC).
5226 * For Spectrum this is used for egress mirroring.
5228 #define MLXSW_REG_SBIB_ID 0xB006
5229 #define MLXSW_REG_SBIB_LEN 0x10
5231 static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5232 .id = MLXSW_REG_SBIB_ID,
5233 .len = MLXSW_REG_SBIB_LEN,
5236 /* reg_sbib_local_port
5238 * Not supported for CPU port and router port
5241 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5243 /* reg_sbib_buff_size
5244 * Units represented in cells
5245 * Allowed range is 0 to (cap_max_headroom_size - 1)
5249 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5251 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5254 MLXSW_REG_ZERO(sbib, payload);
5255 mlxsw_reg_sbib_local_port_set(payload, local_port);
5256 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5259 static inline const char *mlxsw_reg_id_str(u16 reg_id)
5262 case MLXSW_REG_SGCR_ID:
5264 case MLXSW_REG_SPAD_ID:
5266 case MLXSW_REG_SMID_ID:
5268 case MLXSW_REG_SSPR_ID:
5270 case MLXSW_REG_SFDAT_ID:
5272 case MLXSW_REG_SFD_ID:
5274 case MLXSW_REG_SFN_ID:
5276 case MLXSW_REG_SPMS_ID:
5278 case MLXSW_REG_SPVID_ID:
5280 case MLXSW_REG_SPVM_ID:
5282 case MLXSW_REG_SPAFT_ID:
5284 case MLXSW_REG_SFGC_ID:
5286 case MLXSW_REG_SFTR_ID:
5288 case MLXSW_REG_SFDF_ID:
5290 case MLXSW_REG_SLDR_ID:
5292 case MLXSW_REG_SLCR_ID:
5294 case MLXSW_REG_SLCOR_ID:
5296 case MLXSW_REG_SPMLR_ID:
5298 case MLXSW_REG_SVFA_ID:
5300 case MLXSW_REG_SVPE_ID:
5302 case MLXSW_REG_SFMR_ID:
5304 case MLXSW_REG_SPVMLR_ID:
5306 case MLXSW_REG_QTCT_ID:
5308 case MLXSW_REG_QEEC_ID:
5310 case MLXSW_REG_PMLP_ID:
5312 case MLXSW_REG_PMTU_ID:
5314 case MLXSW_REG_PTYS_ID:
5316 case MLXSW_REG_PPAD_ID:
5318 case MLXSW_REG_PAOS_ID:
5320 case MLXSW_REG_PFCC_ID:
5322 case MLXSW_REG_PPCNT_ID:
5324 case MLXSW_REG_PPTB_ID:
5326 case MLXSW_REG_PBMC_ID:
5328 case MLXSW_REG_PSPA_ID:
5330 case MLXSW_REG_HTGT_ID:
5332 case MLXSW_REG_HPKT_ID:
5334 case MLXSW_REG_RGCR_ID:
5336 case MLXSW_REG_RITR_ID:
5338 case MLXSW_REG_RATR_ID:
5340 case MLXSW_REG_RALTA_ID:
5342 case MLXSW_REG_RALST_ID:
5344 case MLXSW_REG_RALTB_ID:
5346 case MLXSW_REG_RALUE_ID:
5348 case MLXSW_REG_RAUHT_ID:
5350 case MLXSW_REG_RALEU_ID:
5352 case MLXSW_REG_RAUHTD_ID:
5354 case MLXSW_REG_MFCR_ID:
5356 case MLXSW_REG_MFSC_ID:
5358 case MLXSW_REG_MFSM_ID:
5360 case MLXSW_REG_MTCAP_ID:
5362 case MLXSW_REG_MPAT_ID:
5364 case MLXSW_REG_MPAR_ID:
5366 case MLXSW_REG_MTMP_ID:
5368 case MLXSW_REG_MLCR_ID:
5370 case MLXSW_REG_SBPR_ID:
5372 case MLXSW_REG_SBCM_ID:
5374 case MLXSW_REG_SBPM_ID:
5376 case MLXSW_REG_SBMM_ID:
5378 case MLXSW_REG_SBSR_ID:
5380 case MLXSW_REG_SBIB_ID:
5387 /* PUDE - Port Up / Down Event
5388 * ---------------------------
5389 * Reports the operational state change of a port.
5391 #define MLXSW_REG_PUDE_LEN 0x10
5394 * Switch partition ID with which to associate the port.
5397 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5399 /* reg_pude_local_port
5400 * Local port number.
5403 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5405 /* reg_pude_admin_status
5406 * Port administrative state (the desired state).
5409 * 3 - Up once. This means that in case of link failure, the port won't go
5410 * into polling mode, but will wait to be re-enabled by software.
5411 * 4 - Disabled by system. Can only be set by hardware.
5414 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5416 /* reg_pude_oper_status
5417 * Port operatioanl state.
5420 * 3 - Down by port failure. This means that the device will not let the
5421 * port up again until explicitly specified by software.
5424 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);