2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #ifndef _MLXSW_SPECTRUM_H
38 #define _MLXSW_SPECTRUM_H
40 #include <linux/types.h>
41 #include <linux/netdevice.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
44 #include <linux/list.h>
45 #include <linux/dcbnl.h>
46 #include <linux/in6.h>
47 #include <net/switchdev.h>
52 #define MLXSW_SP_VFID_BASE VLAN_N_VID
53 #define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
54 #define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
55 #define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
57 #define MLXSW_SP_LAG_MAX 64
58 #define MLXSW_SP_PORT_PER_LAG_MAX 16
60 #define MLXSW_SP_MID_MAX 7000
62 #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
64 #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
65 #define MLXSW_SP_LPM_TREE_MAX 22
66 #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
68 #define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
70 #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
72 #define MLXSW_SP_BYTES_PER_CELL 96
74 #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
75 #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
77 /* Maximum delay buffer needed in case of PAUSE frames, in cells.
78 * Assumes 100m cable and maximum MTU.
80 #define MLXSW_SP_PAUSE_DELAY 612
82 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
84 #define MLXSW_SP_RIF_MAX 800
86 static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
88 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
89 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
94 struct mlxsw_sp_upper {
95 struct net_device *dev;
96 unsigned int ref_count;
100 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
101 struct list_head list;
102 unsigned int ref_count;
103 struct net_device *dev;
108 struct mlxsw_sp_rif {
109 struct net_device *dev;
113 struct mlxsw_sp_mid {
114 struct list_head list;
115 unsigned char addr[ETH_ALEN];
118 unsigned int ref_count;
121 static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
123 return MLXSW_SP_VFID_BASE + vfid;
126 static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
128 return fid - MLXSW_SP_VFID_BASE;
131 static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
133 return fid >= MLXSW_SP_VFID_BASE;
136 struct mlxsw_sp_sb_pr {
137 enum mlxsw_reg_sbpr_mode mode;
141 struct mlxsw_cp_sb_occ {
146 struct mlxsw_sp_sb_cm {
150 struct mlxsw_cp_sb_occ occ;
153 struct mlxsw_sp_sb_pm {
156 struct mlxsw_cp_sb_occ occ;
159 #define MLXSW_SP_SB_POOL_COUNT 4
160 #define MLXSW_SP_SB_TC_COUNT 8
163 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
165 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
166 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
167 } ports[MLXSW_PORT_MAX_PORTS];
170 #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
172 struct mlxsw_sp_prefix_usage {
173 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
176 enum mlxsw_sp_l3proto {
177 MLXSW_SP_L3_PROTO_IPV4,
178 MLXSW_SP_L3_PROTO_IPV6,
181 struct mlxsw_sp_lpm_tree {
183 unsigned int ref_count;
184 enum mlxsw_sp_l3proto proto;
185 struct mlxsw_sp_prefix_usage prefix_usage;
191 u16 id; /* virtual router ID */
193 enum mlxsw_sp_l3proto proto;
194 u32 tb_id; /* kernel fib table id */
195 struct mlxsw_sp_lpm_tree *lpm_tree;
196 struct mlxsw_sp_fib *fib;
199 struct mlxsw_sp_router {
200 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
201 struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX];
206 struct list_head list;
207 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_PORT_MAX);
210 struct list_head list;
211 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_BR_MAX);
214 struct list_head list;
215 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
217 struct list_head fids; /* VLAN-aware bridge FIDs */
218 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
219 struct mlxsw_sp_port **ports;
220 struct mlxsw_core *core;
221 const struct mlxsw_bus_info *bus_info;
222 unsigned char base_mac[ETH_ALEN];
224 struct delayed_work dw;
225 #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
226 unsigned int interval; /* ms */
228 #define MLXSW_SP_MIN_AGEING_TIME 10
229 #define MLXSW_SP_MAX_AGEING_TIME 1000000
230 #define MLXSW_SP_DEFAULT_AGEING_TIME 300
232 struct mlxsw_sp_upper master_bridge;
233 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
234 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
235 struct mlxsw_sp_sb sb;
236 struct mlxsw_sp_router router;
239 static inline struct mlxsw_sp_upper *
240 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
242 return &mlxsw_sp->lags[lag_id];
245 struct mlxsw_sp_port_pcpu_stats {
250 struct u64_stats_sync syncp;
254 struct mlxsw_sp_port {
255 struct mlxsw_core_port core_port; /* must be first */
256 struct net_device *dev;
257 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
258 struct mlxsw_sp *mlxsw_sp;
270 struct list_head list;
271 struct mlxsw_sp_fid *f;
279 struct ieee_ets *ets;
280 struct ieee_maxrate *maxrate;
281 struct ieee_pfc *pfc;
288 /* 802.1Q bridge VLANs */
289 unsigned long *active_vlans;
290 unsigned long *untagged_vlans;
291 /* VLAN interfaces */
292 struct list_head vports_list;
296 mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
298 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
301 static inline struct mlxsw_sp_port *
302 mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
304 struct mlxsw_sp_port *mlxsw_sp_port;
307 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
309 mlxsw_sp_port = mlxsw_sp->ports[local_port];
310 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
314 mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
316 return mlxsw_sp_vport->vport.vid;
320 mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
322 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
327 static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
328 struct mlxsw_sp_fid *f)
330 mlxsw_sp_vport->vport.f = f;
333 static inline struct mlxsw_sp_fid *
334 mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
336 return mlxsw_sp_vport->vport.f;
339 static inline struct net_device *
340 mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
342 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
344 return f ? f->dev : NULL;
347 static inline struct mlxsw_sp_port *
348 mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
350 struct mlxsw_sp_port *mlxsw_sp_vport;
352 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
354 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
355 return mlxsw_sp_vport;
361 static inline struct mlxsw_sp_port *
362 mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
365 struct mlxsw_sp_port *mlxsw_sp_vport;
367 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
369 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
371 if (f && f->fid == fid)
372 return mlxsw_sp_vport;
378 static inline struct mlxsw_sp_rif *
379 mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
380 const struct net_device *dev)
384 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
385 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
386 return mlxsw_sp->rifs[i];
391 enum mlxsw_sp_flood_table {
392 MLXSW_SP_FLOOD_TABLE_UC,
393 MLXSW_SP_FLOOD_TABLE_BM,
396 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
397 void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
398 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
399 int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
400 unsigned int sb_index, u16 pool_index,
401 struct devlink_sb_pool_info *pool_info);
402 int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
403 unsigned int sb_index, u16 pool_index, u32 size,
404 enum devlink_sb_threshold_type threshold_type);
405 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
406 unsigned int sb_index, u16 pool_index,
408 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
409 unsigned int sb_index, u16 pool_index,
411 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
412 unsigned int sb_index, u16 tc_index,
413 enum devlink_sb_pool_type pool_type,
414 u16 *p_pool_index, u32 *p_threshold);
415 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
416 unsigned int sb_index, u16 tc_index,
417 enum devlink_sb_pool_type pool_type,
418 u16 pool_index, u32 threshold);
419 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
420 unsigned int sb_index);
421 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
422 unsigned int sb_index);
423 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
424 unsigned int sb_index, u16 pool_index,
425 u32 *p_cur, u32 *p_max);
426 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
427 unsigned int sb_index, u16 tc_index,
428 enum devlink_sb_pool_type pool_type,
429 u32 *p_cur, u32 *p_max);
431 int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
432 void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
433 int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
434 void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
435 void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
436 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
437 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
439 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
440 u16 vid_end, bool is_member, bool untagged);
441 int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
443 int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
445 void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
446 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
447 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
448 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
449 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
450 bool dwrr, u8 dwrr_weight);
451 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
452 u8 switch_prio, u8 tclass);
453 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
454 u8 *prio_tc, bool pause_en,
455 struct ieee_pfc *my_pfc);
456 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
457 enum mlxsw_reg_qeec_hr hr, u8 index,
458 u8 next_index, u32 maxrate);
460 #ifdef CONFIG_MLXSW_SPECTRUM_DCB
462 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
463 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
467 static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
472 static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
477 int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
478 void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
479 int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port,
480 const struct switchdev_obj_ipv4_fib *fib4,
481 struct switchdev_trans *trans);
482 int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port,
483 const struct switchdev_obj_ipv4_fib *fib4);