drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_H
  10 #define _QED_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18 #include <linux/mutex.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/string.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/zlib.h>
  24 #include <linux/hashtable.h>
  25 #include <linux/qed/qed_if.h>
  26 #include "qed_hsi.h"
  27
  28 extern const struct qed_common_ops qed_common_ops_pass;
  29 #define DRV_MODULE_VERSION "8.10.9.20"
  30
  31 #define MAX_HWFNS_PER_DEVICE    (4)
  32 #define NAME_SIZE 16
  33 #define VER_SIZE 16
  34
  35 #define QED_WFQ_UNIT    100
  36
  37 /* cau states */
  38 enum qed_coalescing_mode {
  39         QED_COAL_MODE_DISABLE,
  40         QED_COAL_MODE_ENABLE
  41 };
  42
  43 struct qed_eth_cb_ops;
  44 struct qed_dev_info;
  45 union qed_mcp_protocol_stats;
  46 enum qed_mcp_protocol_type;
  47
  48 /* helpers */
  49 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  50 {
  51         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  52                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
  53
  54         return db_addr;
  55 }
  56
  57 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
  58         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
  59          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
  60
  61 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
  62
  63 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
  64         (val == (cond1) ? true1 :                     \
  65          (val == (cond2) ? true2 : def))
  66
  67 /* forward */
  68 struct qed_ptt_pool;
  69 struct qed_spq;
  70 struct qed_sb_info;
  71 struct qed_sb_attn_info;
  72 struct qed_cxt_mngr;
  73 struct qed_sb_sp_info;
  74 struct qed_mcp_info;
  75
  76 struct qed_rt_data {
  77         u32     *init_val;
  78         bool    *b_valid;
  79 };
  80
  81 enum qed_tunn_mode {
  82         QED_MODE_L2GENEVE_TUNN,
  83         QED_MODE_IPGENEVE_TUNN,
  84         QED_MODE_L2GRE_TUNN,
  85         QED_MODE_IPGRE_TUNN,
  86         QED_MODE_VXLAN_TUNN,
  87 };
  88
  89 enum qed_tunn_clss {
  90         QED_TUNN_CLSS_MAC_VLAN,
  91         QED_TUNN_CLSS_MAC_VNI,
  92         QED_TUNN_CLSS_INNER_MAC_VLAN,
  93         QED_TUNN_CLSS_INNER_MAC_VNI,
  94         MAX_QED_TUNN_CLSS,
  95 };
  96
  97 struct qed_tunn_start_params {
  98         unsigned long   tunn_mode;
  99         u16             vxlan_udp_port;
 100         u16             geneve_udp_port;
 101         u8              update_vxlan_udp_port;
 102         u8              update_geneve_udp_port;
 103         u8              tunn_clss_vxlan;
 104         u8              tunn_clss_l2geneve;
 105         u8              tunn_clss_ipgeneve;
 106         u8              tunn_clss_l2gre;
 107         u8              tunn_clss_ipgre;
 108 };
 109
 110 struct qed_tunn_update_params {
 111         unsigned long   tunn_mode_update_mask;
 112         unsigned long   tunn_mode;
 113         u16             vxlan_udp_port;
 114         u16             geneve_udp_port;
 115         u8              update_rx_pf_clss;
 116         u8              update_tx_pf_clss;
 117         u8              update_vxlan_udp_port;
 118         u8              update_geneve_udp_port;
 119         u8              tunn_clss_vxlan;
 120         u8              tunn_clss_l2geneve;
 121         u8              tunn_clss_ipgeneve;
 122         u8              tunn_clss_l2gre;
 123         u8              tunn_clss_ipgre;
 124 };
 125
 126 /* The PCI personality is not quite synonymous to protocol ID:
 127  * 1. All personalities need CORE connections
 128  * 2. The Ethernet personality may support also the RoCE protocol
 129  */
 130 enum qed_pci_personality {
 131         QED_PCI_ETH,
 132         QED_PCI_ISCSI,
 133         QED_PCI_ETH_ROCE,
 134         QED_PCI_DEFAULT /* default in shmem */
 135 };
 136
 137 /* All VFs are symmetric, all counters are PF + all VFs */
 138 struct qed_qm_iids {
 139         u32 cids;
 140         u32 vf_cids;
 141         u32 tids;
 142 };
 143
 144 enum QED_RESOURCES {
 145         QED_SB,
 146         QED_L2_QUEUE,
 147         QED_VPORT,
 148         QED_RSS_ENG,
 149         QED_PQ,
 150         QED_RL,
 151         QED_MAC,
 152         QED_VLAN,
 153         QED_ILT,
 154         QED_MAX_RESC,
 155 };
 156
 157 enum QED_FEATURE {
 158         QED_PF_L2_QUE,
 159         QED_VF,
 160         QED_MAX_FEATURES,
 161 };
 162
 163 enum QED_PORT_MODE {
 164         QED_PORT_MODE_DE_2X40G,
 165         QED_PORT_MODE_DE_2X50G,
 166         QED_PORT_MODE_DE_1X100G,
 167         QED_PORT_MODE_DE_4X10G_F,
 168         QED_PORT_MODE_DE_4X10G_E,
 169         QED_PORT_MODE_DE_4X20G,
 170         QED_PORT_MODE_DE_1X40G,
 171         QED_PORT_MODE_DE_2X25G,
 172         QED_PORT_MODE_DE_1X25G
 173 };
 174
 175 enum qed_dev_cap {
 176         QED_DEV_CAP_ETH,
 177         QED_DEV_CAP_ISCSI,
 178         QED_DEV_CAP_ROCE,
 179 };
 180
 181 struct qed_hw_info {
 182         /* PCI personality */
 183         enum qed_pci_personality        personality;
 184
 185         /* Resource Allocation scheme results */
 186         u32                             resc_start[QED_MAX_RESC];
 187         u32                             resc_num[QED_MAX_RESC];
 188         u32                             feat_num[QED_MAX_FEATURES];
 189
 190 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 191 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 192 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 193                                  RESC_NUM(_p_hwfn, resc))
 194 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 195
 196         u8                              num_tc;
 197         u8                              offload_tc;
 198         u8                              non_offload_tc;
 199
 200         u32                             concrete_fid;
 201         u16                             opaque_fid;
 202         u16                             ovlan;
 203         u32                             part_num[4];
 204
 205         unsigned char                   hw_mac_addr[ETH_ALEN];
 206
 207         struct qed_igu_info             *p_igu_info;
 208
 209         u32                             port_mode;
 210         u32                             hw_mode;
 211         unsigned long           device_capabilities;
 212 };
 213
 214 struct qed_hw_cid_data {
 215         u32     cid;
 216         bool    b_cid_allocated;
 217
 218         /* Additional identifiers */
 219         u16     opaque_fid;
 220         u8      vport_id;
 221 };
 222
 223 /* maximun size of read/write commands (HW limit) */
 224 #define DMAE_MAX_RW_SIZE        0x2000
 225
 226 struct qed_dmae_info {
 227         /* Mutex for synchronizing access to functions */
 228         struct mutex    mutex;
 229
 230         u8              channel;
 231
 232         dma_addr_t      completion_word_phys_addr;
 233
 234         /* The memory location where the DMAE writes the completion
 235          * value when an operation is finished on this context.
 236          */
 237         u32             *p_completion_word;
 238
 239         dma_addr_t      intermediate_buffer_phys_addr;
 240
 241         /* An intermediate buffer for DMAE operations that use virtual
 242          * addresses - data is DMA'd to/from this buffer and then
 243          * memcpy'd to/from the virtual address
 244          */
 245         u32             *p_intermediate_buffer;
 246
 247         dma_addr_t      dmae_cmd_phys_addr;
 248         struct dmae_cmd *p_dmae_cmd;
 249 };
 250
 251 struct qed_wfq_data {
 252         /* when feature is configured for at least 1 vport */
 253         u32     min_speed;
 254         bool    configured;
 255 };
 256
 257 struct qed_qm_info {
 258         struct init_qm_pq_params        *qm_pq_params;
 259         struct init_qm_vport_params     *qm_vport_params;
 260         struct init_qm_port_params      *qm_port_params;
 261         u16                             start_pq;
 262         u8                              start_vport;
 263         u8                              pure_lb_pq;
 264         u8                              offload_pq;
 265         u8                              pure_ack_pq;
 266         u8 ooo_pq;
 267         u8                              vf_queues_offset;
 268         u16                             num_pqs;
 269         u16                             num_vf_pqs;
 270         u8                              num_vports;
 271         u8                              max_phys_tcs_per_port;
 272         bool                            pf_rl_en;
 273         bool                            pf_wfq_en;
 274         bool                            vport_rl_en;
 275         bool                            vport_wfq_en;
 276         u8                              pf_wfq;
 277         u32                             pf_rl;
 278         struct qed_wfq_data             *wfq_data;
 279         u8 num_pf_rls;
 280 };
 281
 282 struct storm_stats {
 283         u32     address;
 284         u32     len;
 285 };
 286
 287 struct qed_storm_stats {
 288         struct storm_stats mstats;
 289         struct storm_stats pstats;
 290         struct storm_stats tstats;
 291         struct storm_stats ustats;
 292 };
 293
 294 struct qed_fw_data {
 295         struct fw_ver_info      *fw_ver_info;
 296         const u8                *modes_tree_buf;
 297         union init_op           *init_ops;
 298         const u32               *arr_data;
 299         u32                     init_ops_size;
 300 };
 301
 302 struct qed_simd_fp_handler {
 303         void    *token;
 304         void    (*func)(void *);
 305 };
 306
 307 struct qed_hwfn {
 308         struct qed_dev                  *cdev;
 309         u8                              my_id;          /* ID inside the PF */
 310 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 311         u8                              rel_pf_id;      /* Relative to engine*/
 312         u8                              abs_pf_id;
 313 #define QED_PATH_ID(_p_hwfn)            ((_p_hwfn)->abs_pf_id & 1)
 314         u8                              port_id;
 315         bool                            b_active;
 316
 317         u32                             dp_module;
 318         u8                              dp_level;
 319         char                            name[NAME_SIZE];
 320
 321         bool                            first_on_engine;
 322         bool                            hw_init_done;
 323
 324         u8                              num_funcs_on_engine;
 325         u8 enabled_func_idx;
 326
 327         /* BAR access */
 328         void __iomem                    *regview;
 329         void __iomem                    *doorbells;
 330         u64                             db_phys_addr;
 331         unsigned long                   db_size;
 332
 333         /* PTT pool */
 334         struct qed_ptt_pool             *p_ptt_pool;
 335
 336         /* HW info */
 337         struct qed_hw_info              hw_info;
 338
 339         /* rt_array (for init-tool) */
 340         struct qed_rt_data              rt_data;
 341
 342         /* SPQ */
 343         struct qed_spq                  *p_spq;
 344
 345         /* EQ */
 346         struct qed_eq                   *p_eq;
 347
 348         /* Consolidate Q*/
 349         struct qed_consq                *p_consq;
 350
 351         /* Slow-Path definitions */
 352         struct tasklet_struct           *sp_dpc;
 353         bool                            b_sp_dpc_enabled;
 354
 355         struct qed_ptt                  *p_main_ptt;
 356         struct qed_ptt                  *p_dpc_ptt;
 357
 358         struct qed_sb_sp_info           *p_sp_sb;
 359         struct qed_sb_attn_info         *p_sb_attn;
 360
 361         /* Protocol related */
 362         struct qed_pf_params            pf_params;
 363
 364         bool b_rdma_enabled_in_prs;
 365         u32 rdma_prs_search_reg;
 366
 367         /* Array of sb_info of all status blocks */
 368         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 369         u16                             num_sbs;
 370
 371         struct qed_cxt_mngr             *p_cxt_mngr;
 372
 373         /* Flag indicating whether interrupts are enabled or not*/
 374         bool                            b_int_enabled;
 375         bool                            b_int_requested;
 376
 377         /* True if the driver requests for the link */
 378         bool                            b_drv_link_init;
 379
 380         struct qed_vf_iov               *vf_iov_info;
 381         struct qed_pf_iov               *pf_iov_info;
 382         struct qed_mcp_info             *mcp_info;
 383
 384         struct qed_dcbx_info            *p_dcbx_info;
 385
 386         struct qed_hw_cid_data          *p_tx_cids;
 387         struct qed_hw_cid_data          *p_rx_cids;
 388
 389         struct qed_dmae_info            dmae_info;
 390
 391         /* QM init */
 392         struct qed_qm_info              qm_info;
 393         struct qed_storm_stats          storm_stats;
 394
 395         /* Buffer for unzipping firmware data */
 396         void                            *unzip_buf;
 397
 398         struct qed_simd_fp_handler      simd_proto_handler[64];
 399
 400 #ifdef CONFIG_QED_SRIOV
 401         struct workqueue_struct *iov_wq;
 402         struct delayed_work iov_task;
 403         unsigned long iov_task_flags;
 404 #endif
 405
 406         struct z_stream_s               *stream;
 407 };
 408
 409 struct pci_params {
 410         int             pm_cap;
 411
 412         unsigned long   mem_start;
 413         unsigned long   mem_end;
 414         unsigned int    irq;
 415         u8              pf_num;
 416 };
 417
 418 struct qed_int_param {
 419         u32     int_mode;
 420         u8      num_vectors;
 421         u8      min_msix_cnt; /* for minimal functionality */
 422 };
 423
 424 struct qed_int_params {
 425         struct qed_int_param    in;
 426         struct qed_int_param    out;
 427         struct msix_entry       *msix_table;
 428         bool                    fp_initialized;
 429         u8                      fp_msix_base;
 430         u8                      fp_msix_cnt;
 431 };
 432
 433 struct qed_dev {
 434         u32     dp_module;
 435         u8      dp_level;
 436         char    name[NAME_SIZE];
 437
 438         u8      type;
 439 #define QED_DEV_TYPE_BB (0 << 0)
 440 #define QED_DEV_TYPE_AH BIT(0)
 441 /* Translate type/revision combo into the proper conditions */
 442 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 443 #define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
 444                                  CHIP_REV_IS_A0(dev))
 445 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 446                                  CHIP_REV_IS_B0(dev))
 447
 448 #define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
 449                                  QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
 450
 451         u16     vendor_id;
 452         u16     device_id;
 453
 454         u16     chip_num;
 455 #define CHIP_NUM_MASK                   0xffff
 456 #define CHIP_NUM_SHIFT                  16
 457
 458         u16     chip_rev;
 459 #define CHIP_REV_MASK                   0xf
 460 #define CHIP_REV_SHIFT                  12
 461 #define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
 462 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 463
 464         u16                             chip_metal;
 465 #define CHIP_METAL_MASK                 0xff
 466 #define CHIP_METAL_SHIFT                4
 467
 468         u16                             chip_bond_id;
 469 #define CHIP_BOND_ID_MASK               0xf
 470 #define CHIP_BOND_ID_SHIFT              0
 471
 472         u8                              num_engines;
 473         u8                              num_ports_in_engines;
 474         u8                              num_funcs_in_port;
 475
 476         u8                              path_id;
 477         enum qed_mf_mode                mf_mode;
 478 #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
 479 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
 480 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
 481
 482         int                             pcie_width;
 483         int                             pcie_speed;
 484         u8                              ver_str[VER_SIZE];
 485
 486         /* Add MF related configuration */
 487         u8                              mcp_rev;
 488         u8                              boot_mode;
 489
 490         u8                              wol;
 491
 492         u32                             int_mode;
 493         enum qed_coalescing_mode        int_coalescing_mode;
 494         u16                             rx_coalesce_usecs;
 495         u16                             tx_coalesce_usecs;
 496
 497         /* Start Bar offset of first hwfn */
 498         void __iomem                    *regview;
 499         void __iomem                    *doorbells;
 500         u64                             db_phys_addr;
 501         unsigned long                   db_size;
 502
 503         /* PCI */
 504         u8                              cache_shift;
 505
 506         /* Init */
 507         const struct iro                *iro_arr;
 508 #define IRO (p_hwfn->cdev->iro_arr)
 509
 510         /* HW functions */
 511         u8                              num_hwfns;
 512         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 513
 514         /* SRIOV */
 515         struct qed_hw_sriov_info *p_iov_info;
 516 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 517
 518         unsigned long                   tunn_mode;
 519
 520         bool                            b_is_vf;
 521         u32                             drv_type;
 522
 523         struct qed_eth_stats            *reset_stats;
 524         struct qed_fw_data              *fw_data;
 525
 526         u32                             mcp_nvm_resp;
 527
 528         /* Linux specific here */
 529         struct  qede_dev                *edev;
 530         struct  pci_dev                 *pdev;
 531         int                             msg_enable;
 532
 533         struct pci_params               pci_params;
 534
 535         struct qed_int_params           int_params;
 536
 537         u8                              protocol;
 538 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 539
 540         /* Callbacks to protocol driver */
 541         union {
 542                 struct qed_common_cb_ops        *common;
 543                 struct qed_eth_cb_ops           *eth;
 544         } protocol_ops;
 545         void                            *ops_cookie;
 546
 547         const struct firmware           *firmware;
 548 };
 549
 550 #define NUM_OF_VFS(dev)         MAX_NUM_VFS_BB
 551 #define NUM_OF_L2_QUEUES(dev)   MAX_NUM_L2_QUEUES_BB
 552 #define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
 553 #define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB
 554
 555 /**
 556  * @brief qed_concrete_to_sw_fid - get the sw function id from
 557  *        the concrete value.
 558  *
 559  * @param concrete_fid
 560  *
 561  * @return inline u8
 562  */
 563 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 564                                         u32 concrete_fid)
 565 {
 566         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 567         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 568         u8 vf_valid = GET_FIELD(concrete_fid,
 569                                 PXP_CONCRETE_FID_VFVALID);
 570         u8 sw_fid;
 571
 572         if (vf_valid)
 573                 sw_fid = vfid + MAX_NUM_PFS;
 574         else
 575                 sw_fid = pfid;
 576
 577         return sw_fid;
 578 }
 579
 580 #define PURE_LB_TC 8
 581 #define OOO_LB_TC 9
 582
 583 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 584 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
 585
 586 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 587 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 588
 589 /* Other Linux specific common definitions */
 590 #define DP_NAME(cdev) ((cdev)->name)
 591
 592 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 593                                                 (cdev->regview) + \
 594                                                          (offset))
 595
 596 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 597 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 598 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 599
 600 #define DOORBELL(cdev, db_addr, val)                     \
 601         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 602                                           (cdev->doorbells) + (db_addr)))
 603
 604 /* Prototypes */
 605 int qed_fill_dev_info(struct qed_dev *cdev,
 606                       struct qed_dev_info *dev_info);
 607 void qed_link_update(struct qed_hwfn *hwfn);
 608 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 609                    u32 input_len, u8 *input_buf,
 610                    u32 max_size, u8 *unzip_buf);
 611 void qed_get_protocol_stats(struct qed_dev *cdev,
 612                             enum qed_mcp_protocol_type type,
 613                             union qed_mcp_protocol_stats *stats);
 614 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 615
 616 #endif /* _QED_H */