1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/mutex.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/workqueue.h>
23 #include <linux/zlib.h>
24 #include <linux/hashtable.h>
25 #include <linux/qed/qed_if.h>
28 extern const struct qed_common_ops qed_common_ops_pass;
29 #define DRV_MODULE_VERSION "8.7.1.20"
31 #define MAX_HWFNS_PER_DEVICE (4)
36 enum qed_coalescing_mode {
37 QED_COAL_MODE_DISABLE,
41 struct qed_eth_cb_ops;
45 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
47 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
48 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
53 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
54 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
55 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
57 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
59 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
60 (val == (cond1) ? true1 : \
61 (val == (cond2) ? true2 : def))
67 struct qed_sb_attn_info;
69 struct qed_sb_sp_info;
78 QED_MODE_L2GENEVE_TUNN,
79 QED_MODE_IPGENEVE_TUNN,
86 QED_TUNN_CLSS_MAC_VLAN,
87 QED_TUNN_CLSS_MAC_VNI,
88 QED_TUNN_CLSS_INNER_MAC_VLAN,
89 QED_TUNN_CLSS_INNER_MAC_VNI,
93 struct qed_tunn_start_params {
94 unsigned long tunn_mode;
97 u8 update_vxlan_udp_port;
98 u8 update_geneve_udp_port;
100 u8 tunn_clss_l2geneve;
101 u8 tunn_clss_ipgeneve;
106 struct qed_tunn_update_params {
107 unsigned long tunn_mode_update_mask;
108 unsigned long tunn_mode;
111 u8 update_rx_pf_clss;
112 u8 update_tx_pf_clss;
113 u8 update_vxlan_udp_port;
114 u8 update_geneve_udp_port;
116 u8 tunn_clss_l2geneve;
117 u8 tunn_clss_ipgeneve;
122 /* The PCI personality is not quite synonymous to protocol ID:
123 * 1. All personalities need CORE connections
124 * 2. The Ethernet personality may support also the RoCE protocol
126 enum qed_pci_personality {
128 QED_PCI_DEFAULT /* default in shmem */
131 /* All VFs are symmetric, all counters are PF + all VFs */
157 QED_PORT_MODE_DE_2X40G,
158 QED_PORT_MODE_DE_2X50G,
159 QED_PORT_MODE_DE_1X100G,
160 QED_PORT_MODE_DE_4X10G_F,
161 QED_PORT_MODE_DE_4X10G_E,
162 QED_PORT_MODE_DE_4X20G,
163 QED_PORT_MODE_DE_1X40G,
164 QED_PORT_MODE_DE_2X25G,
165 QED_PORT_MODE_DE_1X25G
173 /* PCI personality */
174 enum qed_pci_personality personality;
176 /* Resource Allocation scheme results */
177 u32 resc_start[QED_MAX_RESC];
178 u32 resc_num[QED_MAX_RESC];
179 u32 feat_num[QED_MAX_FEATURES];
181 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
182 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
183 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
194 unsigned char hw_mac_addr[ETH_ALEN];
196 struct qed_igu_info *p_igu_info;
200 unsigned long device_capabilities;
203 struct qed_hw_cid_data {
205 bool b_cid_allocated;
207 /* Additional identifiers */
212 /* maximun size of read/write commands (HW limit) */
213 #define DMAE_MAX_RW_SIZE 0x2000
215 struct qed_dmae_info {
216 /* Mutex for synchronizing access to functions */
221 dma_addr_t completion_word_phys_addr;
223 /* The memory location where the DMAE writes the completion
224 * value when an operation is finished on this context.
226 u32 *p_completion_word;
228 dma_addr_t intermediate_buffer_phys_addr;
230 /* An intermediate buffer for DMAE operations that use virtual
231 * addresses - data is DMA'd to/from this buffer and then
232 * memcpy'd to/from the virtual address
234 u32 *p_intermediate_buffer;
236 dma_addr_t dmae_cmd_phys_addr;
237 struct dmae_cmd *p_dmae_cmd;
241 struct init_qm_pq_params *qm_pq_params;
242 struct init_qm_vport_params *qm_vport_params;
243 struct init_qm_port_params *qm_port_params;
253 u8 max_phys_tcs_per_port;
267 struct qed_storm_stats {
268 struct storm_stats mstats;
269 struct storm_stats pstats;
270 struct storm_stats tstats;
271 struct storm_stats ustats;
275 struct fw_ver_info *fw_ver_info;
276 const u8 *modes_tree_buf;
277 union init_op *init_ops;
282 struct qed_simd_fp_handler {
284 void (*func)(void *);
288 struct qed_dev *cdev;
289 u8 my_id; /* ID inside the PF */
290 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
291 u8 rel_pf_id; /* Relative to engine*/
293 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
299 char name[NAME_SIZE];
301 bool first_on_engine;
305 void __iomem *regview;
306 void __iomem *doorbells;
308 unsigned long db_size;
311 struct qed_ptt_pool *p_ptt_pool;
314 struct qed_hw_info hw_info;
316 /* rt_array (for init-tool) */
317 struct qed_rt_data rt_data;
320 struct qed_spq *p_spq;
326 struct qed_consq *p_consq;
328 /* Slow-Path definitions */
329 struct tasklet_struct *sp_dpc;
330 bool b_sp_dpc_enabled;
332 struct qed_ptt *p_main_ptt;
333 struct qed_ptt *p_dpc_ptt;
335 struct qed_sb_sp_info *p_sp_sb;
336 struct qed_sb_attn_info *p_sb_attn;
338 /* Protocol related */
339 struct qed_pf_params pf_params;
341 /* Array of sb_info of all status blocks */
342 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
345 struct qed_cxt_mngr *p_cxt_mngr;
347 /* Flag indicating whether interrupts are enabled or not*/
349 bool b_int_requested;
351 /* True if the driver requests for the link */
352 bool b_drv_link_init;
354 struct qed_mcp_info *mcp_info;
356 struct qed_hw_cid_data *p_tx_cids;
357 struct qed_hw_cid_data *p_rx_cids;
359 struct qed_dmae_info dmae_info;
362 struct qed_qm_info qm_info;
363 struct qed_storm_stats storm_stats;
365 /* Buffer for unzipping firmware data */
368 struct qed_simd_fp_handler simd_proto_handler[64];
370 struct z_stream_s *stream;
376 unsigned long mem_start;
377 unsigned long mem_end;
382 struct qed_int_param {
385 u8 min_msix_cnt; /* for minimal functionality */
388 struct qed_int_params {
389 struct qed_int_param in;
390 struct qed_int_param out;
391 struct msix_entry *msix_table;
400 char name[NAME_SIZE];
403 #define QED_DEV_TYPE_BB (0 << 0)
404 #define QED_DEV_TYPE_AH BIT(0)
405 /* Translate type/revision combo into the proper conditions */
406 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
407 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
409 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
412 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
413 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
419 #define CHIP_NUM_MASK 0xffff
420 #define CHIP_NUM_SHIFT 16
423 #define CHIP_REV_MASK 0xf
424 #define CHIP_REV_SHIFT 12
425 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
426 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
429 #define CHIP_METAL_MASK 0xff
430 #define CHIP_METAL_SHIFT 4
433 #define CHIP_BOND_ID_MASK 0xf
434 #define CHIP_BOND_ID_SHIFT 0
437 u8 num_ports_in_engines;
438 u8 num_funcs_in_port;
441 enum qed_mf_mode mf_mode;
442 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
443 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
444 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
448 u8 ver_str[VER_SIZE];
450 /* Add MF related configuration */
457 enum qed_coalescing_mode int_coalescing_mode;
458 u8 rx_coalesce_usecs;
459 u8 tx_coalesce_usecs;
461 /* Start Bar offset of first hwfn */
462 void __iomem *regview;
463 void __iomem *doorbells;
465 unsigned long db_size;
471 const struct iro *iro_arr;
472 #define IRO (p_hwfn->cdev->iro_arr)
476 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
478 unsigned long tunn_mode;
481 struct qed_eth_stats *reset_stats;
482 struct qed_fw_data *fw_data;
486 /* Linux specific here */
487 struct qede_dev *edev;
488 struct pci_dev *pdev;
491 struct pci_params pci_params;
493 struct qed_int_params int_params;
496 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
498 /* Callbacks to protocol driver */
500 struct qed_common_cb_ops *common;
501 struct qed_eth_cb_ops *eth;
505 const struct firmware *firmware;
508 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
509 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
512 * @brief qed_concrete_to_sw_fid - get the sw function id from
513 * the concrete value.
515 * @param concrete_fid
519 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
522 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
529 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
531 /* Other Linux specific common definitions */
532 #define DP_NAME(cdev) ((cdev)->name)
534 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
538 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
539 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
540 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
542 #define DOORBELL(cdev, db_addr, val) \
543 writel((u32)val, (void __iomem *)((u8 __iomem *)\
544 (cdev->doorbells) + (db_addr)))
547 int qed_fill_dev_info(struct qed_dev *cdev,
548 struct qed_dev_info *dev_info);
549 void qed_link_update(struct qed_hwfn *hwfn);
550 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
551 u32 input_len, u8 *input_buf,
552 u32 max_size, u8 *unzip_buf);
554 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);