1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/mutex.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/workqueue.h>
23 #include <linux/zlib.h>
24 #include <linux/hashtable.h>
25 #include <linux/qed/qed_if.h>
28 extern const struct qed_common_ops qed_common_ops_pass;
29 #define DRV_MODULE_VERSION "8.7.0.0"
31 #define MAX_HWFNS_PER_DEVICE (4)
36 enum qed_coalescing_mode {
37 QED_COAL_MODE_DISABLE,
41 struct qed_eth_cb_ops;
45 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
47 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
48 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
53 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
54 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
55 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
57 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
59 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
60 (val == (cond1) ? true1 : \
61 (val == (cond2) ? true2 : def))
67 struct qed_sb_attn_info;
69 struct qed_sb_sp_info;
77 /* The PCI personality is not quite synonymous to protocol ID:
78 * 1. All personalities need CORE connections
79 * 2. The Ethernet personality may support also the RoCE protocol
81 enum qed_pci_personality {
83 QED_PCI_DEFAULT /* default in shmem */
86 /* All VFs are symmetric, all counters are PF + all VFs */
112 QED_PORT_MODE_DE_2X40G,
113 QED_PORT_MODE_DE_2X50G,
114 QED_PORT_MODE_DE_1X100G,
115 QED_PORT_MODE_DE_4X10G_F,
116 QED_PORT_MODE_DE_4X10G_E,
117 QED_PORT_MODE_DE_4X20G,
118 QED_PORT_MODE_DE_1X40G,
119 QED_PORT_MODE_DE_2X25G,
120 QED_PORT_MODE_DE_1X25G
128 /* PCI personality */
129 enum qed_pci_personality personality;
131 /* Resource Allocation scheme results */
132 u32 resc_start[QED_MAX_RESC];
133 u32 resc_num[QED_MAX_RESC];
134 u32 feat_num[QED_MAX_FEATURES];
136 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
137 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
138 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
149 unsigned char hw_mac_addr[ETH_ALEN];
151 struct qed_igu_info *p_igu_info;
155 unsigned long device_capabilities;
158 struct qed_hw_cid_data {
160 bool b_cid_allocated;
162 /* Additional identifiers */
167 /* maximun size of read/write commands (HW limit) */
168 #define DMAE_MAX_RW_SIZE 0x2000
170 struct qed_dmae_info {
171 /* Mutex for synchronizing access to functions */
176 dma_addr_t completion_word_phys_addr;
178 /* The memory location where the DMAE writes the completion
179 * value when an operation is finished on this context.
181 u32 *p_completion_word;
183 dma_addr_t intermediate_buffer_phys_addr;
185 /* An intermediate buffer for DMAE operations that use virtual
186 * addresses - data is DMA'd to/from this buffer and then
187 * memcpy'd to/from the virtual address
189 u32 *p_intermediate_buffer;
191 dma_addr_t dmae_cmd_phys_addr;
192 struct dmae_cmd *p_dmae_cmd;
196 struct init_qm_pq_params *qm_pq_params;
197 struct init_qm_vport_params *qm_vport_params;
198 struct init_qm_port_params *qm_port_params;
208 u8 max_phys_tcs_per_port;
222 struct qed_storm_stats {
223 struct storm_stats mstats;
224 struct storm_stats pstats;
225 struct storm_stats tstats;
226 struct storm_stats ustats;
230 struct fw_ver_info *fw_ver_info;
231 const u8 *modes_tree_buf;
232 union init_op *init_ops;
237 struct qed_simd_fp_handler {
239 void (*func)(void *);
243 struct qed_dev *cdev;
244 u8 my_id; /* ID inside the PF */
245 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
246 u8 rel_pf_id; /* Relative to engine*/
248 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
254 char name[NAME_SIZE];
256 bool first_on_engine;
260 void __iomem *regview;
261 void __iomem *doorbells;
263 unsigned long db_size;
266 struct qed_ptt_pool *p_ptt_pool;
269 struct qed_hw_info hw_info;
271 /* rt_array (for init-tool) */
272 struct qed_rt_data rt_data;
275 struct qed_spq *p_spq;
281 struct qed_consq *p_consq;
283 /* Slow-Path definitions */
284 struct tasklet_struct *sp_dpc;
285 bool b_sp_dpc_enabled;
287 struct qed_ptt *p_main_ptt;
288 struct qed_ptt *p_dpc_ptt;
290 struct qed_sb_sp_info *p_sp_sb;
291 struct qed_sb_attn_info *p_sb_attn;
293 /* Protocol related */
294 struct qed_pf_params pf_params;
296 /* Array of sb_info of all status blocks */
297 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
300 struct qed_cxt_mngr *p_cxt_mngr;
302 /* Flag indicating whether interrupts are enabled or not*/
304 bool b_int_requested;
306 /* True if the driver requests for the link */
307 bool b_drv_link_init;
309 struct qed_mcp_info *mcp_info;
311 struct qed_hw_cid_data *p_tx_cids;
312 struct qed_hw_cid_data *p_rx_cids;
314 struct qed_dmae_info dmae_info;
317 struct qed_qm_info qm_info;
318 struct qed_storm_stats storm_stats;
320 /* Buffer for unzipping firmware data */
323 struct qed_simd_fp_handler simd_proto_handler[64];
325 struct z_stream_s *stream;
331 unsigned long mem_start;
332 unsigned long mem_end;
337 struct qed_int_param {
340 u8 min_msix_cnt; /* for minimal functionality */
343 struct qed_int_params {
344 struct qed_int_param in;
345 struct qed_int_param out;
346 struct msix_entry *msix_table;
355 char name[NAME_SIZE];
358 #define QED_DEV_TYPE_BB (0 << 0)
359 #define QED_DEV_TYPE_AH BIT(0)
360 /* Translate type/revision combo into the proper conditions */
361 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
362 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
364 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
367 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
368 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
374 #define CHIP_NUM_MASK 0xffff
375 #define CHIP_NUM_SHIFT 16
378 #define CHIP_REV_MASK 0xf
379 #define CHIP_REV_SHIFT 12
380 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
381 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
384 #define CHIP_METAL_MASK 0xff
385 #define CHIP_METAL_SHIFT 4
388 #define CHIP_BOND_ID_MASK 0xf
389 #define CHIP_BOND_ID_SHIFT 0
392 u8 num_ports_in_engines;
393 u8 num_funcs_in_port;
396 enum qed_mf_mode mf_mode;
397 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
398 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
399 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
403 u8 ver_str[VER_SIZE];
405 /* Add MF related configuration */
412 enum qed_coalescing_mode int_coalescing_mode;
413 u8 rx_coalesce_usecs;
414 u8 tx_coalesce_usecs;
416 /* Start Bar offset of first hwfn */
417 void __iomem *regview;
418 void __iomem *doorbells;
420 unsigned long db_size;
426 const struct iro *iro_arr;
427 #define IRO (p_hwfn->cdev->iro_arr)
431 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
435 struct qed_eth_stats *reset_stats;
436 struct qed_fw_data *fw_data;
440 /* Linux specific here */
441 struct qede_dev *edev;
442 struct pci_dev *pdev;
445 struct pci_params pci_params;
447 struct qed_int_params int_params;
450 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
452 /* Callbacks to protocol driver */
454 struct qed_common_cb_ops *common;
455 struct qed_eth_cb_ops *eth;
459 const struct firmware *firmware;
462 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
463 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
466 * @brief qed_concrete_to_sw_fid - get the sw function id from
467 * the concrete value.
469 * @param concrete_fid
473 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
476 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
483 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
485 /* Other Linux specific common definitions */
486 #define DP_NAME(cdev) ((cdev)->name)
488 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
492 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
493 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
494 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
496 #define DOORBELL(cdev, db_addr, val) \
497 writel((u32)val, (void __iomem *)((u8 __iomem *)\
498 (cdev->doorbells) + (db_addr)))
501 int qed_fill_dev_info(struct qed_dev *cdev,
502 struct qed_dev_info *dev_info);
503 void qed_link_update(struct qed_hwfn *hwfn);
504 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
505 u32 input_len, u8 *input_buf,
506 u32 max_size, u8 *unzip_buf);
508 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
510 #define QED_ETH_INTERFACE_VERSION 300