drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/qed/qed_chain.h>
  23 #include <linux/qed/qed_if.h>
  24 #include "qed.h"
  25 #include "qed_cxt.h"
  26 #include "qed_dcbx.h"
  27 #include "qed_dev_api.h"
  28 #include "qed_hsi.h"
  29 #include "qed_hw.h"
  30 #include "qed_init_ops.h"
  31 #include "qed_int.h"
  32 #include "qed_mcp.h"
  33 #include "qed_reg_addr.h"
  34 #include "qed_sp.h"
  35 #include "qed_sriov.h"
  36 #include "qed_vf.h"
  37
  38 static DEFINE_SPINLOCK(qm_lock);
  39
  40 /* API common to all protocols */
  41 enum BAR_ID {
  42         BAR_ID_0,       /* used for GRC */
  43         BAR_ID_1        /* Used for doorbells */
  44 };
  45
  46 static u32 qed_hw_bar_size(struct qed_hwfn      *p_hwfn,
  47                            enum BAR_ID          bar_id)
  48 {
  49         u32 bar_reg = (bar_id == BAR_ID_0 ?
  50                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  51         u32 val;
  52
  53         if (IS_VF(p_hwfn->cdev))
  54                 return 1 << 17;
  55
  56         val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  57         if (val)
  58                 return 1 << (val + 15);
  59
  60         /* Old MFW initialized above registered only conditionally */
  61         if (p_hwfn->cdev->num_hwfns > 1) {
  62                 DP_INFO(p_hwfn,
  63                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  64                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  65         } else {
  66                 DP_INFO(p_hwfn,
  67                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  68                         return 512 * 1024;
  69         }
  70 }
  71
  72 void qed_init_dp(struct qed_dev *cdev,
  73                  u32 dp_module, u8 dp_level)
  74 {
  75         u32 i;
  76
  77         cdev->dp_level = dp_level;
  78         cdev->dp_module = dp_module;
  79         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  80                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  81
  82                 p_hwfn->dp_level = dp_level;
  83                 p_hwfn->dp_module = dp_module;
  84         }
  85 }
  86
  87 void qed_init_struct(struct qed_dev *cdev)
  88 {
  89         u8 i;
  90
  91         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  92                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  93
  94                 p_hwfn->cdev = cdev;
  95                 p_hwfn->my_id = i;
  96                 p_hwfn->b_active = false;
  97
  98                 mutex_init(&p_hwfn->dmae_info.mutex);
  99         }
 100
 101         /* hwfn 0 is always active */
 102         cdev->hwfns[0].b_active = true;
 103
 104         /* set the default cache alignment to 128 */
 105         cdev->cache_shift = 7;
 106 }
 107
 108 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 109 {
 110         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 111
 112         kfree(qm_info->qm_pq_params);
 113         qm_info->qm_pq_params = NULL;
 114         kfree(qm_info->qm_vport_params);
 115         qm_info->qm_vport_params = NULL;
 116         kfree(qm_info->qm_port_params);
 117         qm_info->qm_port_params = NULL;
 118         kfree(qm_info->wfq_data);
 119         qm_info->wfq_data = NULL;
 120 }
 121
 122 void qed_resc_free(struct qed_dev *cdev)
 123 {
 124         int i;
 125
 126         if (IS_VF(cdev))
 127                 return;
 128
 129         kfree(cdev->fw_data);
 130         cdev->fw_data = NULL;
 131
 132         kfree(cdev->reset_stats);
 133
 134         for_each_hwfn(cdev, i) {
 135                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 136
 137                 kfree(p_hwfn->p_tx_cids);
 138                 p_hwfn->p_tx_cids = NULL;
 139                 kfree(p_hwfn->p_rx_cids);
 140                 p_hwfn->p_rx_cids = NULL;
 141         }
 142
 143         for_each_hwfn(cdev, i) {
 144                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 145
 146                 qed_cxt_mngr_free(p_hwfn);
 147                 qed_qm_info_free(p_hwfn);
 148                 qed_spq_free(p_hwfn);
 149                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 150                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 151                 qed_int_free(p_hwfn);
 152                 qed_iov_free(p_hwfn);
 153                 qed_dmae_info_free(p_hwfn);
 154                 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 155         }
 156 }
 157
 158 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
 159 {
 160         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
 161         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 162         struct init_qm_port_params *p_qm_port;
 163         bool init_rdma_offload_pq = false;
 164         bool init_pure_ack_pq = false;
 165         bool init_ooo_pq = false;
 166         u16 num_pqs, multi_cos_tcs = 1;
 167         u8 pf_wfq = qm_info->pf_wfq;
 168         u32 pf_rl = qm_info->pf_rl;
 169         u16 num_pf_rls = 0;
 170         u16 num_vfs = 0;
 171
 172 #ifdef CONFIG_QED_SRIOV
 173         if (p_hwfn->cdev->p_iov_info)
 174                 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
 175 #endif
 176         memset(qm_info, 0, sizeof(*qm_info));
 177
 178         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 179         num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
 180
 181         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 182                 num_pqs++;      /* for RoCE queue */
 183                 init_rdma_offload_pq = true;
 184                 /* we subtract num_vfs because each require a rate limiter,
 185                  * and one default rate limiter
 186                  */
 187                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
 188                         num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
 189
 190                 num_pqs += num_pf_rls;
 191                 qm_info->num_pf_rls = (u8) num_pf_rls;
 192         }
 193
 194         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 195                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 196                 init_pure_ack_pq = true;
 197                 init_ooo_pq = true;
 198         }
 199
 200         /* Sanity checking that setup requires legal number of resources */
 201         if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
 202                 DP_ERR(p_hwfn,
 203                        "Need too many Physical queues - 0x%04x when only %04x are available\n",
 204                        num_pqs, RESC_NUM(p_hwfn, QED_PQ));
 205                 return -EINVAL;
 206         }
 207
 208         /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
 209          */
 210         qm_info->qm_pq_params = kcalloc(num_pqs,
 211                                         sizeof(struct init_qm_pq_params),
 212                                         b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 213         if (!qm_info->qm_pq_params)
 214                 goto alloc_err;
 215
 216         qm_info->qm_vport_params = kcalloc(num_vports,
 217                                            sizeof(struct init_qm_vport_params),
 218                                            b_sleepable ? GFP_KERNEL
 219                                                        : GFP_ATOMIC);
 220         if (!qm_info->qm_vport_params)
 221                 goto alloc_err;
 222
 223         qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
 224                                           sizeof(struct init_qm_port_params),
 225                                           b_sleepable ? GFP_KERNEL
 226                                                       : GFP_ATOMIC);
 227         if (!qm_info->qm_port_params)
 228                 goto alloc_err;
 229
 230         qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
 231                                     b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 232         if (!qm_info->wfq_data)
 233                 goto alloc_err;
 234
 235         vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
 236
 237         /* First init rate limited queues */
 238         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 239                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 240                 qm_info->qm_pq_params[curr_queue].tc_id =
 241                     p_hwfn->hw_info.non_offload_tc;
 242                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 243                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 244         }
 245
 246         /* First init per-TC PQs */
 247         for (i = 0; i < multi_cos_tcs; i++) {
 248                 struct init_qm_pq_params *params =
 249                     &qm_info->qm_pq_params[curr_queue++];
 250
 251                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
 252                     p_hwfn->hw_info.personality == QED_PCI_ETH) {
 253                         params->vport_id = vport_id;
 254                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 255                         params->wrr_group = 1;
 256                 } else {
 257                         params->vport_id = vport_id;
 258                         params->tc_id = p_hwfn->hw_info.offload_tc;
 259                         params->wrr_group = 1;
 260                 }
 261         }
 262
 263         /* Then init pure-LB PQ */
 264         qm_info->pure_lb_pq = curr_queue;
 265         qm_info->qm_pq_params[curr_queue].vport_id =
 266             (u8) RESC_START(p_hwfn, QED_VPORT);
 267         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 268         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 269         curr_queue++;
 270
 271         qm_info->offload_pq = 0;
 272         if (init_rdma_offload_pq) {
 273                 qm_info->offload_pq = curr_queue;
 274                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 275                 qm_info->qm_pq_params[curr_queue].tc_id =
 276                     p_hwfn->hw_info.offload_tc;
 277                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 278                 curr_queue++;
 279         }
 280
 281         if (init_pure_ack_pq) {
 282                 qm_info->pure_ack_pq = curr_queue;
 283                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 284                 qm_info->qm_pq_params[curr_queue].tc_id =
 285                     p_hwfn->hw_info.offload_tc;
 286                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 287                 curr_queue++;
 288         }
 289
 290         if (init_ooo_pq) {
 291                 qm_info->ooo_pq = curr_queue;
 292                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 293                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 294                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 295                 curr_queue++;
 296         }
 297
 298         /* Then init per-VF PQs */
 299         vf_offset = curr_queue;
 300         for (i = 0; i < num_vfs; i++) {
 301                 /* First vport is used by the PF */
 302                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 303                 qm_info->qm_pq_params[curr_queue].tc_id =
 304                     p_hwfn->hw_info.non_offload_tc;
 305                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 306                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 307                 curr_queue++;
 308         }
 309
 310         qm_info->vf_queues_offset = vf_offset;
 311         qm_info->num_pqs = num_pqs;
 312         qm_info->num_vports = num_vports;
 313
 314         /* Initialize qm port parameters */
 315         num_ports = p_hwfn->cdev->num_ports_in_engines;
 316         for (i = 0; i < num_ports; i++) {
 317                 p_qm_port = &qm_info->qm_port_params[i];
 318                 p_qm_port->active = 1;
 319                 if (num_ports == 4)
 320                         p_qm_port->active_phys_tcs = 0x7;
 321                 else
 322                         p_qm_port->active_phys_tcs = 0x9f;
 323                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 324                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 325         }
 326
 327         qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 328
 329         qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
 330
 331         qm_info->num_vf_pqs = num_vfs;
 332         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 333
 334         for (i = 0; i < qm_info->num_vports; i++)
 335                 qm_info->qm_vport_params[i].vport_wfq = 1;
 336
 337         qm_info->vport_rl_en = 1;
 338         qm_info->vport_wfq_en = 1;
 339         qm_info->pf_rl = pf_rl;
 340         qm_info->pf_wfq = pf_wfq;
 341
 342         return 0;
 343
 344 alloc_err:
 345         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 346         qed_qm_info_free(p_hwfn);
 347         return -ENOMEM;
 348 }
 349
 350 /* This function reconfigures the QM pf on the fly.
 351  * For this purpose we:
 352  * 1. reconfigure the QM database
 353  * 2. set new values to runtime arrat
 354  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 355  * 4. activate init tool in QM_PF stage
 356  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 357  */
 358 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 359 {
 360         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 361         bool b_rc;
 362         int rc;
 363
 364         /* qm_info is allocated in qed_init_qm_info() which is already called
 365          * from qed_resc_alloc() or previous call of qed_qm_reconf().
 366          * The allocated size may change each init, so we free it before next
 367          * allocation.
 368          */
 369         qed_qm_info_free(p_hwfn);
 370
 371         /* initialize qed's qm data structure */
 372         rc = qed_init_qm_info(p_hwfn, false);
 373         if (rc)
 374                 return rc;
 375
 376         /* stop PF's qm queues */
 377         spin_lock_bh(&qm_lock);
 378         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 379                                     qm_info->start_pq, qm_info->num_pqs);
 380         spin_unlock_bh(&qm_lock);
 381         if (!b_rc)
 382                 return -EINVAL;
 383
 384         /* clear the QM_PF runtime phase leftovers from previous init */
 385         qed_init_clear_rt_data(p_hwfn);
 386
 387         /* prepare QM portion of runtime array */
 388         qed_qm_init_pf(p_hwfn);
 389
 390         /* activate init tool on runtime array */
 391         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 392                           p_hwfn->hw_info.hw_mode);
 393         if (rc)
 394                 return rc;
 395
 396         /* start PF's qm queues */
 397         spin_lock_bh(&qm_lock);
 398         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 399                                     qm_info->start_pq, qm_info->num_pqs);
 400         spin_unlock_bh(&qm_lock);
 401         if (!b_rc)
 402                 return -EINVAL;
 403
 404         return 0;
 405 }
 406
 407 int qed_resc_alloc(struct qed_dev *cdev)
 408 {
 409         struct qed_consq *p_consq;
 410         struct qed_eq *p_eq;
 411         int i, rc = 0;
 412
 413         if (IS_VF(cdev))
 414                 return rc;
 415
 416         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 417         if (!cdev->fw_data)
 418                 return -ENOMEM;
 419
 420         /* Allocate Memory for the Queue->CID mapping */
 421         for_each_hwfn(cdev, i) {
 422                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 423                 int tx_size = sizeof(struct qed_hw_cid_data) *
 424                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 425                 int rx_size = sizeof(struct qed_hw_cid_data) *
 426                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 427
 428                 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
 429                 if (!p_hwfn->p_tx_cids) {
 430                         DP_NOTICE(p_hwfn,
 431                                   "Failed to allocate memory for Tx Cids\n");
 432                         goto alloc_no_mem;
 433                 }
 434
 435                 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
 436                 if (!p_hwfn->p_rx_cids) {
 437                         DP_NOTICE(p_hwfn,
 438                                   "Failed to allocate memory for Rx Cids\n");
 439                         goto alloc_no_mem;
 440                 }
 441         }
 442
 443         for_each_hwfn(cdev, i) {
 444                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 445                 u32 n_eqes, num_cons;
 446
 447                 /* First allocate the context manager structure */
 448                 rc = qed_cxt_mngr_alloc(p_hwfn);
 449                 if (rc)
 450                         goto alloc_err;
 451
 452                 /* Set the HW cid/tid numbers (in the contest manager)
 453                  * Must be done prior to any further computations.
 454                  */
 455                 rc = qed_cxt_set_pf_params(p_hwfn);
 456                 if (rc)
 457                         goto alloc_err;
 458
 459                 /* Prepare and process QM requirements */
 460                 rc = qed_init_qm_info(p_hwfn, true);
 461                 if (rc)
 462                         goto alloc_err;
 463
 464                 /* Compute the ILT client partition */
 465                 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
 466                 if (rc)
 467                         goto alloc_err;
 468
 469                 /* CID map / ILT shadow table / T2
 470                  * The talbes sizes are determined by the computations above
 471                  */
 472                 rc = qed_cxt_tables_alloc(p_hwfn);
 473                 if (rc)
 474                         goto alloc_err;
 475
 476                 /* SPQ, must follow ILT because initializes SPQ context */
 477                 rc = qed_spq_alloc(p_hwfn);
 478                 if (rc)
 479                         goto alloc_err;
 480
 481                 /* SP status block allocation */
 482                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 483                                                          RESERVED_PTT_DPC);
 484
 485                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 486                 if (rc)
 487                         goto alloc_err;
 488
 489                 rc = qed_iov_alloc(p_hwfn);
 490                 if (rc)
 491                         goto alloc_err;
 492
 493                 /* EQ */
 494                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 495                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 496                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 497                                                                PROTOCOLID_ROCE,
 498                                                                0) * 2;
 499                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 500                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 501                         num_cons =
 502                             qed_cxt_get_proto_cid_count(p_hwfn,
 503                                                         PROTOCOLID_ISCSI, 0);
 504                         n_eqes += 2 * num_cons;
 505                 }
 506
 507                 if (n_eqes > 0xFFFF) {
 508                         DP_ERR(p_hwfn,
 509                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 510                                n_eqes, 0xFFFF);
 511                         rc = -EINVAL;
 512                         goto alloc_err;
 513                 }
 514
 515                 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 516                 if (!p_eq)
 517                         goto alloc_no_mem;
 518                 p_hwfn->p_eq = p_eq;
 519
 520                 p_consq = qed_consq_alloc(p_hwfn);
 521                 if (!p_consq)
 522                         goto alloc_no_mem;
 523                 p_hwfn->p_consq = p_consq;
 524
 525                 /* DMA info initialization */
 526                 rc = qed_dmae_info_alloc(p_hwfn);
 527                 if (rc) {
 528                         DP_NOTICE(p_hwfn,
 529                                   "Failed to allocate memory for dmae_info structure\n");
 530                         goto alloc_err;
 531                 }
 532
 533                 /* DCBX initialization */
 534                 rc = qed_dcbx_info_alloc(p_hwfn);
 535                 if (rc) {
 536                         DP_NOTICE(p_hwfn,
 537                                   "Failed to allocate memory for dcbx structure\n");
 538                         goto alloc_err;
 539                 }
 540         }
 541
 542         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 543         if (!cdev->reset_stats) {
 544                 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
 545                 rc = -ENOMEM;
 546                 goto alloc_err;
 547         }
 548
 549         return 0;
 550
 551 alloc_no_mem:
 552         rc = -ENOMEM;
 553 alloc_err:
 554         qed_resc_free(cdev);
 555         return rc;
 556 }
 557
 558 void qed_resc_setup(struct qed_dev *cdev)
 559 {
 560         int i;
 561
 562         if (IS_VF(cdev))
 563                 return;
 564
 565         for_each_hwfn(cdev, i) {
 566                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 567
 568                 qed_cxt_mngr_setup(p_hwfn);
 569                 qed_spq_setup(p_hwfn);
 570                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
 571                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
 572
 573                 /* Read shadow of current MFW mailbox */
 574                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 575                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 576                        p_hwfn->mcp_info->mfw_mb_cur,
 577                        p_hwfn->mcp_info->mfw_mb_length);
 578
 579                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 580
 581                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 582         }
 583 }
 584
 585 #define FINAL_CLEANUP_POLL_CNT          (100)
 586 #define FINAL_CLEANUP_POLL_TIME         (10)
 587 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
 588                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
 589 {
 590         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 591         int rc = -EBUSY;
 592
 593         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 594                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 595
 596         if (is_vf)
 597                 id += 0x10;
 598
 599         command |= X_FINAL_CLEANUP_AGG_INT <<
 600                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 601         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 602         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 603         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 604
 605         /* Make sure notification is not set before initiating final cleanup */
 606         if (REG_RD(p_hwfn, addr)) {
 607                 DP_NOTICE(
 608                         p_hwfn,
 609                         "Unexpected; Found final cleanup notification before initiating final cleanup\n");
 610                 REG_WR(p_hwfn, addr, 0);
 611         }
 612
 613         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
 614                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 615                    id, command);
 616
 617         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 618
 619         /* Poll until completion */
 620         while (!REG_RD(p_hwfn, addr) && count--)
 621                 msleep(FINAL_CLEANUP_POLL_TIME);
 622
 623         if (REG_RD(p_hwfn, addr))
 624                 rc = 0;
 625         else
 626                 DP_NOTICE(p_hwfn,
 627                           "Failed to receive FW final cleanup notification\n");
 628
 629         /* Cleanup afterwards */
 630         REG_WR(p_hwfn, addr, 0);
 631
 632         return rc;
 633 }
 634
 635 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
 636 {
 637         int hw_mode = 0;
 638
 639         hw_mode = (1 << MODE_BB_B0);
 640
 641         switch (p_hwfn->cdev->num_ports_in_engines) {
 642         case 1:
 643                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 644                 break;
 645         case 2:
 646                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 647                 break;
 648         case 4:
 649                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 650                 break;
 651         default:
 652                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
 653                           p_hwfn->cdev->num_ports_in_engines);
 654                 return;
 655         }
 656
 657         switch (p_hwfn->cdev->mf_mode) {
 658         case QED_MF_DEFAULT:
 659         case QED_MF_NPAR:
 660                 hw_mode |= 1 << MODE_MF_SI;
 661                 break;
 662         case QED_MF_OVLAN:
 663                 hw_mode |= 1 << MODE_MF_SD;
 664                 break;
 665         default:
 666                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 667                 hw_mode |= 1 << MODE_MF_SI;
 668         }
 669
 670         hw_mode |= 1 << MODE_ASIC;
 671
 672         if (p_hwfn->cdev->num_hwfns > 1)
 673                 hw_mode |= 1 << MODE_100G;
 674
 675         p_hwfn->hw_info.hw_mode = hw_mode;
 676
 677         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
 678                    "Configuring function for hw_mode: 0x%08x\n",
 679                    p_hwfn->hw_info.hw_mode);
 680 }
 681
 682 /* Init run time data for all PFs on an engine. */
 683 static void qed_init_cau_rt_data(struct qed_dev *cdev)
 684 {
 685         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 686         int i, sb_id;
 687
 688         for_each_hwfn(cdev, i) {
 689                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 690                 struct qed_igu_info *p_igu_info;
 691                 struct qed_igu_block *p_block;
 692                 struct cau_sb_entry sb_entry;
 693
 694                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 695
 696                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
 697                      sb_id++) {
 698                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 699                         if (!p_block->is_pf)
 700                                 continue;
 701
 702                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
 703                                               p_block->function_id,
 704                                               0, 0);
 705                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
 706                                          sb_entry);
 707                 }
 708         }
 709 }
 710
 711 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
 712                               struct qed_ptt *p_ptt,
 713                               int hw_mode)
 714 {
 715         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 716         struct qed_qm_common_rt_init_params params;
 717         struct qed_dev *cdev = p_hwfn->cdev;
 718         u16 num_pfs, pf_id;
 719         u32 concrete_fid;
 720         int rc = 0;
 721         u8 vf_id;
 722
 723         qed_init_cau_rt_data(cdev);
 724
 725         /* Program GTT windows */
 726         qed_gtt_init(p_hwfn);
 727
 728         if (p_hwfn->mcp_info) {
 729                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 730                         qm_info->pf_rl_en = 1;
 731                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 732                         qm_info->pf_wfq_en = 1;
 733         }
 734
 735         memset(&params, 0, sizeof(params));
 736         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
 737         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
 738         params.pf_rl_en = qm_info->pf_rl_en;
 739         params.pf_wfq_en = qm_info->pf_wfq_en;
 740         params.vport_rl_en = qm_info->vport_rl_en;
 741         params.vport_wfq_en = qm_info->vport_wfq_en;
 742         params.port_params = qm_info->qm_port_params;
 743
 744         qed_qm_common_rt_init(p_hwfn, &params);
 745
 746         qed_cxt_hw_init_common(p_hwfn);
 747
 748         /* Close gate from NIG to BRB/Storm; By default they are open, but
 749          * we close them to prevent NIG from passing data to reset blocks.
 750          * Should have been done in the ENGINE phase, but init-tool lacks
 751          * proper port-pretend capabilities.
 752          */
 753         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 754         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 755         qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 756         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 757         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 758         qed_port_unpretend(p_hwfn, p_ptt);
 759
 760         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 761         if (rc != 0)
 762                 return rc;
 763
 764         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 765         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 766
 767         if (QED_IS_BB(p_hwfn->cdev)) {
 768                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
 769                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
 770                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
 771                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 772                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 773                 }
 774                 /* pretend to original PF */
 775                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 776         }
 777
 778         for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
 779                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
 780                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
 781                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 782         }
 783         /* pretend to original PF */
 784         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 785
 786         return rc;
 787 }
 788
 789 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
 790                             struct qed_ptt *p_ptt,
 791                             int hw_mode)
 792 {
 793         int rc = 0;
 794
 795         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
 796         if (rc != 0)
 797                 return rc;
 798
 799         if (hw_mode & (1 << MODE_MF_SI)) {
 800                 u8 pf_id = 0;
 801
 802                 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
 803                         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
 804                                    "PF[%08x] is first eth on engine\n", pf_id);
 805
 806                         /* We should have configured BIT for ppfid, i.e., the
 807                          * relative function number in the port. But there's a
 808                          * bug in LLH in BB where the ppfid is actually engine
 809                          * based, so we need to take this into account.
 810                          */
 811                         qed_wr(p_hwfn, p_ptt,
 812                                NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
 813                 }
 814
 815                 /* Take the protocol-based hit vector if there is a hit,
 816                  * otherwise take the other vector.
 817                  */
 818                 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2);
 819         }
 820         return rc;
 821 }
 822
 823 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 824                           struct qed_ptt *p_ptt,
 825                           struct qed_tunn_start_params *p_tunn,
 826                           int hw_mode,
 827                           bool b_hw_start,
 828                           enum qed_int_mode int_mode,
 829                           bool allow_npar_tx_switch)
 830 {
 831         u8 rel_pf_id = p_hwfn->rel_pf_id;
 832         int rc = 0;
 833
 834         if (p_hwfn->mcp_info) {
 835                 struct qed_mcp_function_info *p_info;
 836
 837                 p_info = &p_hwfn->mcp_info->func_info;
 838                 if (p_info->bandwidth_min)
 839                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
 840
 841                 /* Update rate limit once we'll actually have a link */
 842                 p_hwfn->qm_info.pf_rl = 100000;
 843         }
 844
 845         qed_cxt_hw_init_pf(p_hwfn);
 846
 847         qed_int_igu_init_rt(p_hwfn);
 848
 849         /* Set VLAN in NIG if needed */
 850         if (hw_mode & (1 << MODE_MF_SD)) {
 851                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
 852                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
 853                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
 854                              p_hwfn->hw_info.ovlan);
 855         }
 856
 857         /* Enable classification by MAC if needed */
 858         if (hw_mode & (1 << MODE_MF_SI)) {
 859                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 860                            "Configuring TAGMAC_CLS_TYPE\n");
 861                 STORE_RT_REG(p_hwfn,
 862                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
 863         }
 864
 865         /* Protocl Configuration  */
 866         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
 867                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
 868         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
 869         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
 870
 871         /* Cleanup chip from previous driver if such remains exist */
 872         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
 873         if (rc != 0)
 874                 return rc;
 875
 876         /* PF Init sequence */
 877         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
 878         if (rc)
 879                 return rc;
 880
 881         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
 882         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
 883         if (rc)
 884                 return rc;
 885
 886         /* Pure runtime initializations - directly to the HW  */
 887         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
 888
 889         if (hw_mode & (1 << MODE_MF_SI)) {
 890                 u8 pf_id = 0;
 891                 u32 val = 0;
 892
 893                 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
 894                         if (p_hwfn->rel_pf_id == pf_id) {
 895                                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
 896                                            "PF[%d] is first ETH on engine\n",
 897                                            pf_id);
 898                                 val = 1;
 899                         }
 900                         qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
 901                 }
 902         }
 903
 904         if (b_hw_start) {
 905                 /* enable interrupts */
 906                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
 907
 908                 /* send function start command */
 909                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
 910                                      allow_npar_tx_switch);
 911                 if (rc)
 912                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
 913         }
 914         return rc;
 915 }
 916
 917 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
 918                                struct qed_ptt *p_ptt,
 919                                u8 enable)
 920 {
 921         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
 922
 923         /* Change PF in PXP */
 924         qed_wr(p_hwfn, p_ptt,
 925                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
 926
 927         /* wait until value is set - try for 1 second every 50us */
 928         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
 929                 val = qed_rd(p_hwfn, p_ptt,
 930                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
 931                 if (val == set_val)
 932                         break;
 933
 934                 usleep_range(50, 60);
 935         }
 936
 937         if (val != set_val) {
 938                 DP_NOTICE(p_hwfn,
 939                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
 940                 return -EAGAIN;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
 947                                 struct qed_ptt *p_main_ptt)
 948 {
 949         /* Read shadow of current MFW mailbox */
 950         qed_mcp_read_mb(p_hwfn, p_main_ptt);
 951         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 952                p_hwfn->mcp_info->mfw_mb_cur,
 953                p_hwfn->mcp_info->mfw_mb_length);
 954 }
 955
 956 int qed_hw_init(struct qed_dev *cdev,
 957                 struct qed_tunn_start_params *p_tunn,
 958                 bool b_hw_start,
 959                 enum qed_int_mode int_mode,
 960                 bool allow_npar_tx_switch,
 961                 const u8 *bin_fw_data)
 962 {
 963         u32 load_code, param;
 964         int rc, mfw_rc, i;
 965
 966         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 967                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 968                 return -EINVAL;
 969         }
 970
 971         if (IS_PF(cdev)) {
 972                 rc = qed_init_fw_data(cdev, bin_fw_data);
 973                 if (rc != 0)
 974                         return rc;
 975         }
 976
 977         for_each_hwfn(cdev, i) {
 978                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 979
 980                 if (IS_VF(cdev)) {
 981                         p_hwfn->b_int_enabled = 1;
 982                         continue;
 983                 }
 984
 985                 /* Enable DMAE in PXP */
 986                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
 987
 988                 qed_calc_hw_mode(p_hwfn);
 989
 990                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
 991                                       &load_code);
 992                 if (rc) {
 993                         DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
 994                         return rc;
 995                 }
 996
 997                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
 998
 999                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1000                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1001                            rc, load_code);
1002
1003                 p_hwfn->first_on_engine = (load_code ==
1004                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1005
1006                 switch (load_code) {
1007                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1008                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1009                                                 p_hwfn->hw_info.hw_mode);
1010                         if (rc)
1011                                 break;
1012                 /* Fall into */
1013                 case FW_MSG_CODE_DRV_LOAD_PORT:
1014                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1015                                               p_hwfn->hw_info.hw_mode);
1016                         if (rc)
1017                                 break;
1018
1019                 /* Fall into */
1020                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1021                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1022                                             p_tunn, p_hwfn->hw_info.hw_mode,
1023                                             b_hw_start, int_mode,
1024                                             allow_npar_tx_switch);
1025                         break;
1026                 default:
1027                         rc = -EINVAL;
1028                         break;
1029                 }
1030
1031                 if (rc)
1032                         DP_NOTICE(p_hwfn,
1033                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1034                                    load_code, rc);
1035
1036                 /* ACK mfw regardless of success or failure of initialization */
1037                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1038                                      DRV_MSG_CODE_LOAD_DONE,
1039                                      0, &load_code, &param);
1040                 if (rc)
1041                         return rc;
1042                 if (mfw_rc) {
1043                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1044                         return mfw_rc;
1045                 }
1046
1047                 /* send DCBX attention request command */
1048                 DP_VERBOSE(p_hwfn,
1049                            QED_MSG_DCB,
1050                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1051                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1052                                      DRV_MSG_CODE_SET_DCBX,
1053                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1054                                      &load_code, &param);
1055                 if (mfw_rc) {
1056                         DP_NOTICE(p_hwfn,
1057                                   "Failed to send DCBX attention request\n");
1058                         return mfw_rc;
1059                 }
1060
1061                 p_hwfn->hw_init_done = true;
1062         }
1063
1064         return 0;
1065 }
1066
1067 #define QED_HW_STOP_RETRY_LIMIT (10)
1068 static inline void qed_hw_timers_stop(struct qed_dev *cdev,
1069                                       struct qed_hwfn *p_hwfn,
1070                                       struct qed_ptt *p_ptt)
1071 {
1072         int i;
1073
1074         /* close timers */
1075         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1076         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1077
1078         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1079                 if ((!qed_rd(p_hwfn, p_ptt,
1080                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1081                     (!qed_rd(p_hwfn, p_ptt,
1082                              TM_REG_PF_SCAN_ACTIVE_TASK)))
1083                         break;
1084
1085                 /* Dependent on number of connection/tasks, possibly
1086                  * 1ms sleep is required between polls
1087                  */
1088                 usleep_range(1000, 2000);
1089         }
1090
1091         if (i < QED_HW_STOP_RETRY_LIMIT)
1092                 return;
1093
1094         DP_NOTICE(p_hwfn,
1095                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1096                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1097                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1098 }
1099
1100 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1101 {
1102         int j;
1103
1104         for_each_hwfn(cdev, j) {
1105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1106                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1107
1108                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1109         }
1110 }
1111
1112 int qed_hw_stop(struct qed_dev *cdev)
1113 {
1114         int rc = 0, t_rc;
1115         int j;
1116
1117         for_each_hwfn(cdev, j) {
1118                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1119                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1120
1121                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1122
1123                 if (IS_VF(cdev)) {
1124                         qed_vf_pf_int_cleanup(p_hwfn);
1125                         continue;
1126                 }
1127
1128                 /* mark the hw as uninitialized... */
1129                 p_hwfn->hw_init_done = false;
1130
1131                 rc = qed_sp_pf_stop(p_hwfn);
1132                 if (rc)
1133                         DP_NOTICE(p_hwfn,
1134                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1135
1136                 qed_wr(p_hwfn, p_ptt,
1137                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1138
1139                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1140                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1141                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1142                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1143                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1144
1145                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1146
1147                 /* Disable Attention Generation */
1148                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1149
1150                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1151                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1152
1153                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1154
1155                 /* Need to wait 1ms to guarantee SBs are cleared */
1156                 usleep_range(1000, 2000);
1157         }
1158
1159         if (IS_PF(cdev)) {
1160                 /* Disable DMAE in PXP - in CMT, this should only be done for
1161                  * first hw-function, and only after all transactions have
1162                  * stopped for all active hw-functions.
1163                  */
1164                 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1165                                            cdev->hwfns[0].p_main_ptt, false);
1166                 if (t_rc != 0)
1167                         rc = t_rc;
1168         }
1169
1170         return rc;
1171 }
1172
1173 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1174 {
1175         int j;
1176
1177         for_each_hwfn(cdev, j) {
1178                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1179                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1180
1181                 if (IS_VF(cdev)) {
1182                         qed_vf_pf_int_cleanup(p_hwfn);
1183                         continue;
1184                 }
1185
1186                 DP_VERBOSE(p_hwfn,
1187                            NETIF_MSG_IFDOWN,
1188                            "Shutting down the fastpath\n");
1189
1190                 qed_wr(p_hwfn, p_ptt,
1191                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1192
1193                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1194                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1195                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1196                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1197                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1198
1199                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1200
1201                 /* Need to wait 1ms to guarantee SBs are cleared */
1202                 usleep_range(1000, 2000);
1203         }
1204 }
1205
1206 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1207 {
1208         if (IS_VF(p_hwfn->cdev))
1209                 return;
1210
1211         /* Re-open incoming traffic */
1212         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1213                NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1214 }
1215
1216 static int qed_reg_assert(struct qed_hwfn *hwfn,
1217                           struct qed_ptt *ptt, u32 reg,
1218                           bool expected)
1219 {
1220         u32 assert_val = qed_rd(hwfn, ptt, reg);
1221
1222         if (assert_val != expected) {
1223                 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
1224                           reg, expected);
1225                 return -EINVAL;
1226         }
1227
1228         return 0;
1229 }
1230
1231 int qed_hw_reset(struct qed_dev *cdev)
1232 {
1233         int rc = 0;
1234         u32 unload_resp, unload_param;
1235         int i;
1236
1237         for_each_hwfn(cdev, i) {
1238                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1239
1240                 if (IS_VF(cdev)) {
1241                         rc = qed_vf_pf_reset(p_hwfn);
1242                         if (rc)
1243                                 return rc;
1244                         continue;
1245                 }
1246
1247                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1248
1249                 /* Check for incorrect states */
1250                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1251                                QM_REG_USG_CNT_PF_TX, 0);
1252                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1253                                QM_REG_USG_CNT_PF_OTHER, 0);
1254
1255                 /* Disable PF in HW blocks */
1256                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1257                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1258                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1259                        TCFC_REG_STRONG_ENABLE_PF, 0);
1260                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1261                        CCFC_REG_STRONG_ENABLE_PF, 0);
1262
1263                 /* Send unload command to MCP */
1264                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1265                                  DRV_MSG_CODE_UNLOAD_REQ,
1266                                  DRV_MB_PARAM_UNLOAD_WOL_MCP,
1267                                  &unload_resp, &unload_param);
1268                 if (rc) {
1269                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1270                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1271                 }
1272
1273                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1274                                  DRV_MSG_CODE_UNLOAD_DONE,
1275                                  0, &unload_resp, &unload_param);
1276                 if (rc) {
1277                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1278                         return rc;
1279                 }
1280         }
1281
1282         return rc;
1283 }
1284
1285 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1286 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1287 {
1288         qed_ptt_pool_free(p_hwfn);
1289         kfree(p_hwfn->hw_info.p_igu_info);
1290 }
1291
1292 /* Setup bar access */
1293 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1294 {
1295         /* clear indirect access */
1296         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1297         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1298         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1299         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1300
1301         /* Clean Previous errors if such exist */
1302         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1303                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1304                1 << p_hwfn->abs_pf_id);
1305
1306         /* enable internal target-read */
1307         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1308                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1309 }
1310
1311 static void get_function_id(struct qed_hwfn *p_hwfn)
1312 {
1313         /* ME Register */
1314         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1315
1316         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1317
1318         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1319         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1320                                       PXP_CONCRETE_FID_PFID);
1321         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1322                                     PXP_CONCRETE_FID_PORT);
1323 }
1324
1325 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1326 {
1327         u32 *feat_num = p_hwfn->hw_info.feat_num;
1328         int num_features = 1;
1329
1330         feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1331                                                 num_features,
1332                                         RESC_NUM(p_hwfn, QED_L2_QUEUE));
1333         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1334                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1335                    feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1336                    num_features);
1337 }
1338
1339 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1340 {
1341         u8 enabled_func_idx = p_hwfn->enabled_func_idx;
1342         u32 *resc_start = p_hwfn->hw_info.resc_start;
1343         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1344         u32 *resc_num = p_hwfn->hw_info.resc_num;
1345         struct qed_sb_cnt_info sb_cnt_info;
1346         int i, max_vf_vlan_filters;
1347
1348         memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1349
1350 #ifdef CONFIG_QED_SRIOV
1351         max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1352 #else
1353         max_vf_vlan_filters = 0;
1354 #endif
1355
1356         qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1357
1358         resc_num[QED_SB] = min_t(u32,
1359                                  (MAX_SB_PER_PATH_BB / num_funcs),
1360                                  sb_cnt_info.sb_cnt);
1361         resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1362         resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1363         resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1364         resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1365         resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
1366         resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1367         resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1368                              num_funcs;
1369         resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1370
1371         for (i = 0; i < QED_MAX_RESC; i++)
1372                 resc_start[i] = resc_num[i] * enabled_func_idx;
1373
1374         /* Sanity for ILT */
1375         if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
1376                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1377                           RESC_START(p_hwfn, QED_ILT),
1378                           RESC_END(p_hwfn, QED_ILT) - 1);
1379                 return -EINVAL;
1380         }
1381
1382         qed_hw_set_feat(p_hwfn);
1383
1384         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1385                    "The numbers for each resource are:\n"
1386                    "SB = %d start = %d\n"
1387                    "L2_QUEUE = %d start = %d\n"
1388                    "VPORT = %d start = %d\n"
1389                    "PQ = %d start = %d\n"
1390                    "RL = %d start = %d\n"
1391                    "MAC = %d start = %d\n"
1392                    "VLAN = %d start = %d\n"
1393                    "ILT = %d start = %d\n",
1394                    p_hwfn->hw_info.resc_num[QED_SB],
1395                    p_hwfn->hw_info.resc_start[QED_SB],
1396                    p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1397                    p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1398                    p_hwfn->hw_info.resc_num[QED_VPORT],
1399                    p_hwfn->hw_info.resc_start[QED_VPORT],
1400                    p_hwfn->hw_info.resc_num[QED_PQ],
1401                    p_hwfn->hw_info.resc_start[QED_PQ],
1402                    p_hwfn->hw_info.resc_num[QED_RL],
1403                    p_hwfn->hw_info.resc_start[QED_RL],
1404                    p_hwfn->hw_info.resc_num[QED_MAC],
1405                    p_hwfn->hw_info.resc_start[QED_MAC],
1406                    p_hwfn->hw_info.resc_num[QED_VLAN],
1407                    p_hwfn->hw_info.resc_start[QED_VLAN],
1408                    p_hwfn->hw_info.resc_num[QED_ILT],
1409                    p_hwfn->hw_info.resc_start[QED_ILT]);
1410
1411         return 0;
1412 }
1413
1414 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1415                                struct qed_ptt *p_ptt)
1416 {
1417         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1418         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1419         struct qed_mcp_link_params *link;
1420
1421         /* Read global nvm_cfg address */
1422         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1423
1424         /* Verify MCP has initialized it */
1425         if (!nvm_cfg_addr) {
1426                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1427                 return -EINVAL;
1428         }
1429
1430         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1431         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1432
1433         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1434                offsetof(struct nvm_cfg1, glob) +
1435                offsetof(struct nvm_cfg1_glob, core_cfg);
1436
1437         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1438
1439         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1440                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1441         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
1442                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1443                 break;
1444         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
1445                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1446                 break;
1447         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
1448                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1449                 break;
1450         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
1451                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1452                 break;
1453         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
1454                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1455                 break;
1456         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
1457                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1458                 break;
1459         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
1460                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1461                 break;
1462         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
1463                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1464                 break;
1465         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
1466                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1467                 break;
1468         default:
1469                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1470                           core_cfg);
1471                 break;
1472         }
1473
1474         /* Read default link configuration */
1475         link = &p_hwfn->mcp_info->link_input;
1476         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1477                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1478         link_temp = qed_rd(p_hwfn, p_ptt,
1479                            port_cfg_addr +
1480                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
1481         link->speed.advertised_speeds =
1482                 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1483
1484         p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1485                                                 link->speed.advertised_speeds;
1486
1487         link_temp = qed_rd(p_hwfn, p_ptt,
1488                            port_cfg_addr +
1489                            offsetof(struct nvm_cfg1_port, link_settings));
1490         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1491                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1492         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1493                 link->speed.autoneg = true;
1494                 break;
1495         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1496                 link->speed.forced_speed = 1000;
1497                 break;
1498         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1499                 link->speed.forced_speed = 10000;
1500                 break;
1501         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1502                 link->speed.forced_speed = 25000;
1503                 break;
1504         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1505                 link->speed.forced_speed = 40000;
1506                 break;
1507         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1508                 link->speed.forced_speed = 50000;
1509                 break;
1510         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
1511                 link->speed.forced_speed = 100000;
1512                 break;
1513         default:
1514                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1515                           link_temp);
1516         }
1517
1518         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1519         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1520         link->pause.autoneg = !!(link_temp &
1521                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1522         link->pause.forced_rx = !!(link_temp &
1523                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1524         link->pause.forced_tx = !!(link_temp &
1525                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1526         link->loopback_mode = 0;
1527
1528         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1529                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1530                    link->speed.forced_speed, link->speed.advertised_speeds,
1531                    link->speed.autoneg, link->pause.autoneg);
1532
1533         /* Read Multi-function information from shmem */
1534         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1535                offsetof(struct nvm_cfg1, glob) +
1536                offsetof(struct nvm_cfg1_glob, generic_cont0);
1537
1538         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1539
1540         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1541                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
1542
1543         switch (mf_mode) {
1544         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1545                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1546                 break;
1547         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1548                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1549                 break;
1550         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1551                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1552                 break;
1553         }
1554         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1555                 p_hwfn->cdev->mf_mode);
1556
1557         /* Read Multi-function information from shmem */
1558         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1559                 offsetof(struct nvm_cfg1, glob) +
1560                 offsetof(struct nvm_cfg1_glob, device_capabilities);
1561
1562         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1563         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1564                 __set_bit(QED_DEV_CAP_ETH,
1565                           &p_hwfn->hw_info.device_capabilities);
1566         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1567                 __set_bit(QED_DEV_CAP_ISCSI,
1568                           &p_hwfn->hw_info.device_capabilities);
1569         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1570                 __set_bit(QED_DEV_CAP_ROCE,
1571                           &p_hwfn->hw_info.device_capabilities);
1572
1573         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1574 }
1575
1576 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1577 {
1578         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1579         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1580
1581         num_funcs = MAX_NUM_PFS_BB;
1582
1583         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1584          * in the other bits are selected.
1585          * Bits 1-15 are for functions 1-15, respectively, and their value is
1586          * '0' only for enabled functions (function 0 always exists and
1587          * enabled).
1588          * In case of CMT, only the "even" functions are enabled, and thus the
1589          * number of functions for both hwfns is learnt from the same bits.
1590          */
1591         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1592
1593         if (reg_function_hide & 0x1) {
1594                 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1595                         num_funcs = 0;
1596                         eng_mask = 0xaaaa;
1597                 } else {
1598                         num_funcs = 1;
1599                         eng_mask = 0x5554;
1600                 }
1601
1602                 /* Get the number of the enabled functions on the engine */
1603                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1604                 while (tmp) {
1605                         if (tmp & 0x1)
1606                                 num_funcs++;
1607                         tmp >>= 0x1;
1608                 }
1609
1610                 /* Get the PF index within the enabled functions */
1611                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1612                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1613                 while (tmp) {
1614                         if (tmp & 0x1)
1615                                 enabled_func_idx--;
1616                         tmp >>= 0x1;
1617                 }
1618         }
1619
1620         p_hwfn->num_funcs_on_engine = num_funcs;
1621         p_hwfn->enabled_func_idx = enabled_func_idx;
1622
1623         DP_VERBOSE(p_hwfn,
1624                    NETIF_MSG_PROBE,
1625                    "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1626                    p_hwfn->rel_pf_id,
1627                    p_hwfn->abs_pf_id,
1628                    p_hwfn->num_funcs_on_engine);
1629 }
1630
1631 static int
1632 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1633                 struct qed_ptt *p_ptt,
1634                 enum qed_pci_personality personality)
1635 {
1636         u32 port_mode;
1637         int rc;
1638
1639         /* Since all information is common, only first hwfns should do this */
1640         if (IS_LEAD_HWFN(p_hwfn)) {
1641                 rc = qed_iov_hw_info(p_hwfn);
1642                 if (rc)
1643                         return rc;
1644         }
1645
1646         /* Read the port mode */
1647         port_mode = qed_rd(p_hwfn, p_ptt,
1648                            CNIG_REG_NW_PORT_MODE_BB_B0);
1649
1650         if (port_mode < 3) {
1651                 p_hwfn->cdev->num_ports_in_engines = 1;
1652         } else if (port_mode <= 5) {
1653                 p_hwfn->cdev->num_ports_in_engines = 2;
1654         } else {
1655                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1656                           p_hwfn->cdev->num_ports_in_engines);
1657
1658                 /* Default num_ports_in_engines to something */
1659                 p_hwfn->cdev->num_ports_in_engines = 1;
1660         }
1661
1662         qed_hw_get_nvm_info(p_hwfn, p_ptt);
1663
1664         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1665         if (rc)
1666                 return rc;
1667
1668         if (qed_mcp_is_init(p_hwfn))
1669                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1670                                 p_hwfn->mcp_info->func_info.mac);
1671         else
1672                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1673
1674         if (qed_mcp_is_init(p_hwfn)) {
1675                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1676                         p_hwfn->hw_info.ovlan =
1677                                 p_hwfn->mcp_info->func_info.ovlan;
1678
1679                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1680         }
1681
1682         if (qed_mcp_is_init(p_hwfn)) {
1683                 enum qed_pci_personality protocol;
1684
1685                 protocol = p_hwfn->mcp_info->func_info.protocol;
1686                 p_hwfn->hw_info.personality = protocol;
1687         }
1688
1689         qed_get_num_funcs(p_hwfn, p_ptt);
1690
1691         return qed_hw_get_resc(p_hwfn);
1692 }
1693
1694 static int qed_get_dev_info(struct qed_dev *cdev)
1695 {
1696         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1697         u32 tmp;
1698
1699         /* Read Vendor Id / Device Id */
1700         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1701                              &cdev->vendor_id);
1702         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1703                              &cdev->device_id);
1704         cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1705                                      MISCS_REG_CHIP_NUM);
1706         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1707                                      MISCS_REG_CHIP_REV);
1708         MASK_FIELD(CHIP_REV, cdev->chip_rev);
1709
1710         cdev->type = QED_DEV_TYPE_BB;
1711         /* Learn number of HW-functions */
1712         tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1713                      MISCS_REG_CMT_ENABLED_FOR_PAIR);
1714
1715         if (tmp & (1 << p_hwfn->rel_pf_id)) {
1716                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1717                 cdev->num_hwfns = 2;
1718         } else {
1719                 cdev->num_hwfns = 1;
1720         }
1721
1722         cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1723                                     MISCS_REG_CHIP_TEST_REG) >> 4;
1724         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1725         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1726                                        MISCS_REG_CHIP_METAL);
1727         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1728
1729         DP_INFO(cdev->hwfns,
1730                 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1731                 cdev->chip_num, cdev->chip_rev,
1732                 cdev->chip_bond_id, cdev->chip_metal);
1733
1734         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1735                 DP_NOTICE(cdev->hwfns,
1736                           "The chip type/rev (BB A0) is not supported!\n");
1737                 return -EINVAL;
1738         }
1739
1740         return 0;
1741 }
1742
1743 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1744                                  void __iomem *p_regview,
1745                                  void __iomem *p_doorbells,
1746                                  enum qed_pci_personality personality)
1747 {
1748         int rc = 0;
1749
1750         /* Split PCI bars evenly between hwfns */
1751         p_hwfn->regview = p_regview;
1752         p_hwfn->doorbells = p_doorbells;
1753
1754         if (IS_VF(p_hwfn->cdev))
1755                 return qed_vf_hw_prepare(p_hwfn);
1756
1757         /* Validate that chip access is feasible */
1758         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1759                 DP_ERR(p_hwfn,
1760                        "Reading the ME register returns all Fs; Preventing further chip access\n");
1761                 return -EINVAL;
1762         }
1763
1764         get_function_id(p_hwfn);
1765
1766         /* Allocate PTT pool */
1767         rc = qed_ptt_pool_alloc(p_hwfn);
1768         if (rc) {
1769                 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1770                 goto err0;
1771         }
1772
1773         /* Allocate the main PTT */
1774         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1775
1776         /* First hwfn learns basic information, e.g., number of hwfns */
1777         if (!p_hwfn->my_id) {
1778                 rc = qed_get_dev_info(p_hwfn->cdev);
1779                 if (rc != 0)
1780                         goto err1;
1781         }
1782
1783         qed_hw_hwfn_prepare(p_hwfn);
1784
1785         /* Initialize MCP structure */
1786         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1787         if (rc) {
1788                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1789                 goto err1;
1790         }
1791
1792         /* Read the device configuration information from the HW and SHMEM */
1793         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1794         if (rc) {
1795                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1796                 goto err2;
1797         }
1798
1799         /* Allocate the init RT array and initialize the init-ops engine */
1800         rc = qed_init_alloc(p_hwfn);
1801         if (rc) {
1802                 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1803                 goto err2;
1804         }
1805
1806         return rc;
1807 err2:
1808         if (IS_LEAD_HWFN(p_hwfn))
1809                 qed_iov_free_hw_info(p_hwfn->cdev);
1810         qed_mcp_free(p_hwfn);
1811 err1:
1812         qed_hw_hwfn_free(p_hwfn);
1813 err0:
1814         return rc;
1815 }
1816
1817 int qed_hw_prepare(struct qed_dev *cdev,
1818                    int personality)
1819 {
1820         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1821         int rc;
1822
1823         /* Store the precompiled init data ptrs */
1824         if (IS_PF(cdev))
1825                 qed_init_iro_array(cdev);
1826
1827         /* Initialize the first hwfn - will learn number of hwfns */
1828         rc = qed_hw_prepare_single(p_hwfn,
1829                                    cdev->regview,
1830                                    cdev->doorbells, personality);
1831         if (rc)
1832                 return rc;
1833
1834         personality = p_hwfn->hw_info.personality;
1835
1836         /* Initialize the rest of the hwfns */
1837         if (cdev->num_hwfns > 1) {
1838                 void __iomem *p_regview, *p_doorbell;
1839                 u8 __iomem *addr;
1840
1841                 /* adjust bar offset for second engine */
1842                 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1843                 p_regview = addr;
1844
1845                 /* adjust doorbell bar offset for second engine */
1846                 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1847                 p_doorbell = addr;
1848
1849                 /* prepare second hw function */
1850                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1851                                            p_doorbell, personality);
1852
1853                 /* in case of error, need to free the previously
1854                  * initiliazed hwfn 0.
1855                  */
1856                 if (rc) {
1857                         if (IS_PF(cdev)) {
1858                                 qed_init_free(p_hwfn);
1859                                 qed_mcp_free(p_hwfn);
1860                                 qed_hw_hwfn_free(p_hwfn);
1861                         }
1862                 }
1863         }
1864
1865         return rc;
1866 }
1867
1868 void qed_hw_remove(struct qed_dev *cdev)
1869 {
1870         int i;
1871
1872         for_each_hwfn(cdev, i) {
1873                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1874
1875                 if (IS_VF(cdev)) {
1876                         qed_vf_pf_release(p_hwfn);
1877                         continue;
1878                 }
1879
1880                 qed_init_free(p_hwfn);
1881                 qed_hw_hwfn_free(p_hwfn);
1882                 qed_mcp_free(p_hwfn);
1883         }
1884
1885         qed_iov_free_hw_info(cdev);
1886 }
1887
1888 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
1889                                     struct qed_chain *p_chain)
1890 {
1891         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
1892         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
1893         struct qed_chain_next *p_next;
1894         u32 size, i;
1895
1896         if (!p_virt)
1897                 return;
1898
1899         size = p_chain->elem_size * p_chain->usable_per_page;
1900
1901         for (i = 0; i < p_chain->page_cnt; i++) {
1902                 if (!p_virt)
1903                         break;
1904
1905                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
1906                 p_virt_next = p_next->next_virt;
1907                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
1908
1909                 dma_free_coherent(&cdev->pdev->dev,
1910                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
1911
1912                 p_virt = p_virt_next;
1913                 p_phys = p_phys_next;
1914         }
1915 }
1916
1917 static void qed_chain_free_single(struct qed_dev *cdev,
1918                                   struct qed_chain *p_chain)
1919 {
1920         if (!p_chain->p_virt_addr)
1921                 return;
1922
1923         dma_free_coherent(&cdev->pdev->dev,
1924                           QED_CHAIN_PAGE_SIZE,
1925                           p_chain->p_virt_addr, p_chain->p_phys_addr);
1926 }
1927
1928 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
1929 {
1930         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
1931         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
1932         u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
1933
1934         if (!pp_virt_addr_tbl)
1935                 return;
1936
1937         if (!p_chain->pbl.p_virt_table)
1938                 goto out;
1939
1940         for (i = 0; i < page_cnt; i++) {
1941                 if (!pp_virt_addr_tbl[i])
1942                         break;
1943
1944                 dma_free_coherent(&cdev->pdev->dev,
1945                                   QED_CHAIN_PAGE_SIZE,
1946                                   pp_virt_addr_tbl[i],
1947                                   *(dma_addr_t *)p_pbl_virt);
1948
1949                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
1950         }
1951
1952         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1953         dma_free_coherent(&cdev->pdev->dev,
1954                           pbl_size,
1955                           p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
1956 out:
1957         vfree(p_chain->pbl.pp_virt_addr_tbl);
1958 }
1959
1960 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
1961 {
1962         switch (p_chain->mode) {
1963         case QED_CHAIN_MODE_NEXT_PTR:
1964                 qed_chain_free_next_ptr(cdev, p_chain);
1965                 break;
1966         case QED_CHAIN_MODE_SINGLE:
1967                 qed_chain_free_single(cdev, p_chain);
1968                 break;
1969         case QED_CHAIN_MODE_PBL:
1970                 qed_chain_free_pbl(cdev, p_chain);
1971                 break;
1972         }
1973 }
1974
1975 static int
1976 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
1977                              enum qed_chain_cnt_type cnt_type,
1978                              size_t elem_size, u32 page_cnt)
1979 {
1980         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
1981
1982         /* The actual chain size can be larger than the maximal possible value
1983          * after rounding up the requested elements number to pages, and after
1984          * taking into acount the unusuable elements (next-ptr elements).
1985          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
1986          * size/capacity fields are of a u32 type.
1987          */
1988         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
1989              chain_size > 0x10000) ||
1990             (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
1991              chain_size > 0x100000000ULL)) {
1992                 DP_NOTICE(cdev,
1993                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
1994                           chain_size);
1995                 return -EINVAL;
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int
2002 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2003 {
2004         void *p_virt = NULL, *p_virt_prev = NULL;
2005         dma_addr_t p_phys = 0;
2006         u32 i;
2007
2008         for (i = 0; i < p_chain->page_cnt; i++) {
2009                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2010                                             QED_CHAIN_PAGE_SIZE,
2011                                             &p_phys, GFP_KERNEL);
2012                 if (!p_virt) {
2013                         DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2014                         return -ENOMEM;
2015                 }
2016
2017                 if (i == 0) {
2018                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2019                         qed_chain_reset(p_chain);
2020                 } else {
2021                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2022                                                      p_virt, p_phys);
2023                 }
2024
2025                 p_virt_prev = p_virt;
2026         }
2027         /* Last page's next element should point to the beginning of the
2028          * chain.
2029          */
2030         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2031                                      p_chain->p_virt_addr,
2032                                      p_chain->p_phys_addr);
2033
2034         return 0;
2035 }
2036
2037 static int
2038 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2039 {
2040         dma_addr_t p_phys = 0;
2041         void *p_virt = NULL;
2042
2043         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2044                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2045         if (!p_virt) {
2046                 DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2047                 return -ENOMEM;
2048         }
2049
2050         qed_chain_init_mem(p_chain, p_virt, p_phys);
2051         qed_chain_reset(p_chain);
2052
2053         return 0;
2054 }
2055
2056 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2057 {
2058         u32 page_cnt = p_chain->page_cnt, size, i;
2059         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2060         void **pp_virt_addr_tbl = NULL;
2061         u8 *p_pbl_virt = NULL;
2062         void *p_virt = NULL;
2063
2064         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2065         pp_virt_addr_tbl = vmalloc(size);
2066         if (!pp_virt_addr_tbl) {
2067                 DP_NOTICE(cdev,
2068                           "Failed to allocate memory for the chain virtual addresses table\n");
2069                 return -ENOMEM;
2070         }
2071         memset(pp_virt_addr_tbl, 0, size);
2072
2073         /* The allocation of the PBL table is done with its full size, since it
2074          * is expected to be successive.
2075          * qed_chain_init_pbl_mem() is called even in a case of an allocation
2076          * failure, since pp_virt_addr_tbl was previously allocated, and it
2077          * should be saved to allow its freeing during the error flow.
2078          */
2079         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2080         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2081                                         size, &p_pbl_phys, GFP_KERNEL);
2082         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2083                                pp_virt_addr_tbl);
2084         if (!p_pbl_virt) {
2085                 DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n");
2086                 return -ENOMEM;
2087         }
2088
2089         for (i = 0; i < page_cnt; i++) {
2090                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2091                                             QED_CHAIN_PAGE_SIZE,
2092                                             &p_phys, GFP_KERNEL);
2093                 if (!p_virt) {
2094                         DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2095                         return -ENOMEM;
2096                 }
2097
2098                 if (i == 0) {
2099                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2100                         qed_chain_reset(p_chain);
2101                 }
2102
2103                 /* Fill the PBL table with the physical address of the page */
2104                 *(dma_addr_t *)p_pbl_virt = p_phys;
2105                 /* Keep the virtual address of the page */
2106                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2107
2108                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2109         }
2110
2111         return 0;
2112 }
2113
2114 int qed_chain_alloc(struct qed_dev *cdev,
2115                     enum qed_chain_use_mode intended_use,
2116                     enum qed_chain_mode mode,
2117                     enum qed_chain_cnt_type cnt_type,
2118                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
2119 {
2120         u32 page_cnt;
2121         int rc = 0;
2122
2123         if (mode == QED_CHAIN_MODE_SINGLE)
2124                 page_cnt = 1;
2125         else
2126                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2127
2128         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2129         if (rc) {
2130                 DP_NOTICE(cdev,
2131                           "Cannot allocate a chain with the given arguments:\n"
2132                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2133                           intended_use, mode, cnt_type, num_elems, elem_size);
2134                 return rc;
2135         }
2136
2137         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2138                               mode, cnt_type);
2139
2140         switch (mode) {
2141         case QED_CHAIN_MODE_NEXT_PTR:
2142                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2143                 break;
2144         case QED_CHAIN_MODE_SINGLE:
2145                 rc = qed_chain_alloc_single(cdev, p_chain);
2146                 break;
2147         case QED_CHAIN_MODE_PBL:
2148                 rc = qed_chain_alloc_pbl(cdev, p_chain);
2149                 break;
2150         }
2151         if (rc)
2152                 goto nomem;
2153
2154         return 0;
2155
2156 nomem:
2157         qed_chain_free(cdev, p_chain);
2158         return rc;
2159 }
2160
2161 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
2162 {
2163         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2164                 u16 min, max;
2165
2166                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
2167                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2168                 DP_NOTICE(p_hwfn,
2169                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2170                           src_id, min, max);
2171
2172                 return -EINVAL;
2173         }
2174
2175         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2176
2177         return 0;
2178 }
2179
2180 int qed_fw_vport(struct qed_hwfn *p_hwfn,
2181                  u8 src_id, u8 *dst_id)
2182 {
2183         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2184                 u8 min, max;
2185
2186                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2187                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2188                 DP_NOTICE(p_hwfn,
2189                           "vport id [%d] is not valid, available indices [%d - %d]\n",
2190                           src_id, min, max);
2191
2192                 return -EINVAL;
2193         }
2194
2195         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2196
2197         return 0;
2198 }
2199
2200 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
2201                    u8 src_id, u8 *dst_id)
2202 {
2203         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2204                 u8 min, max;
2205
2206                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2207                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2208                 DP_NOTICE(p_hwfn,
2209                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2210                           src_id, min, max);
2211
2212                 return -EINVAL;
2213         }
2214
2215         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2216
2217         return 0;
2218 }
2219
2220 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2221                             u32 hw_addr, void *p_eth_qzone,
2222                             size_t eth_qzone_size, u8 timeset)
2223 {
2224         struct coalescing_timeset *p_coal_timeset;
2225
2226         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2227                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2228                 return -EINVAL;
2229         }
2230
2231         p_coal_timeset = p_eth_qzone;
2232         memset(p_coal_timeset, 0, eth_qzone_size);
2233         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2234         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2235         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2236
2237         return 0;
2238 }
2239
2240 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2241                          u16 coalesce, u8 qid, u16 sb_id)
2242 {
2243         struct ustorm_eth_queue_zone eth_qzone;
2244         u8 timeset, timer_res;
2245         u16 fw_qid = 0;
2246         u32 address;
2247         int rc;
2248
2249         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2250         if (coalesce <= 0x7F) {
2251                 timer_res = 0;
2252         } else if (coalesce <= 0xFF) {
2253                 timer_res = 1;
2254         } else if (coalesce <= 0x1FF) {
2255                 timer_res = 2;
2256         } else {
2257                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2258                 return -EINVAL;
2259         }
2260         timeset = (u8)(coalesce >> timer_res);
2261
2262         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2263         if (rc)
2264                 return rc;
2265
2266         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2267         if (rc)
2268                 goto out;
2269
2270         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2271
2272         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2273                               sizeof(struct ustorm_eth_queue_zone), timeset);
2274         if (rc)
2275                 goto out;
2276
2277         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2278 out:
2279         return rc;
2280 }
2281
2282 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2283                          u16 coalesce, u8 qid, u16 sb_id)
2284 {
2285         struct xstorm_eth_queue_zone eth_qzone;
2286         u8 timeset, timer_res;
2287         u16 fw_qid = 0;
2288         u32 address;
2289         int rc;
2290
2291         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2292         if (coalesce <= 0x7F) {
2293                 timer_res = 0;
2294         } else if (coalesce <= 0xFF) {
2295                 timer_res = 1;
2296         } else if (coalesce <= 0x1FF) {
2297                 timer_res = 2;
2298         } else {
2299                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2300                 return -EINVAL;
2301         }
2302         timeset = (u8)(coalesce >> timer_res);
2303
2304         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2305         if (rc)
2306                 return rc;
2307
2308         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2309         if (rc)
2310                 goto out;
2311
2312         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2313
2314         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2315                               sizeof(struct xstorm_eth_queue_zone), timeset);
2316         if (rc)
2317                 goto out;
2318
2319         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2320 out:
2321         return rc;
2322 }
2323
2324 /* Calculate final WFQ values for all vports and configure them.
2325  * After this configuration each vport will have
2326  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2327  */
2328 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2329                                              struct qed_ptt *p_ptt,
2330                                              u32 min_pf_rate)
2331 {
2332         struct init_qm_vport_params *vport_params;
2333         int i;
2334
2335         vport_params = p_hwfn->qm_info.qm_vport_params;
2336
2337         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2338                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2339
2340                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2341                                                 min_pf_rate;
2342                 qed_init_vport_wfq(p_hwfn, p_ptt,
2343                                    vport_params[i].first_tx_pq_id,
2344                                    vport_params[i].vport_wfq);
2345         }
2346 }
2347
2348 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2349                                        u32 min_pf_rate)
2350
2351 {
2352         int i;
2353
2354         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2355                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2356 }
2357
2358 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2359                                            struct qed_ptt *p_ptt,
2360                                            u32 min_pf_rate)
2361 {
2362         struct init_qm_vport_params *vport_params;
2363         int i;
2364
2365         vport_params = p_hwfn->qm_info.qm_vport_params;
2366
2367         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2368                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2369                 qed_init_vport_wfq(p_hwfn, p_ptt,
2370                                    vport_params[i].first_tx_pq_id,
2371                                    vport_params[i].vport_wfq);
2372         }
2373 }
2374
2375 /* This function performs several validations for WFQ
2376  * configuration and required min rate for a given vport
2377  * 1. req_rate must be greater than one percent of min_pf_rate.
2378  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2379  *    rates to get less than one percent of min_pf_rate.
2380  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2381  */
2382 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
2383                               u16 vport_id, u32 req_rate,
2384                               u32 min_pf_rate)
2385 {
2386         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2387         int non_requested_count = 0, req_count = 0, i, num_vports;
2388
2389         num_vports = p_hwfn->qm_info.num_vports;
2390
2391         /* Accounting for the vports which are configured for WFQ explicitly */
2392         for (i = 0; i < num_vports; i++) {
2393                 u32 tmp_speed;
2394
2395                 if ((i != vport_id) &&
2396                     p_hwfn->qm_info.wfq_data[i].configured) {
2397                         req_count++;
2398                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2399                         total_req_min_rate += tmp_speed;
2400                 }
2401         }
2402
2403         /* Include current vport data as well */
2404         req_count++;
2405         total_req_min_rate += req_rate;
2406         non_requested_count = num_vports - req_count;
2407
2408         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2409                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2410                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2411                            vport_id, req_rate, min_pf_rate);
2412                 return -EINVAL;
2413         }
2414
2415         if (num_vports > QED_WFQ_UNIT) {
2416                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2417                            "Number of vports is greater than %d\n",
2418                            QED_WFQ_UNIT);
2419                 return -EINVAL;
2420         }
2421
2422         if (total_req_min_rate > min_pf_rate) {
2423                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2424                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2425                            total_req_min_rate, min_pf_rate);
2426                 return -EINVAL;
2427         }
2428
2429         total_left_rate = min_pf_rate - total_req_min_rate;
2430
2431         left_rate_per_vp = total_left_rate / non_requested_count;
2432         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
2433                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2434                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2435                            left_rate_per_vp, min_pf_rate);
2436                 return -EINVAL;
2437         }
2438
2439         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2440         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2441
2442         for (i = 0; i < num_vports; i++) {
2443                 if (p_hwfn->qm_info.wfq_data[i].configured)
2444                         continue;
2445
2446                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2447         }
2448
2449         return 0;
2450 }
2451
2452 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2453                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2454 {
2455         struct qed_mcp_link_state *p_link;
2456         int rc = 0;
2457
2458         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2459
2460         if (!p_link->min_pf_rate) {
2461                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2462                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2463                 return rc;
2464         }
2465
2466         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2467
2468         if (rc == 0)
2469                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2470                                                  p_link->min_pf_rate);
2471         else
2472                 DP_NOTICE(p_hwfn,
2473                           "Validation failed while configuring min rate\n");
2474
2475         return rc;
2476 }
2477
2478 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2479                                                  struct qed_ptt *p_ptt,
2480                                                  u32 min_pf_rate)
2481 {
2482         bool use_wfq = false;
2483         int rc = 0;
2484         u16 i;
2485
2486         /* Validate all pre configured vports for wfq */
2487         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2488                 u32 rate;
2489
2490                 if (!p_hwfn->qm_info.wfq_data[i].configured)
2491                         continue;
2492
2493                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2494                 use_wfq = true;
2495
2496                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2497                 if (rc) {
2498                         DP_NOTICE(p_hwfn,
2499                                   "WFQ validation failed while configuring min rate\n");
2500                         break;
2501                 }
2502         }
2503
2504         if (!rc && use_wfq)
2505                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2506         else
2507                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2508
2509         return rc;
2510 }
2511
2512 /* Main API for qed clients to configure vport min rate.
2513  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2514  * rate - Speed in Mbps needs to be assigned to a given vport.
2515  */
2516 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2517 {
2518         int i, rc = -EINVAL;
2519
2520         /* Currently not supported; Might change in future */
2521         if (cdev->num_hwfns > 1) {
2522                 DP_NOTICE(cdev,
2523                           "WFQ configuration is not supported for this device\n");
2524                 return rc;
2525         }
2526
2527         for_each_hwfn(cdev, i) {
2528                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2529                 struct qed_ptt *p_ptt;
2530
2531                 p_ptt = qed_ptt_acquire(p_hwfn);
2532                 if (!p_ptt)
2533                         return -EBUSY;
2534
2535                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2536
2537                 if (rc) {
2538                         qed_ptt_release(p_hwfn, p_ptt);
2539                         return rc;
2540                 }
2541
2542                 qed_ptt_release(p_hwfn, p_ptt);
2543         }
2544
2545         return rc;
2546 }
2547
2548 /* API to configure WFQ from mcp link change */
2549 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2550 {
2551         int i;
2552
2553         if (cdev->num_hwfns > 1) {
2554                 DP_VERBOSE(cdev,
2555                            NETIF_MSG_LINK,
2556                            "WFQ configuration is not supported for this device\n");
2557                 return;
2558         }
2559
2560         for_each_hwfn(cdev, i) {
2561                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2562
2563                 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2564                                                       p_hwfn->p_dpc_ptt,
2565                                                       min_pf_rate);
2566         }
2567 }
2568
2569 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2570                                      struct qed_ptt *p_ptt,
2571                                      struct qed_mcp_link_state *p_link,
2572                                      u8 max_bw)
2573 {
2574         int rc = 0;
2575
2576         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2577
2578         if (!p_link->line_speed && (max_bw != 100))
2579                 return rc;
2580
2581         p_link->speed = (p_link->line_speed * max_bw) / 100;
2582         p_hwfn->qm_info.pf_rl = p_link->speed;
2583
2584         /* Since the limiter also affects Tx-switched traffic, we don't want it
2585          * to limit such traffic in case there's no actual limit.
2586          * In that case, set limit to imaginary high boundary.
2587          */
2588         if (max_bw == 100)
2589                 p_hwfn->qm_info.pf_rl = 100000;
2590
2591         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2592                             p_hwfn->qm_info.pf_rl);
2593
2594         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2595                    "Configured MAX bandwidth to be %08x Mb/sec\n",
2596                    p_link->speed);
2597
2598         return rc;
2599 }
2600
2601 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2602 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2603 {
2604         int i, rc = -EINVAL;
2605
2606         if (max_bw < 1 || max_bw > 100) {
2607                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2608                 return rc;
2609         }
2610
2611         for_each_hwfn(cdev, i) {
2612                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2613                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2614                 struct qed_mcp_link_state *p_link;
2615                 struct qed_ptt *p_ptt;
2616
2617                 p_link = &p_lead->mcp_info->link_output;
2618
2619                 p_ptt = qed_ptt_acquire(p_hwfn);
2620                 if (!p_ptt)
2621                         return -EBUSY;
2622
2623                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2624                                                       p_link, max_bw);
2625
2626                 qed_ptt_release(p_hwfn, p_ptt);
2627
2628                 if (rc)
2629                         break;
2630         }
2631
2632         return rc;
2633 }
2634
2635 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2636                                      struct qed_ptt *p_ptt,
2637                                      struct qed_mcp_link_state *p_link,
2638                                      u8 min_bw)
2639 {
2640         int rc = 0;
2641
2642         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2643         p_hwfn->qm_info.pf_wfq = min_bw;
2644
2645         if (!p_link->line_speed)
2646                 return rc;
2647
2648         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2649
2650         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2651
2652         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2653                    "Configured MIN bandwidth to be %d Mb/sec\n",
2654                    p_link->min_pf_rate);
2655
2656         return rc;
2657 }
2658
2659 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2660 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2661 {
2662         int i, rc = -EINVAL;
2663
2664         if (min_bw < 1 || min_bw > 100) {
2665                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2666                 return rc;
2667         }
2668
2669         for_each_hwfn(cdev, i) {
2670                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2671                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2672                 struct qed_mcp_link_state *p_link;
2673                 struct qed_ptt *p_ptt;
2674
2675                 p_link = &p_lead->mcp_info->link_output;
2676
2677                 p_ptt = qed_ptt_acquire(p_hwfn);
2678                 if (!p_ptt)
2679                         return -EBUSY;
2680
2681                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2682                                                       p_link, min_bw);
2683                 if (rc) {
2684                         qed_ptt_release(p_hwfn, p_ptt);
2685                         return rc;
2686                 }
2687
2688                 if (p_link->min_pf_rate) {
2689                         u32 min_rate = p_link->min_pf_rate;
2690
2691                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2692                                                                    p_ptt,
2693                                                                    min_rate);
2694                 }
2695
2696                 qed_ptt_release(p_hwfn, p_ptt);
2697         }
2698
2699         return rc;
2700 }
2701
2702 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2703 {
2704         struct qed_mcp_link_state *p_link;
2705
2706         p_link = &p_hwfn->mcp_info->link_output;
2707
2708         if (p_link->min_pf_rate)
2709                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2710                                                p_link->min_pf_rate);
2711
2712         memset(p_hwfn->qm_info.wfq_data, 0,
2713                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2714 }