1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/slab.h>
19 #include <linux/qed/common_hsi.h>
20 #include <linux/qed/eth_common.h>
24 /********************************/
25 /* Add include to common target */
26 /********************************/
28 /* opcodes for the event ring */
29 enum common_event_opcode {
30 COMMON_EVENT_PF_START,
32 COMMON_EVENT_RESERVED,
33 COMMON_EVENT_RESERVED2,
34 COMMON_EVENT_RESERVED3,
35 COMMON_EVENT_RESERVED4,
36 COMMON_EVENT_RESERVED5,
37 COMMON_EVENT_RESERVED6,
39 MAX_COMMON_EVENT_OPCODE
42 /* Common Ramrod Command IDs */
43 enum common_ramrod_cmd_id {
45 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
46 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
47 COMMON_RAMROD_RESERVED,
48 COMMON_RAMROD_RESERVED2,
49 COMMON_RAMROD_RESERVED3,
51 MAX_COMMON_RAMROD_CMD_ID
54 /* The core storm context for the Ystorm */
55 struct ystorm_core_conn_st_ctx {
59 /* The core storm context for the Pstorm */
60 struct pstorm_core_conn_st_ctx {
64 /* Core Slowpath Connection storm context of Xstorm */
65 struct xstorm_core_conn_st_ctx {
66 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
67 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
68 struct regpair consolid_base_addr;
69 __le16 spq_cons /* SPQ Ring Consumer */;
70 __le16 consolid_cons /* Consolidation Ring Consumer */;
71 __le32 reserved0[55] /* Pad to 15 cycles */;
74 struct xstorm_core_conn_ag_ctx {
75 u8 reserved0 /* cdu_validation */;
76 u8 core_state /* state */;
78 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
79 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
80 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
81 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
82 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
84 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
85 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
98 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
101 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
102 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
103 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
104 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
105 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
106 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
107 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
108 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
109 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
110 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
112 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
113 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
114 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
115 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
116 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
117 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
118 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
119 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
121 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
122 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
123 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
124 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
125 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
126 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
127 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
128 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
130 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
131 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
132 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
133 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
134 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
135 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
136 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
137 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
139 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
140 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
141 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
142 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
143 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
144 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
145 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
146 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
148 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */
149 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
150 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
151 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
152 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
153 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
154 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
155 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
157 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
158 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
159 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
160 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
161 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
162 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
163 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
164 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
165 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
166 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
168 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
169 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
170 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
171 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
172 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
173 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
174 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
175 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
176 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
177 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
178 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
179 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
180 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
181 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
182 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
183 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
185 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
186 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
187 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
188 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
189 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
190 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
191 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
192 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
193 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
194 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
195 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
196 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
197 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */
198 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
199 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
200 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
202 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
203 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
204 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
205 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
206 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
207 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
208 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
209 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
210 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
211 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
212 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
213 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
214 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
215 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
216 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
217 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
222 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
223 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
224 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
225 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
226 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
227 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
228 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
229 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
230 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
231 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
232 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
233 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
234 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
236 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
237 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
238 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
239 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
240 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
241 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
242 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
243 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
244 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
245 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
246 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
247 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
248 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
249 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
250 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
251 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
253 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
254 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
255 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
256 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
257 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
258 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
259 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
260 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
270 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
271 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
272 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
273 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
274 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
275 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
276 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
277 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
278 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
279 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
280 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
281 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
282 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
283 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
284 u8 byte2 /* byte2 */;
285 __le16 physical_q0 /* physical_q0 */;
286 __le16 consolid_prod /* physical_q1 */;
287 __le16 reserved16 /* physical_q2 */;
288 __le16 tx_bd_cons /* word3 */;
289 __le16 tx_bd_or_spq_prod /* word4 */;
290 __le16 word5 /* word5 */;
291 __le16 conn_dpi /* conn_dpi */;
292 u8 byte3 /* byte3 */;
293 u8 byte4 /* byte4 */;
294 u8 byte5 /* byte5 */;
295 u8 byte6 /* byte6 */;
296 __le32 reg0 /* reg0 */;
297 __le32 reg1 /* reg1 */;
298 __le32 reg2 /* reg2 */;
299 __le32 reg3 /* reg3 */;
300 __le32 reg4 /* reg4 */;
301 __le32 reg5 /* cf_array0 */;
302 __le32 reg6 /* cf_array1 */;
303 __le16 word7 /* word7 */;
304 __le16 word8 /* word8 */;
305 __le16 word9 /* word9 */;
306 __le16 word10 /* word10 */;
307 __le32 reg7 /* reg7 */;
308 __le32 reg8 /* reg8 */;
309 __le32 reg9 /* reg9 */;
310 u8 byte7 /* byte7 */;
311 u8 byte8 /* byte8 */;
312 u8 byte9 /* byte9 */;
313 u8 byte10 /* byte10 */;
314 u8 byte11 /* byte11 */;
315 u8 byte12 /* byte12 */;
316 u8 byte13 /* byte13 */;
317 u8 byte14 /* byte14 */;
318 u8 byte15 /* byte15 */;
319 u8 byte16 /* byte16 */;
320 __le16 word11 /* word11 */;
321 __le32 reg10 /* reg10 */;
322 __le32 reg11 /* reg11 */;
323 __le32 reg12 /* reg12 */;
324 __le32 reg13 /* reg13 */;
325 __le32 reg14 /* reg14 */;
326 __le32 reg15 /* reg15 */;
327 __le32 reg16 /* reg16 */;
328 __le32 reg17 /* reg17 */;
329 __le32 reg18 /* reg18 */;
330 __le32 reg19 /* reg19 */;
331 __le16 word12 /* word12 */;
332 __le16 word13 /* word13 */;
333 __le16 word14 /* word14 */;
334 __le16 word15 /* word15 */;
337 struct tstorm_core_conn_ag_ctx {
338 u8 byte0 /* cdu_validation */;
339 u8 byte1 /* state */;
341 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
342 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
343 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
344 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
345 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
346 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
347 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
348 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
349 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
350 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
351 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
352 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
353 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
354 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
356 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
357 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
358 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
359 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
360 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
361 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
362 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
363 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
365 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
366 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
367 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
368 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
369 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
370 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
371 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
372 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
374 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
375 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
376 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
377 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
378 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
379 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
380 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
381 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
382 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
383 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
384 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
385 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
387 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
388 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
389 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
390 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
391 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
392 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
393 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
394 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
395 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
396 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
397 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
398 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
399 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
400 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
401 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
402 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
404 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
405 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
406 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
407 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
408 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
409 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
410 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
411 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
412 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
413 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
414 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
415 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
416 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
417 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
418 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
419 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
420 __le32 reg0 /* reg0 */;
421 __le32 reg1 /* reg1 */;
422 __le32 reg2 /* reg2 */;
423 __le32 reg3 /* reg3 */;
424 __le32 reg4 /* reg4 */;
425 __le32 reg5 /* reg5 */;
426 __le32 reg6 /* reg6 */;
427 __le32 reg7 /* reg7 */;
428 __le32 reg8 /* reg8 */;
429 u8 byte2 /* byte2 */;
430 u8 byte3 /* byte3 */;
431 __le16 word0 /* word0 */;
432 u8 byte4 /* byte4 */;
433 u8 byte5 /* byte5 */;
434 __le16 word1 /* word1 */;
435 __le16 word2 /* conn_dpi */;
436 __le16 word3 /* word3 */;
437 __le32 reg9 /* reg9 */;
438 __le32 reg10 /* reg10 */;
441 struct ustorm_core_conn_ag_ctx {
442 u8 reserved /* cdu_validation */;
443 u8 byte1 /* state */;
445 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
446 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
447 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
448 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
449 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
450 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
451 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
452 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
453 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
454 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
456 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
457 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
458 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
459 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
460 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
461 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
462 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
463 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
465 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
466 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
467 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
468 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
469 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
470 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
471 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
472 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
473 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
474 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
475 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
476 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
477 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
478 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
479 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
480 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
482 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
483 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
484 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
485 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
486 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
487 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
488 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
489 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
490 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
491 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
492 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
493 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
494 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
495 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
496 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
497 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
498 u8 byte2 /* byte2 */;
499 u8 byte3 /* byte3 */;
500 __le16 word0 /* conn_dpi */;
501 __le16 word1 /* word1 */;
502 __le32 rx_producers /* reg0 */;
503 __le32 reg1 /* reg1 */;
504 __le32 reg2 /* reg2 */;
505 __le32 reg3 /* reg3 */;
506 __le16 word2 /* word2 */;
507 __le16 word3 /* word3 */;
510 /* The core storm context for the Mstorm */
511 struct mstorm_core_conn_st_ctx {
515 /* The core storm context for the Ustorm */
516 struct ustorm_core_conn_st_ctx {
520 /* core connection context */
521 struct core_conn_context {
522 struct ystorm_core_conn_st_ctx ystorm_st_context;
523 struct regpair ystorm_st_padding[2] /* padding */;
524 struct pstorm_core_conn_st_ctx pstorm_st_context;
525 struct regpair pstorm_st_padding[2];
526 struct xstorm_core_conn_st_ctx xstorm_st_context;
527 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
528 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
529 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
530 struct mstorm_core_conn_st_ctx mstorm_st_context;
531 struct ustorm_core_conn_st_ctx ustorm_st_context;
532 struct regpair ustorm_st_padding[2] /* padding */;
535 struct eth_mstorm_per_queue_stat {
536 struct regpair ttl0_discard;
537 struct regpair packet_too_big_discard;
538 struct regpair no_buff_discard;
539 struct regpair not_active_discard;
540 struct regpair tpa_coalesced_pkts;
541 struct regpair tpa_coalesced_events;
542 struct regpair tpa_aborts_num;
543 struct regpair tpa_coalesced_bytes;
546 struct eth_pstorm_per_queue_stat {
547 struct regpair sent_ucast_bytes;
548 struct regpair sent_mcast_bytes;
549 struct regpair sent_bcast_bytes;
550 struct regpair sent_ucast_pkts;
551 struct regpair sent_mcast_pkts;
552 struct regpair sent_bcast_pkts;
553 struct regpair error_drop_pkts;
556 struct eth_ustorm_per_queue_stat {
557 struct regpair rcv_ucast_bytes;
558 struct regpair rcv_mcast_bytes;
559 struct regpair rcv_bcast_bytes;
560 struct regpair rcv_ucast_pkts;
561 struct regpair rcv_mcast_pkts;
562 struct regpair rcv_bcast_pkts;
565 /* Event Ring Next Page Address */
566 struct event_ring_next_addr {
567 struct regpair addr /* Next Page Address */;
568 __le32 reserved[2] /* Reserved */;
571 union event_ring_element {
572 struct event_ring_entry entry /* Event Ring Entry */;
573 struct event_ring_next_addr next_addr;
576 enum personality_type {
578 PERSONALITY_RESERVED,
579 PERSONALITY_RESERVED2,
580 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
581 PERSONALITY_RESERVED3,
583 PERSONALITY_ETH /* Ethernet */,
584 PERSONALITY_RESERVED4,
588 struct pf_start_tunnel_config {
589 u8 set_vxlan_udp_port_flg;
590 u8 set_geneve_udp_port_flg;
591 u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
592 u8 tx_enable_l2geneve;
593 u8 tx_enable_ipgeneve;
594 u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
595 u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
596 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
597 u8 tunnel_clss_l2geneve;
598 u8 tunnel_clss_ipgeneve;
599 u8 tunnel_clss_l2gre;
600 u8 tunnel_clss_ipgre;
601 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
602 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
605 /* Ramrod data for PF start ramrod */
606 struct pf_start_ramrod_data {
607 struct regpair event_ring_pbl_addr;
608 struct regpair consolid_q_pbl_addr;
609 struct pf_start_tunnel_config tunnel_config;
610 __le16 event_ring_sb_id;
613 u8 event_ring_num_pages;
614 u8 event_ring_sb_index;
619 __le16 log_type_mask;
620 u8 mf_mode /* Multi function mode */;
621 u8 integ_phase /* Integration phase */;
622 u8 allow_npar_tx_switching;
623 u8 inner_to_outer_pri_map[8];
630 ENGX2_PORTX1 /* 2 engines x 1 port */,
631 ENGX2_PORTX2 /* 2 engines x 2 ports */,
632 ENGX1_PORTX1 /* 1 engine x 1 port */,
633 ENGX1_PORTX2 /* 1 engine x 2 ports */,
634 ENGX1_PORTX4 /* 1 engine x 4 ports */,
638 /* Ramrod Header of SPQE */
639 struct ramrod_header {
640 __le32 cid /* Slowpath Connection CID */;
641 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
642 u8 protocol_id /* Ramrod Protocol ID */;
643 __le16 echo /* Ramrod echo */;
646 /* Slowpath Element (SPQE) */
647 struct slow_path_element {
648 struct ramrod_header hdr /* Ramrod Header */;
649 struct regpair data_ptr;
652 struct tstorm_per_port_stat {
653 struct regpair trunc_error_discard;
654 struct regpair mac_error_discard;
655 struct regpair mftag_filter_discard;
656 struct regpair eth_mac_filter_discard;
657 struct regpair ll2_mac_filter_discard;
658 struct regpair ll2_conn_disabled_discard;
659 struct regpair iscsi_irregular_pkt;
660 struct regpair fcoe_irregular_pkt;
661 struct regpair roce_irregular_pkt;
662 struct regpair eth_irregular_pkt;
663 struct regpair toe_irregular_pkt;
664 struct regpair preroce_irregular_pkt;
667 struct atten_status_block {
671 __le16 sb_index /* status block running index */;
676 GRCBASE_GRC = 0x50000,
677 GRCBASE_MISCS = 0x9000,
678 GRCBASE_MISC = 0x8000,
679 GRCBASE_DBU = 0xa000,
680 GRCBASE_PGLUE_B = 0x2a8000,
681 GRCBASE_CNIG = 0x218000,
682 GRCBASE_CPMU = 0x30000,
683 GRCBASE_NCSI = 0x40000,
684 GRCBASE_OPTE = 0x53000,
685 GRCBASE_BMB = 0x540000,
686 GRCBASE_PCIE = 0x54000,
687 GRCBASE_MCP = 0xe00000,
688 GRCBASE_MCP2 = 0x52000,
689 GRCBASE_PSWHST = 0x2a0000,
690 GRCBASE_PSWHST2 = 0x29e000,
691 GRCBASE_PSWRD = 0x29c000,
692 GRCBASE_PSWRD2 = 0x29d000,
693 GRCBASE_PSWWR = 0x29a000,
694 GRCBASE_PSWWR2 = 0x29b000,
695 GRCBASE_PSWRQ = 0x280000,
696 GRCBASE_PSWRQ2 = 0x240000,
698 GRCBASE_PTU = 0x560000,
699 GRCBASE_DMAE = 0xc000,
700 GRCBASE_TCM = 0x1180000,
701 GRCBASE_MCM = 0x1200000,
702 GRCBASE_UCM = 0x1280000,
703 GRCBASE_XCM = 0x1000000,
704 GRCBASE_YCM = 0x1080000,
705 GRCBASE_PCM = 0x1100000,
706 GRCBASE_QM = 0x2f0000,
707 GRCBASE_TM = 0x2c0000,
708 GRCBASE_DORQ = 0x100000,
709 GRCBASE_BRB = 0x340000,
710 GRCBASE_SRC = 0x238000,
711 GRCBASE_PRS = 0x1f0000,
712 GRCBASE_TSDM = 0xfb0000,
713 GRCBASE_MSDM = 0xfc0000,
714 GRCBASE_USDM = 0xfd0000,
715 GRCBASE_XSDM = 0xf80000,
716 GRCBASE_YSDM = 0xf90000,
717 GRCBASE_PSDM = 0xfa0000,
718 GRCBASE_TSEM = 0x1700000,
719 GRCBASE_MSEM = 0x1800000,
720 GRCBASE_USEM = 0x1900000,
721 GRCBASE_XSEM = 0x1400000,
722 GRCBASE_YSEM = 0x1500000,
723 GRCBASE_PSEM = 0x1600000,
724 GRCBASE_RSS = 0x238800,
725 GRCBASE_TMLD = 0x4d0000,
726 GRCBASE_MULD = 0x4e0000,
727 GRCBASE_YULD = 0x4c8000,
728 GRCBASE_XYLD = 0x4c0000,
729 GRCBASE_PRM = 0x230000,
730 GRCBASE_PBF_PB1 = 0xda0000,
731 GRCBASE_PBF_PB2 = 0xda4000,
732 GRCBASE_RPB = 0x23c000,
733 GRCBASE_BTB = 0xdb0000,
734 GRCBASE_PBF = 0xd80000,
735 GRCBASE_RDIF = 0x300000,
736 GRCBASE_TDIF = 0x310000,
737 GRCBASE_CDU = 0x580000,
738 GRCBASE_CCFC = 0x2e0000,
739 GRCBASE_TCFC = 0x2d0000,
740 GRCBASE_IGU = 0x180000,
741 GRCBASE_CAU = 0x1c0000,
742 GRCBASE_UMAC = 0x51000,
743 GRCBASE_XMAC = 0x210000,
744 GRCBASE_DBG = 0x10000,
745 GRCBASE_NIG = 0x500000,
746 GRCBASE_WOL = 0x600000,
747 GRCBASE_BMBN = 0x610000,
748 GRCBASE_IPC = 0x20000,
749 GRCBASE_NWM = 0x800000,
750 GRCBASE_NWS = 0x700000,
751 GRCBASE_MS = 0x6a0000,
752 GRCBASE_PHY_PCIE = 0x620000,
753 GRCBASE_MISC_AEU = 0x8000,
754 GRCBASE_BAR0_MAP = 0x1c00000,
841 enum command_type_bit {
842 IGU_COMMAND_TYPE_NOP = 0,
843 IGU_COMMAND_TYPE_SET = 1,
849 #define DMAE_CMD_SRC_MASK 0x1
850 #define DMAE_CMD_SRC_SHIFT 0
851 #define DMAE_CMD_DST_MASK 0x3
852 #define DMAE_CMD_DST_SHIFT 1
853 #define DMAE_CMD_C_DST_MASK 0x1
854 #define DMAE_CMD_C_DST_SHIFT 3
855 #define DMAE_CMD_CRC_RESET_MASK 0x1
856 #define DMAE_CMD_CRC_RESET_SHIFT 4
857 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
858 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
859 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
860 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
861 #define DMAE_CMD_COMP_FUNC_MASK 0x1
862 #define DMAE_CMD_COMP_FUNC_SHIFT 7
863 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
864 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
865 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
866 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
867 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
868 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
869 #define DMAE_CMD_RESERVED1_MASK 0x1
870 #define DMAE_CMD_RESERVED1_SHIFT 13
871 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
872 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
873 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
874 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
875 #define DMAE_CMD_PORT_ID_MASK 0x3
876 #define DMAE_CMD_PORT_ID_SHIFT 18
877 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
878 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
879 #define DMAE_CMD_DST_PF_ID_MASK 0xF
880 #define DMAE_CMD_DST_PF_ID_SHIFT 24
881 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
882 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
883 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
884 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
885 #define DMAE_CMD_RESERVED2_MASK 0x3
886 #define DMAE_CMD_RESERVED2_SHIFT 30
891 __le16 length /* Length in DW */;
893 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
894 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
895 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
896 #define DMAE_CMD_DST_VF_ID_SHIFT 8
897 __le32 comp_addr_lo /* PCIe completion address low or grc address */;
899 __le32 comp_val /* Value to write to copmletion address */;
900 __le32 crc32 /* crc16 result */;
901 __le32 crc_32_c /* crc32_c result */;
902 __le16 crc16 /* crc16 result */;
903 __le16 crc16_c /* crc16_c result */;
904 __le16 crc10 /* crc_t10 result */;
906 __le16 xsum16 /* checksum16 result */;
907 __le16 xsum8 /* checksum8 result */;
911 __le32 sb_id_and_flags;
912 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
913 #define IGU_CLEANUP_RESERVED0_SHIFT 0
914 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */
915 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
916 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
917 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
918 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
919 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
924 struct igu_prod_cons_update prod_cons_update;
925 struct igu_cleanup cleanup;
928 struct igu_command_reg_ctrl {
930 __le16 igu_command_reg_ctrl_fields;
931 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
932 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
933 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
934 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
935 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
936 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
939 struct igu_mapping_line {
940 __le32 igu_mapping_line_fields;
941 #define IGU_MAPPING_LINE_VALID_MASK 0x1
942 #define IGU_MAPPING_LINE_VALID_SHIFT 0
943 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
944 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
945 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
946 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
947 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
948 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
949 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
950 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
951 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
952 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
955 struct igu_msix_vector {
956 struct regpair address;
958 __le32 msix_vector_fields;
959 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
960 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
961 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
962 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
963 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
964 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
965 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
966 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
981 MODE_PORTS_PER_ENG_1,
982 MODE_PORTS_PER_ENG_2,
983 MODE_PORTS_PER_ENG_4,
985 MODE_EAGLE_ENG1_WORKAROUND,
998 /* per encapsulation type enabling flags */
999 struct prs_reg_encapsulation_type_en {
1001 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1002 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1003 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1004 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1005 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1006 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1007 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1008 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1009 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1010 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1011 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1012 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1013 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1014 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1017 enum pxp_tph_st_hint {
1018 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
1019 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
1021 TPH_ST_HINT_TARGET_PRIO,
1025 /* QM hardware structure of enable bypass credit mask */
1026 struct qm_rf_bypass_mask {
1028 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1029 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1030 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1031 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1032 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1033 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1034 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1035 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1036 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1037 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1038 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1039 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1040 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1041 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1042 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1043 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1046 /* QM hardware structure of opportunistic credit mask */
1047 struct qm_rf_opportunistic_mask {
1049 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1050 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1051 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1052 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1053 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1054 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1055 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1056 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1057 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1058 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1059 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1060 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1061 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1062 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1063 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1064 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1065 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1066 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1067 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1068 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1071 /* QM hardware structure of QM map memory */
1072 struct qm_rf_pq_map {
1074 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
1075 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1076 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
1077 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1078 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1079 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1080 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
1081 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
1082 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
1083 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1084 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
1085 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1086 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1087 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1090 /* Completion params for aggregated interrupt completion */
1091 struct sdm_agg_int_comp_params {
1093 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1094 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1095 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1096 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1097 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1098 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1101 /* SDM operation gen command (generate aggregative interrupt) */
1104 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */
1105 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1106 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
1107 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1108 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
1109 #define SDM_OP_GEN_RESERVED_SHIFT 20
1112 /*********************************** Init ************************************/
1114 /* Width of GRC address in bits (addresses are specified in dwords) */
1115 #define GRC_ADDR_BITS 23
1116 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
1118 /* indicates an init that should be applied to any phase ID */
1119 #define ANY_PHASE_ID 0xffff
1121 /* init pattern size in bytes */
1122 #define INIT_PATTERN_SIZE_BITS 4
1123 #define MAX_INIT_PATTERN_SIZE BIT(INIT_PATTERN_SIZE_BITS)
1125 /* Max size in dwords of a zipped array */
1126 #define MAX_ZIPPED_SIZE 8192
1128 /* Global PXP window */
1129 #define NUM_OF_PXP_WIN 19
1130 #define PXP_WIN_DWORD_SIZE_BITS 10
1131 #define PXP_WIN_DWORD_SIZE BIT(PXP_WIN_DWORD_SIZE_BITS)
1132 #define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
1133 #define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
1135 /********************************* GRC Dump **********************************/
1137 /* width of GRC dump register sequence length in bits */
1138 #define DUMP_SEQ_LEN_BITS 8
1139 #define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
1141 /* width of GRC dump memory length in bits */
1142 #define DUMP_MEM_LEN_BITS 18
1143 #define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
1145 /* width of register type ID in bits */
1146 #define REG_TYPE_ID_BITS 6
1147 #define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
1149 /* width of block ID in bits */
1150 #define BLOCK_ID_BITS 8
1151 #define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
1153 /******************************** Idle Check *********************************/
1155 /* max number of idle check predicate immediates */
1156 #define MAX_IDLE_CHK_PRED_IMM 3
1158 /* max number of idle check argument registers */
1159 #define MAX_IDLE_CHK_READ_REGS 3
1161 /* max number of idle check loops */
1162 #define MAX_IDLE_CHK_LOOPS 0x10000
1164 /* max idle check address increment */
1165 #define MAX_IDLE_CHK_INCREMENT 0x10000
1167 /* inicates an undefined idle check line index */
1168 #define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
1170 /* max number of register values following the idle check header */
1171 #define IDLE_CHK_MAX_DUMP_REGS 2
1173 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1174 #define IDLE_CHK_QM_RD_WR_PTR 0
1175 #define IDLE_CHK_QM_RD_WR_BANK 1
1177 /**************************************/
1178 /* HSI Functions constants and macros */
1179 /**************************************/
1181 /* Number of VLAN priorities */
1182 #define NUM_OF_VLAN_PRIORITIES 8
1184 /* the MCP Trace meta data signautre is duplicated in the perl script that
1185 * generats the NVRAM images.
1187 #define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
1189 /* Binary buffer header */
1190 struct bin_buffer_hdr {
1192 u32 length /* buffer length in bytes */;
1195 /* binary buffer types */
1196 enum bin_buffer_type {
1197 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1198 BIN_BUF_INIT_CMD /* init commands */,
1199 BIN_BUF_INIT_VAL /* init data */,
1200 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1201 BIN_BUF_IRO /* internal RAM offsets array */,
1207 CHIP_BB_A0 /* BB A0 chip ID */,
1208 CHIP_BB_B0 /* BB B0 chip ID */,
1209 CHIP_K2 /* AH chip ID */,
1213 struct init_array_raw_hdr {
1215 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
1216 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
1217 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
1218 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1221 struct init_array_standard_hdr {
1223 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
1224 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1225 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
1226 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1229 struct init_array_zipped_hdr {
1231 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
1232 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
1233 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
1234 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1237 struct init_array_pattern_hdr {
1239 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
1240 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
1241 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
1242 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1243 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
1244 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
1247 union init_array_hdr {
1248 struct init_array_raw_hdr raw /* raw init array header */;
1249 struct init_array_standard_hdr standard;
1250 struct init_array_zipped_hdr zipped /* zipped init array header */;
1251 struct init_array_pattern_hdr pattern /* pattern init array header */;
1254 enum init_array_types {
1255 INIT_ARR_STANDARD /* standard init array */,
1256 INIT_ARR_ZIPPED /* zipped init array */,
1257 INIT_ARR_PATTERN /* a repeated pattern */,
1258 MAX_INIT_ARRAY_TYPES
1261 /* init operation: callback */
1262 struct init_callback_op {
1264 #define INIT_CALLBACK_OP_OP_MASK 0xF
1265 #define INIT_CALLBACK_OP_OP_SHIFT 0
1266 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
1267 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1268 __le16 callback_id /* Callback ID */;
1269 __le16 block_id /* Blocks ID */;
1272 /* init operation: delay */
1273 struct init_delay_op {
1275 #define INIT_DELAY_OP_OP_MASK 0xF
1276 #define INIT_DELAY_OP_OP_SHIFT 0
1277 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
1278 #define INIT_DELAY_OP_RESERVED_SHIFT 4
1279 __le32 delay /* delay in us */;
1282 /* init operation: if_mode */
1283 struct init_if_mode_op {
1285 #define INIT_IF_MODE_OP_OP_MASK 0xF
1286 #define INIT_IF_MODE_OP_OP_SHIFT 0
1287 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
1288 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
1289 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
1290 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1292 __le16 modes_buf_offset;
1295 /* init operation: if_phase */
1296 struct init_if_phase_op {
1298 #define INIT_IF_PHASE_OP_OP_MASK 0xF
1299 #define INIT_IF_PHASE_OP_OP_SHIFT 0
1300 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
1301 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1302 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
1303 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
1304 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
1305 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
1307 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
1308 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
1309 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
1310 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
1311 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
1312 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
1315 /* init mode operators */
1316 enum init_mode_ops {
1317 INIT_MODE_OP_NOT /* init mode not operator */,
1318 INIT_MODE_OP_OR /* init mode or operator */,
1319 INIT_MODE_OP_AND /* init mode and operator */,
1323 /* init operation: raw */
1324 struct init_raw_op {
1326 #define INIT_RAW_OP_OP_MASK 0xF
1327 #define INIT_RAW_OP_OP_SHIFT 0
1328 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
1329 #define INIT_RAW_OP_PARAM1_SHIFT 4
1330 __le32 param2 /* Init param 2 */;
1333 /* init array params */
1334 struct init_op_array_params {
1335 __le16 size /* array size in dwords */;
1336 __le16 offset /* array start offset in dwords */;
1339 /* Write init operation arguments */
1340 union init_write_args {
1343 __le32 array_offset;
1344 struct init_op_array_params runtime;
1347 /* init operation: write */
1348 struct init_write_op {
1350 #define INIT_WRITE_OP_OP_MASK 0xF
1351 #define INIT_WRITE_OP_OP_SHIFT 0
1352 #define INIT_WRITE_OP_SOURCE_MASK 0x7
1353 #define INIT_WRITE_OP_SOURCE_SHIFT 4
1354 #define INIT_WRITE_OP_RESERVED_MASK 0x1
1355 #define INIT_WRITE_OP_RESERVED_SHIFT 7
1356 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
1357 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1358 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
1359 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
1360 union init_write_args args /* Write init operation arguments */;
1363 /* init operation: read */
1364 struct init_read_op {
1366 #define INIT_READ_OP_OP_MASK 0xF
1367 #define INIT_READ_OP_OP_SHIFT 0
1368 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
1369 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
1370 #define INIT_READ_OP_RESERVED_MASK 0x1
1371 #define INIT_READ_OP_RESERVED_SHIFT 8
1372 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
1373 #define INIT_READ_OP_ADDRESS_SHIFT 9
1374 __le32 expected_val;
1377 /* Init operations union */
1379 struct init_raw_op raw /* raw init operation */;
1380 struct init_write_op write /* write init operation */;
1381 struct init_read_op read /* read init operation */;
1382 struct init_if_mode_op if_mode /* if_mode init operation */;
1383 struct init_if_phase_op if_phase /* if_phase init operation */;
1384 struct init_callback_op callback /* callback init operation */;
1385 struct init_delay_op delay /* delay init operation */;
1388 /* Init command operation types */
1389 enum init_op_types {
1390 INIT_OP_READ /* GRC read init command */,
1391 INIT_OP_WRITE /* GRC write init command */,
1394 INIT_OP_DELAY /* delay init command */,
1395 INIT_OP_CALLBACK /* callback init command */,
1399 enum init_poll_types {
1400 INIT_POLL_NONE /* No polling */,
1401 INIT_POLL_EQ /* init value is included in the init command */,
1402 INIT_POLL_OR /* init value is all zeros */,
1403 INIT_POLL_AND /* init value is an array of values */,
1407 /* init source types */
1408 enum init_source_types {
1409 INIT_SRC_INLINE /* init value is included in the init command */,
1410 INIT_SRC_ZEROS /* init value is all zeros */,
1411 INIT_SRC_ARRAY /* init value is an array of values */,
1412 INIT_SRC_RUNTIME /* init value is provided during runtime */,
1413 MAX_INIT_SOURCE_TYPES
1416 /* Internal RAM Offsets macro data */
1418 u32 base /* RAM field offset */;
1419 u16 m1 /* multiplier 1 */;
1420 u16 m2 /* multiplier 2 */;
1421 u16 m3 /* multiplier 3 */;
1422 u16 size /* RAM field size */;
1425 /* QM per-port init parameters */
1426 struct init_qm_port_params {
1427 u8 active /* Indicates if this port is active */;
1428 u8 num_active_phys_tcs;
1429 u16 num_pbf_cmd_lines;
1434 /* QM per-PQ init parameters */
1435 struct init_qm_pq_params {
1436 u8 vport_id /* VPORT ID */;
1437 u8 tc_id /* TC ID */;
1438 u8 wrr_group /* WRR group */;
1442 /* QM per-vport init parameters */
1443 struct init_qm_vport_params {
1446 u16 first_tx_pq_id[NUM_OF_TCS];
1450 #define GTT_BAR0_MAP_REG_IGU_CMD \
1453 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1456 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1459 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1462 #define GTT_BAR0_MAP_REG_USDM_RAM \
1465 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1468 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1471 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1474 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1477 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1481 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1483 * Returns the required host memory size in 4KB units.
1484 * Must be called before all QM init HSI functions.
1486 * @param pf_id - physical function ID
1487 * @param num_pf_cids - number of connections used by this PF
1488 * @param num_vf_cids - number of connections used by VFs of this PF
1489 * @param num_tids - number of tasks used by this PF
1490 * @param num_pf_pqs - number of PQs used by this PF
1491 * @param num_vf_pqs - number of PQs used by VFs of this PF
1493 * @return The required host memory size in 4KB units.
1495 u32 qed_qm_pf_mem_size(u8 pf_id,
1502 struct qed_qm_common_rt_init_params {
1503 u8 max_ports_per_engine;
1504 u8 max_phys_tcs_per_port;
1509 struct init_qm_port_params *port_params;
1513 * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1517 * @param max_ports_per_engine - max number of ports per engine in HW
1518 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1519 * @param pf_rl_en - enable per-PF rate limiters
1520 * @param pf_wfq_en - enable per-PF WFQ
1521 * @param vport_rl_en - enable per-VPORT rate limiters
1522 * @param vport_wfq_en - enable per-VPORT WFQ
1523 * @param port_params - array of size MAX_NUM_PORTS with
1524 * arameters for each port
1526 * @return 0 on success, -1 on error.
1528 int qed_qm_common_rt_init(
1529 struct qed_hwfn *p_hwfn,
1530 struct qed_qm_common_rt_init_params *p_params);
1532 struct qed_qm_pf_rt_init_params {
1535 u8 max_phys_tcs_per_port;
1547 struct init_qm_pq_params *pq_params;
1548 struct init_qm_vport_params *vport_params;
1551 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
1552 struct qed_ptt *p_ptt,
1553 struct qed_qm_pf_rt_init_params *p_params);
1556 * @brief qed_init_pf_rl Initializes the rate limit of the specified PF
1559 * @param p_ptt - ptt window used for writing the registers
1560 * @param pf_id - PF ID
1561 * @param pf_rl - rate limit in Mb/sec units
1563 * @return 0 on success, -1 on error.
1565 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1566 struct qed_ptt *p_ptt,
1571 * @brief qed_init_vport_rl Initializes the rate limit of the specified VPORT
1574 * @param p_ptt - ptt window used for writing the registers
1575 * @param vport_id - VPORT ID
1576 * @param vport_rl - rate limit in Mb/sec units
1578 * @return 0 on success, -1 on error.
1581 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
1582 struct qed_ptt *p_ptt,
1586 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
1589 * @param p_ptt - ptt window used for writing the registers
1590 * @param is_release_cmd - true for release, false for stop.
1591 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
1592 * @param start_pq - first PQ ID to stop
1593 * @param num_pqs - Number of PQs to stop, starting from start_pq.
1595 * @return bool, true if successful, false if timeout occurred while waiting
1596 * for QM command done.
1599 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1600 struct qed_ptt *p_ptt,
1601 bool is_release_cmd,
1606 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1607 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
1608 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
1609 /* Tstorm port statistics */
1610 #define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
1611 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
1612 /* Tstorm ll2 port statistics */
1613 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
1614 (IRO[2].base + ((port_id) * IRO[2].m1))
1615 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
1616 /* Ustorm VF-PF Channel ready flag */
1617 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
1618 (IRO[3].base + ((vf_id) * IRO[3].m1))
1619 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
1620 /* Ustorm Final flr cleanup ack */
1621 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
1622 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
1623 /* Ustorm Event ring consumer */
1624 #define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
1625 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
1626 /* Ustorm Common Queue ring consumer */
1627 #define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
1628 (IRO[6].base + ((global_queue_id) * IRO[6].m1))
1629 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[6].size)
1630 /* Xstorm Integration Test Data */
1631 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
1632 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
1633 /* Ystorm Integration Test Data */
1634 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
1635 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
1636 /* Pstorm Integration Test Data */
1637 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
1638 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
1639 /* Tstorm Integration Test Data */
1640 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
1641 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
1642 /* Mstorm Integration Test Data */
1643 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
1644 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
1645 /* Ustorm Integration Test Data */
1646 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
1647 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
1648 /* Tstorm producers */
1649 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
1650 (IRO[13].base + ((core_rx_queue_id) * IRO[13].m1))
1651 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[13].size)
1652 /* Tstorm LightL2 queue statistics */
1653 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1654 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
1655 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[14].size)
1656 /* Ustorm LiteL2 queue statistics */
1657 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1658 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
1659 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
1660 /* Pstorm LiteL2 queue statistics */
1661 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
1662 (IRO[16].base + ((core_tx_stats_id) * IRO[16].m1))
1663 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
1664 /* Mstorm queue statistics */
1665 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1666 (IRO[17].base + ((stat_counter_id) * IRO[17].m1))
1667 #define MSTORM_QUEUE_STAT_SIZE (IRO[17].size)
1668 /* Mstorm producers */
1669 #define MSTORM_PRODS_OFFSET(queue_id) (IRO[18].base + ((queue_id) * IRO[18].m1))
1670 #define MSTORM_PRODS_SIZE (IRO[18].size)
1671 /* TPA agregation timeout in us resolution (on ASIC) */
1672 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[19].base)
1673 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[19].size)
1674 /* Ustorm queue statistics */
1675 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1676 (IRO[20].base + ((stat_counter_id) * IRO[20].m1))
1677 #define USTORM_QUEUE_STAT_SIZE (IRO[20].size)
1678 /* Ustorm queue zone */
1679 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1680 (IRO[21].base + ((queue_id) * IRO[21].m1))
1681 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[21].size)
1682 /* Pstorm queue statistics */
1683 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1684 (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
1685 #define PSTORM_QUEUE_STAT_SIZE (IRO[22].size)
1686 /* Tstorm last parser message */
1687 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[23].base)
1688 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[23].size)
1689 /* Tstorm Eth limit Rx rate */
1690 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
1691 #define ETH_RX_RATE_LIMIT_SIZE (IRO[24].size)
1692 /* Ystorm queue zone */
1693 #define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1694 (IRO[25].base + ((queue_id) * IRO[25].m1))
1695 #define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[25].size)
1696 /* Ystorm cqe producer */
1697 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1698 (IRO[26].base + ((rss_id) * IRO[26].m1))
1699 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[26].size)
1700 /* Ustorm cqe producer */
1701 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1702 (IRO[27].base + ((rss_id) * IRO[27].m1))
1703 #define USTORM_TOE_CQ_PROD_SIZE (IRO[27].size)
1704 /* Ustorm grq producer */
1705 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
1706 (IRO[28].base + ((pf_id) * IRO[28].m1))
1707 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[28].size)
1708 /* Tstorm cmdq-cons of given command queue-id */
1709 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
1710 (IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
1711 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[29].size)
1712 /* Mstorm rq-cons of given queue-id */
1713 #define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
1714 (IRO[30].base + ((rq_queue_id) * IRO[30].m1))
1715 #define MSTORM_SCSI_RQ_CONS_SIZE (IRO[30].size)
1716 /* Mstorm bdq-external-producer of given BDQ function ID, BDqueue-id */
1717 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1718 (IRO[31].base + ((func_id) * IRO[31].m1) + ((bdq_id) * IRO[31].m2))
1719 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[31].size)
1720 /* Tstorm (reflects M-Storm) bdq-external-producer of given fn ID, BDqueue-id */
1721 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1722 (IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
1723 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
1724 /* Tstorm iSCSI RX stats */
1725 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1726 (IRO[33].base + ((pf_id) * IRO[33].m1))
1727 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[33].size)
1728 /* Mstorm iSCSI RX stats */
1729 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1730 (IRO[34].base + ((pf_id) * IRO[34].m1))
1731 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[34].size)
1732 /* Ustorm iSCSI RX stats */
1733 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1734 (IRO[35].base + ((pf_id) * IRO[35].m1))
1735 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[35].size)
1736 /* Xstorm iSCSI TX stats */
1737 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1738 (IRO[36].base + ((pf_id) * IRO[36].m1))
1739 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[36].size)
1740 /* Ystorm iSCSI TX stats */
1741 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1742 (IRO[37].base + ((pf_id) * IRO[37].m1))
1743 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[37].size)
1744 /* Pstorm iSCSI TX stats */
1745 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1746 (IRO[38].base + ((pf_id) * IRO[38].m1))
1747 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[38].size)
1748 /* Tstorm FCoE RX stats */
1749 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1750 (IRO[39].base + ((pf_id) * IRO[39].m1))
1751 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[39].size)
1752 /* Mstorm FCoE RX stats */
1753 #define MSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1754 (IRO[40].base + ((pf_id) * IRO[40].m1))
1755 #define MSTORM_FCOE_RX_STATS_SIZE (IRO[40].size)
1756 /* Pstorm FCoE TX stats */
1757 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
1758 (IRO[41].base + ((pf_id) * IRO[41].m1))
1759 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[41].size)
1760 /* Pstorm RoCE statistics */
1761 #define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1762 (IRO[42].base + ((stat_counter_id) * IRO[42].m1))
1763 #define PSTORM_ROCE_STAT_SIZE (IRO[42].size)
1764 /* Tstorm RoCE statistics */
1765 #define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1766 (IRO[43].base + ((stat_counter_id) * IRO[43].m1))
1767 #define TSTORM_ROCE_STAT_SIZE (IRO[43].size)
1769 static const struct iro iro_arr[44] = {
1770 { 0x10, 0x0, 0x0, 0x0, 0x8 },
1771 { 0x47c8, 0x60, 0x0, 0x0, 0x60 },
1772 { 0x5e30, 0x20, 0x0, 0x0, 0x20 },
1773 { 0x510, 0x8, 0x0, 0x0, 0x4 },
1774 { 0x490, 0x8, 0x0, 0x0, 0x4 },
1775 { 0x10, 0x8, 0x0, 0x0, 0x2 },
1776 { 0x90, 0x8, 0x0, 0x0, 0x2 },
1777 { 0x4940, 0x0, 0x0, 0x0, 0x78 },
1778 { 0x3de0, 0x0, 0x0, 0x0, 0x78 },
1779 { 0x2998, 0x0, 0x0, 0x0, 0x78 },
1780 { 0x4750, 0x0, 0x0, 0x0, 0x78 },
1781 { 0x56d0, 0x0, 0x0, 0x0, 0x78 },
1782 { 0x7e50, 0x0, 0x0, 0x0, 0x78 },
1783 { 0x100, 0x8, 0x0, 0x0, 0x8 },
1784 { 0x5c10, 0x10, 0x0, 0x0, 0x10 },
1785 { 0xb508, 0x30, 0x0, 0x0, 0x30 },
1786 { 0x95c0, 0x30, 0x0, 0x0, 0x30 },
1787 { 0x58a0, 0x40, 0x0, 0x0, 0x40 },
1788 { 0x200, 0x10, 0x0, 0x0, 0x8 },
1789 { 0xa230, 0x0, 0x0, 0x0, 0x4 },
1790 { 0x8058, 0x40, 0x0, 0x0, 0x30 },
1791 { 0xd00, 0x8, 0x0, 0x0, 0x8 },
1792 { 0x2b30, 0x80, 0x0, 0x0, 0x38 },
1793 { 0xa808, 0x0, 0x0, 0x0, 0xf0 },
1794 { 0xa8f8, 0x8, 0x0, 0x0, 0x8 },
1795 { 0x80, 0x8, 0x0, 0x0, 0x8 },
1796 { 0xac0, 0x8, 0x0, 0x0, 0x8 },
1797 { 0x2580, 0x8, 0x0, 0x0, 0x8 },
1798 { 0x2500, 0x8, 0x0, 0x0, 0x8 },
1799 { 0x440, 0x8, 0x0, 0x0, 0x2 },
1800 { 0x1800, 0x8, 0x0, 0x0, 0x2 },
1801 { 0x1a00, 0x10, 0x8, 0x0, 0x2 },
1802 { 0x640, 0x10, 0x8, 0x0, 0x2 },
1803 { 0xd9b8, 0x38, 0x0, 0x0, 0x24 },
1804 { 0x11048, 0x10, 0x0, 0x0, 0x8 },
1805 { 0x11678, 0x38, 0x0, 0x0, 0x18 },
1806 { 0xaec0, 0x30, 0x0, 0x0, 0x10 },
1807 { 0x8700, 0x28, 0x0, 0x0, 0x18 },
1808 { 0xec00, 0x10, 0x0, 0x0, 0x10 },
1809 { 0xde38, 0x40, 0x0, 0x0, 0x30 },
1810 { 0x121a8, 0x38, 0x0, 0x0, 0x8 },
1811 { 0xf068, 0x20, 0x0, 0x0, 0x20 },
1812 { 0x2b68, 0x80, 0x0, 0x0, 0x10 },
1813 { 0x4ab8, 0x10, 0x0, 0x0, 0x10 },
1816 /* Runtime array offsets */
1817 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
1818 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
1819 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
1820 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
1821 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
1822 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
1823 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
1824 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
1825 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
1826 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
1827 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
1828 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
1829 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
1830 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
1831 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
1832 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
1833 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
1834 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
1835 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
1836 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
1837 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
1838 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
1839 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
1840 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
1841 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
1842 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1843 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1844 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1845 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1846 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
1847 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
1848 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
1849 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
1850 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
1851 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
1852 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
1853 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
1854 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
1855 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
1856 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
1857 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
1858 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
1859 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
1860 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
1861 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
1862 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
1863 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
1864 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
1865 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
1866 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
1867 #define SRC_REG_FIRSTFREE_RT_SIZE 2
1868 #define SRC_REG_LASTFREE_RT_OFFSET 6667
1869 #define SRC_REG_LASTFREE_RT_SIZE 2
1870 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
1871 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
1872 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
1873 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
1874 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
1875 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
1876 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
1877 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6676
1878 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6677
1879 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6678
1880 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6679
1881 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6680
1882 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6681
1883 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6682
1884 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6683
1885 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6684
1886 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6685
1887 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6686
1888 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6687
1889 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6688
1890 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
1891 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
1892 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6691
1893 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6692
1894 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6693
1895 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6694
1896 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6695
1897 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6696
1898 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6697
1899 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6698
1900 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6699
1901 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6700
1902 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6701
1903 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6702
1904 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6703
1905 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
1906 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28703
1907 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28704
1908 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28705
1909 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28706
1910 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28707
1911 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28708
1912 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28709
1913 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28710
1914 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28711
1915 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28712
1916 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28713
1917 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
1918 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29129
1919 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
1920 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29641
1921 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29642
1922 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29643
1923 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29644
1924 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29645
1925 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29646
1926 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29647
1927 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29648
1928 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29649
1929 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29650
1930 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29651
1931 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29652
1932 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29653
1933 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29654
1934 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29655
1935 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29656
1936 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29657
1937 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29658
1938 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29659
1939 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29660
1940 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29661
1941 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29662
1942 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29663
1943 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29664
1944 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29665
1945 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29666
1946 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29667
1947 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29668
1948 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29669
1949 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29670
1950 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29671
1951 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29672
1952 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29673
1953 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29674
1954 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29675
1955 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29676
1956 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29677
1957 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29678
1958 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29679
1959 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29680
1960 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29681
1961 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29682
1962 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29683
1963 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29684
1964 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29685
1965 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29686
1966 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29687
1967 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29688
1968 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29689
1969 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29690
1970 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29691
1971 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29692
1972 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29693
1973 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29694
1974 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29695
1975 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29696
1976 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29697
1977 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29698
1978 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29699
1979 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29700
1980 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29701
1981 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29702
1982 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29703
1983 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29704
1984 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29705
1985 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29706
1986 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29707
1987 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29708
1988 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
1989 #define QM_REG_VOQCRDLINE_RT_OFFSET 29836
1990 #define QM_REG_VOQCRDLINE_RT_SIZE 20
1991 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29856
1992 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
1993 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29876
1994 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29877
1995 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29878
1996 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29879
1997 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29880
1998 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29881
1999 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29882
2000 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29883
2001 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29884
2002 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29885
2003 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29886
2004 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29887
2005 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29888
2006 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29889
2007 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29890
2008 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29891
2009 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29892
2010 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29893
2011 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29894
2012 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29895
2013 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29896
2014 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29897
2015 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29898
2016 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29899
2017 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29900
2018 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29901
2019 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29902
2020 #define QM_REG_PQTX2PF_0_RT_OFFSET 29903
2021 #define QM_REG_PQTX2PF_1_RT_OFFSET 29904
2022 #define QM_REG_PQTX2PF_2_RT_OFFSET 29905
2023 #define QM_REG_PQTX2PF_3_RT_OFFSET 29906
2024 #define QM_REG_PQTX2PF_4_RT_OFFSET 29907
2025 #define QM_REG_PQTX2PF_5_RT_OFFSET 29908
2026 #define QM_REG_PQTX2PF_6_RT_OFFSET 29909
2027 #define QM_REG_PQTX2PF_7_RT_OFFSET 29910
2028 #define QM_REG_PQTX2PF_8_RT_OFFSET 29911
2029 #define QM_REG_PQTX2PF_9_RT_OFFSET 29912
2030 #define QM_REG_PQTX2PF_10_RT_OFFSET 29913
2031 #define QM_REG_PQTX2PF_11_RT_OFFSET 29914
2032 #define QM_REG_PQTX2PF_12_RT_OFFSET 29915
2033 #define QM_REG_PQTX2PF_13_RT_OFFSET 29916
2034 #define QM_REG_PQTX2PF_14_RT_OFFSET 29917
2035 #define QM_REG_PQTX2PF_15_RT_OFFSET 29918
2036 #define QM_REG_PQTX2PF_16_RT_OFFSET 29919
2037 #define QM_REG_PQTX2PF_17_RT_OFFSET 29920
2038 #define QM_REG_PQTX2PF_18_RT_OFFSET 29921
2039 #define QM_REG_PQTX2PF_19_RT_OFFSET 29922
2040 #define QM_REG_PQTX2PF_20_RT_OFFSET 29923
2041 #define QM_REG_PQTX2PF_21_RT_OFFSET 29924
2042 #define QM_REG_PQTX2PF_22_RT_OFFSET 29925
2043 #define QM_REG_PQTX2PF_23_RT_OFFSET 29926
2044 #define QM_REG_PQTX2PF_24_RT_OFFSET 29927
2045 #define QM_REG_PQTX2PF_25_RT_OFFSET 29928
2046 #define QM_REG_PQTX2PF_26_RT_OFFSET 29929
2047 #define QM_REG_PQTX2PF_27_RT_OFFSET 29930
2048 #define QM_REG_PQTX2PF_28_RT_OFFSET 29931
2049 #define QM_REG_PQTX2PF_29_RT_OFFSET 29932
2050 #define QM_REG_PQTX2PF_30_RT_OFFSET 29933
2051 #define QM_REG_PQTX2PF_31_RT_OFFSET 29934
2052 #define QM_REG_PQTX2PF_32_RT_OFFSET 29935
2053 #define QM_REG_PQTX2PF_33_RT_OFFSET 29936
2054 #define QM_REG_PQTX2PF_34_RT_OFFSET 29937
2055 #define QM_REG_PQTX2PF_35_RT_OFFSET 29938
2056 #define QM_REG_PQTX2PF_36_RT_OFFSET 29939
2057 #define QM_REG_PQTX2PF_37_RT_OFFSET 29940
2058 #define QM_REG_PQTX2PF_38_RT_OFFSET 29941
2059 #define QM_REG_PQTX2PF_39_RT_OFFSET 29942
2060 #define QM_REG_PQTX2PF_40_RT_OFFSET 29943
2061 #define QM_REG_PQTX2PF_41_RT_OFFSET 29944
2062 #define QM_REG_PQTX2PF_42_RT_OFFSET 29945
2063 #define QM_REG_PQTX2PF_43_RT_OFFSET 29946
2064 #define QM_REG_PQTX2PF_44_RT_OFFSET 29947
2065 #define QM_REG_PQTX2PF_45_RT_OFFSET 29948
2066 #define QM_REG_PQTX2PF_46_RT_OFFSET 29949
2067 #define QM_REG_PQTX2PF_47_RT_OFFSET 29950
2068 #define QM_REG_PQTX2PF_48_RT_OFFSET 29951
2069 #define QM_REG_PQTX2PF_49_RT_OFFSET 29952
2070 #define QM_REG_PQTX2PF_50_RT_OFFSET 29953
2071 #define QM_REG_PQTX2PF_51_RT_OFFSET 29954
2072 #define QM_REG_PQTX2PF_52_RT_OFFSET 29955
2073 #define QM_REG_PQTX2PF_53_RT_OFFSET 29956
2074 #define QM_REG_PQTX2PF_54_RT_OFFSET 29957
2075 #define QM_REG_PQTX2PF_55_RT_OFFSET 29958
2076 #define QM_REG_PQTX2PF_56_RT_OFFSET 29959
2077 #define QM_REG_PQTX2PF_57_RT_OFFSET 29960
2078 #define QM_REG_PQTX2PF_58_RT_OFFSET 29961
2079 #define QM_REG_PQTX2PF_59_RT_OFFSET 29962
2080 #define QM_REG_PQTX2PF_60_RT_OFFSET 29963
2081 #define QM_REG_PQTX2PF_61_RT_OFFSET 29964
2082 #define QM_REG_PQTX2PF_62_RT_OFFSET 29965
2083 #define QM_REG_PQTX2PF_63_RT_OFFSET 29966
2084 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29967
2085 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29968
2086 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29969
2087 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29970
2088 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29971
2089 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29972
2090 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29973
2091 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29974
2092 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29975
2093 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29976
2094 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29977
2095 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29978
2096 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29979
2097 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29980
2098 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29981
2099 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29982
2100 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29983
2101 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29984
2102 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29985
2103 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29986
2104 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29987
2105 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29988
2106 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29989
2107 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29990
2108 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29991
2109 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29992
2110 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29993
2111 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29994
2112 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29995
2113 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
2114 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30251
2115 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
2116 #define QM_REG_RLGLBLCRD_RT_OFFSET 30507
2117 #define QM_REG_RLGLBLCRD_RT_SIZE 256
2118 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30763
2119 #define QM_REG_RLPFPERIOD_RT_OFFSET 30764
2120 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30765
2121 #define QM_REG_RLPFINCVAL_RT_OFFSET 30766
2122 #define QM_REG_RLPFINCVAL_RT_SIZE 16
2123 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30782
2124 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
2125 #define QM_REG_RLPFCRD_RT_OFFSET 30798
2126 #define QM_REG_RLPFCRD_RT_SIZE 16
2127 #define QM_REG_RLPFENABLE_RT_OFFSET 30814
2128 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30815
2129 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30816
2130 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
2131 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30832
2132 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
2133 #define QM_REG_WFQPFCRD_RT_OFFSET 30848
2134 #define QM_REG_WFQPFCRD_RT_SIZE 160
2135 #define QM_REG_WFQPFENABLE_RT_OFFSET 31008
2136 #define QM_REG_WFQVPENABLE_RT_OFFSET 31009
2137 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31010
2138 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
2139 #define QM_REG_TXPQMAP_RT_OFFSET 31522
2140 #define QM_REG_TXPQMAP_RT_SIZE 512
2141 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32034
2142 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
2143 #define QM_REG_WFQVPCRD_RT_OFFSET 32546
2144 #define QM_REG_WFQVPCRD_RT_SIZE 512
2145 #define QM_REG_WFQVPMAP_RT_OFFSET 33058
2146 #define QM_REG_WFQVPMAP_RT_SIZE 512
2147 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33570
2148 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
2149 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33730
2150 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33731
2151 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33732
2152 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33733
2153 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33734
2154 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33735
2155 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33736
2156 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33737
2157 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
2158 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33741
2159 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
2160 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33745
2161 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
2162 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33749
2163 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33750
2164 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
2165 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33782
2166 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
2167 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33798
2168 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
2169 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33814
2170 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
2171 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33830
2172 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
2173 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33846
2174 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33847
2175 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33848
2176 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33849
2177 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33850
2178 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33851
2179 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33852
2180 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33853
2181 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33854
2182 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33855
2183 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33856
2184 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33857
2185 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33858
2186 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33859
2187 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33860
2188 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33861
2189 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33862
2190 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33863
2191 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33864
2192 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33865
2193 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33866
2194 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33867
2195 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33868
2196 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33869
2197 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33870
2198 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33871
2199 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33872
2200 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33873
2201 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33874
2202 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33875
2203 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33876
2204 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33877
2205 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33878
2206 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33879
2207 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33880
2208 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33881
2209 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33882
2210 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33883
2211 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33884
2212 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33885
2213 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33886
2214 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33887
2215 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33888
2216 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33889
2217 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33890
2218 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33891
2219 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33892
2220 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33893
2221 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33894
2222 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33895
2223 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33896
2224 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33897
2225 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33898
2226 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33899
2227 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33900
2228 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33901
2229 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33902
2230 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33903
2231 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33904
2232 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33905
2233 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33906
2234 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33907
2235 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33908
2236 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33909
2237 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33910
2238 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33911
2239 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33912
2240 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33913
2241 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33914
2242 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33915
2243 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33916
2244 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33917
2245 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33918
2246 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33919
2247 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33920
2248 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33921
2249 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33922
2251 #define RUNTIME_ARRAY_SIZE 33923
2253 /* The eth storm context for the Tstorm */
2254 struct tstorm_eth_conn_st_ctx {
2258 /* The eth storm context for the Pstorm */
2259 struct pstorm_eth_conn_st_ctx {
2263 /* The eth storm context for the Xstorm */
2264 struct xstorm_eth_conn_st_ctx {
2265 __le32 reserved[60];
2268 struct xstorm_eth_conn_ag_ctx {
2269 u8 reserved0 /* cdu_validation */;
2270 u8 eth_state /* state */;
2272 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2273 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2274 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
2275 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
2276 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
2277 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
2278 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2279 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2280 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2281 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
2282 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
2283 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
2284 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2285 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
2286 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2287 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
2289 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2290 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
2291 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2292 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
2293 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
2294 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
2295 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2296 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
2297 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2298 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
2299 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2300 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
2301 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
2302 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2303 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
2304 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2306 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2307 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
2308 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2309 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
2310 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2311 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
2312 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2313 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
2315 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2316 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
2317 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2318 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
2319 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2320 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
2321 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2322 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
2324 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2325 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
2326 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2327 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
2328 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2329 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
2330 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2331 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
2333 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2334 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
2335 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2336 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
2337 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2338 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
2339 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2340 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
2342 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
2343 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2344 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2345 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2346 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
2347 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
2348 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
2349 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2351 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
2352 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2353 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
2354 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
2355 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2356 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2357 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2358 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
2359 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2360 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
2362 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2363 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
2364 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2365 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
2366 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2367 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
2368 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2369 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
2370 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2371 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
2372 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2373 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
2374 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2375 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
2376 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2377 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
2379 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2380 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
2381 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2382 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
2383 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2384 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
2385 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2386 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
2387 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2388 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
2389 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2390 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
2391 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */
2392 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2393 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2394 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2396 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
2397 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2398 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
2399 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2400 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
2401 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2402 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
2403 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
2404 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2405 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2406 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */
2407 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2408 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
2409 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
2410 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
2411 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
2413 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
2414 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
2415 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
2416 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
2417 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
2418 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2419 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2420 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
2421 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2422 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
2423 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2424 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
2425 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2426 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2427 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2428 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
2430 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2431 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
2432 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2433 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
2434 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2435 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2436 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2437 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2438 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2439 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
2440 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2441 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
2442 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2443 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
2444 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2445 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
2447 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2448 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
2449 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2450 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
2451 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2452 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2453 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2454 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2455 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2456 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2457 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2458 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2459 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2460 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2461 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2462 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2464 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */
2465 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2466 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */
2467 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2468 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */
2469 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2470 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */
2471 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2472 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */
2473 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2474 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2475 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2476 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2477 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2478 u8 edpm_event_id /* byte2 */;
2479 __le16 physical_q0 /* physical_q0 */;
2480 __le16 word1 /* physical_q1 */;
2481 __le16 edpm_num_bds /* physical_q2 */;
2482 __le16 tx_bd_cons /* word3 */;
2483 __le16 tx_bd_prod /* word4 */;
2484 __le16 go_to_bd_cons /* word5 */;
2485 __le16 conn_dpi /* conn_dpi */;
2486 u8 byte3 /* byte3 */;
2487 u8 byte4 /* byte4 */;
2488 u8 byte5 /* byte5 */;
2489 u8 byte6 /* byte6 */;
2490 __le32 reg0 /* reg0 */;
2491 __le32 reg1 /* reg1 */;
2492 __le32 reg2 /* reg2 */;
2493 __le32 reg3 /* reg3 */;
2494 __le32 reg4 /* reg4 */;
2495 __le32 reg5 /* cf_array0 */;
2496 __le32 reg6 /* cf_array1 */;
2497 __le16 word7 /* word7 */;
2498 __le16 word8 /* word8 */;
2499 __le16 word9 /* word9 */;
2500 __le16 word10 /* word10 */;
2501 __le32 reg7 /* reg7 */;
2502 __le32 reg8 /* reg8 */;
2503 __le32 reg9 /* reg9 */;
2504 u8 byte7 /* byte7 */;
2505 u8 byte8 /* byte8 */;
2506 u8 byte9 /* byte9 */;
2507 u8 byte10 /* byte10 */;
2508 u8 byte11 /* byte11 */;
2509 u8 byte12 /* byte12 */;
2510 u8 byte13 /* byte13 */;
2511 u8 byte14 /* byte14 */;
2512 u8 byte15 /* byte15 */;
2513 u8 byte16 /* byte16 */;
2514 __le16 word11 /* word11 */;
2515 __le32 reg10 /* reg10 */;
2516 __le32 reg11 /* reg11 */;
2517 __le32 reg12 /* reg12 */;
2518 __le32 reg13 /* reg13 */;
2519 __le32 reg14 /* reg14 */;
2520 __le32 reg15 /* reg15 */;
2521 __le32 reg16 /* reg16 */;
2522 __le32 reg17 /* reg17 */;
2523 __le32 reg18 /* reg18 */;
2524 __le32 reg19 /* reg19 */;
2525 __le16 word12 /* word12 */;
2526 __le16 word13 /* word13 */;
2527 __le16 word14 /* word14 */;
2528 __le16 word15 /* word15 */;
2531 /* The eth storm context for the Ystorm */
2532 struct ystorm_eth_conn_st_ctx {
2536 struct ystorm_eth_conn_ag_ctx {
2537 u8 byte0 /* cdu_validation */;
2538 u8 byte1 /* state */;
2540 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2541 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2542 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2543 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2544 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
2545 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
2546 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
2547 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
2548 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2549 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2551 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */
2552 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
2553 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2554 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
2555 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2556 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2557 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2558 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
2559 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2560 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
2561 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2562 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
2563 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2564 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
2565 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2566 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
2567 u8 byte2 /* byte2 */;
2568 u8 byte3 /* byte3 */;
2569 __le16 word0 /* word0 */;
2570 __le32 terminate_spqe /* reg0 */;
2571 __le32 reg1 /* reg1 */;
2572 __le16 tx_bd_cons_upd /* word1 */;
2573 __le16 word2 /* word2 */;
2574 __le16 word3 /* word3 */;
2575 __le16 word4 /* word4 */;
2576 __le32 reg2 /* reg2 */;
2577 __le32 reg3 /* reg3 */;
2580 struct tstorm_eth_conn_ag_ctx {
2581 u8 byte0 /* cdu_validation */;
2582 u8 byte1 /* state */;
2584 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2585 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2586 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2587 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2588 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
2589 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
2590 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
2591 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
2592 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
2593 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
2594 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
2595 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
2596 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2597 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
2599 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2600 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
2601 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2602 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
2603 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2604 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
2605 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2606 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
2608 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2609 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
2610 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2611 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
2612 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2613 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
2614 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2615 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
2617 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2618 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
2619 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2620 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
2621 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2622 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
2623 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2624 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
2625 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2626 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
2627 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2628 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
2630 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2631 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
2632 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2633 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
2634 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2635 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
2636 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2637 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
2638 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2639 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
2640 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2641 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
2642 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2643 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
2644 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2645 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2647 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2648 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2649 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2650 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2651 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2652 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2653 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2654 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2655 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2656 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2657 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
2658 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2659 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2660 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2661 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2662 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2663 __le32 reg0 /* reg0 */;
2664 __le32 reg1 /* reg1 */;
2665 __le32 reg2 /* reg2 */;
2666 __le32 reg3 /* reg3 */;
2667 __le32 reg4 /* reg4 */;
2668 __le32 reg5 /* reg5 */;
2669 __le32 reg6 /* reg6 */;
2670 __le32 reg7 /* reg7 */;
2671 __le32 reg8 /* reg8 */;
2672 u8 byte2 /* byte2 */;
2673 u8 byte3 /* byte3 */;
2674 __le16 rx_bd_cons /* word0 */;
2675 u8 byte4 /* byte4 */;
2676 u8 byte5 /* byte5 */;
2677 __le16 rx_bd_prod /* word1 */;
2678 __le16 word2 /* conn_dpi */;
2679 __le16 word3 /* word3 */;
2680 __le32 reg9 /* reg9 */;
2681 __le32 reg10 /* reg10 */;
2684 struct ustorm_eth_conn_ag_ctx {
2685 u8 byte0 /* cdu_validation */;
2686 u8 byte1 /* state */;
2688 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2689 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2690 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2691 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2692 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */
2693 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
2694 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */
2695 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
2696 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2697 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2699 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2700 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
2701 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */
2702 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
2703 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */
2704 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
2705 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */
2706 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
2708 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */
2709 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
2710 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2711 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
2712 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2713 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2714 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2715 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
2716 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */
2717 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
2718 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */
2719 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
2720 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */
2721 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
2722 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2723 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2725 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2726 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2727 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2728 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2729 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2730 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2731 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2732 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2733 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2734 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2735 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2736 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
2737 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2738 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2739 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2740 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2741 u8 byte2 /* byte2 */;
2742 u8 byte3 /* byte3 */;
2743 __le16 word0 /* conn_dpi */;
2744 __le16 tx_bd_cons /* word1 */;
2745 __le32 reg0 /* reg0 */;
2746 __le32 reg1 /* reg1 */;
2747 __le32 reg2 /* reg2 */;
2748 __le32 tx_int_coallecing_timeset /* reg3 */;
2749 __le16 tx_drv_bd_cons /* word2 */;
2750 __le16 rx_drv_cqe_cons /* word3 */;
2753 /* The eth storm context for the Ustorm */
2754 struct ustorm_eth_conn_st_ctx {
2755 __le32 reserved[40];
2758 /* The eth storm context for the Mstorm */
2759 struct mstorm_eth_conn_st_ctx {
2763 /* eth connection context */
2764 struct eth_conn_context {
2765 struct tstorm_eth_conn_st_ctx tstorm_st_context;
2766 struct regpair tstorm_st_padding[2];
2767 struct pstorm_eth_conn_st_ctx pstorm_st_context;
2768 struct xstorm_eth_conn_st_ctx xstorm_st_context;
2769 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
2770 struct ystorm_eth_conn_st_ctx ystorm_st_context;
2771 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
2772 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
2773 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
2774 struct ustorm_eth_conn_st_ctx ustorm_st_context;
2775 struct mstorm_eth_conn_st_ctx mstorm_st_context;
2778 enum eth_filter_action {
2779 ETH_FILTER_ACTION_REMOVE,
2780 ETH_FILTER_ACTION_ADD,
2781 ETH_FILTER_ACTION_REMOVE_ALL,
2782 MAX_ETH_FILTER_ACTION
2785 struct eth_filter_cmd {
2786 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2787 u8 vport_id /* the vport id */;
2788 u8 action /* filter command action: add/remove/replace */;
2797 struct eth_filter_cmd_header {
2805 enum eth_filter_type {
2806 ETH_FILTER_TYPE_MAC,
2807 ETH_FILTER_TYPE_VLAN,
2808 ETH_FILTER_TYPE_PAIR,
2809 ETH_FILTER_TYPE_INNER_MAC,
2810 ETH_FILTER_TYPE_INNER_VLAN,
2811 ETH_FILTER_TYPE_INNER_PAIR,
2812 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2813 ETH_FILTER_TYPE_MAC_VNI_PAIR,
2814 ETH_FILTER_TYPE_VNI,
2818 enum eth_ramrod_cmd_id {
2820 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2821 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2822 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2823 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2824 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2825 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2826 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2827 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2828 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2829 ETH_RAMROD_RESERVED,
2830 ETH_RAMROD_RESERVED2,
2831 ETH_RAMROD_RESERVED3,
2832 ETH_RAMROD_RESERVED4,
2833 ETH_RAMROD_RESERVED5,
2834 ETH_RAMROD_RESERVED6,
2835 ETH_RAMROD_RESERVED7,
2836 ETH_RAMROD_RESERVED8,
2837 MAX_ETH_RAMROD_CMD_ID
2841 ETH_TX_ERR_DROP /* Drop erronous packet. */,
2842 ETH_TX_ERR_ASSERT_MALICIOUS,
2846 struct eth_tx_err_vals {
2848 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
2849 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
2850 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
2851 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
2852 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
2853 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
2854 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
2855 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
2856 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
2857 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
2858 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
2859 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
2860 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
2861 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
2862 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
2863 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
2866 struct eth_vport_rss_config {
2867 __le16 capabilities;
2868 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
2869 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
2870 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
2871 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
2872 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
2873 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
2874 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
2875 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
2876 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
2877 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
2878 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
2879 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
2880 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
2881 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2882 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
2883 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
2887 u8 update_rss_ind_table;
2888 u8 update_rss_capabilities;
2890 __le32 reserved2[2];
2891 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2892 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2893 __le32 reserved3[2];
2896 enum eth_vport_rss_mode {
2897 ETH_VPORT_RSS_MODE_DISABLED,
2898 ETH_VPORT_RSS_MODE_REGULAR,
2899 MAX_ETH_VPORT_RSS_MODE
2902 struct eth_vport_rx_mode {
2904 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
2905 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
2906 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2907 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2908 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
2909 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
2910 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
2911 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
2912 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2913 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
2914 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2915 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
2916 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
2917 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
2918 __le16 reserved2[3];
2921 struct eth_vport_tpa_param {
2925 struct eth_vport_tx_mode {
2927 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
2928 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
2929 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2930 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2931 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
2932 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
2933 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2934 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
2935 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2936 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
2937 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
2938 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
2939 __le16 reserved2[3];
2942 struct rx_queue_start_ramrod_data {
2944 __le16 num_of_pbl_pages;
2945 __le16 bd_max_bytes;
2949 u8 default_rss_queue_flg;
2950 u8 complete_cqe_flg;
2951 u8 complete_event_flg;
2952 u8 stats_counter_id;
2954 u8 pxp_tph_valid_bd;
2955 u8 pxp_tph_valid_pkt;
2957 __le16 pxp_st_index;
2963 struct regpair cqe_pbl_addr;
2964 struct regpair bd_base;
2965 struct regpair reserved2;
2968 struct rx_queue_stop_ramrod_data {
2970 u8 complete_cqe_flg;
2971 u8 complete_event_flg;
2976 struct rx_queue_update_ramrod_data {
2978 u8 complete_cqe_flg;
2979 u8 complete_event_flg;
2987 struct regpair reserved6;
2990 struct tx_queue_start_ramrod_data {
2995 u8 stats_counter_id;
2998 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
2999 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
3000 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
3001 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
3002 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
3003 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
3004 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
3005 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
3006 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
3007 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
3008 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
3009 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
3010 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
3011 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
3013 u8 pxp_tph_valid_bd;
3014 u8 pxp_tph_valid_pkt;
3015 __le16 pxp_st_index;
3016 __le16 comp_agg_size;
3017 __le16 queue_zone_id;
3018 __le16 test_dup_count;
3021 struct regpair pbl_base_addr;
3022 struct regpair bd_cons_address;
3025 struct tx_queue_stop_ramrod_data {
3029 struct vport_filter_update_ramrod_data {
3030 struct eth_filter_cmd_header filter_cmd_hdr;
3031 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
3034 struct vport_start_ramrod_data {
3039 u8 inner_vlan_removal_en;
3040 struct eth_vport_rx_mode rx_mode;
3041 struct eth_vport_tx_mode tx_mode;
3042 struct eth_vport_tpa_param tpa_param;
3043 __le16 default_vlan;
3045 u8 anti_spoofing_en;
3048 u8 silent_vlan_removal_en;
3050 struct eth_tx_err_vals tx_err_behav;
3051 u8 zero_placement_offset;
3055 struct vport_stop_ramrod_data {
3060 struct vport_update_ramrod_data_cmn {
3062 u8 update_rx_active_flg;
3064 u8 update_tx_active_flg;
3066 u8 update_rx_mode_flg;
3067 u8 update_tx_mode_flg;
3068 u8 update_approx_mcast_flg;
3070 u8 update_inner_vlan_removal_en_flg;
3071 u8 inner_vlan_removal_en;
3072 u8 update_tpa_param_flg;
3073 u8 update_tpa_en_flg;
3074 u8 update_tx_switching_en_flg;
3076 u8 update_anti_spoofing_en_flg;
3077 u8 anti_spoofing_en;
3078 u8 update_handle_ptp_pkts;
3080 u8 update_default_vlan_en_flg;
3082 u8 update_default_vlan_flg;
3083 __le16 default_vlan;
3084 u8 update_accept_any_vlan_flg;
3086 u8 silent_vlan_removal_en;
3092 struct vport_update_ramrod_mcast {
3093 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3096 struct vport_update_ramrod_data {
3097 struct vport_update_ramrod_data_cmn common;
3098 struct eth_vport_rx_mode rx_mode;
3099 struct eth_vport_tx_mode tx_mode;
3100 struct eth_vport_tpa_param tpa_param;
3101 struct vport_update_ramrod_mcast approx_mcast;
3102 struct eth_vport_rss_config rss_config;
3105 #define VF_MAX_STATIC 192 /* In case of K2 */
3107 #define MCP_GLOB_PATH_MAX 2
3108 #define MCP_PORT_MAX 2 /* Global */
3109 #define MCP_GLOB_PORT_MAX 4 /* Global */
3110 #define MCP_GLOB_FUNC_MAX 16 /* Global */
3112 typedef u32 offsize_t; /* In DWORDS !!! */
3113 /* Offset from the beginning of the MCP scratchpad */
3114 #define OFFSIZE_OFFSET_SHIFT 0
3115 #define OFFSIZE_OFFSET_MASK 0x0000ffff
3116 /* Size of specific element (not the whole array if any) */
3117 #define OFFSIZE_SIZE_SHIFT 16
3118 #define OFFSIZE_SIZE_MASK 0xffff0000
3120 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3121 #define SECTION_OFFSET(_offsize) ((((_offsize & \
3122 OFFSIZE_OFFSET_MASK) >> \
3123 OFFSIZE_OFFSET_SHIFT) << 2))
3125 /* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3126 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
3127 OFFSIZE_SIZE_MASK) >> \
3128 OFFSIZE_SIZE_SHIFT) << 2)
3130 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3133 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
3134 SECTION_OFFSET(_offsize) + \
3135 (QED_SECTION_SIZE(_offsize) * idx))
3137 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3138 * Use offsetof, since the OFFSETUP collide with the firmware definition
3140 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + \
3143 sections[_section]))
3144 /* PHY configuration */
3145 struct pmm_phy_cfg {
3147 #define PMM_SPEED_AUTONEG 0
3149 u32 pause; /* bitmask */
3150 #define PMM_PAUSE_NONE 0x0
3151 #define PMM_PAUSE_AUTONEG 0x1
3152 #define PMM_PAUSE_RX 0x2
3153 #define PMM_PAUSE_TX 0x4
3155 u32 adv_speed; /* Default should be the speed_cap_mask */
3157 #define PMM_LOOPBACK_NONE 0
3158 #define PMM_LOOPBACK_INT_PHY 1
3159 #define PMM_LOOPBACK_EXT_PHY 2
3160 #define PMM_LOOPBACK_EXT 3
3161 #define PMM_LOOPBACK_MAC 4
3164 u32 feature_config_flags;
3167 struct port_mf_cfg {
3168 u32 dynamic_cfg; /* device control channel */
3169 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
3170 #define PORT_MF_CFG_OV_TAG_SHIFT 0
3171 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
3176 /* DO NOT add new fields in the middle
3177 * MUST be synced with struct pmm_stats_map
3180 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3181 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3191 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3192 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
3193 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3194 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3195 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3196 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
3197 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3198 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3199 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3200 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
3201 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3211 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3212 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
3215 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
3216 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
3217 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
3218 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
3220 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
3221 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
3222 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
3223 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
3224 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
3228 u64 brb_truncate[8];
3233 struct brb_stats brb;
3234 struct pmm_stats pmm;
3239 #define CMT_TEAM_MAX 2
3241 struct couple_mode_teaming {
3242 u8 port_cmt[MCP_GLOB_PORT_MAX];
3243 #define PORT_CMT_IN_TEAM BIT(0)
3245 #define PORT_CMT_PORT_ROLE BIT(1)
3246 #define PORT_CMT_PORT_INACTIVE (0 << 1)
3247 #define PORT_CMT_PORT_ACTIVE BIT(1)
3249 #define PORT_CMT_TEAM_MASK BIT(2)
3250 #define PORT_CMT_TEAM0 (0 << 2)
3251 #define PORT_CMT_TEAM1 BIT(2)
3254 /**************************************
3255 * LLDP and DCBX HSI structures
3256 **************************************/
3257 #define LLDP_CHASSIS_ID_STAT_LEN 4
3258 #define LLDP_PORT_ID_STAT_LEN 4
3259 #define DCBX_MAX_APP_PROTOCOL 32
3260 #define MAX_SYSTEM_LLDP_TLV_DATA 32
3263 LLDP_NEAREST_BRIDGE = 0,
3264 LLDP_NEAREST_NON_TPMR_BRIDGE,
3265 LLDP_NEAREST_CUSTOMER_BRIDGE,
3266 LLDP_MAX_LLDP_AGENTS
3269 struct lldp_config_params_s {
3271 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
3272 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
3273 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
3274 #define LLDP_CONFIG_HOLD_SHIFT 8
3275 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
3276 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
3277 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
3278 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
3279 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
3280 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
3281 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3282 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
3285 struct lldp_status_params_s {
3287 u32 status; /* TBD */
3289 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3290 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3292 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3293 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
3297 struct dcbx_ets_feature {
3299 #define DCBX_ETS_ENABLED_MASK 0x00000001
3300 #define DCBX_ETS_ENABLED_SHIFT 0
3301 #define DCBX_ETS_WILLING_MASK 0x00000002
3302 #define DCBX_ETS_WILLING_SHIFT 1
3303 #define DCBX_ETS_ERROR_MASK 0x00000004
3304 #define DCBX_ETS_ERROR_SHIFT 2
3305 #define DCBX_ETS_CBS_MASK 0x00000008
3306 #define DCBX_ETS_CBS_SHIFT 3
3307 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
3308 #define DCBX_ETS_MAX_TCS_SHIFT 4
3310 #define DCBX_ISCSI_OOO_TC 4
3311 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
3314 #define DCBX_ETS_TSA_STRICT 0
3315 #define DCBX_ETS_TSA_CBS 1
3316 #define DCBX_ETS_TSA_ETS 2
3319 struct dcbx_app_priority_entry {
3321 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
3322 #define DCBX_APP_PRI_MAP_SHIFT 0
3323 #define DCBX_APP_PRI_0 0x01
3324 #define DCBX_APP_PRI_1 0x02
3325 #define DCBX_APP_PRI_2 0x04
3326 #define DCBX_APP_PRI_3 0x08
3327 #define DCBX_APP_PRI_4 0x10
3328 #define DCBX_APP_PRI_5 0x20
3329 #define DCBX_APP_PRI_6 0x40
3330 #define DCBX_APP_PRI_7 0x80
3331 #define DCBX_APP_SF_MASK 0x00000300
3332 #define DCBX_APP_SF_SHIFT 8
3333 #define DCBX_APP_SF_ETHTYPE 0
3334 #define DCBX_APP_SF_PORT 1
3335 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
3336 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
3339 /* FW structure in BE */
3340 struct dcbx_app_priority_feature {
3342 #define DCBX_APP_ENABLED_MASK 0x00000001
3343 #define DCBX_APP_ENABLED_SHIFT 0
3344 #define DCBX_APP_WILLING_MASK 0x00000002
3345 #define DCBX_APP_WILLING_SHIFT 1
3346 #define DCBX_APP_ERROR_MASK 0x00000004
3347 #define DCBX_APP_ERROR_SHIFT 2
3349 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
3350 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
3352 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
3353 #define DCBX_APP_MAX_TCS_SHIFT 12
3354 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
3355 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
3356 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3359 /* FW structure in BE */
3360 struct dcbx_features {
3362 struct dcbx_ets_feature ets;
3366 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
3367 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
3368 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
3369 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
3370 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
3371 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
3372 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
3373 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
3374 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
3375 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
3377 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
3378 #define DCBX_PFC_FLAGS_SHIFT 8
3379 #define DCBX_PFC_CAPS_MASK 0x00000f00
3380 #define DCBX_PFC_CAPS_SHIFT 8
3381 #define DCBX_PFC_MBC_MASK 0x00004000
3382 #define DCBX_PFC_MBC_SHIFT 14
3383 #define DCBX_PFC_WILLING_MASK 0x00008000
3384 #define DCBX_PFC_WILLING_SHIFT 15
3385 #define DCBX_PFC_ENABLED_MASK 0x00010000
3386 #define DCBX_PFC_ENABLED_SHIFT 16
3387 #define DCBX_PFC_ERROR_MASK 0x00020000
3388 #define DCBX_PFC_ERROR_SHIFT 17
3391 struct dcbx_app_priority_feature app;
3394 struct dcbx_local_params {
3396 #define DCBX_CONFIG_VERSION_MASK 0x00000003
3397 #define DCBX_CONFIG_VERSION_SHIFT 0
3398 #define DCBX_CONFIG_VERSION_DISABLED 0
3399 #define DCBX_CONFIG_VERSION_IEEE 1
3400 #define DCBX_CONFIG_VERSION_CEE 2
3403 struct dcbx_features features;
3409 struct dcbx_features features;
3413 struct lldp_system_tlvs_buffer_s {
3416 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
3419 /**************************************/
3421 /* P U B L I C G L O B A L */
3423 /**************************************/
3424 struct public_global {
3426 #define MAX_PATH_BIG_BEAR 2
3427 #define MAX_PATH_K2 1
3433 u32 debug_mb_offset;
3434 u32 phymod_dbg_mb_offset;
3435 struct couple_mode_teaming cmt;
3436 s32 internal_temperature;
3438 u32 running_bundle_id;
3441 /**************************************/
3443 /* P U B L I C P A T H */
3445 /**************************************/
3447 /****************************************************************************
3448 * Shared Memory 2 Region *
3449 ****************************************************************************/
3450 /* The fw_flr_ack is actually built in the following way: */
3452 /* 128 bit: VF ack */
3453 /* 8 bit: ios_dis_ack */
3454 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
3455 /* u32. The fw must have the VF right after the PF since this is how it */
3456 /* access arrays(it expects always the VF to reside after the PF, and that */
3457 /* makes the calculation much easier for it. ) */
3458 /* In order to answer both limitations, and keep the struct small, the code */
3459 /* will abuse the structure defined here to achieve the actual partition */
3461 /****************************************************************************/
3465 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3466 #define ACCUM_ACK_PF_BASE 0
3467 #define ACCUM_ACK_PF_SHIFT 0
3469 #define ACCUM_ACK_VF_BASE 8
3470 #define ACCUM_ACK_VF_SHIFT 3
3472 #define ACCUM_ACK_IOV_DIS_BASE 256
3473 #define ACCUM_ACK_IOV_DIS_SHIFT 8
3476 struct public_path {
3477 struct fw_flr_mb flr_mb;
3478 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
3481 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
3482 #define PROCESS_KILL_COUNTER_SHIFT 0
3483 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
3484 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
3485 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3488 /**************************************/
3490 /* P U B L I C P O R T */
3492 /**************************************/
3494 /****************************************************************************
3495 * Driver <-> FW Mailbox *
3496 ****************************************************************************/
3498 struct public_port {
3499 u32 validity_map; /* 0x0 (4*2 = 0x8) */
3502 #define MCP_VALIDITY_PCI_CFG 0x00100000
3503 #define MCP_VALIDITY_MB 0x00200000
3504 #define MCP_VALIDITY_DEV_INFO 0x00400000
3505 #define MCP_VALIDITY_RESERVED 0x00000007
3507 /* One licensing bit should be set */
3508 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
3509 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
3510 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
3511 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
3514 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
3515 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
3516 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
3517 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
3520 #define LINK_STATUS_LINK_UP \
3522 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
3523 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1)
3524 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
3525 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
3526 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
3527 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
3528 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
3529 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
3530 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
3532 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
3534 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
3535 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
3537 #define LINK_STATUS_PFC_ENABLED \
3539 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
3540 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
3541 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
3542 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
3543 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
3544 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
3545 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
3546 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
3548 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
3549 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
3550 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18)
3551 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
3552 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
3554 #define LINK_STATUS_SFP_TX_FAULT \
3556 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
3557 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
3560 u32 ext_phy_fw_version;
3561 u32 drv_phy_cfg_addr;
3567 struct port_mf_cfg port_mf_config;
3568 struct port_stats stats;
3571 #define MEDIA_UNSPECIFIED 0x0
3572 #define MEDIA_SFPP_10G_FIBER 0x1
3573 #define MEDIA_XFP_FIBER 0x2
3574 #define MEDIA_DA_TWINAX 0x3
3575 #define MEDIA_BASE_T 0x4
3576 #define MEDIA_SFP_1G_FIBER 0x5
3577 #define MEDIA_KR 0xf0
3578 #define MEDIA_NOT_PRESENT 0xff
3581 #define LFA_LINK_FLAP_REASON_OFFSET 0
3582 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
3583 #define LFA_NO_REASON (0 << 0)
3584 #define LFA_LINK_DOWN BIT(0)
3585 #define LFA_FORCE_INIT BIT(1)
3586 #define LFA_LOOPBACK_MISMATCH BIT(2)
3587 #define LFA_SPEED_MISMATCH BIT(3)
3588 #define LFA_FLOW_CTRL_MISMATCH BIT(4)
3589 #define LFA_ADV_SPEED_MISMATCH BIT(5)
3590 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
3591 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
3592 #define LINK_FLAP_COUNT_OFFSET 16
3593 #define LINK_FLAP_COUNT_MASK 0x00ff0000
3595 u32 link_change_count;
3598 struct lldp_config_params_s lldp_config_params[
3599 LLDP_MAX_LLDP_AGENTS];
3600 struct lldp_status_params_s lldp_status_params[
3601 LLDP_MAX_LLDP_AGENTS];
3602 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
3604 /* DCBX related MIB */
3605 struct dcbx_local_params local_admin_dcbx_mib;
3606 struct dcbx_mib remote_dcbx_mib;
3607 struct dcbx_mib operational_dcbx_mib;
3609 u32 fc_npiv_nvram_tbl_addr;
3610 u32 fc_npiv_nvram_tbl_size;
3611 u32 transceiver_data;
3614 /**************************************/
3616 /* P U B L I C F U N C */
3618 /**************************************/
3620 struct public_func {
3621 u32 iscsi_boot_signature;
3622 u32 iscsi_boot_block_offset;
3625 u32 c2s_pcp_map_lower;
3626 u32 c2s_pcp_map_upper;
3627 u32 c2s_pcp_map_default;
3633 /* function 0 of each port cannot be hidden */
3634 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
3635 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
3636 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
3638 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
3639 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
3640 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
3641 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
3642 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
3643 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
3644 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
3647 /* value range - 0..100, increments in 1 % */
3648 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
3649 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
3650 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
3651 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
3652 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
3653 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
3656 #define FUNC_STATUS_VLINK_DOWN 0x00000001
3658 u32 mac_upper; /* MAC */
3659 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
3660 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
3661 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
3663 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
3665 u32 fcoe_wwn_port_name_upper;
3666 u32 fcoe_wwn_port_name_lower;
3668 u32 fcoe_wwn_node_name_upper;
3669 u32 fcoe_wwn_node_name_lower;
3671 u32 ovlan_stag; /* tags */
3672 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
3673 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
3674 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
3676 u32 pf_allocation; /* vf per pf */
3678 u32 preserve_data; /* Will be used bt CCM */
3680 u32 driver_last_activity_ts;
3682 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3685 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
3686 #define DRV_ID_PDA_COMP_VER_SHIFT 0
3688 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
3689 #define DRV_ID_MCP_HSI_VER_SHIFT 16
3690 #define DRV_ID_MCP_HSI_VER_CURRENT BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3692 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
3693 #define DRV_ID_DRV_TYPE_SHIFT 24
3694 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
3695 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
3696 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
3697 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
3698 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
3699 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
3700 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
3701 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
3702 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
3704 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
3705 #define DRV_ID_DRV_INIT_HW_SHIFT 31
3706 #define DRV_ID_DRV_INIT_HW_FLAG BIT(DRV_ID_DRV_INIT_HW_SHIFT)
3709 /**************************************/
3711 /* P U B L I C M B */
3713 /**************************************/
3714 /* This is the only section that the driver can write to, and each */
3715 /* Basically each driver request to set feature parameters,
3716 * will be done using a different command, which will be linked
3717 * to a specific data structure from the union below.
3718 * For huge strucuture, the common blank structure should be used.
3722 u32 mac_upper; /* Upper 16 bits are always zeroes */
3731 struct mcp_file_att {
3736 #define MCP_DRV_VER_STR_SIZE 16
3737 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3738 #define MCP_DRV_NVM_BUF_LEN 32
3739 struct drv_version_stc {
3741 u8 name[MCP_DRV_VER_STR_SIZE - 4];
3744 union drv_union_data {
3745 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3746 struct mcp_mac wol_mac;
3748 struct pmm_phy_cfg drv_phy_cfg;
3750 struct mcp_val64 val64; /* For PHY / AVS commands */
3752 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
3754 struct mcp_file_att file_att;
3756 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
3758 struct drv_version_stc drv_version;
3761 struct public_drv_mb {
3763 #define DRV_MSG_CODE_MASK 0xffff0000
3764 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
3765 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
3766 #define DRV_MSG_CODE_INIT_HW 0x12000000
3767 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
3768 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
3769 #define DRV_MSG_CODE_INIT_PHY 0x22000000
3770 /* Params - FORCE - Reinitialize the link regardless of LFA */
3771 /* - DONT_CARE - Don't flap the link if up */
3772 #define DRV_MSG_CODE_LINK_RESET 0x23000000
3774 #define DRV_MSG_CODE_SET_LLDP 0x24000000
3775 #define DRV_MSG_CODE_SET_DCBX 0x25000000
3777 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
3779 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
3780 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
3781 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
3782 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
3783 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
3784 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
3785 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
3786 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
3787 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
3788 #define DRV_MSG_CODE_MCP_RESET 0x00090000
3789 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
3790 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
3791 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
3792 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
3793 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
3794 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
3796 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
3798 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
3802 /* UNLOAD_REQ params */
3803 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
3804 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
3805 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
3806 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
3808 /* UNLOAD_DONE_params */
3809 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
3811 /* INIT_PHY params */
3812 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
3813 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
3815 /* LLDP / DCBX params*/
3816 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
3817 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
3818 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
3819 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
3820 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
3821 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
3823 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
3824 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
3826 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
3827 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
3829 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
3830 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
3831 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
3832 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
3834 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
3835 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
3836 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16
3837 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
3838 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
3839 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
3840 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30
3841 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
3843 /* configure vf MSIX params*/
3844 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
3845 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
3846 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
3847 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
3849 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
3850 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
3851 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
3854 #define FW_MSG_CODE_MASK 0xffff0000
3855 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
3856 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
3857 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
3858 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
3859 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
3860 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
3861 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
3862 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
3863 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
3864 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
3865 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
3866 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
3867 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
3868 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
3869 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
3870 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
3871 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
3872 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
3873 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
3874 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
3875 #define FW_MSG_CODE_FLR_ACK 0x02000000
3876 #define FW_MSG_CODE_FLR_NACK 0x02100000
3878 #define FW_MSG_CODE_NVM_OK 0x00010000
3879 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
3880 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
3881 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
3882 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
3883 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
3884 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
3885 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
3886 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
3887 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
3888 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
3889 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
3890 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
3891 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
3892 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
3893 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
3894 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
3895 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
3896 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
3897 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
3898 #define FW_MSG_CODE_PHY_OK 0x00110000
3899 #define FW_MSG_CODE_PHY_ERROR 0x00120000
3900 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
3901 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
3902 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
3903 #define FW_MSG_CODE_OK 0x00160000
3905 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
3910 #define DRV_PULSE_SEQ_MASK 0x00007fff
3911 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
3912 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
3914 #define MCP_PULSE_SEQ_MASK 0x00007fff
3915 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
3916 #define MCP_EVENT_MASK 0xffff0000
3917 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
3919 union drv_union_data union_data;
3923 /**********************************************************************
3925 * Incremental Aggregative
3926 * 8-bit MFW counter per message
3927 * 8-bit ack-counter per message
3929 * Provides up to 256 aggregative message per type
3930 * Provides 4 message types in dword
3931 * Message type pointers to byte offset
3932 * Backward Compatibility by using sizeof for the counters.
3933 * No lock requires for 32bit messages
3935 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
3936 * is required to prevent data corruption.
3937 **********************************************************************/
3938 enum MFW_DRV_MSG_TYPE {
3939 MFW_DRV_MSG_LINK_CHANGE,
3940 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
3941 MFW_DRV_MSG_VF_DISABLED,
3942 MFW_DRV_MSG_LLDP_DATA_UPDATED,
3943 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
3944 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
3945 MFW_DRV_MSG_ERROR_RECOVERY,
3949 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
3950 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
3951 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
3952 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
3954 struct public_mfw_mb {
3956 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3957 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3960 /**************************************/
3962 /* P U B L I C D A T A */
3964 /**************************************/
3965 enum public_sections {
3966 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
3967 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
3975 struct drv_ver_info_stc {
3980 struct mcp_public_data {
3981 /* The sections fields is an array */
3983 offsize_t sections[PUBLIC_MAX_SECTIONS];
3984 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
3985 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
3986 struct public_global global;
3987 struct public_path path[MCP_GLOB_PATH_MAX];
3988 struct public_port port[MCP_GLOB_PORT_MAX];
3989 struct public_func func[MCP_GLOB_FUNC_MAX];
3990 struct drv_ver_info_stc drv_info;
3993 struct nvm_cfg_mac_address {
3995 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
3996 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
4001 /******************************************
4003 ******************************************/
4005 struct nvm_cfg1_glob {
4006 u32 generic_cont0; /* 0x0 */
4007 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
4008 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
4009 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
4010 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
4011 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
4012 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
4013 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
4014 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
4015 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
4016 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
4017 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
4018 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
4019 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
4020 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
4021 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
4022 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
4023 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
4024 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
4025 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
4026 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
4027 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
4028 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
4029 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
4030 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
4031 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
4032 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
4033 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
4034 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
4035 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
4036 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
4037 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
4038 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
4039 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
4040 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
4041 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
4042 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
4044 u32 engineering_change[3]; /* 0x4 */
4046 u32 manufacturing_id; /* 0x10 */
4048 u32 serial_number[4]; /* 0x14 */
4050 u32 pcie_cfg; /* 0x24 */
4051 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
4052 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
4053 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
4054 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
4055 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
4056 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
4057 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
4058 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
4059 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
4060 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
4061 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
4062 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
4063 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
4064 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
4065 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
4066 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK 0x00000020
4067 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET 5
4068 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED 0x0
4069 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED 0x1
4070 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
4071 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
4072 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
4073 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
4074 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
4075 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
4076 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
4077 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
4078 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
4079 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
4080 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
4081 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
4082 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
4083 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
4085 u32 mgmt_traffic; /* 0x28 */
4086 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
4087 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
4088 #define NVM_CFG1_GLOB_RESERVED60_100KHZ 0x0
4089 #define NVM_CFG1_GLOB_RESERVED60_400KHZ 0x1
4090 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
4091 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
4092 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
4093 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
4094 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
4095 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
4096 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
4097 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
4098 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
4099 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
4100 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
4102 u32 core_cfg; /* 0x2C */
4103 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
4104 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
4105 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
4106 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
4107 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
4108 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
4109 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
4110 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
4111 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
4112 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
4113 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
4114 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
4115 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
4116 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4117 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4118 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
4119 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
4120 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4121 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4122 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
4123 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
4124 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
4125 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
4126 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
4127 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
4128 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
4129 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP 0x1
4130 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
4131 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
4132 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
4133 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
4134 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
4136 u32 e_lane_cfg1; /* 0x30 */
4137 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4138 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4139 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4140 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4141 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4142 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4143 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4144 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4145 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4146 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4147 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4148 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4149 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4150 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4151 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4152 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4154 u32 e_lane_cfg2; /* 0x34 */
4155 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4156 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4157 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4158 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4159 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4160 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4161 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4162 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4163 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4164 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4165 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4166 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4167 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4168 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4169 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4170 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4171 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
4172 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
4173 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
4174 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
4175 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
4176 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
4177 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
4178 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
4179 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
4181 u32 f_lane_cfg1; /* 0x38 */
4182 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4183 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4184 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4185 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4186 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4187 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4188 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4189 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4190 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4191 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4192 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4193 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4194 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4195 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4196 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4197 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4199 u32 f_lane_cfg2; /* 0x3C */
4200 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4201 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4202 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4203 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4204 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4205 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4206 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4207 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4208 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4209 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4210 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4211 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4212 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4213 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4214 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4215 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4217 u32 eagle_preemphasis; /* 0x40 */
4218 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4219 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4220 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4221 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4222 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4223 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4224 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4225 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4227 u32 eagle_driver_current; /* 0x44 */
4228 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4229 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4230 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4231 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4232 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4233 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4234 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4235 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4237 u32 falcon_preemphasis; /* 0x48 */
4238 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4239 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4240 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4241 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4242 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4243 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4244 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4245 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4247 u32 falcon_driver_current; /* 0x4C */
4248 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4249 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4250 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4251 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4252 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4253 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4254 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4255 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4257 u32 pci_id; /* 0x50 */
4258 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
4259 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
4261 u32 pci_subsys_id; /* 0x54 */
4262 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
4263 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
4264 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
4265 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
4268 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
4269 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
4270 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
4271 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
4272 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
4273 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
4274 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
4275 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
4276 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
4277 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
4278 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
4279 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
4280 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
4281 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
4282 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
4283 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
4284 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
4285 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
4286 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
4287 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
4288 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
4289 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
4290 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
4291 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
4292 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
4293 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
4294 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
4295 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
4296 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
4297 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
4298 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
4299 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
4300 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
4301 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
4302 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
4303 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
4304 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
4305 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
4306 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
4307 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
4308 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
4309 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
4310 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
4311 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
4312 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
4313 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
4314 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
4315 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
4316 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
4317 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
4318 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
4319 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
4320 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
4321 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
4323 u32 eagle_txfir_main; /* 0x5C */
4324 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4325 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4326 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4327 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4328 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4329 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4330 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4331 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4333 u32 eagle_txfir_post; /* 0x60 */
4334 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4335 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4336 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4337 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4338 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4339 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4340 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4341 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4343 u32 falcon_txfir_main; /* 0x64 */
4344 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4345 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4346 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4347 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4348 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4349 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4350 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4351 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4353 u32 falcon_txfir_post; /* 0x68 */
4354 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4355 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4356 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4357 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4358 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4359 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4360 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4361 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4363 u32 manufacture_ver; /* 0x6C */
4364 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
4365 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
4366 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
4367 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
4368 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
4369 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
4370 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
4371 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
4372 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
4373 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
4375 u32 manufacture_time; /* 0x70 */
4376 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
4377 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
4378 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
4379 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
4380 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
4381 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
4383 u32 led_global_settings; /* 0x74 */
4384 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
4385 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
4386 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
4387 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
4388 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
4389 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
4390 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
4391 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
4393 u32 generic_cont1; /* 0x78 */
4394 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
4395 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
4397 u32 mbi_version; /* 0x7C */
4398 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
4399 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
4400 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
4401 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
4402 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
4403 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
4405 u32 mbi_date; /* 0x80 */
4407 u32 misc_sig; /* 0x84 */
4409 /* Define the GPIO mapping to switch i2c mux */
4410 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
4411 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
4412 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
4413 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
4414 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
4415 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
4416 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
4417 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
4418 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
4419 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
4420 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
4421 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
4422 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
4423 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
4424 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
4425 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
4426 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
4427 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
4428 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
4429 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
4430 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
4431 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
4432 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
4433 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
4434 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
4435 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
4436 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
4437 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
4438 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
4439 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
4440 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
4441 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
4442 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
4443 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
4444 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
4445 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
4446 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
4447 u32 device_capabilities; /* 0x88 */
4448 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
4449 u32 power_dissipated; /* 0x8C */
4450 u32 power_consumed; /* 0x90 */
4451 u32 efi_version; /* 0x94 */
4452 u32 reserved[42]; /* 0x98 */
4455 struct nvm_cfg1_path {
4456 u32 reserved[30]; /* 0x0 */
4459 struct nvm_cfg1_port {
4460 u32 reserved__m_relocated_to_option_123; /* 0x0 */
4461 u32 reserved__m_relocated_to_option_124; /* 0x4 */
4462 u32 generic_cont0; /* 0x8 */
4463 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
4464 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
4465 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
4466 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
4467 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
4468 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
4469 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
4470 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
4471 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
4472 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
4473 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
4474 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
4475 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
4476 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
4477 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
4478 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
4479 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
4480 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
4481 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
4482 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
4483 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
4484 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
4485 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
4486 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
4487 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
4488 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
4489 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
4490 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
4491 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
4492 u32 pcie_cfg; /* 0xC */
4493 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
4494 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
4496 u32 features; /* 0x10 */
4497 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
4498 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
4499 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
4500 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
4501 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
4502 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
4503 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
4504 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
4506 u32 speed_cap_mask; /* 0x14 */
4507 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
4508 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
4509 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
4510 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
4511 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
4512 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
4513 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
4514 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
4515 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
4516 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
4517 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
4518 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
4519 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
4520 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
4521 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
4522 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
4524 u32 link_settings; /* 0x18 */
4525 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
4526 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
4527 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
4528 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
4529 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
4530 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
4531 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
4532 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
4533 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
4534 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
4535 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
4536 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
4537 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
4538 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
4539 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
4540 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
4541 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
4542 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
4543 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
4544 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
4545 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
4546 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
4547 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
4548 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
4549 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
4550 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
4551 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
4552 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
4553 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
4554 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
4555 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
4556 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
4558 u32 phy_cfg; /* 0x1C */
4559 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
4560 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
4561 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
4562 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
4563 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
4564 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
4565 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
4566 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
4567 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
4568 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
4569 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
4570 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
4571 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
4572 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
4573 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
4574 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
4575 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
4576 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
4577 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
4578 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
4579 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
4580 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
4581 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
4582 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
4583 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
4584 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
4585 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
4586 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
4587 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
4588 #define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
4589 #define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
4591 u32 mgmt_traffic; /* 0x20 */
4592 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
4593 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
4595 u32 ext_phy; /* 0x24 */
4596 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
4597 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
4598 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
4599 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
4600 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
4601 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
4603 u32 mba_cfg1; /* 0x28 */
4604 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
4605 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
4606 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
4607 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
4608 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
4609 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
4610 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
4611 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
4612 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
4613 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
4614 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
4615 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
4616 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
4617 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
4618 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
4619 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
4620 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
4621 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
4622 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
4623 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
4624 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
4625 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
4626 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
4627 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
4628 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
4629 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
4630 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
4631 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
4632 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
4633 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
4635 u32 mba_cfg2; /* 0x2C */
4636 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
4637 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
4638 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
4639 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
4641 u32 vf_cfg; /* 0x30 */
4642 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
4643 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
4644 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
4645 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
4647 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
4649 u32 led_port_settings; /* 0x3C */
4650 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
4651 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
4652 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
4653 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
4654 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
4655 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
4656 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
4657 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
4658 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
4659 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
4660 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
4661 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
4663 u32 transceiver_00; /* 0x40 */
4665 /* Define for mapping of transceiver signal module absent */
4666 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
4667 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
4668 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
4669 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
4670 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
4671 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
4672 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
4673 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
4674 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
4675 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
4676 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
4677 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
4678 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
4679 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
4680 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
4681 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
4682 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
4683 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
4684 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
4685 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
4686 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
4687 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
4688 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
4689 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
4690 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
4691 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
4692 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
4693 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
4694 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
4695 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
4696 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
4697 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
4698 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
4699 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
4700 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
4701 /* Define the GPIO mux settings to switch i2c mux to this port */
4702 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
4703 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
4704 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
4705 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
4707 u32 reserved[133]; /* 0x44 */
4710 struct nvm_cfg1_func {
4711 struct nvm_cfg_mac_address mac_address; /* 0x0 */
4713 u32 rsrv1; /* 0x8 */
4714 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
4715 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
4716 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
4717 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
4719 u32 rsrv2; /* 0xC */
4720 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
4721 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
4722 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
4723 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
4725 u32 device_id; /* 0x10 */
4726 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
4727 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
4728 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
4729 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
4731 u32 cmn_cfg; /* 0x14 */
4732 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
4733 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
4734 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
4735 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
4736 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
4737 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
4738 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
4739 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
4740 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
4741 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
4742 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
4743 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
4744 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
4745 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
4746 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
4747 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
4748 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
4749 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
4750 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
4751 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
4753 u32 pci_cfg; /* 0x18 */
4754 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
4755 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
4756 #define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
4757 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
4758 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
4759 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
4760 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
4761 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
4762 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
4763 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
4764 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
4765 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
4766 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
4767 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
4768 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
4769 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
4770 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
4771 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
4772 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
4773 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
4774 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
4775 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
4776 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
4777 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
4779 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
4781 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
4782 u32 preboot_generic_cfg; /* 0x2C */
4783 u32 reserved[8]; /* 0x30 */
4787 struct nvm_cfg1_glob glob; /* 0x0 */
4789 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
4791 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
4793 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
4796 /******************************************
4798 ******************************************/
4800 enum nvm_cfg_sections {
4801 NVM_CFG_SECTION_NVM_CFG1,
4807 u32 sections_offset[NVM_CFG_SECTION_MAX];
4808 struct nvm_cfg1 cfg1;
4816 extern struct spad_layout g_spad;
4818 #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
4820 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4822 #define TO_OFFSIZE(_offset, _size) \
4823 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4824 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4826 enum spad_sections {
4828 SPAD_SECTION_NVM_CFG,
4829 SPAD_SECTION_PUBLIC,
4830 SPAD_SECTION_PRIVATE,
4834 struct spad_layout {
4835 struct nvm_cfg nvm_cfg;
4836 struct mcp_public_data public_data;
4839 #define CRC_MAGIC_VALUE 0xDEBB20E3
4840 #define CRC32_POLYNOMIAL 0xEDB88320
4841 #define NVM_CRC_SIZE (sizeof(u32))
4843 enum nvm_sw_arbitrator {
4850 /****************************************************************************
4851 * Boot Strap Region *
4852 ****************************************************************************/
4853 struct legacy_bootstrap_region {
4855 #define NVM_MAGIC_VALUE 0x669955aa
4856 u32 sram_start_addr;
4857 u32 code_len; /* boot code length (in dwords) */
4858 u32 code_start_addr;
4859 u32 crc; /* 32-bit CRC */
4862 /****************************************************************************
4863 * Directories Region *
4864 ****************************************************************************/
4865 struct nvm_code_entry {
4866 u32 image_type; /* Image type */
4867 u32 nvm_start_addr; /* NVM address of the image */
4868 u32 len; /* Include CRC */
4869 u32 sram_start_addr;
4870 u32 sram_run_addr; /* Relevant in case of MIM only */
4873 enum nvm_image_type {
4874 NVM_TYPE_TIM1 = 0x01,
4875 NVM_TYPE_TIM2 = 0x02,
4876 NVM_TYPE_MIM1 = 0x03,
4877 NVM_TYPE_MIM2 = 0x04,
4878 NVM_TYPE_MBA = 0x05,
4879 NVM_TYPE_MODULES_PN = 0x06,
4880 NVM_TYPE_VPD = 0x07,
4881 NVM_TYPE_MFW_TRACE1 = 0x08,
4882 NVM_TYPE_MFW_TRACE2 = 0x09,
4883 NVM_TYPE_NVM_CFG1 = 0x0a,
4884 NVM_TYPE_L2B = 0x0b,
4885 NVM_TYPE_DIR1 = 0x0c,
4886 NVM_TYPE_EAGLE_FW1 = 0x0d,
4887 NVM_TYPE_FALCON_FW1 = 0x0e,
4888 NVM_TYPE_PCIE_FW1 = 0x0f,
4889 NVM_TYPE_HW_SET = 0x10,
4890 NVM_TYPE_LIM = 0x11,
4891 NVM_TYPE_AVS_FW1 = 0x12,
4892 NVM_TYPE_DIR2 = 0x13,
4893 NVM_TYPE_CCM = 0x14,
4894 NVM_TYPE_EAGLE_FW2 = 0x15,
4895 NVM_TYPE_FALCON_FW2 = 0x16,
4896 NVM_TYPE_PCIE_FW2 = 0x17,
4897 NVM_TYPE_AVS_FW2 = 0x18,
4902 #define MAX_NVM_DIR_ENTRIES 200
4906 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
4907 #define NVM_DIR_SEQ_MASK 0xfffffffe
4908 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
4910 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
4914 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
4917 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
4919 1) * sizeof(struct nvm_code_entry) + \
4922 struct nvm_vpd_image {
4923 u32 format_revision;
4924 #define VPD_IMAGE_VERSION 1
4926 /* This array length depends on the number of VPD fields */
4930 /****************************************************************************
4932 ****************************************************************************/
4933 #define DIR_ID_1 (0)
4934 #define DIR_ID_2 (1)
4935 #define MAX_DIR_IDS (2)
4937 #define MFW_BUNDLE_1 (0)
4938 #define MFW_BUNDLE_2 (1)
4939 #define MAX_MFW_BUNDLES (2)
4941 #define FLASH_PAGE_SIZE 0x1000
4942 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
4943 #define ASIC_MIM_MAX_SIZE (300 * FLASH_PAGE_SIZE) /* 1.2Mb */
4944 #define FPGA_MIM_MAX_SIZE (25 * FLASH_PAGE_SIZE) /* 60Kb */
4946 #define LIM_MAX_SIZE ((2 * \
4947 FLASH_PAGE_SIZE) - \
4948 sizeof(struct legacy_bootstrap_region) - \
4950 #define LIM_OFFSET (NVM_OFFSET(lim_image))
4951 #define NVM_RSV_SIZE (44)
4952 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
4954 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
4956 NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
4957 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
4958 MIM_MAX_SIZE(is_asic) * 2)
4960 union nvm_dir_union {
4962 u8 page[FLASH_PAGE_SIZE];
4966 * +-------------------+ 0x000000
4969 * | sram_start_addr |
4971 * | code_start_addr |
4973 * +-------------------+ 0x000014
4975 * +-------------------+ 0x000040
4977 * +-------------------+ 0x002000
4979 * +-------------------+ 0x003000
4981 * +-------------------+ 0x004000
4983 * +-------------------+ 0x130000
4985 * +-------------------+ 0x25C000
4989 * | Eagle/Falcon FW |
4995 * +-------------------+ 0x400000
4998 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
4999 /* NVM Offset (size) */
5000 struct legacy_bootstrap_region bootstrap;
5001 u8 rsrv[NVM_RSV_SIZE];
5002 u8 lim_image[LIM_MAX_SIZE];
5003 union nvm_dir_union dir[MAX_MFW_BUNDLES];
5005 /* MIM1_IMAGE 0x004000 (0x12c000) */
5006 /* MIM2_IMAGE 0x130000 (0x12c000) */
5007 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5010 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5012 struct hw_set_info {
5014 #define GRC_REG_TYPE 1
5015 #define PHY_REG_TYPE 2
5016 #define PCI_REG_TYPE 4
5023 #define RMW_SET_OP 3
5024 #define RMW_CLR_OP 4
5030 #define POR_RESET_TYPE BIT(0)
5031 #define HARD_RESET_TYPE BIT(1)
5032 #define CORE_RESET_TYPE BIT(2)
5033 #define MCP_RESET_TYPE BIT(3)
5034 #define PERSET_ASSERT BIT(4)
5035 #define PERSET_DEASSERT BIT(5)
5038 struct hw_set_image {
5040 #define HW_SET_IMAGE_VERSION 1
5043 /* This array length depends on the no_hw_sets */
5044 struct hw_set_info hw_sets[1];