1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define XSDM_REG_OPERATION_GEN \
32 #define NIG_REG_RX_BRB_OUT_EN \
34 #define NIG_REG_STORM_OUT_EN \
36 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
38 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
40 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
42 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
44 #define BAR0_MAP_REG_MSDM_RAM \
46 #define BAR0_MAP_REG_USDM_RAM \
48 #define BAR0_MAP_REG_PSDM_RAM \
50 #define BAR0_MAP_REG_TSDM_RAM \
52 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
54 #define PRS_REG_SEARCH_TCP \
56 #define PRS_REG_SEARCH_UDP \
58 #define PRS_REG_SEARCH_FCOE \
60 #define PRS_REG_SEARCH_ROCE \
62 #define PRS_REG_SEARCH_OPENFLOW \
64 #define TM_REG_PF_ENABLE_CONN \
66 #define TM_REG_PF_ENABLE_TASK \
68 #define TM_REG_PF_SCAN_ACTIVE_CONN \
70 #define TM_REG_PF_SCAN_ACTIVE_TASK \
72 #define IGU_REG_LEADING_EDGE_LATCH \
74 #define IGU_REG_TRAILING_EDGE_LATCH \
76 #define QM_REG_USG_CNT_PF_TX \
78 #define QM_REG_USG_CNT_PF_OTHER \
80 #define DORQ_REG_PF_DB_ENABLE \
82 #define QM_REG_PF_EN \
84 #define TCFC_REG_STRONG_ENABLE_PF \
86 #define CCFC_REG_STRONG_ENABLE_PF \
88 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
90 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
92 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
94 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
96 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
98 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
100 #define MISC_REG_GEN_PURP_CR0 \
102 #define MCP_REG_SCRATCH \
104 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
106 #define MISCS_REG_CHIP_NUM \
108 #define MISCS_REG_CHIP_REV \
110 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
112 #define MISCS_REG_CHIP_TEST_REG \
114 #define MISCS_REG_CHIP_METAL \
116 #define MISCS_REG_FUNCTION_HIDE \
118 #define BRB_REG_HEADER_SIZE \
120 #define BTB_REG_HEADER_SIZE \
122 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
124 #define CCFC_REG_ACTIVITY_COUNTER \
126 #define CCFC_REG_STRONG_ENABLE_VF \
128 #define CDU_REG_CID_ADDR_PARAMS \
130 #define DBG_REG_CLIENT_ENABLE \
132 #define DMAE_REG_INIT \
134 #define DORQ_REG_IFEN \
136 #define DORQ_REG_DB_DROP_REASON \
138 #define DORQ_REG_DB_DROP_DETAILS \
140 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
142 #define GRC_REG_TIMEOUT_EN \
144 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
146 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
148 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
150 #define IGU_REG_BLOCK_CONFIGURATION \
152 #define MCM_REG_INIT \
154 #define MCP2_REG_DBG_DWORD_ENABLE \
156 #define MISC_REG_PORT_MODE \
158 #define MISCS_REG_CLK_100G_MODE \
160 #define MSDM_REG_ENABLE_IN1 \
162 #define MSEM_REG_ENABLE_IN \
164 #define NIG_REG_CM_HDR \
166 #define NCSI_REG_CONFIG \
168 #define PBF_REG_INIT \
170 #define PTU_REG_ATC_INIT_ARRAY \
172 #define PCM_REG_INIT \
174 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
176 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
178 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
180 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
182 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
184 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
186 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
188 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
190 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
192 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
194 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
196 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
198 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
200 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
202 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
204 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
206 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
208 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
210 #define PRM_REG_DISABLE_PRM \
212 #define PRS_REG_SOFT_RST \
214 #define PSDM_REG_ENABLE_IN1 \
216 #define PSEM_REG_ENABLE_IN \
218 #define PSWRQ_REG_DBG_SELECT \
220 #define PSWRQ2_REG_CDUT_P_SIZE \
222 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
224 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
226 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
228 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
230 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
232 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
234 #define PSWRD_REG_DBG_SELECT \
236 #define PSWRD2_REG_CONF11 \
238 #define PSWWR_REG_USDM_FULL_TH \
240 #define PSWWR2_REG_CDU_FULL_TH2 \
242 #define QM_REG_MAXPQSIZE_0 \
244 #define RSS_REG_RSS_INIT_EN \
246 #define RDIF_REG_STOP_ON_ERROR \
248 #define SRC_REG_SOFT_RST \
250 #define TCFC_REG_ACTIVITY_COUNTER \
252 #define TCM_REG_INIT \
254 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
256 #define TSDM_REG_ENABLE_IN1 \
258 #define TSEM_REG_ENABLE_IN \
260 #define TDIF_REG_STOP_ON_ERROR \
262 #define UCM_REG_INIT \
264 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
266 #define USDM_REG_ENABLE_IN1 \
268 #define USEM_REG_ENABLE_IN \
270 #define XCM_REG_INIT \
272 #define XSDM_REG_ENABLE_IN1 \
274 #define XSEM_REG_ENABLE_IN \
276 #define YCM_REG_INIT \
278 #define YSDM_REG_ENABLE_IN1 \
280 #define YSEM_REG_ENABLE_IN \
282 #define XYLD_REG_SCBD_STRICT_PRIO \
284 #define TMLD_REG_SCBD_STRICT_PRIO \
286 #define MULD_REG_SCBD_STRICT_PRIO \
288 #define YULD_REG_SCBD_STRICT_PRIO \
290 #define MISC_REG_SHARED_MEM_ADDR \
292 #define DMAE_REG_GO_C0 \
294 #define DMAE_REG_GO_C1 \
296 #define DMAE_REG_GO_C2 \
298 #define DMAE_REG_GO_C3 \
300 #define DMAE_REG_GO_C4 \
302 #define DMAE_REG_GO_C5 \
304 #define DMAE_REG_GO_C6 \
306 #define DMAE_REG_GO_C7 \
308 #define DMAE_REG_GO_C8 \
310 #define DMAE_REG_GO_C9 \
312 #define DMAE_REG_GO_C10 \
314 #define DMAE_REG_GO_C11 \
316 #define DMAE_REG_GO_C12 \
318 #define DMAE_REG_GO_C13 \
320 #define DMAE_REG_GO_C14 \
322 #define DMAE_REG_GO_C15 \
324 #define DMAE_REG_GO_C16 \
326 #define DMAE_REG_GO_C17 \
328 #define DMAE_REG_GO_C18 \
330 #define DMAE_REG_GO_C19 \
332 #define DMAE_REG_GO_C20 \
334 #define DMAE_REG_GO_C21 \
336 #define DMAE_REG_GO_C22 \
338 #define DMAE_REG_GO_C23 \
340 #define DMAE_REG_GO_C24 \
342 #define DMAE_REG_GO_C25 \
344 #define DMAE_REG_GO_C26 \
346 #define DMAE_REG_GO_C27 \
348 #define DMAE_REG_GO_C28 \
350 #define DMAE_REG_GO_C29 \
352 #define DMAE_REG_GO_C30 \
354 #define DMAE_REG_GO_C31 \
356 #define DMAE_REG_CMD_MEM \
358 #define QM_REG_MAXPQSIZETXSEL_0 \
360 #define QM_REG_SDMCMDREADY \
362 #define QM_REG_SDMCMDADDR \
364 #define QM_REG_SDMCMDDATALSB \
366 #define QM_REG_SDMCMDDATAMSB \
368 #define QM_REG_SDMCMDGO \
370 #define QM_REG_RLPFCRD \
372 #define QM_REG_RLPFINCVAL \
374 #define QM_REG_RLGLBLCRD \
376 #define QM_REG_RLGLBLINCVAL \
378 #define IGU_REG_ATTENTION_ENABLE \
380 #define IGU_REG_ATTN_MSG_ADDR_L \
382 #define IGU_REG_ATTN_MSG_ADDR_H \
384 #define MISC_REG_AEU_GENERAL_ATTN_0 \
386 #define CAU_REG_SB_ADDR_MEMORY \
388 #define CAU_REG_SB_VAR_MEMORY \
390 #define CAU_REG_PI_MEMORY \
392 #define IGU_REG_PF_CONFIGURATION \
394 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
396 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
398 #define MISC_REG_AEU_MASK_ATTN_IGU \
400 #define IGU_REG_CLEANUP_STATUS_0 \
402 #define IGU_REG_CLEANUP_STATUS_1 \
404 #define IGU_REG_CLEANUP_STATUS_2 \
406 #define IGU_REG_CLEANUP_STATUS_3 \
408 #define IGU_REG_CLEANUP_STATUS_4 \
410 #define IGU_REG_COMMAND_REG_32LSB_DATA \
412 #define IGU_REG_COMMAND_REG_CTRL \
414 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
416 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
418 #define IGU_REG_MAPPING_MEMORY \
420 #define MISCS_REG_GENERIC_POR_0 \
422 #define MCP_REG_NVM_CFG4 \
424 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
426 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
428 #define MCP_REG_CPU_STATE \
430 #define MCP_REG_CPU_EVENT_MASK \
432 #define PGLUE_B_REG_PF_BAR0_SIZE \
434 #define PGLUE_B_REG_PF_BAR1_SIZE \
436 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
437 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
438 #define PRS_REG_VXLAN_PORT 0x1f0738UL
439 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
440 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
442 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
443 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
444 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
445 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
446 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
447 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
449 #define NIG_REG_VXLAN_PORT 0x50105cUL
450 #define PBF_REG_VXLAN_PORT 0xd80518UL
451 #define PBF_REG_NGE_PORT 0xd8051cUL
452 #define PRS_REG_NGE_PORT 0x1f086cUL
453 #define NIG_REG_NGE_PORT 0x508b38UL
455 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
456 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
457 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
458 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
459 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
461 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
462 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
463 #define NIG_REG_NGE_COMP_VER 0x508b30UL
464 #define PBF_REG_NGE_COMP_VER 0xd80524UL
465 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
467 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
468 #define QM_REG_WFQVPWEIGHT 0x2fa000UL