drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_SLOTS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  66
  67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  69         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  70
  71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  72    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  73 static const int multicast_filter_limit = 32;
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define JUMBO_1K        ETH_DATA_LEN
 149 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 150 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 151 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 152 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 153
 154 #define _R(NAME,TD,FW,SZ,B) {   \
 155         .name = NAME,           \
 156         .txd_version = TD,      \
 157         .fw_name = FW,          \
 158         .jumbo_max = SZ,        \
 159         .jumbo_tx_csum = B      \
 160 }
 161
 162 static const struct {
 163         const char *name;
 164         enum rtl_tx_desc_version txd_version;
 165         const char *fw_name;
 166         u16 jumbo_max;
 167         bool jumbo_tx_csum;
 168 } rtl_chip_infos[] = {
 169         /* PCI devices. */
 170         [RTL_GIGA_MAC_VER_01] =
 171                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_02] =
 173                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_03] =
 175                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_04] =
 177                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_05] =
 179                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_06] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         /* PCI-E devices. */
 183         [RTL_GIGA_MAC_VER_07] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_08] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_09] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_10] =
 190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_11] =
 192                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 193         [RTL_GIGA_MAC_VER_12] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 195         [RTL_GIGA_MAC_VER_13] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_14] =
 198                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_15] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_16] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_17] =
 204                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_18] =
 206                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_19] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_20] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_21] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_22] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_23] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_24] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_25] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_26] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_31] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_32] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_33] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_34] =
 244                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_35] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_36] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 251                                                         JUMBO_9K, false),
 252 };
 253 #undef _R
 254
 255 enum cfg_version {
 256         RTL_CFG_0 = 0x00,
 257         RTL_CFG_1,
 258         RTL_CFG_2
 259 };
 260
 261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 271         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 272                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 273         { 0x0001,                               0x8168,
 274                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 275         {0,},
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 279
 280 static int rx_buf_sz = 16383;
 281 static int use_dac;
 282 static struct {
 283         u32 msg_enable;
 284 } debug = { -1 };
 285
 286 enum rtl_registers {
 287         MAC0            = 0,    /* Ethernet hardware address. */
 288         MAC4            = 4,
 289         MAR0            = 8,    /* Multicast filter. */
 290         CounterAddrLow          = 0x10,
 291         CounterAddrHigh         = 0x14,
 292         TxDescStartAddrLow      = 0x20,
 293         TxDescStartAddrHigh     = 0x24,
 294         TxHDescStartAddrLow     = 0x28,
 295         TxHDescStartAddrHigh    = 0x2c,
 296         FLASH           = 0x30,
 297         ERSR            = 0x36,
 298         ChipCmd         = 0x37,
 299         TxPoll          = 0x38,
 300         IntrMask        = 0x3c,
 301         IntrStatus      = 0x3e,
 302
 303         TxConfig        = 0x40,
 304 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 305 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 306
 307         RxConfig        = 0x44,
 308 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 309 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 310 #define RXCFG_FIFO_SHIFT                13
 311                                         /* No threshold before first PCI xfer */
 312 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 313 #define RXCFG_DMA_SHIFT                 8
 314                                         /* Unlimited maximum PCI burst. */
 315 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 316
 317         RxMissed        = 0x4c,
 318         Cfg9346         = 0x50,
 319         Config0         = 0x51,
 320         Config1         = 0x52,
 321         Config2         = 0x53,
 322 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 323
 324         Config3         = 0x54,
 325         Config4         = 0x55,
 326         Config5         = 0x56,
 327         MultiIntr       = 0x5c,
 328         PHYAR           = 0x60,
 329         PHYstatus       = 0x6c,
 330         RxMaxSize       = 0xda,
 331         CPlusCmd        = 0xe0,
 332         IntrMitigate    = 0xe2,
 333         RxDescAddrLow   = 0xe4,
 334         RxDescAddrHigh  = 0xe8,
 335         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 336
 337 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 338
 339         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 340
 341 #define TxPacketMax     (8064 >> 7)
 342 #define EarlySize       0x27
 343
 344         FuncEvent       = 0xf0,
 345         FuncEventMask   = 0xf4,
 346         FuncPresetState = 0xf8,
 347         FuncForceEvent  = 0xfc,
 348 };
 349
 350 enum rtl8110_registers {
 351         TBICSR                  = 0x64,
 352         TBI_ANAR                = 0x68,
 353         TBI_LPAR                = 0x6a,
 354 };
 355
 356 enum rtl8168_8101_registers {
 357         CSIDR                   = 0x64,
 358         CSIAR                   = 0x68,
 359 #define CSIAR_FLAG                      0x80000000
 360 #define CSIAR_WRITE_CMD                 0x80000000
 361 #define CSIAR_BYTE_ENABLE               0x0f
 362 #define CSIAR_BYTE_ENABLE_SHIFT         12
 363 #define CSIAR_ADDR_MASK                 0x0fff
 364         PMCH                    = 0x6f,
 365         EPHYAR                  = 0x80,
 366 #define EPHYAR_FLAG                     0x80000000
 367 #define EPHYAR_WRITE_CMD                0x80000000
 368 #define EPHYAR_REG_MASK                 0x1f
 369 #define EPHYAR_REG_SHIFT                16
 370 #define EPHYAR_DATA_MASK                0xffff
 371         DLLPR                   = 0xd0,
 372 #define PFM_EN                          (1 << 6)
 373         DBG_REG                 = 0xd1,
 374 #define FIX_NAK_1                       (1 << 4)
 375 #define FIX_NAK_2                       (1 << 3)
 376         TWSI                    = 0xd2,
 377         MCU                     = 0xd3,
 378 #define NOW_IS_OOB                      (1 << 7)
 379 #define EN_NDP                          (1 << 3)
 380 #define EN_OOB_RESET                    (1 << 2)
 381         EFUSEAR                 = 0xdc,
 382 #define EFUSEAR_FLAG                    0x80000000
 383 #define EFUSEAR_WRITE_CMD               0x80000000
 384 #define EFUSEAR_READ_CMD                0x00000000
 385 #define EFUSEAR_REG_MASK                0x03ff
 386 #define EFUSEAR_REG_SHIFT               8
 387 #define EFUSEAR_DATA_MASK               0xff
 388 };
 389
 390 enum rtl8168_registers {
 391         LED_FREQ                = 0x1a,
 392         EEE_LED                 = 0x1b,
 393         ERIDR                   = 0x70,
 394         ERIAR                   = 0x74,
 395 #define ERIAR_FLAG                      0x80000000
 396 #define ERIAR_WRITE_CMD                 0x80000000
 397 #define ERIAR_READ_CMD                  0x00000000
 398 #define ERIAR_ADDR_BYTE_ALIGN           4
 399 #define ERIAR_TYPE_SHIFT                16
 400 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 402 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 403 #define ERIAR_MASK_SHIFT                12
 404 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 405 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 406 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 407         EPHY_RXER_NUM           = 0x7c,
 408         OCPDR                   = 0xb0, /* OCP GPHY access */
 409 #define OCPDR_WRITE_CMD                 0x80000000
 410 #define OCPDR_READ_CMD                  0x00000000
 411 #define OCPDR_REG_MASK                  0x7f
 412 #define OCPDR_GPHY_REG_SHIFT            16
 413 #define OCPDR_DATA_MASK                 0xffff
 414         OCPAR                   = 0xb4,
 415 #define OCPAR_FLAG                      0x80000000
 416 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 417 #define OCPAR_GPHY_READ_CMD             0x0000f060
 418         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 419         MISC                    = 0xf0, /* 8168e only. */
 420 #define TXPLA_RST                       (1 << 29)
 421 #define PWM_EN                          (1 << 22)
 422 };
 423
 424 enum rtl_register_content {
 425         /* InterruptStatusBits */
 426         SYSErr          = 0x8000,
 427         PCSTimeout      = 0x4000,
 428         SWInt           = 0x0100,
 429         TxDescUnavail   = 0x0080,
 430         RxFIFOOver      = 0x0040,
 431         LinkChg         = 0x0020,
 432         RxOverflow      = 0x0010,
 433         TxErr           = 0x0008,
 434         TxOK            = 0x0004,
 435         RxErr           = 0x0002,
 436         RxOK            = 0x0001,
 437
 438         /* RxStatusDesc */
 439         RxBOVF  = (1 << 24),
 440         RxFOVF  = (1 << 23),
 441         RxRWT   = (1 << 22),
 442         RxRES   = (1 << 21),
 443         RxRUNT  = (1 << 20),
 444         RxCRC   = (1 << 19),
 445
 446         /* ChipCmdBits */
 447         StopReq         = 0x80,
 448         CmdReset        = 0x10,
 449         CmdRxEnb        = 0x08,
 450         CmdTxEnb        = 0x04,
 451         RxBufEmpty      = 0x01,
 452
 453         /* TXPoll register p.5 */
 454         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 455         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 456         FSWInt          = 0x01,         /* Forced software interrupt */
 457
 458         /* Cfg9346Bits */
 459         Cfg9346_Lock    = 0x00,
 460         Cfg9346_Unlock  = 0xc0,
 461
 462         /* rx_mode_bits */
 463         AcceptErr       = 0x20,
 464         AcceptRunt      = 0x10,
 465         AcceptBroadcast = 0x08,
 466         AcceptMulticast = 0x04,
 467         AcceptMyPhys    = 0x02,
 468         AcceptAllPhys   = 0x01,
 469 #define RX_CONFIG_ACCEPT_MASK           0x3f
 470
 471         /* TxConfigBits */
 472         TxInterFrameGapShift = 24,
 473         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 474
 475         /* Config1 register p.24 */
 476         LEDS1           = (1 << 7),
 477         LEDS0           = (1 << 6),
 478         Speed_down      = (1 << 4),
 479         MEMMAP          = (1 << 3),
 480         IOMAP           = (1 << 2),
 481         VPD             = (1 << 1),
 482         PMEnable        = (1 << 0),     /* Power Management Enable */
 483
 484         /* Config2 register p. 25 */
 485         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 486         PCI_Clock_66MHz = 0x01,
 487         PCI_Clock_33MHz = 0x00,
 488
 489         /* Config3 register p.25 */
 490         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 491         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 492         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 493         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 494
 495         /* Config4 register */
 496         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 497
 498         /* Config5 register p.27 */
 499         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 500         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 501         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 502         Spi_en          = (1 << 3),
 503         LanWake         = (1 << 1),     /* LanWake enable/disable */
 504         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 505
 506         /* TBICSR p.28 */
 507         TBIReset        = 0x80000000,
 508         TBILoopback     = 0x40000000,
 509         TBINwEnable     = 0x20000000,
 510         TBINwRestart    = 0x10000000,
 511         TBILinkOk       = 0x02000000,
 512         TBINwComplete   = 0x01000000,
 513
 514         /* CPlusCmd p.31 */
 515         EnableBist      = (1 << 15),    // 8168 8101
 516         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 517         Normal_mode     = (1 << 13),    // unused
 518         Force_half_dup  = (1 << 12),    // 8168 8101
 519         Force_rxflow_en = (1 << 11),    // 8168 8101
 520         Force_txflow_en = (1 << 10),    // 8168 8101
 521         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 522         ASF             = (1 << 8),     // 8168 8101
 523         PktCntrDisable  = (1 << 7),     // 8168 8101
 524         Mac_dbgo_sel    = 0x001c,       // 8168
 525         RxVlan          = (1 << 6),
 526         RxChkSum        = (1 << 5),
 527         PCIDAC          = (1 << 4),
 528         PCIMulRW        = (1 << 3),
 529         INTT_0          = 0x0000,       // 8168
 530         INTT_1          = 0x0001,       // 8168
 531         INTT_2          = 0x0002,       // 8168
 532         INTT_3          = 0x0003,       // 8168
 533
 534         /* rtl8169_PHYstatus */
 535         TBI_Enable      = 0x80,
 536         TxFlowCtrl      = 0x40,
 537         RxFlowCtrl      = 0x20,
 538         _1000bpsF       = 0x10,
 539         _100bps         = 0x08,
 540         _10bps          = 0x04,
 541         LinkStatus      = 0x02,
 542         FullDup         = 0x01,
 543
 544         /* _TBICSRBit */
 545         TBILinkOK       = 0x02000000,
 546
 547         /* DumpCounterCommand */
 548         CounterDump     = 0x8,
 549 };
 550
 551 enum rtl_desc_bit {
 552         /* First doubleword. */
 553         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 554         RingEnd         = (1 << 30), /* End of descriptor ring */
 555         FirstFrag       = (1 << 29), /* First segment of a packet */
 556         LastFrag        = (1 << 28), /* Final segment of a packet */
 557 };
 558
 559 /* Generic case. */
 560 enum rtl_tx_desc_bit {
 561         /* First doubleword. */
 562         TD_LSO          = (1 << 27),            /* Large Send Offload */
 563 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 564
 565         /* Second doubleword. */
 566         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 567 };
 568
 569 /* 8169, 8168b and 810x except 8102e. */
 570 enum rtl_tx_desc_bit_0 {
 571         /* First doubleword. */
 572 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 573         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 574         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 575         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 576 };
 577
 578 /* 8102e, 8168c and beyond. */
 579 enum rtl_tx_desc_bit_1 {
 580         /* Second doubleword. */
 581 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 582         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 583         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 584         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 585 };
 586
 587 static const struct rtl_tx_desc_info {
 588         struct {
 589                 u32 udp;
 590                 u32 tcp;
 591         } checksum;
 592         u16 mss_shift;
 593         u16 opts_offset;
 594 } tx_desc_info [] = {
 595         [RTL_TD_0] = {
 596                 .checksum = {
 597                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 598                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 599                 },
 600                 .mss_shift      = TD0_MSS_SHIFT,
 601                 .opts_offset    = 0
 602         },
 603         [RTL_TD_1] = {
 604                 .checksum = {
 605                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 606                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 607                 },
 608                 .mss_shift      = TD1_MSS_SHIFT,
 609                 .opts_offset    = 1
 610         }
 611 };
 612
 613 enum rtl_rx_desc_bit {
 614         /* Rx private */
 615         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 616         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 617
 618 #define RxProtoUDP      (PID1)
 619 #define RxProtoTCP      (PID0)
 620 #define RxProtoIP       (PID1 | PID0)
 621 #define RxProtoMask     RxProtoIP
 622
 623         IPFail          = (1 << 16), /* IP checksum failed */
 624         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 625         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 626         RxVlanTag       = (1 << 16), /* VLAN tag available */
 627 };
 628
 629 #define RsvdMask        0x3fffc000
 630
 631 struct TxDesc {
 632         __le32 opts1;
 633         __le32 opts2;
 634         __le64 addr;
 635 };
 636
 637 struct RxDesc {
 638         __le32 opts1;
 639         __le32 opts2;
 640         __le64 addr;
 641 };
 642
 643 struct ring_info {
 644         struct sk_buff  *skb;
 645         u32             len;
 646         u8              __pad[sizeof(void *) - sizeof(u32)];
 647 };
 648
 649 enum features {
 650         RTL_FEATURE_WOL         = (1 << 0),
 651         RTL_FEATURE_MSI         = (1 << 1),
 652         RTL_FEATURE_GMII        = (1 << 2),
 653 };
 654
 655 struct rtl8169_counters {
 656         __le64  tx_packets;
 657         __le64  rx_packets;
 658         __le64  tx_errors;
 659         __le32  rx_errors;
 660         __le16  rx_missed;
 661         __le16  align_errors;
 662         __le32  tx_one_collision;
 663         __le32  tx_multi_collision;
 664         __le64  rx_unicast;
 665         __le64  rx_broadcast;
 666         __le32  rx_multicast;
 667         __le16  tx_aborted;
 668         __le16  tx_underun;
 669 };
 670
 671 enum rtl_flag {
 672         RTL_FLAG_TASK_ENABLED,
 673         RTL_FLAG_TASK_SLOW_PENDING,
 674         RTL_FLAG_TASK_RESET_PENDING,
 675         RTL_FLAG_TASK_PHY_PENDING,
 676         RTL_FLAG_MAX
 677 };
 678
 679 struct rtl8169_stats {
 680         u64                     packets;
 681         u64                     bytes;
 682         struct u64_stats_sync   syncp;
 683 };
 684
 685 struct rtl8169_private {
 686         void __iomem *mmio_addr;        /* memory map physical address */
 687         struct pci_dev *pci_dev;
 688         struct net_device *dev;
 689         struct napi_struct napi;
 690         u32 msg_enable;
 691         u16 txd_version;
 692         u16 mac_version;
 693         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 694         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 695         u32 dirty_rx;
 696         u32 dirty_tx;
 697         struct rtl8169_stats rx_stats;
 698         struct rtl8169_stats tx_stats;
 699         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 700         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 701         dma_addr_t TxPhyAddr;
 702         dma_addr_t RxPhyAddr;
 703         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 704         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 705         struct timer_list timer;
 706         u16 cp_cmd;
 707
 708         u16 event_slow;
 709         bool runtime_suspended;
 710
 711         struct mdio_ops {
 712                 void (*write)(void __iomem *, int, int);
 713                 int (*read)(void __iomem *, int);
 714         } mdio_ops;
 715
 716         struct pll_power_ops {
 717                 void (*down)(struct rtl8169_private *);
 718                 void (*up)(struct rtl8169_private *);
 719         } pll_power_ops;
 720
 721         struct jumbo_ops {
 722                 void (*enable)(struct rtl8169_private *);
 723                 void (*disable)(struct rtl8169_private *);
 724         } jumbo_ops;
 725
 726         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 727         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 728         void (*phy_reset_enable)(struct rtl8169_private *tp);
 729         void (*hw_start)(struct net_device *);
 730         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 731         unsigned int (*link_ok)(void __iomem *);
 732         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 733
 734         struct {
 735                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 736                 struct mutex mutex;
 737                 struct work_struct work;
 738         } wk;
 739
 740         unsigned features;
 741
 742         struct mii_if_info mii;
 743         struct rtl8169_counters counters;
 744         u32 saved_wolopts;
 745         u32 opts1_mask;
 746
 747         struct rtl_fw {
 748                 const struct firmware *fw;
 749
 750 #define RTL_VER_SIZE            32
 751
 752                 char version[RTL_VER_SIZE];
 753
 754                 struct rtl_fw_phy_action {
 755                         __le32 *code;
 756                         size_t size;
 757                 } phy_action;
 758         } *rtl_fw;
 759 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 760 };
 761
 762 static int aspm_disable = 0;
 763 module_param(aspm_disable, int, 0444);
 764 MODULE_PARM_DESC(aspm_disable, "Disable ASPM completely.");
 765
 766 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 767 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 768 module_param(use_dac, int, 0);
 769 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 770 module_param_named(debug, debug.msg_enable, int, 0);
 771 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 772 MODULE_LICENSE("GPL");
 773 MODULE_VERSION(RTL8169_VERSION);
 774 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 775 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 776 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 777 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 778 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 779 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 780 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 781 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 782
 783 static void rtl_lock_work(struct rtl8169_private *tp)
 784 {
 785         mutex_lock(&tp->wk.mutex);
 786 }
 787
 788 static void rtl_unlock_work(struct rtl8169_private *tp)
 789 {
 790         mutex_unlock(&tp->wk.mutex);
 791 }
 792
 793 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 794 {
 795         int cap = pci_pcie_cap(pdev);
 796
 797         if (cap) {
 798                 u16 ctl;
 799
 800                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 801                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 802                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 803         }
 804 }
 805
 806 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 807 {
 808         void __iomem *ioaddr = tp->mmio_addr;
 809         int i;
 810
 811         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 812         for (i = 0; i < 20; i++) {
 813                 udelay(100);
 814                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 815                         break;
 816         }
 817         return RTL_R32(OCPDR);
 818 }
 819
 820 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 821 {
 822         void __iomem *ioaddr = tp->mmio_addr;
 823         int i;
 824
 825         RTL_W32(OCPDR, data);
 826         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 827         for (i = 0; i < 20; i++) {
 828                 udelay(100);
 829                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 830                         break;
 831         }
 832 }
 833
 834 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 835 {
 836         void __iomem *ioaddr = tp->mmio_addr;
 837         int i;
 838
 839         RTL_W8(ERIDR, cmd);
 840         RTL_W32(ERIAR, 0x800010e8);
 841         msleep(2);
 842         for (i = 0; i < 5; i++) {
 843                 udelay(100);
 844                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 845                         break;
 846         }
 847
 848         ocp_write(tp, 0x1, 0x30, 0x00000001);
 849 }
 850
 851 #define OOB_CMD_RESET           0x00
 852 #define OOB_CMD_DRIVER_START    0x05
 853 #define OOB_CMD_DRIVER_STOP     0x06
 854
 855 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 856 {
 857         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 858 }
 859
 860 static void rtl8168_driver_start(struct rtl8169_private *tp)
 861 {
 862         u16 reg;
 863         int i;
 864
 865         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 866
 867         reg = rtl8168_get_ocp_reg(tp);
 868
 869         for (i = 0; i < 10; i++) {
 870                 msleep(10);
 871                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 872                         break;
 873         }
 874 }
 875
 876 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 877 {
 878         u16 reg;
 879         int i;
 880
 881         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 882
 883         reg = rtl8168_get_ocp_reg(tp);
 884
 885         for (i = 0; i < 10; i++) {
 886                 msleep(10);
 887                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 888                         break;
 889         }
 890 }
 891
 892 static int r8168dp_check_dash(struct rtl8169_private *tp)
 893 {
 894         u16 reg = rtl8168_get_ocp_reg(tp);
 895
 896         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 897 }
 898
 899 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 900 {
 901         int i;
 902
 903         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 904
 905         for (i = 20; i > 0; i--) {
 906                 /*
 907                  * Check if the RTL8169 has completed writing to the specified
 908                  * MII register.
 909                  */
 910                 if (!(RTL_R32(PHYAR) & 0x80000000))
 911                         break;
 912                 udelay(25);
 913         }
 914         /*
 915          * According to hardware specs a 20us delay is required after write
 916          * complete indication, but before sending next command.
 917          */
 918         udelay(20);
 919 }
 920
 921 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 922 {
 923         int i, value = -1;
 924
 925         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 926
 927         for (i = 20; i > 0; i--) {
 928                 /*
 929                  * Check if the RTL8169 has completed retrieving data from
 930                  * the specified MII register.
 931                  */
 932                 if (RTL_R32(PHYAR) & 0x80000000) {
 933                         value = RTL_R32(PHYAR) & 0xffff;
 934                         break;
 935                 }
 936                 udelay(25);
 937         }
 938         /*
 939          * According to hardware specs a 20us delay is required after read
 940          * complete indication, but before sending next command.
 941          */
 942         udelay(20);
 943
 944         return value;
 945 }
 946
 947 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 948 {
 949         int i;
 950
 951         RTL_W32(OCPDR, data |
 952                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 953         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 954         RTL_W32(EPHY_RXER_NUM, 0);
 955
 956         for (i = 0; i < 100; i++) {
 957                 mdelay(1);
 958                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 959                         break;
 960         }
 961 }
 962
 963 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 964 {
 965         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 966                 (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 970 {
 971         int i;
 972
 973         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(EPHY_RXER_NUM, 0);
 978
 979         for (i = 0; i < 100; i++) {
 980                 mdelay(1);
 981                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 982                         break;
 983         }
 984
 985         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 986 }
 987
 988 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 989
 990 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 991 {
 992         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 996 {
 997         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 998 }
 999
1000 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1001 {
1002         r8168dp_2_mdio_start(ioaddr);
1003
1004         r8169_mdio_write(ioaddr, reg_addr, value);
1005
1006         r8168dp_2_mdio_stop(ioaddr);
1007 }
1008
1009 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1010 {
1011         int value;
1012
1013         r8168dp_2_mdio_start(ioaddr);
1014
1015         value = r8169_mdio_read(ioaddr, reg_addr);
1016
1017         r8168dp_2_mdio_stop(ioaddr);
1018
1019         return value;
1020 }
1021
1022 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1023 {
1024         tp->mdio_ops.write(tp->mmio_addr, location, val);
1025 }
1026
1027 static int rtl_readphy(struct rtl8169_private *tp, int location)
1028 {
1029         return tp->mdio_ops.read(tp->mmio_addr, location);
1030 }
1031
1032 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1033 {
1034         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035 }
1036
1037 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1038 {
1039         int val;
1040
1041         val = rtl_readphy(tp, reg_addr);
1042         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1043 }
1044
1045 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1046                            int val)
1047 {
1048         struct rtl8169_private *tp = netdev_priv(dev);
1049
1050         rtl_writephy(tp, location, val);
1051 }
1052
1053 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056
1057         return rtl_readphy(tp, location);
1058 }
1059
1060 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1061 {
1062         unsigned int i;
1063
1064         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1066
1067         for (i = 0; i < 100; i++) {
1068                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1069                         break;
1070                 udelay(10);
1071         }
1072 }
1073
1074 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1075 {
1076         u16 value = 0xffff;
1077         unsigned int i;
1078
1079         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1080
1081         for (i = 0; i < 100; i++) {
1082                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1084                         break;
1085                 }
1086                 udelay(10);
1087         }
1088
1089         return value;
1090 }
1091
1092 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1093 {
1094         unsigned int i;
1095
1096         RTL_W32(CSIDR, value);
1097         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099
1100         for (i = 0; i < 100; i++) {
1101                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1102                         break;
1103                 udelay(10);
1104         }
1105 }
1106
1107 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1108 {
1109         u32 value = ~0x00;
1110         unsigned int i;
1111
1112         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1114
1115         for (i = 0; i < 100; i++) {
1116                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117                         value = RTL_R32(CSIDR);
1118                         break;
1119                 }
1120                 udelay(10);
1121         }
1122
1123         return value;
1124 }
1125
1126 static
1127 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1128 {
1129         unsigned int i;
1130
1131         BUG_ON((addr & 3) || (mask == 0));
1132         RTL_W32(ERIDR, val);
1133         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1134
1135         for (i = 0; i < 100; i++) {
1136                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1137                         break;
1138                 udelay(100);
1139         }
1140 }
1141
1142 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1143 {
1144         u32 value = ~0x00;
1145         unsigned int i;
1146
1147         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1148
1149         for (i = 0; i < 100; i++) {
1150                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151                         value = RTL_R32(ERIDR);
1152                         break;
1153                 }
1154                 udelay(100);
1155         }
1156
1157         return value;
1158 }
1159
1160 static void
1161 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1162 {
1163         u32 val;
1164
1165         val = rtl_eri_read(ioaddr, addr, type);
1166         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1167 }
1168
1169 struct exgmac_reg {
1170         u16 addr;
1171         u16 mask;
1172         u32 val;
1173 };
1174
1175 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176                                    const struct exgmac_reg *r, int len)
1177 {
1178         while (len-- > 0) {
1179                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1180                 r++;
1181         }
1182 }
1183
1184 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1185 {
1186         u8 value = 0xff;
1187         unsigned int i;
1188
1189         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1190
1191         for (i = 0; i < 300; i++) {
1192                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1194                         break;
1195                 }
1196                 udelay(100);
1197         }
1198
1199         return value;
1200 }
1201
1202 static u16 rtl_get_events(struct rtl8169_private *tp)
1203 {
1204         void __iomem *ioaddr = tp->mmio_addr;
1205
1206         return RTL_R16(IntrStatus);
1207 }
1208
1209 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         RTL_W16(IntrStatus, bits);
1214         mmiowb();
1215 }
1216
1217 static void rtl_irq_disable(struct rtl8169_private *tp)
1218 {
1219         void __iomem *ioaddr = tp->mmio_addr;
1220
1221         RTL_W16(IntrMask, 0);
1222         mmiowb();
1223 }
1224
1225 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1226 {
1227         void __iomem *ioaddr = tp->mmio_addr;
1228
1229         RTL_W16(IntrMask, bits);
1230 }
1231
1232 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1235
1236 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1237 {
1238         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1239 }
1240
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1242 {
1243         void __iomem *ioaddr = tp->mmio_addr;
1244
1245         rtl_irq_disable(tp);
1246         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1247         RTL_R8(ChipCmd);
1248 }
1249
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         return RTL_R32(TBICSR) & TBIReset;
1255 }
1256
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1258 {
1259         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1260 }
1261
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1263 {
1264         return RTL_R32(TBICSR) & TBILinkOk;
1265 }
1266
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1268 {
1269         return RTL_R8(PHYstatus) & LinkStatus;
1270 }
1271
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1277 }
1278
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1280 {
1281         unsigned int val;
1282
1283         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1285 }
1286
1287 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1288 {
1289         void __iomem *ioaddr = tp->mmio_addr;
1290         struct net_device *dev = tp->dev;
1291
1292         if (!netif_running(dev))
1293                 return;
1294
1295         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298                                       0x00000011, ERIAR_EXGMAC);
1299                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300                                       0x00000005, ERIAR_EXGMAC);
1301                 } else if (RTL_R8(PHYstatus) & _100bps) {
1302                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303                                       0x0000001f, ERIAR_EXGMAC);
1304                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305                                       0x00000005, ERIAR_EXGMAC);
1306                 } else {
1307                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308                                       0x0000001f, ERIAR_EXGMAC);
1309                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310                                       0x0000003f, ERIAR_EXGMAC);
1311                 }
1312                 /* Reset packet filter */
1313                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1314                              ERIAR_EXGMAC);
1315                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1316                              ERIAR_EXGMAC);
1317         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321                                       0x00000011, ERIAR_EXGMAC);
1322                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323                                       0x00000005, ERIAR_EXGMAC);
1324                 } else {
1325                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326                                       0x0000001f, ERIAR_EXGMAC);
1327                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328                                       0x0000003f, ERIAR_EXGMAC);
1329                 }
1330         }
1331 }
1332
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334                                         struct rtl8169_private *tp,
1335                                         void __iomem *ioaddr, bool pm)
1336 {
1337         if (tp->link_ok(ioaddr)) {
1338                 rtl_link_chg_patch(tp);
1339                 /* This is to cancel a scheduled suspend if there's one. */
1340                 if (pm)
1341                         pm_request_resume(&tp->pci_dev->dev);
1342                 netif_carrier_on(dev);
1343                 if (net_ratelimit())
1344                         netif_info(tp, ifup, dev, "link up\n");
1345         } else {
1346                 netif_carrier_off(dev);
1347                 netif_info(tp, ifdown, dev, "link down\n");
1348                 if (pm)
1349                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1350         }
1351 }
1352
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354                                       struct rtl8169_private *tp,
1355                                       void __iomem *ioaddr)
1356 {
1357         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358 }
1359
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365         u8 options;
1366         u32 wolopts = 0;
1367
1368         options = RTL_R8(Config1);
1369         if (!(options & PMEnable))
1370                 return 0;
1371
1372         options = RTL_R8(Config3);
1373         if (options & LinkUp)
1374                 wolopts |= WAKE_PHY;
1375         if (options & MagicPacket)
1376                 wolopts |= WAKE_MAGIC;
1377
1378         options = RTL_R8(Config5);
1379         if (options & UWF)
1380                 wolopts |= WAKE_UCAST;
1381         if (options & BWF)
1382                 wolopts |= WAKE_BCAST;
1383         if (options & MWF)
1384                 wolopts |= WAKE_MCAST;
1385
1386         return wolopts;
1387 }
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394
1395         wol->supported = WAKE_ANY;
1396         wol->wolopts = __rtl8169_get_wol(tp);
1397
1398         rtl_unlock_work(tp);
1399 }
1400
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404         unsigned int i;
1405         static const struct {
1406                 u32 opt;
1407                 u16 reg;
1408                 u8  mask;
1409         } cfg[] = {
1410                 { WAKE_PHY,   Config3, LinkUp },
1411                 { WAKE_MAGIC, Config3, MagicPacket },
1412                 { WAKE_UCAST, Config5, UWF },
1413                 { WAKE_BCAST, Config5, BWF },
1414                 { WAKE_MCAST, Config5, MWF },
1415                 { WAKE_ANY,   Config5, LanWake }
1416         };
1417         u8 options;
1418
1419         RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(cfg[i].reg, options);
1426         }
1427
1428         switch (tp->mac_version) {
1429         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1430                 options = RTL_R8(Config1) & ~PMEnable;
1431                 if (wolopts)
1432                         options |= PMEnable;
1433                 RTL_W8(Config1, options);
1434                 break;
1435         default:
1436                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1437                 if (wolopts)
1438                         options |= PME_SIGNAL;
1439                 RTL_W8(Config2, options);
1440                 break;
1441         }
1442
1443         RTL_W8(Cfg9346, Cfg9346_Lock);
1444 }
1445
1446 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1447 {
1448         struct rtl8169_private *tp = netdev_priv(dev);
1449
1450         rtl_lock_work(tp);
1451
1452         if (wol->wolopts)
1453                 tp->features |= RTL_FEATURE_WOL;
1454         else
1455                 tp->features &= ~RTL_FEATURE_WOL;
1456         __rtl8169_set_wol(tp, wol->wolopts);
1457
1458         rtl_unlock_work(tp);
1459
1460         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1461
1462         return 0;
1463 }
1464
1465 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1466 {
1467         return rtl_chip_infos[tp->mac_version].fw_name;
1468 }
1469
1470 static void rtl8169_get_drvinfo(struct net_device *dev,
1471                                 struct ethtool_drvinfo *info)
1472 {
1473         struct rtl8169_private *tp = netdev_priv(dev);
1474         struct rtl_fw *rtl_fw = tp->rtl_fw;
1475
1476         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1478         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1479         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1480         if (!IS_ERR_OR_NULL(rtl_fw))
1481                 strlcpy(info->fw_version, rtl_fw->version,
1482                         sizeof(info->fw_version));
1483 }
1484
1485 static int rtl8169_get_regs_len(struct net_device *dev)
1486 {
1487         return R8169_REGS_SIZE;
1488 }
1489
1490 static int rtl8169_set_speed_tbi(struct net_device *dev,
1491                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1492 {
1493         struct rtl8169_private *tp = netdev_priv(dev);
1494         void __iomem *ioaddr = tp->mmio_addr;
1495         int ret = 0;
1496         u32 reg;
1497
1498         reg = RTL_R32(TBICSR);
1499         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1500             (duplex == DUPLEX_FULL)) {
1501                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1502         } else if (autoneg == AUTONEG_ENABLE)
1503                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1504         else {
1505                 netif_warn(tp, link, dev,
1506                            "incorrect speed setting refused in TBI mode\n");
1507                 ret = -EOPNOTSUPP;
1508         }
1509
1510         return ret;
1511 }
1512
1513 static int rtl8169_set_speed_xmii(struct net_device *dev,
1514                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1515 {
1516         struct rtl8169_private *tp = netdev_priv(dev);
1517         int giga_ctrl, bmcr;
1518         int rc = -EINVAL;
1519
1520         rtl_writephy(tp, 0x1f, 0x0000);
1521
1522         if (autoneg == AUTONEG_ENABLE) {
1523                 int auto_nego;
1524
1525                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1526                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1527                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1528
1529                 if (adv & ADVERTISED_10baseT_Half)
1530                         auto_nego |= ADVERTISE_10HALF;
1531                 if (adv & ADVERTISED_10baseT_Full)
1532                         auto_nego |= ADVERTISE_10FULL;
1533                 if (adv & ADVERTISED_100baseT_Half)
1534                         auto_nego |= ADVERTISE_100HALF;
1535                 if (adv & ADVERTISED_100baseT_Full)
1536                         auto_nego |= ADVERTISE_100FULL;
1537
1538                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1539
1540                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1541                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1542
1543                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1544                 if (tp->mii.supports_gmii) {
1545                         if (adv & ADVERTISED_1000baseT_Half)
1546                                 giga_ctrl |= ADVERTISE_1000HALF;
1547                         if (adv & ADVERTISED_1000baseT_Full)
1548                                 giga_ctrl |= ADVERTISE_1000FULL;
1549                 } else if (adv & (ADVERTISED_1000baseT_Half |
1550                                   ADVERTISED_1000baseT_Full)) {
1551                         netif_info(tp, link, dev,
1552                                    "PHY does not support 1000Mbps\n");
1553                         goto out;
1554                 }
1555
1556                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1557
1558                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1559                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1560         } else {
1561                 giga_ctrl = 0;
1562
1563                 if (speed == SPEED_10)
1564                         bmcr = 0;
1565                 else if (speed == SPEED_100)
1566                         bmcr = BMCR_SPEED100;
1567                 else
1568                         goto out;
1569
1570                 if (duplex == DUPLEX_FULL)
1571                         bmcr |= BMCR_FULLDPLX;
1572         }
1573
1574         rtl_writephy(tp, MII_BMCR, bmcr);
1575
1576         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1577             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1578                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1579                         rtl_writephy(tp, 0x17, 0x2138);
1580                         rtl_writephy(tp, 0x0e, 0x0260);
1581                 } else {
1582                         rtl_writephy(tp, 0x17, 0x2108);
1583                         rtl_writephy(tp, 0x0e, 0x0000);
1584                 }
1585         }
1586
1587         rc = 0;
1588 out:
1589         return rc;
1590 }
1591
1592 static int rtl8169_set_speed(struct net_device *dev,
1593                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         int ret;
1597
1598         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1599         if (ret < 0)
1600                 goto out;
1601
1602         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1603             (advertising & ADVERTISED_1000baseT_Full)) {
1604                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1605         }
1606 out:
1607         return ret;
1608 }
1609
1610 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1611 {
1612         struct rtl8169_private *tp = netdev_priv(dev);
1613         int ret;
1614
1615         del_timer_sync(&tp->timer);
1616
1617         rtl_lock_work(tp);
1618         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1619                                 cmd->duplex, cmd->advertising);
1620         rtl_unlock_work(tp);
1621
1622         return ret;
1623 }
1624
1625 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1626         netdev_features_t features)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629
1630         if (dev->mtu > TD_MSS_MAX)
1631                 features &= ~NETIF_F_ALL_TSO;
1632
1633         if (dev->mtu > JUMBO_1K &&
1634             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1635                 features &= ~NETIF_F_IP_CSUM;
1636
1637         return features;
1638 }
1639
1640 static void __rtl8169_set_features(struct net_device *dev,
1641                                    netdev_features_t features)
1642 {
1643         struct rtl8169_private *tp = netdev_priv(dev);
1644         netdev_features_t changed = features ^ dev->features;
1645         void __iomem *ioaddr = tp->mmio_addr;
1646
1647         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1648                 return;
1649
1650         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1651                 if (features & NETIF_F_RXCSUM)
1652                         tp->cp_cmd |= RxChkSum;
1653                 else
1654                         tp->cp_cmd &= ~RxChkSum;
1655
1656                 if (dev->features & NETIF_F_HW_VLAN_RX)
1657                         tp->cp_cmd |= RxVlan;
1658                 else
1659                         tp->cp_cmd &= ~RxVlan;
1660
1661                 RTL_W16(CPlusCmd, tp->cp_cmd);
1662                 RTL_R16(CPlusCmd);
1663         }
1664         if (changed & NETIF_F_RXALL) {
1665                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1666                 if (features & NETIF_F_RXALL)
1667                         tmp |= (AcceptErr | AcceptRunt);
1668                 RTL_W32(RxConfig, tmp);
1669         }
1670 }
1671
1672 static int rtl8169_set_features(struct net_device *dev,
1673                                 netdev_features_t features)
1674 {
1675         struct rtl8169_private *tp = netdev_priv(dev);
1676
1677         rtl_lock_work(tp);
1678         __rtl8169_set_features(dev, features);
1679         rtl_unlock_work(tp);
1680
1681         return 0;
1682 }
1683
1684
1685 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1686                                       struct sk_buff *skb)
1687 {
1688         return (vlan_tx_tag_present(skb)) ?
1689                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1690 }
1691
1692 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1693 {
1694         u32 opts2 = le32_to_cpu(desc->opts2);
1695
1696         if (opts2 & RxVlanTag)
1697                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1698
1699         desc->opts2 = 0;
1700 }
1701
1702 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1703 {
1704         struct rtl8169_private *tp = netdev_priv(dev);
1705         void __iomem *ioaddr = tp->mmio_addr;
1706         u32 status;
1707
1708         cmd->supported =
1709                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1710         cmd->port = PORT_FIBRE;
1711         cmd->transceiver = XCVR_INTERNAL;
1712
1713         status = RTL_R32(TBICSR);
1714         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1715         cmd->autoneg = !!(status & TBINwEnable);
1716
1717         ethtool_cmd_speed_set(cmd, SPEED_1000);
1718         cmd->duplex = DUPLEX_FULL; /* Always set */
1719
1720         return 0;
1721 }
1722
1723 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1724 {
1725         struct rtl8169_private *tp = netdev_priv(dev);
1726
1727         return mii_ethtool_gset(&tp->mii, cmd);
1728 }
1729
1730 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1731 {
1732         struct rtl8169_private *tp = netdev_priv(dev);
1733         int rc;
1734
1735         rtl_lock_work(tp);
1736         rc = tp->get_settings(dev, cmd);
1737         rtl_unlock_work(tp);
1738
1739         return rc;
1740 }
1741
1742 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1743                              void *p)
1744 {
1745         struct rtl8169_private *tp = netdev_priv(dev);
1746
1747         if (regs->len > R8169_REGS_SIZE)
1748                 regs->len = R8169_REGS_SIZE;
1749
1750         rtl_lock_work(tp);
1751         memcpy_fromio(p, tp->mmio_addr, regs->len);
1752         rtl_unlock_work(tp);
1753 }
1754
1755 static u32 rtl8169_get_msglevel(struct net_device *dev)
1756 {
1757         struct rtl8169_private *tp = netdev_priv(dev);
1758
1759         return tp->msg_enable;
1760 }
1761
1762 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1763 {
1764         struct rtl8169_private *tp = netdev_priv(dev);
1765
1766         tp->msg_enable = value;
1767 }
1768
1769 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1770         "tx_packets",
1771         "rx_packets",
1772         "tx_errors",
1773         "rx_errors",
1774         "rx_missed",
1775         "align_errors",
1776         "tx_single_collisions",
1777         "tx_multi_collisions",
1778         "unicast",
1779         "broadcast",
1780         "multicast",
1781         "tx_aborted",
1782         "tx_underrun",
1783 };
1784
1785 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1786 {
1787         switch (sset) {
1788         case ETH_SS_STATS:
1789                 return ARRAY_SIZE(rtl8169_gstrings);
1790         default:
1791                 return -EOPNOTSUPP;
1792         }
1793 }
1794
1795 static void rtl8169_update_counters(struct net_device *dev)
1796 {
1797         struct rtl8169_private *tp = netdev_priv(dev);
1798         void __iomem *ioaddr = tp->mmio_addr;
1799         struct device *d = &tp->pci_dev->dev;
1800         struct rtl8169_counters *counters;
1801         dma_addr_t paddr;
1802         u32 cmd;
1803         int wait = 1000;
1804
1805         /*
1806          * Some chips are unable to dump tally counters when the receiver
1807          * is disabled.
1808          */
1809         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1810                 return;
1811
1812         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1813         if (!counters)
1814                 return;
1815
1816         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1817         cmd = (u64)paddr & DMA_BIT_MASK(32);
1818         RTL_W32(CounterAddrLow, cmd);
1819         RTL_W32(CounterAddrLow, cmd | CounterDump);
1820
1821         while (wait--) {
1822                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1823                         memcpy(&tp->counters, counters, sizeof(*counters));
1824                         break;
1825                 }
1826                 udelay(10);
1827         }
1828
1829         RTL_W32(CounterAddrLow, 0);
1830         RTL_W32(CounterAddrHigh, 0);
1831
1832         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1833 }
1834
1835 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1836                                       struct ethtool_stats *stats, u64 *data)
1837 {
1838         struct rtl8169_private *tp = netdev_priv(dev);
1839
1840         ASSERT_RTNL();
1841
1842         rtl8169_update_counters(dev);
1843
1844         data[0] = le64_to_cpu(tp->counters.tx_packets);
1845         data[1] = le64_to_cpu(tp->counters.rx_packets);
1846         data[2] = le64_to_cpu(tp->counters.tx_errors);
1847         data[3] = le32_to_cpu(tp->counters.rx_errors);
1848         data[4] = le16_to_cpu(tp->counters.rx_missed);
1849         data[5] = le16_to_cpu(tp->counters.align_errors);
1850         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1851         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1852         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1853         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1854         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1855         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1856         data[12] = le16_to_cpu(tp->counters.tx_underun);
1857 }
1858
1859 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1860 {
1861         switch(stringset) {
1862         case ETH_SS_STATS:
1863                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1864                 break;
1865         }
1866 }
1867
1868 static const struct ethtool_ops rtl8169_ethtool_ops = {
1869         .get_drvinfo            = rtl8169_get_drvinfo,
1870         .get_regs_len           = rtl8169_get_regs_len,
1871         .get_link               = ethtool_op_get_link,
1872         .get_settings           = rtl8169_get_settings,
1873         .set_settings           = rtl8169_set_settings,
1874         .get_msglevel           = rtl8169_get_msglevel,
1875         .set_msglevel           = rtl8169_set_msglevel,
1876         .get_regs               = rtl8169_get_regs,
1877         .get_wol                = rtl8169_get_wol,
1878         .set_wol                = rtl8169_set_wol,
1879         .get_strings            = rtl8169_get_strings,
1880         .get_sset_count         = rtl8169_get_sset_count,
1881         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1882 };
1883
1884 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1885                                     struct net_device *dev, u8 default_version)
1886 {
1887         void __iomem *ioaddr = tp->mmio_addr;
1888         /*
1889          * The driver currently handles the 8168Bf and the 8168Be identically
1890          * but they can be identified more specifically through the test below
1891          * if needed:
1892          *
1893          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1894          *
1895          * Same thing for the 8101Eb and the 8101Ec:
1896          *
1897          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1898          */
1899         static const struct rtl_mac_info {
1900                 u32 mask;
1901                 u32 val;
1902                 int mac_version;
1903         } mac_info[] = {
1904                 /* 8168F family. */
1905                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1906                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1907
1908                 /* 8168E family. */
1909                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1910                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1911                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1912                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1913
1914                 /* 8168D family. */
1915                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1916                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1917                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1918
1919                 /* 8168DP family. */
1920                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1921                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1922                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1923
1924                 /* 8168C family. */
1925                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1926                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1927                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1928                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1929                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1930                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1931                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1932                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1933                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1934
1935                 /* 8168B family. */
1936                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1937                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1938                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1939                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1940
1941                 /* 8101 family. */
1942                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1943                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1944                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1945                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1946                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1947                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1948                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1949                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1950                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1951                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1952                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1953                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1954                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1955                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1956                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1957                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1958                 /* FIXME: where did these entries come from ? -- FR */
1959                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1960                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1961
1962                 /* 8110 family. */
1963                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1964                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1965                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1966                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1967                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1968                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1969
1970                 /* Catch-all */
1971                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1972         };
1973         const struct rtl_mac_info *p = mac_info;
1974         u32 reg;
1975
1976         reg = RTL_R32(TxConfig);
1977         while ((reg & p->mask) != p->val)
1978                 p++;
1979         tp->mac_version = p->mac_version;
1980
1981         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1982                 netif_notice(tp, probe, dev,
1983                              "unknown MAC, using family default\n");
1984                 tp->mac_version = default_version;
1985         }
1986 }
1987
1988 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1989 {
1990         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1991 }
1992
1993 struct phy_reg {
1994         u16 reg;
1995         u16 val;
1996 };
1997
1998 static void rtl_writephy_batch(struct rtl8169_private *tp,
1999                                const struct phy_reg *regs, int len)
2000 {
2001         while (len-- > 0) {
2002                 rtl_writephy(tp, regs->reg, regs->val);
2003                 regs++;
2004         }
2005 }
2006
2007 #define PHY_READ                0x00000000
2008 #define PHY_DATA_OR             0x10000000
2009 #define PHY_DATA_AND            0x20000000
2010 #define PHY_BJMPN               0x30000000
2011 #define PHY_READ_EFUSE          0x40000000
2012 #define PHY_READ_MAC_BYTE       0x50000000
2013 #define PHY_WRITE_MAC_BYTE      0x60000000
2014 #define PHY_CLEAR_READCOUNT     0x70000000
2015 #define PHY_WRITE               0x80000000
2016 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2017 #define PHY_COMP_EQ_SKIPN       0xa0000000
2018 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2019 #define PHY_WRITE_PREVIOUS      0xc0000000
2020 #define PHY_SKIPN               0xd0000000
2021 #define PHY_DELAY_MS            0xe0000000
2022 #define PHY_WRITE_ERI_WORD      0xf0000000
2023
2024 struct fw_info {
2025         u32     magic;
2026         char    version[RTL_VER_SIZE];
2027         __le32  fw_start;
2028         __le32  fw_len;
2029         u8      chksum;
2030 } __packed;
2031
2032 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2033
2034 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2035 {
2036         const struct firmware *fw = rtl_fw->fw;
2037         struct fw_info *fw_info = (struct fw_info *)fw->data;
2038         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2039         char *version = rtl_fw->version;
2040         bool rc = false;
2041
2042         if (fw->size < FW_OPCODE_SIZE)
2043                 goto out;
2044
2045         if (!fw_info->magic) {
2046                 size_t i, size, start;
2047                 u8 checksum = 0;
2048
2049                 if (fw->size < sizeof(*fw_info))
2050                         goto out;
2051
2052                 for (i = 0; i < fw->size; i++)
2053                         checksum += fw->data[i];
2054                 if (checksum != 0)
2055                         goto out;
2056
2057                 start = le32_to_cpu(fw_info->fw_start);
2058                 if (start > fw->size)
2059                         goto out;
2060
2061                 size = le32_to_cpu(fw_info->fw_len);
2062                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2063                         goto out;
2064
2065                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2066
2067                 pa->code = (__le32 *)(fw->data + start);
2068                 pa->size = size;
2069         } else {
2070                 if (fw->size % FW_OPCODE_SIZE)
2071                         goto out;
2072
2073                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2074
2075                 pa->code = (__le32 *)fw->data;
2076                 pa->size = fw->size / FW_OPCODE_SIZE;
2077         }
2078         version[RTL_VER_SIZE - 1] = 0;
2079
2080         rc = true;
2081 out:
2082         return rc;
2083 }
2084
2085 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2086                            struct rtl_fw_phy_action *pa)
2087 {
2088         bool rc = false;
2089         size_t index;
2090
2091         for (index = 0; index < pa->size; index++) {
2092                 u32 action = le32_to_cpu(pa->code[index]);
2093                 u32 regno = (action & 0x0fff0000) >> 16;
2094
2095                 switch(action & 0xf0000000) {
2096                 case PHY_READ:
2097                 case PHY_DATA_OR:
2098                 case PHY_DATA_AND:
2099                 case PHY_READ_EFUSE:
2100                 case PHY_CLEAR_READCOUNT:
2101                 case PHY_WRITE:
2102                 case PHY_WRITE_PREVIOUS:
2103                 case PHY_DELAY_MS:
2104                         break;
2105
2106                 case PHY_BJMPN:
2107                         if (regno > index) {
2108                                 netif_err(tp, ifup, tp->dev,
2109                                           "Out of range of firmware\n");
2110                                 goto out;
2111                         }
2112                         break;
2113                 case PHY_READCOUNT_EQ_SKIP:
2114                         if (index + 2 >= pa->size) {
2115                                 netif_err(tp, ifup, tp->dev,
2116                                           "Out of range of firmware\n");
2117                                 goto out;
2118                         }
2119                         break;
2120                 case PHY_COMP_EQ_SKIPN:
2121                 case PHY_COMP_NEQ_SKIPN:
2122                 case PHY_SKIPN:
2123                         if (index + 1 + regno >= pa->size) {
2124                                 netif_err(tp, ifup, tp->dev,
2125                                           "Out of range of firmware\n");
2126                                 goto out;
2127                         }
2128                         break;
2129
2130                 case PHY_READ_MAC_BYTE:
2131                 case PHY_WRITE_MAC_BYTE:
2132                 case PHY_WRITE_ERI_WORD:
2133                 default:
2134                         netif_err(tp, ifup, tp->dev,
2135                                   "Invalid action 0x%08x\n", action);
2136                         goto out;
2137                 }
2138         }
2139         rc = true;
2140 out:
2141         return rc;
2142 }
2143
2144 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2145 {
2146         struct net_device *dev = tp->dev;
2147         int rc = -EINVAL;
2148
2149         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2150                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2151                 goto out;
2152         }
2153
2154         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2155                 rc = 0;
2156 out:
2157         return rc;
2158 }
2159
2160 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2161 {
2162         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2163         u32 predata, count;
2164         size_t index;
2165
2166         predata = count = 0;
2167
2168         for (index = 0; index < pa->size; ) {
2169                 u32 action = le32_to_cpu(pa->code[index]);
2170                 u32 data = action & 0x0000ffff;
2171                 u32 regno = (action & 0x0fff0000) >> 16;
2172
2173                 if (!action)
2174                         break;
2175
2176                 switch(action & 0xf0000000) {
2177                 case PHY_READ:
2178                         predata = rtl_readphy(tp, regno);
2179                         count++;
2180                         index++;
2181                         break;
2182                 case PHY_DATA_OR:
2183                         predata |= data;
2184                         index++;
2185                         break;
2186                 case PHY_DATA_AND:
2187                         predata &= data;
2188                         index++;
2189                         break;
2190                 case PHY_BJMPN:
2191                         index -= regno;
2192                         break;
2193                 case PHY_READ_EFUSE:
2194                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2195                         index++;
2196                         break;
2197                 case PHY_CLEAR_READCOUNT:
2198                         count = 0;
2199                         index++;
2200                         break;
2201                 case PHY_WRITE:
2202                         rtl_writephy(tp, regno, data);
2203                         index++;
2204                         break;
2205                 case PHY_READCOUNT_EQ_SKIP:
2206                         index += (count == data) ? 2 : 1;
2207                         break;
2208                 case PHY_COMP_EQ_SKIPN:
2209                         if (predata == data)
2210                                 index += regno;
2211                         index++;
2212                         break;
2213                 case PHY_COMP_NEQ_SKIPN:
2214                         if (predata != data)
2215                                 index += regno;
2216                         index++;
2217                         break;
2218                 case PHY_WRITE_PREVIOUS:
2219                         rtl_writephy(tp, regno, predata);
2220                         index++;
2221                         break;
2222                 case PHY_SKIPN:
2223                         index += regno + 1;
2224                         break;
2225                 case PHY_DELAY_MS:
2226                         mdelay(data);
2227                         index++;
2228                         break;
2229
2230                 case PHY_READ_MAC_BYTE:
2231                 case PHY_WRITE_MAC_BYTE:
2232                 case PHY_WRITE_ERI_WORD:
2233                 default:
2234                         BUG();
2235                 }
2236         }
2237 }
2238
2239 static void rtl_release_firmware(struct rtl8169_private *tp)
2240 {
2241         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2242                 release_firmware(tp->rtl_fw->fw);
2243                 kfree(tp->rtl_fw);
2244         }
2245         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2246 }
2247
2248 static void rtl_apply_firmware(struct rtl8169_private *tp)
2249 {
2250         struct rtl_fw *rtl_fw = tp->rtl_fw;
2251
2252         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2253         if (!IS_ERR_OR_NULL(rtl_fw))
2254                 rtl_phy_write_fw(tp, rtl_fw);
2255 }
2256
2257 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2258 {
2259         if (rtl_readphy(tp, reg) != val)
2260                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2261         else
2262                 rtl_apply_firmware(tp);
2263 }
2264
2265 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2266 {
2267         static const struct phy_reg phy_reg_init[] = {
2268                 { 0x1f, 0x0001 },
2269                 { 0x06, 0x006e },
2270                 { 0x08, 0x0708 },
2271                 { 0x15, 0x4000 },
2272                 { 0x18, 0x65c7 },
2273
2274                 { 0x1f, 0x0001 },
2275                 { 0x03, 0x00a1 },
2276                 { 0x02, 0x0008 },
2277                 { 0x01, 0x0120 },
2278                 { 0x00, 0x1000 },
2279                 { 0x04, 0x0800 },
2280                 { 0x04, 0x0000 },
2281
2282                 { 0x03, 0xff41 },
2283                 { 0x02, 0xdf60 },
2284                 { 0x01, 0x0140 },
2285                 { 0x00, 0x0077 },
2286                 { 0x04, 0x7800 },
2287                 { 0x04, 0x7000 },
2288
2289                 { 0x03, 0x802f },
2290                 { 0x02, 0x4f02 },
2291                 { 0x01, 0x0409 },
2292                 { 0x00, 0xf0f9 },
2293                 { 0x04, 0x9800 },
2294                 { 0x04, 0x9000 },
2295
2296                 { 0x03, 0xdf01 },
2297                 { 0x02, 0xdf20 },
2298                 { 0x01, 0xff95 },
2299                 { 0x00, 0xba00 },
2300                 { 0x04, 0xa800 },
2301                 { 0x04, 0xa000 },
2302
2303                 { 0x03, 0xff41 },
2304                 { 0x02, 0xdf20 },
2305                 { 0x01, 0x0140 },
2306                 { 0x00, 0x00bb },
2307                 { 0x04, 0xb800 },
2308                 { 0x04, 0xb000 },
2309
2310                 { 0x03, 0xdf41 },
2311                 { 0x02, 0xdc60 },
2312                 { 0x01, 0x6340 },
2313                 { 0x00, 0x007d },
2314                 { 0x04, 0xd800 },
2315                 { 0x04, 0xd000 },
2316
2317                 { 0x03, 0xdf01 },
2318                 { 0x02, 0xdf20 },
2319                 { 0x01, 0x100a },
2320                 { 0x00, 0xa0ff },
2321                 { 0x04, 0xf800 },
2322                 { 0x04, 0xf000 },
2323
2324                 { 0x1f, 0x0000 },
2325                 { 0x0b, 0x0000 },
2326                 { 0x00, 0x9200 }
2327         };
2328
2329         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2330 }
2331
2332 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2333 {
2334         static const struct phy_reg phy_reg_init[] = {
2335                 { 0x1f, 0x0002 },
2336                 { 0x01, 0x90d0 },
2337                 { 0x1f, 0x0000 }
2338         };
2339
2340         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2341 }
2342
2343 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2344 {
2345         struct pci_dev *pdev = tp->pci_dev;
2346
2347         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2348             (pdev->subsystem_device != 0xe000))
2349                 return;
2350
2351         rtl_writephy(tp, 0x1f, 0x0001);
2352         rtl_writephy(tp, 0x10, 0xf01b);
2353         rtl_writephy(tp, 0x1f, 0x0000);
2354 }
2355
2356 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2357 {
2358         static const struct phy_reg phy_reg_init[] = {
2359                 { 0x1f, 0x0001 },
2360                 { 0x04, 0x0000 },
2361                 { 0x03, 0x00a1 },
2362                 { 0x02, 0x0008 },
2363                 { 0x01, 0x0120 },
2364                 { 0x00, 0x1000 },
2365                 { 0x04, 0x0800 },
2366                 { 0x04, 0x9000 },
2367                 { 0x03, 0x802f },
2368                 { 0x02, 0x4f02 },
2369                 { 0x01, 0x0409 },
2370                 { 0x00, 0xf099 },
2371                 { 0x04, 0x9800 },
2372                 { 0x04, 0xa000 },
2373                 { 0x03, 0xdf01 },
2374                 { 0x02, 0xdf20 },
2375                 { 0x01, 0xff95 },
2376                 { 0x00, 0xba00 },
2377                 { 0x04, 0xa800 },
2378                 { 0x04, 0xf000 },
2379                 { 0x03, 0xdf01 },
2380                 { 0x02, 0xdf20 },
2381                 { 0x01, 0x101a },
2382                 { 0x00, 0xa0ff },
2383                 { 0x04, 0xf800 },
2384                 { 0x04, 0x0000 },
2385                 { 0x1f, 0x0000 },
2386
2387                 { 0x1f, 0x0001 },
2388                 { 0x10, 0xf41b },
2389                 { 0x14, 0xfb54 },
2390                 { 0x18, 0xf5c7 },
2391                 { 0x1f, 0x0000 },
2392
2393                 { 0x1f, 0x0001 },
2394                 { 0x17, 0x0cc0 },
2395                 { 0x1f, 0x0000 }
2396         };
2397
2398         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2399
2400         rtl8169scd_hw_phy_config_quirk(tp);
2401 }
2402
2403 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2404 {
2405         static const struct phy_reg phy_reg_init[] = {
2406                 { 0x1f, 0x0001 },
2407                 { 0x04, 0x0000 },
2408                 { 0x03, 0x00a1 },
2409                 { 0x02, 0x0008 },
2410                 { 0x01, 0x0120 },
2411                 { 0x00, 0x1000 },
2412                 { 0x04, 0x0800 },
2413                 { 0x04, 0x9000 },
2414                 { 0x03, 0x802f },
2415                 { 0x02, 0x4f02 },
2416                 { 0x01, 0x0409 },
2417                 { 0x00, 0xf099 },
2418                 { 0x04, 0x9800 },
2419                 { 0x04, 0xa000 },
2420                 { 0x03, 0xdf01 },
2421                 { 0x02, 0xdf20 },
2422                 { 0x01, 0xff95 },
2423                 { 0x00, 0xba00 },
2424                 { 0x04, 0xa800 },
2425                 { 0x04, 0xf000 },
2426                 { 0x03, 0xdf01 },
2427                 { 0x02, 0xdf20 },
2428                 { 0x01, 0x101a },
2429                 { 0x00, 0xa0ff },
2430                 { 0x04, 0xf800 },
2431                 { 0x04, 0x0000 },
2432                 { 0x1f, 0x0000 },
2433
2434                 { 0x1f, 0x0001 },
2435                 { 0x0b, 0x8480 },
2436                 { 0x1f, 0x0000 },
2437
2438                 { 0x1f, 0x0001 },
2439                 { 0x18, 0x67c7 },
2440                 { 0x04, 0x2000 },
2441                 { 0x03, 0x002f },
2442                 { 0x02, 0x4360 },
2443                 { 0x01, 0x0109 },
2444                 { 0x00, 0x3022 },
2445                 { 0x04, 0x2800 },
2446                 { 0x1f, 0x0000 },
2447
2448                 { 0x1f, 0x0001 },
2449                 { 0x17, 0x0cc0 },
2450                 { 0x1f, 0x0000 }
2451         };
2452
2453         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2454 }
2455
2456 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2457 {
2458         static const struct phy_reg phy_reg_init[] = {
2459                 { 0x10, 0xf41b },
2460                 { 0x1f, 0x0000 }
2461         };
2462
2463         rtl_writephy(tp, 0x1f, 0x0001);
2464         rtl_patchphy(tp, 0x16, 1 << 0);
2465
2466         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2467 }
2468
2469 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2470 {
2471         static const struct phy_reg phy_reg_init[] = {
2472                 { 0x1f, 0x0001 },
2473                 { 0x10, 0xf41b },
2474                 { 0x1f, 0x0000 }
2475         };
2476
2477         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2478 }
2479
2480 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2481 {
2482         static const struct phy_reg phy_reg_init[] = {
2483                 { 0x1f, 0x0000 },
2484                 { 0x1d, 0x0f00 },
2485                 { 0x1f, 0x0002 },
2486                 { 0x0c, 0x1ec8 },
2487                 { 0x1f, 0x0000 }
2488         };
2489
2490         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2491 }
2492
2493 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2494 {
2495         static const struct phy_reg phy_reg_init[] = {
2496                 { 0x1f, 0x0001 },
2497                 { 0x1d, 0x3d98 },
2498                 { 0x1f, 0x0000 }
2499         };
2500
2501         rtl_writephy(tp, 0x1f, 0x0000);
2502         rtl_patchphy(tp, 0x14, 1 << 5);
2503         rtl_patchphy(tp, 0x0d, 1 << 5);
2504
2505         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2506 }
2507
2508 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2509 {
2510         static const struct phy_reg phy_reg_init[] = {
2511                 { 0x1f, 0x0001 },
2512                 { 0x12, 0x2300 },
2513                 { 0x1f, 0x0002 },
2514                 { 0x00, 0x88d4 },
2515                 { 0x01, 0x82b1 },
2516                 { 0x03, 0x7002 },
2517                 { 0x08, 0x9e30 },
2518                 { 0x09, 0x01f0 },
2519                 { 0x0a, 0x5500 },
2520                 { 0x0c, 0x00c8 },
2521                 { 0x1f, 0x0003 },
2522                 { 0x12, 0xc096 },
2523                 { 0x16, 0x000a },
2524                 { 0x1f, 0x0000 },
2525                 { 0x1f, 0x0000 },
2526                 { 0x09, 0x2000 },
2527                 { 0x09, 0x0000 }
2528         };
2529
2530         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2531
2532         rtl_patchphy(tp, 0x14, 1 << 5);
2533         rtl_patchphy(tp, 0x0d, 1 << 5);
2534         rtl_writephy(tp, 0x1f, 0x0000);
2535 }
2536
2537 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2538 {
2539         static const struct phy_reg phy_reg_init[] = {
2540                 { 0x1f, 0x0001 },
2541                 { 0x12, 0x2300 },
2542                 { 0x03, 0x802f },
2543                 { 0x02, 0x4f02 },
2544                 { 0x01, 0x0409 },
2545                 { 0x00, 0xf099 },
2546                 { 0x04, 0x9800 },
2547                 { 0x04, 0x9000 },
2548                 { 0x1d, 0x3d98 },
2549                 { 0x1f, 0x0002 },
2550                 { 0x0c, 0x7eb8 },
2551                 { 0x06, 0x0761 },
2552                 { 0x1f, 0x0003 },
2553                 { 0x16, 0x0f0a },
2554                 { 0x1f, 0x0000 }
2555         };
2556
2557         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2558
2559         rtl_patchphy(tp, 0x16, 1 << 0);
2560         rtl_patchphy(tp, 0x14, 1 << 5);
2561         rtl_patchphy(tp, 0x0d, 1 << 5);
2562         rtl_writephy(tp, 0x1f, 0x0000);
2563 }
2564
2565 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2566 {
2567         static const struct phy_reg phy_reg_init[] = {
2568                 { 0x1f, 0x0001 },
2569                 { 0x12, 0x2300 },
2570                 { 0x1d, 0x3d98 },
2571                 { 0x1f, 0x0002 },
2572                 { 0x0c, 0x7eb8 },
2573                 { 0x06, 0x5461 },
2574                 { 0x1f, 0x0003 },
2575                 { 0x16, 0x0f0a },
2576                 { 0x1f, 0x0000 }
2577         };
2578
2579         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2580
2581         rtl_patchphy(tp, 0x16, 1 << 0);
2582         rtl_patchphy(tp, 0x14, 1 << 5);
2583         rtl_patchphy(tp, 0x0d, 1 << 5);
2584         rtl_writephy(tp, 0x1f, 0x0000);
2585 }
2586
2587 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         rtl8168c_3_hw_phy_config(tp);
2590 }
2591
2592 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2593 {
2594         static const struct phy_reg phy_reg_init_0[] = {
2595                 /* Channel Estimation */
2596                 { 0x1f, 0x0001 },
2597                 { 0x06, 0x4064 },
2598                 { 0x07, 0x2863 },
2599                 { 0x08, 0x059c },
2600                 { 0x09, 0x26b4 },
2601                 { 0x0a, 0x6a19 },
2602                 { 0x0b, 0xdcc8 },
2603                 { 0x10, 0xf06d },
2604                 { 0x14, 0x7f68 },
2605                 { 0x18, 0x7fd9 },
2606                 { 0x1c, 0xf0ff },
2607                 { 0x1d, 0x3d9c },
2608                 { 0x1f, 0x0003 },
2609                 { 0x12, 0xf49f },
2610                 { 0x13, 0x070b },
2611                 { 0x1a, 0x05ad },
2612                 { 0x14, 0x94c0 },
2613
2614                 /*
2615                  * Tx Error Issue
2616                  * Enhance line driver power
2617                  */
2618                 { 0x1f, 0x0002 },
2619                 { 0x06, 0x5561 },
2620                 { 0x1f, 0x0005 },
2621                 { 0x05, 0x8332 },
2622                 { 0x06, 0x5561 },
2623
2624                 /*
2625                  * Can not link to 1Gbps with bad cable
2626                  * Decrease SNR threshold form 21.07dB to 19.04dB
2627                  */
2628                 { 0x1f, 0x0001 },
2629                 { 0x17, 0x0cc0 },
2630
2631                 { 0x1f, 0x0000 },
2632                 { 0x0d, 0xf880 }
2633         };
2634         void __iomem *ioaddr = tp->mmio_addr;
2635
2636         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2637
2638         /*
2639          * Rx Error Issue
2640          * Fine Tune Switching regulator parameter
2641          */
2642         rtl_writephy(tp, 0x1f, 0x0002);
2643         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2644         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2645
2646         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2647                 static const struct phy_reg phy_reg_init[] = {
2648                         { 0x1f, 0x0002 },
2649                         { 0x05, 0x669a },
2650                         { 0x1f, 0x0005 },
2651                         { 0x05, 0x8330 },
2652                         { 0x06, 0x669a },
2653                         { 0x1f, 0x0002 }
2654                 };
2655                 int val;
2656
2657                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2658
2659                 val = rtl_readphy(tp, 0x0d);
2660
2661                 if ((val & 0x00ff) != 0x006c) {
2662                         static const u32 set[] = {
2663                                 0x0065, 0x0066, 0x0067, 0x0068,
2664                                 0x0069, 0x006a, 0x006b, 0x006c
2665                         };
2666                         int i;
2667
2668                         rtl_writephy(tp, 0x1f, 0x0002);
2669
2670                         val &= 0xff00;
2671                         for (i = 0; i < ARRAY_SIZE(set); i++)
2672                                 rtl_writephy(tp, 0x0d, val | set[i]);
2673                 }
2674         } else {
2675                 static const struct phy_reg phy_reg_init[] = {
2676                         { 0x1f, 0x0002 },
2677                         { 0x05, 0x6662 },
2678                         { 0x1f, 0x0005 },
2679                         { 0x05, 0x8330 },
2680                         { 0x06, 0x6662 }
2681                 };
2682
2683                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2684         }
2685
2686         /* RSET couple improve */
2687         rtl_writephy(tp, 0x1f, 0x0002);
2688         rtl_patchphy(tp, 0x0d, 0x0300);
2689         rtl_patchphy(tp, 0x0f, 0x0010);
2690
2691         /* Fine tune PLL performance */
2692         rtl_writephy(tp, 0x1f, 0x0002);
2693         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2694         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2695
2696         rtl_writephy(tp, 0x1f, 0x0005);
2697         rtl_writephy(tp, 0x05, 0x001b);
2698
2699         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2700
2701         rtl_writephy(tp, 0x1f, 0x0000);
2702 }
2703
2704 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706         static const struct phy_reg phy_reg_init_0[] = {
2707                 /* Channel Estimation */
2708                 { 0x1f, 0x0001 },
2709                 { 0x06, 0x4064 },
2710                 { 0x07, 0x2863 },
2711                 { 0x08, 0x059c },
2712                 { 0x09, 0x26b4 },
2713                 { 0x0a, 0x6a19 },
2714                 { 0x0b, 0xdcc8 },
2715                 { 0x10, 0xf06d },
2716                 { 0x14, 0x7f68 },
2717                 { 0x18, 0x7fd9 },
2718                 { 0x1c, 0xf0ff },
2719                 { 0x1d, 0x3d9c },
2720                 { 0x1f, 0x0003 },
2721                 { 0x12, 0xf49f },
2722                 { 0x13, 0x070b },
2723                 { 0x1a, 0x05ad },
2724                 { 0x14, 0x94c0 },
2725
2726                 /*
2727                  * Tx Error Issue
2728                  * Enhance line driver power
2729                  */
2730                 { 0x1f, 0x0002 },
2731                 { 0x06, 0x5561 },
2732                 { 0x1f, 0x0005 },
2733                 { 0x05, 0x8332 },
2734                 { 0x06, 0x5561 },
2735
2736                 /*
2737                  * Can not link to 1Gbps with bad cable
2738                  * Decrease SNR threshold form 21.07dB to 19.04dB
2739                  */
2740                 { 0x1f, 0x0001 },
2741                 { 0x17, 0x0cc0 },
2742
2743                 { 0x1f, 0x0000 },
2744                 { 0x0d, 0xf880 }
2745         };
2746         void __iomem *ioaddr = tp->mmio_addr;
2747
2748         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2749
2750         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2751                 static const struct phy_reg phy_reg_init[] = {
2752                         { 0x1f, 0x0002 },
2753                         { 0x05, 0x669a },
2754                         { 0x1f, 0x0005 },
2755                         { 0x05, 0x8330 },
2756                         { 0x06, 0x669a },
2757
2758                         { 0x1f, 0x0002 }
2759                 };
2760                 int val;
2761
2762                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2763
2764                 val = rtl_readphy(tp, 0x0d);
2765                 if ((val & 0x00ff) != 0x006c) {
2766                         static const u32 set[] = {
2767                                 0x0065, 0x0066, 0x0067, 0x0068,
2768                                 0x0069, 0x006a, 0x006b, 0x006c
2769                         };
2770                         int i;
2771
2772                         rtl_writephy(tp, 0x1f, 0x0002);
2773
2774                         val &= 0xff00;
2775                         for (i = 0; i < ARRAY_SIZE(set); i++)
2776                                 rtl_writephy(tp, 0x0d, val | set[i]);
2777                 }
2778         } else {
2779                 static const struct phy_reg phy_reg_init[] = {
2780                         { 0x1f, 0x0002 },
2781                         { 0x05, 0x2642 },
2782                         { 0x1f, 0x0005 },
2783                         { 0x05, 0x8330 },
2784                         { 0x06, 0x2642 }
2785                 };
2786
2787                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2788         }
2789
2790         /* Fine tune PLL performance */
2791         rtl_writephy(tp, 0x1f, 0x0002);
2792         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2793         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2794
2795         /* Switching regulator Slew rate */
2796         rtl_writephy(tp, 0x1f, 0x0002);
2797         rtl_patchphy(tp, 0x0f, 0x0017);
2798
2799         rtl_writephy(tp, 0x1f, 0x0005);
2800         rtl_writephy(tp, 0x05, 0x001b);
2801
2802         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2803
2804         rtl_writephy(tp, 0x1f, 0x0000);
2805 }
2806
2807 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2808 {
2809         static const struct phy_reg phy_reg_init[] = {
2810                 { 0x1f, 0x0002 },
2811                 { 0x10, 0x0008 },
2812                 { 0x0d, 0x006c },
2813
2814                 { 0x1f, 0x0000 },
2815                 { 0x0d, 0xf880 },
2816
2817                 { 0x1f, 0x0001 },
2818                 { 0x17, 0x0cc0 },
2819
2820                 { 0x1f, 0x0001 },
2821                 { 0x0b, 0xa4d8 },
2822                 { 0x09, 0x281c },
2823                 { 0x07, 0x2883 },
2824                 { 0x0a, 0x6b35 },
2825                 { 0x1d, 0x3da4 },
2826                 { 0x1c, 0xeffd },
2827                 { 0x14, 0x7f52 },
2828                 { 0x18, 0x7fc6 },
2829                 { 0x08, 0x0601 },
2830                 { 0x06, 0x4063 },
2831                 { 0x10, 0xf074 },
2832                 { 0x1f, 0x0003 },
2833                 { 0x13, 0x0789 },
2834                 { 0x12, 0xf4bd },
2835                 { 0x1a, 0x04fd },
2836                 { 0x14, 0x84b0 },
2837                 { 0x1f, 0x0000 },
2838                 { 0x00, 0x9200 },
2839
2840                 { 0x1f, 0x0005 },
2841                 { 0x01, 0x0340 },
2842                 { 0x1f, 0x0001 },
2843                 { 0x04, 0x4000 },
2844                 { 0x03, 0x1d21 },
2845                 { 0x02, 0x0c32 },
2846                 { 0x01, 0x0200 },
2847                 { 0x00, 0x5554 },
2848                 { 0x04, 0x4800 },
2849                 { 0x04, 0x4000 },
2850                 { 0x04, 0xf000 },
2851                 { 0x03, 0xdf01 },
2852                 { 0x02, 0xdf20 },
2853                 { 0x01, 0x101a },
2854                 { 0x00, 0xa0ff },
2855                 { 0x04, 0xf800 },
2856                 { 0x04, 0xf000 },
2857                 { 0x1f, 0x0000 },
2858
2859                 { 0x1f, 0x0007 },
2860                 { 0x1e, 0x0023 },
2861                 { 0x16, 0x0000 },
2862                 { 0x1f, 0x0000 }
2863         };
2864
2865         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866 }
2867
2868 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2869 {
2870         static const struct phy_reg phy_reg_init[] = {
2871                 { 0x1f, 0x0001 },
2872                 { 0x17, 0x0cc0 },
2873
2874                 { 0x1f, 0x0007 },
2875                 { 0x1e, 0x002d },
2876                 { 0x18, 0x0040 },
2877                 { 0x1f, 0x0000 }
2878         };
2879
2880         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2881         rtl_patchphy(tp, 0x0d, 1 << 5);
2882 }
2883
2884 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2885 {
2886         static const struct phy_reg phy_reg_init[] = {
2887                 /* Enable Delay cap */
2888                 { 0x1f, 0x0005 },
2889                 { 0x05, 0x8b80 },
2890                 { 0x06, 0xc896 },
2891                 { 0x1f, 0x0000 },
2892
2893                 /* Channel estimation fine tune */
2894                 { 0x1f, 0x0001 },
2895                 { 0x0b, 0x6c20 },
2896                 { 0x07, 0x2872 },
2897                 { 0x1c, 0xefff },
2898                 { 0x1f, 0x0003 },
2899                 { 0x14, 0x6420 },
2900                 { 0x1f, 0x0000 },
2901
2902                 /* Update PFM & 10M TX idle timer */
2903                 { 0x1f, 0x0007 },
2904                 { 0x1e, 0x002f },
2905                 { 0x15, 0x1919 },
2906                 { 0x1f, 0x0000 },
2907
2908                 { 0x1f, 0x0007 },
2909                 { 0x1e, 0x00ac },
2910                 { 0x18, 0x0006 },
2911                 { 0x1f, 0x0000 }
2912         };
2913
2914         rtl_apply_firmware(tp);
2915
2916         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2917
2918         /* DCO enable for 10M IDLE Power */
2919         rtl_writephy(tp, 0x1f, 0x0007);
2920         rtl_writephy(tp, 0x1e, 0x0023);
2921         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2922         rtl_writephy(tp, 0x1f, 0x0000);
2923
2924         /* For impedance matching */
2925         rtl_writephy(tp, 0x1f, 0x0002);
2926         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2927         rtl_writephy(tp, 0x1f, 0x0000);
2928
2929         /* PHY auto speed down */
2930         rtl_writephy(tp, 0x1f, 0x0007);
2931         rtl_writephy(tp, 0x1e, 0x002d);
2932         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2933         rtl_writephy(tp, 0x1f, 0x0000);
2934         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2935
2936         rtl_writephy(tp, 0x1f, 0x0005);
2937         rtl_writephy(tp, 0x05, 0x8b86);
2938         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2939         rtl_writephy(tp, 0x1f, 0x0000);
2940
2941         rtl_writephy(tp, 0x1f, 0x0005);
2942         rtl_writephy(tp, 0x05, 0x8b85);
2943         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2944         rtl_writephy(tp, 0x1f, 0x0007);
2945         rtl_writephy(tp, 0x1e, 0x0020);
2946         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2947         rtl_writephy(tp, 0x1f, 0x0006);
2948         rtl_writephy(tp, 0x00, 0x5a00);
2949         rtl_writephy(tp, 0x1f, 0x0000);
2950         rtl_writephy(tp, 0x0d, 0x0007);
2951         rtl_writephy(tp, 0x0e, 0x003c);
2952         rtl_writephy(tp, 0x0d, 0x4007);
2953         rtl_writephy(tp, 0x0e, 0x0000);
2954         rtl_writephy(tp, 0x0d, 0x0000);
2955 }
2956
2957 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2958 {
2959         static const struct phy_reg phy_reg_init[] = {
2960                 /* Enable Delay cap */
2961                 { 0x1f, 0x0004 },
2962                 { 0x1f, 0x0007 },
2963                 { 0x1e, 0x00ac },
2964                 { 0x18, 0x0006 },
2965                 { 0x1f, 0x0002 },
2966                 { 0x1f, 0x0000 },
2967                 { 0x1f, 0x0000 },
2968
2969                 /* Channel estimation fine tune */
2970                 { 0x1f, 0x0003 },
2971                 { 0x09, 0xa20f },
2972                 { 0x1f, 0x0000 },
2973                 { 0x1f, 0x0000 },
2974
2975                 /* Green Setting */
2976                 { 0x1f, 0x0005 },
2977                 { 0x05, 0x8b5b },
2978                 { 0x06, 0x9222 },
2979                 { 0x05, 0x8b6d },
2980                 { 0x06, 0x8000 },
2981                 { 0x05, 0x8b76 },
2982                 { 0x06, 0x8000 },
2983                 { 0x1f, 0x0000 }
2984         };
2985
2986         rtl_apply_firmware(tp);
2987
2988         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2989
2990         /* For 4-corner performance improve */
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x8b80);
2993         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2994         rtl_writephy(tp, 0x1f, 0x0000);
2995
2996         /* PHY auto speed down */
2997         rtl_writephy(tp, 0x1f, 0x0004);
2998         rtl_writephy(tp, 0x1f, 0x0007);
2999         rtl_writephy(tp, 0x1e, 0x002d);
3000         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3001         rtl_writephy(tp, 0x1f, 0x0002);
3002         rtl_writephy(tp, 0x1f, 0x0000);
3003         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3004
3005         /* improve 10M EEE waveform */
3006         rtl_writephy(tp, 0x1f, 0x0005);
3007         rtl_writephy(tp, 0x05, 0x8b86);
3008         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3009         rtl_writephy(tp, 0x1f, 0x0000);
3010
3011         /* Improve 2-pair detection performance */
3012         rtl_writephy(tp, 0x1f, 0x0005);
3013         rtl_writephy(tp, 0x05, 0x8b85);
3014         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3015         rtl_writephy(tp, 0x1f, 0x0000);
3016
3017         /* EEE setting */
3018         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3019                      ERIAR_EXGMAC);
3020         rtl_writephy(tp, 0x1f, 0x0005);
3021         rtl_writephy(tp, 0x05, 0x8b85);
3022         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3023         rtl_writephy(tp, 0x1f, 0x0004);
3024         rtl_writephy(tp, 0x1f, 0x0007);
3025         rtl_writephy(tp, 0x1e, 0x0020);
3026         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3027         rtl_writephy(tp, 0x1f, 0x0002);
3028         rtl_writephy(tp, 0x1f, 0x0000);
3029         rtl_writephy(tp, 0x0d, 0x0007);
3030         rtl_writephy(tp, 0x0e, 0x003c);
3031         rtl_writephy(tp, 0x0d, 0x4007);
3032         rtl_writephy(tp, 0x0e, 0x0000);
3033         rtl_writephy(tp, 0x0d, 0x0000);
3034
3035         /* Green feature */
3036         rtl_writephy(tp, 0x1f, 0x0003);
3037         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3038         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3039         rtl_writephy(tp, 0x1f, 0x0000);
3040 }
3041
3042 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3043 {
3044         static const struct phy_reg phy_reg_init[] = {
3045                 /* Channel estimation fine tune */
3046                 { 0x1f, 0x0003 },
3047                 { 0x09, 0xa20f },
3048                 { 0x1f, 0x0000 },
3049
3050                 /* Modify green table for giga & fnet */
3051                 { 0x1f, 0x0005 },
3052                 { 0x05, 0x8b55 },
3053                 { 0x06, 0x0000 },
3054                 { 0x05, 0x8b5e },
3055                 { 0x06, 0x0000 },
3056                 { 0x05, 0x8b67 },
3057                 { 0x06, 0x0000 },
3058                 { 0x05, 0x8b70 },
3059                 { 0x06, 0x0000 },
3060                 { 0x1f, 0x0000 },
3061                 { 0x1f, 0x0007 },
3062                 { 0x1e, 0x0078 },
3063                 { 0x17, 0x0000 },
3064                 { 0x19, 0x00fb },
3065                 { 0x1f, 0x0000 },
3066
3067                 /* Modify green table for 10M */
3068                 { 0x1f, 0x0005 },
3069                 { 0x05, 0x8b79 },
3070                 { 0x06, 0xaa00 },
3071                 { 0x1f, 0x0000 },
3072
3073                 /* Disable hiimpedance detection (RTCT) */
3074                 { 0x1f, 0x0003 },
3075                 { 0x01, 0x328a },
3076                 { 0x1f, 0x0000 }
3077         };
3078
3079         rtl_apply_firmware(tp);
3080
3081         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3082
3083         /* For 4-corner performance improve */
3084         rtl_writephy(tp, 0x1f, 0x0005);
3085         rtl_writephy(tp, 0x05, 0x8b80);
3086         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3087         rtl_writephy(tp, 0x1f, 0x0000);
3088
3089         /* PHY auto speed down */
3090         rtl_writephy(tp, 0x1f, 0x0007);
3091         rtl_writephy(tp, 0x1e, 0x002d);
3092         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3093         rtl_writephy(tp, 0x1f, 0x0000);
3094         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3095
3096         /* Improve 10M EEE waveform */
3097         rtl_writephy(tp, 0x1f, 0x0005);
3098         rtl_writephy(tp, 0x05, 0x8b86);
3099         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3100         rtl_writephy(tp, 0x1f, 0x0000);
3101
3102         /* Improve 2-pair detection performance */
3103         rtl_writephy(tp, 0x1f, 0x0005);
3104         rtl_writephy(tp, 0x05, 0x8b85);
3105         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3106         rtl_writephy(tp, 0x1f, 0x0000);
3107 }
3108
3109 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3110 {
3111         rtl_apply_firmware(tp);
3112
3113         /* For 4-corner performance improve */
3114         rtl_writephy(tp, 0x1f, 0x0005);
3115         rtl_writephy(tp, 0x05, 0x8b80);
3116         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3117         rtl_writephy(tp, 0x1f, 0x0000);
3118
3119         /* PHY auto speed down */
3120         rtl_writephy(tp, 0x1f, 0x0007);
3121         rtl_writephy(tp, 0x1e, 0x002d);
3122         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3123         rtl_writephy(tp, 0x1f, 0x0000);
3124         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3125
3126         /* Improve 10M EEE waveform */
3127         rtl_writephy(tp, 0x1f, 0x0005);
3128         rtl_writephy(tp, 0x05, 0x8b86);
3129         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3130         rtl_writephy(tp, 0x1f, 0x0000);
3131 }
3132
3133 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3134 {
3135         static const struct phy_reg phy_reg_init[] = {
3136                 { 0x1f, 0x0003 },
3137                 { 0x08, 0x441d },
3138                 { 0x01, 0x9100 },
3139                 { 0x1f, 0x0000 }
3140         };
3141
3142         rtl_writephy(tp, 0x1f, 0x0000);
3143         rtl_patchphy(tp, 0x11, 1 << 12);
3144         rtl_patchphy(tp, 0x19, 1 << 13);
3145         rtl_patchphy(tp, 0x10, 1 << 15);
3146
3147         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3148 }
3149
3150 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3151 {
3152         static const struct phy_reg phy_reg_init[] = {
3153                 { 0x1f, 0x0005 },
3154                 { 0x1a, 0x0000 },
3155                 { 0x1f, 0x0000 },
3156
3157                 { 0x1f, 0x0004 },
3158                 { 0x1c, 0x0000 },
3159                 { 0x1f, 0x0000 },
3160
3161                 { 0x1f, 0x0001 },
3162                 { 0x15, 0x7701 },
3163                 { 0x1f, 0x0000 }
3164         };
3165
3166         /* Disable ALDPS before ram code */
3167         rtl_writephy(tp, 0x1f, 0x0000);
3168         rtl_writephy(tp, 0x18, 0x0310);
3169         msleep(100);
3170
3171         rtl_apply_firmware(tp);
3172
3173         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3174 }
3175
3176 static void rtl_hw_phy_config(struct net_device *dev)
3177 {
3178         struct rtl8169_private *tp = netdev_priv(dev);
3179
3180         rtl8169_print_mac_version(tp);
3181
3182         switch (tp->mac_version) {
3183         case RTL_GIGA_MAC_VER_01:
3184                 break;
3185         case RTL_GIGA_MAC_VER_02:
3186         case RTL_GIGA_MAC_VER_03:
3187                 rtl8169s_hw_phy_config(tp);
3188                 break;
3189         case RTL_GIGA_MAC_VER_04:
3190                 rtl8169sb_hw_phy_config(tp);
3191                 break;
3192         case RTL_GIGA_MAC_VER_05:
3193                 rtl8169scd_hw_phy_config(tp);
3194                 break;
3195         case RTL_GIGA_MAC_VER_06:
3196                 rtl8169sce_hw_phy_config(tp);
3197                 break;
3198         case RTL_GIGA_MAC_VER_07:
3199         case RTL_GIGA_MAC_VER_08:
3200         case RTL_GIGA_MAC_VER_09:
3201                 rtl8102e_hw_phy_config(tp);
3202                 break;
3203         case RTL_GIGA_MAC_VER_11:
3204                 rtl8168bb_hw_phy_config(tp);
3205                 break;
3206         case RTL_GIGA_MAC_VER_12:
3207                 rtl8168bef_hw_phy_config(tp);
3208                 break;
3209         case RTL_GIGA_MAC_VER_17:
3210                 rtl8168bef_hw_phy_config(tp);
3211                 break;
3212         case RTL_GIGA_MAC_VER_18:
3213                 rtl8168cp_1_hw_phy_config(tp);
3214                 break;
3215         case RTL_GIGA_MAC_VER_19:
3216                 rtl8168c_1_hw_phy_config(tp);
3217                 break;
3218         case RTL_GIGA_MAC_VER_20:
3219                 rtl8168c_2_hw_phy_config(tp);
3220                 break;
3221         case RTL_GIGA_MAC_VER_21:
3222                 rtl8168c_3_hw_phy_config(tp);
3223                 break;
3224         case RTL_GIGA_MAC_VER_22:
3225                 rtl8168c_4_hw_phy_config(tp);
3226                 break;
3227         case RTL_GIGA_MAC_VER_23:
3228         case RTL_GIGA_MAC_VER_24:
3229                 rtl8168cp_2_hw_phy_config(tp);
3230                 break;
3231         case RTL_GIGA_MAC_VER_25:
3232                 rtl8168d_1_hw_phy_config(tp);
3233                 break;
3234         case RTL_GIGA_MAC_VER_26:
3235                 rtl8168d_2_hw_phy_config(tp);
3236                 break;
3237         case RTL_GIGA_MAC_VER_27:
3238                 rtl8168d_3_hw_phy_config(tp);
3239                 break;
3240         case RTL_GIGA_MAC_VER_28:
3241                 rtl8168d_4_hw_phy_config(tp);
3242                 break;
3243         case RTL_GIGA_MAC_VER_29:
3244         case RTL_GIGA_MAC_VER_30:
3245                 rtl8105e_hw_phy_config(tp);
3246                 break;
3247         case RTL_GIGA_MAC_VER_31:
3248                 /* None. */
3249                 break;
3250         case RTL_GIGA_MAC_VER_32:
3251         case RTL_GIGA_MAC_VER_33:
3252                 rtl8168e_1_hw_phy_config(tp);
3253                 break;
3254         case RTL_GIGA_MAC_VER_34:
3255                 rtl8168e_2_hw_phy_config(tp);
3256                 break;
3257         case RTL_GIGA_MAC_VER_35:
3258                 rtl8168f_1_hw_phy_config(tp);
3259                 break;
3260         case RTL_GIGA_MAC_VER_36:
3261                 rtl8168f_2_hw_phy_config(tp);
3262                 break;
3263
3264         default:
3265                 break;
3266         }
3267 }
3268
3269 static void rtl_phy_work(struct rtl8169_private *tp)
3270 {
3271         struct timer_list *timer = &tp->timer;
3272         void __iomem *ioaddr = tp->mmio_addr;
3273         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3274
3275         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3276
3277         if (tp->phy_reset_pending(tp)) {
3278                 /*
3279                  * A busy loop could burn quite a few cycles on nowadays CPU.
3280                  * Let's delay the execution of the timer for a few ticks.
3281                  */
3282                 timeout = HZ/10;
3283                 goto out_mod_timer;
3284         }
3285
3286         if (tp->link_ok(ioaddr))
3287                 return;
3288
3289         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3290
3291         tp->phy_reset_enable(tp);
3292
3293 out_mod_timer:
3294         mod_timer(timer, jiffies + timeout);
3295 }
3296
3297 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3298 {
3299         if (!test_and_set_bit(flag, tp->wk.flags))
3300                 schedule_work(&tp->wk.work);
3301 }
3302
3303 static void rtl8169_phy_timer(unsigned long __opaque)
3304 {
3305         struct net_device *dev = (struct net_device *)__opaque;
3306         struct rtl8169_private *tp = netdev_priv(dev);
3307
3308         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3309 }
3310
3311 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3312                                   void __iomem *ioaddr)
3313 {
3314         iounmap(ioaddr);
3315         pci_release_regions(pdev);
3316         pci_clear_mwi(pdev);
3317         pci_disable_device(pdev);
3318         free_netdev(dev);
3319 }
3320
3321 static void rtl8169_phy_reset(struct net_device *dev,
3322                               struct rtl8169_private *tp)
3323 {
3324         unsigned int i;
3325
3326         tp->phy_reset_enable(tp);
3327         for (i = 0; i < 100; i++) {
3328                 if (!tp->phy_reset_pending(tp))
3329                         return;
3330                 msleep(1);
3331         }
3332         netif_err(tp, link, dev, "PHY reset failed\n");
3333 }
3334
3335 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3336 {
3337         void __iomem *ioaddr = tp->mmio_addr;
3338
3339         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3340             (RTL_R8(PHYstatus) & TBI_Enable);
3341 }
3342
3343 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3344 {
3345         void __iomem *ioaddr = tp->mmio_addr;
3346
3347         rtl_hw_phy_config(dev);
3348
3349         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3350                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3351                 RTL_W8(0x82, 0x01);
3352         }
3353
3354         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3355
3356         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3357                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3358
3359         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3360                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3361                 RTL_W8(0x82, 0x01);
3362                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3363                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3364         }
3365
3366         rtl8169_phy_reset(dev, tp);
3367
3368         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3369                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3370                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3371                           (tp->mii.supports_gmii ?
3372                            ADVERTISED_1000baseT_Half |
3373                            ADVERTISED_1000baseT_Full : 0));
3374
3375         if (rtl_tbi_enabled(tp))
3376                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3377 }
3378
3379 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3380 {
3381         void __iomem *ioaddr = tp->mmio_addr;
3382         u32 high;
3383         u32 low;
3384
3385         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3386         high = addr[4] | (addr[5] << 8);
3387
3388         rtl_lock_work(tp);
3389
3390         RTL_W8(Cfg9346, Cfg9346_Unlock);
3391
3392         RTL_W32(MAC4, high);
3393         RTL_R32(MAC4);
3394
3395         RTL_W32(MAC0, low);
3396         RTL_R32(MAC0);
3397
3398         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3399                 const struct exgmac_reg e[] = {
3400                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3401                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3402                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3403                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3404                                                                 low  >> 16 },
3405                 };
3406
3407                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3408         }
3409
3410         RTL_W8(Cfg9346, Cfg9346_Lock);
3411
3412         rtl_unlock_work(tp);
3413 }
3414
3415 static int rtl_set_mac_address(struct net_device *dev, void *p)
3416 {
3417         struct rtl8169_private *tp = netdev_priv(dev);
3418         struct sockaddr *addr = p;
3419
3420         if (!is_valid_ether_addr(addr->sa_data))
3421                 return -EADDRNOTAVAIL;
3422
3423         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3424
3425         rtl_rar_set(tp, dev->dev_addr);
3426
3427         return 0;
3428 }
3429
3430 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3431 {
3432         struct rtl8169_private *tp = netdev_priv(dev);
3433         struct mii_ioctl_data *data = if_mii(ifr);
3434
3435         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3436 }
3437
3438 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3439                           struct mii_ioctl_data *data, int cmd)
3440 {
3441         switch (cmd) {
3442         case SIOCGMIIPHY:
3443                 data->phy_id = 32; /* Internal PHY */
3444                 return 0;
3445
3446         case SIOCGMIIREG:
3447                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3448                 return 0;
3449
3450         case SIOCSMIIREG:
3451                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3452                 return 0;
3453         }
3454         return -EOPNOTSUPP;
3455 }
3456
3457 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3458 {
3459         return -EOPNOTSUPP;
3460 }
3461
3462 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3463 {
3464         if (tp->features & RTL_FEATURE_MSI) {
3465                 pci_disable_msi(pdev);
3466                 tp->features &= ~RTL_FEATURE_MSI;
3467         }
3468 }
3469
3470 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3471 {
3472         struct mdio_ops *ops = &tp->mdio_ops;
3473
3474         switch (tp->mac_version) {
3475         case RTL_GIGA_MAC_VER_27:
3476                 ops->write      = r8168dp_1_mdio_write;
3477                 ops->read       = r8168dp_1_mdio_read;
3478                 break;
3479         case RTL_GIGA_MAC_VER_28:
3480         case RTL_GIGA_MAC_VER_31:
3481                 ops->write      = r8168dp_2_mdio_write;
3482                 ops->read       = r8168dp_2_mdio_read;
3483                 break;
3484         default:
3485                 ops->write      = r8169_mdio_write;
3486                 ops->read       = r8169_mdio_read;
3487                 break;
3488         }
3489 }
3490
3491 static void rtl_speed_down(struct rtl8169_private *tp)
3492 {
3493         u32 adv;
3494         int lpa;
3495
3496         rtl_writephy(tp, 0x1f, 0x0000);
3497         lpa = rtl_readphy(tp, MII_LPA);
3498
3499         if (lpa & (LPA_10HALF | LPA_10FULL))
3500                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3501         else if (lpa & (LPA_100HALF | LPA_100FULL))
3502                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3503                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3504         else
3505                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3506                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3507                       (tp->mii.supports_gmii ?
3508                        ADVERTISED_1000baseT_Half |
3509                        ADVERTISED_1000baseT_Full : 0);
3510
3511         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3512                           adv);
3513 }
3514
3515 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3516 {
3517         void __iomem *ioaddr = tp->mmio_addr;
3518
3519         switch (tp->mac_version) {
3520         case RTL_GIGA_MAC_VER_29:
3521         case RTL_GIGA_MAC_VER_30:
3522         case RTL_GIGA_MAC_VER_32:
3523         case RTL_GIGA_MAC_VER_33:
3524         case RTL_GIGA_MAC_VER_34:
3525                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3526                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3527                 break;
3528         default:
3529                 break;
3530         }
3531 }
3532
3533 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3534 {
3535         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3536                 return false;
3537
3538         rtl_speed_down(tp);
3539         rtl_wol_suspend_quirk(tp);
3540
3541         return true;
3542 }
3543
3544 static void r810x_phy_power_down(struct rtl8169_private *tp)
3545 {
3546         rtl_writephy(tp, 0x1f, 0x0000);
3547         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3548 }
3549
3550 static void r810x_phy_power_up(struct rtl8169_private *tp)
3551 {
3552         rtl_writephy(tp, 0x1f, 0x0000);
3553         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3554 }
3555
3556 static void r810x_pll_power_down(struct rtl8169_private *tp)
3557 {
3558         if (rtl_wol_pll_power_down(tp))
3559                 return;
3560
3561         r810x_phy_power_down(tp);
3562 }
3563
3564 static void r810x_pll_power_up(struct rtl8169_private *tp)
3565 {
3566         r810x_phy_power_up(tp);
3567 }
3568
3569 static void r8168_phy_power_up(struct rtl8169_private *tp)
3570 {
3571         rtl_writephy(tp, 0x1f, 0x0000);
3572         switch (tp->mac_version) {
3573         case RTL_GIGA_MAC_VER_11:
3574         case RTL_GIGA_MAC_VER_12:
3575         case RTL_GIGA_MAC_VER_17:
3576         case RTL_GIGA_MAC_VER_18:
3577         case RTL_GIGA_MAC_VER_19:
3578         case RTL_GIGA_MAC_VER_20:
3579         case RTL_GIGA_MAC_VER_21:
3580         case RTL_GIGA_MAC_VER_22:
3581         case RTL_GIGA_MAC_VER_23:
3582         case RTL_GIGA_MAC_VER_24:
3583         case RTL_GIGA_MAC_VER_25:
3584         case RTL_GIGA_MAC_VER_26:
3585         case RTL_GIGA_MAC_VER_27:
3586         case RTL_GIGA_MAC_VER_28:
3587         case RTL_GIGA_MAC_VER_31:
3588                 rtl_writephy(tp, 0x0e, 0x0000);
3589                 break;
3590         default:
3591                 break;
3592         }
3593         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3594 }
3595
3596 static void r8168_phy_power_down(struct rtl8169_private *tp)
3597 {
3598         rtl_writephy(tp, 0x1f, 0x0000);
3599         switch (tp->mac_version) {
3600         case RTL_GIGA_MAC_VER_32:
3601         case RTL_GIGA_MAC_VER_33:
3602                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3603                 break;
3604
3605         case RTL_GIGA_MAC_VER_11:
3606         case RTL_GIGA_MAC_VER_12:
3607         case RTL_GIGA_MAC_VER_17:
3608         case RTL_GIGA_MAC_VER_18:
3609         case RTL_GIGA_MAC_VER_19:
3610         case RTL_GIGA_MAC_VER_20:
3611         case RTL_GIGA_MAC_VER_21:
3612         case RTL_GIGA_MAC_VER_22:
3613         case RTL_GIGA_MAC_VER_23:
3614         case RTL_GIGA_MAC_VER_24:
3615         case RTL_GIGA_MAC_VER_25:
3616         case RTL_GIGA_MAC_VER_26:
3617         case RTL_GIGA_MAC_VER_27:
3618         case RTL_GIGA_MAC_VER_28:
3619         case RTL_GIGA_MAC_VER_31:
3620                 rtl_writephy(tp, 0x0e, 0x0200);
3621         default:
3622                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3623                 break;
3624         }
3625 }
3626
3627 static void r8168_pll_power_down(struct rtl8169_private *tp)
3628 {
3629         void __iomem *ioaddr = tp->mmio_addr;
3630
3631         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3632              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3633              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3634             r8168dp_check_dash(tp)) {
3635                 return;
3636         }
3637
3638         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3639              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3640             (RTL_R16(CPlusCmd) & ASF)) {
3641                 return;
3642         }
3643
3644         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3645             tp->mac_version == RTL_GIGA_MAC_VER_33)
3646                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3647
3648         if (rtl_wol_pll_power_down(tp))
3649                 return;
3650
3651         r8168_phy_power_down(tp);
3652
3653         switch (tp->mac_version) {
3654         case RTL_GIGA_MAC_VER_25:
3655         case RTL_GIGA_MAC_VER_26:
3656         case RTL_GIGA_MAC_VER_27:
3657         case RTL_GIGA_MAC_VER_28:
3658         case RTL_GIGA_MAC_VER_31:
3659         case RTL_GIGA_MAC_VER_32:
3660         case RTL_GIGA_MAC_VER_33:
3661                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3662                 break;
3663         }
3664 }
3665
3666 static void r8168_pll_power_up(struct rtl8169_private *tp)
3667 {
3668         void __iomem *ioaddr = tp->mmio_addr;
3669
3670         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3671              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3672              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3673             r8168dp_check_dash(tp)) {
3674                 return;
3675         }
3676
3677         switch (tp->mac_version) {
3678         case RTL_GIGA_MAC_VER_25:
3679         case RTL_GIGA_MAC_VER_26:
3680         case RTL_GIGA_MAC_VER_27:
3681         case RTL_GIGA_MAC_VER_28:
3682         case RTL_GIGA_MAC_VER_31:
3683         case RTL_GIGA_MAC_VER_32:
3684         case RTL_GIGA_MAC_VER_33:
3685                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3686                 break;
3687         }
3688
3689         r8168_phy_power_up(tp);
3690 }
3691
3692 static void rtl_generic_op(struct rtl8169_private *tp,
3693                            void (*op)(struct rtl8169_private *))
3694 {
3695         if (op)
3696                 op(tp);
3697 }
3698
3699 static void rtl_pll_power_down(struct rtl8169_private *tp)
3700 {
3701         rtl_generic_op(tp, tp->pll_power_ops.down);
3702 }
3703
3704 static void rtl_pll_power_up(struct rtl8169_private *tp)
3705 {
3706         rtl_generic_op(tp, tp->pll_power_ops.up);
3707 }
3708
3709 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3710 {
3711         struct pll_power_ops *ops = &tp->pll_power_ops;
3712
3713         switch (tp->mac_version) {
3714         case RTL_GIGA_MAC_VER_07:
3715         case RTL_GIGA_MAC_VER_08:
3716         case RTL_GIGA_MAC_VER_09:
3717         case RTL_GIGA_MAC_VER_10:
3718         case RTL_GIGA_MAC_VER_16:
3719         case RTL_GIGA_MAC_VER_29:
3720         case RTL_GIGA_MAC_VER_30:
3721                 ops->down       = r810x_pll_power_down;
3722                 ops->up         = r810x_pll_power_up;
3723                 break;
3724
3725         case RTL_GIGA_MAC_VER_11:
3726         case RTL_GIGA_MAC_VER_12:
3727         case RTL_GIGA_MAC_VER_17:
3728         case RTL_GIGA_MAC_VER_18:
3729         case RTL_GIGA_MAC_VER_19:
3730         case RTL_GIGA_MAC_VER_20:
3731         case RTL_GIGA_MAC_VER_21:
3732         case RTL_GIGA_MAC_VER_22:
3733         case RTL_GIGA_MAC_VER_23:
3734         case RTL_GIGA_MAC_VER_24:
3735         case RTL_GIGA_MAC_VER_25:
3736         case RTL_GIGA_MAC_VER_26:
3737         case RTL_GIGA_MAC_VER_27:
3738         case RTL_GIGA_MAC_VER_28:
3739         case RTL_GIGA_MAC_VER_31:
3740         case RTL_GIGA_MAC_VER_32:
3741         case RTL_GIGA_MAC_VER_33:
3742         case RTL_GIGA_MAC_VER_34:
3743         case RTL_GIGA_MAC_VER_35:
3744         case RTL_GIGA_MAC_VER_36:
3745                 ops->down       = r8168_pll_power_down;
3746                 ops->up         = r8168_pll_power_up;
3747                 break;
3748
3749         default:
3750                 ops->down       = NULL;
3751                 ops->up         = NULL;
3752                 break;
3753         }
3754 }
3755
3756 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3757 {
3758         void __iomem *ioaddr = tp->mmio_addr;
3759
3760         switch (tp->mac_version) {
3761         case RTL_GIGA_MAC_VER_01:
3762         case RTL_GIGA_MAC_VER_02:
3763         case RTL_GIGA_MAC_VER_03:
3764         case RTL_GIGA_MAC_VER_04:
3765         case RTL_GIGA_MAC_VER_05:
3766         case RTL_GIGA_MAC_VER_06:
3767         case RTL_GIGA_MAC_VER_10:
3768         case RTL_GIGA_MAC_VER_11:
3769         case RTL_GIGA_MAC_VER_12:
3770         case RTL_GIGA_MAC_VER_13:
3771         case RTL_GIGA_MAC_VER_14:
3772         case RTL_GIGA_MAC_VER_15:
3773         case RTL_GIGA_MAC_VER_16:
3774         case RTL_GIGA_MAC_VER_17:
3775                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3776                 break;
3777         case RTL_GIGA_MAC_VER_18:
3778         case RTL_GIGA_MAC_VER_19:
3779         case RTL_GIGA_MAC_VER_20:
3780         case RTL_GIGA_MAC_VER_21:
3781         case RTL_GIGA_MAC_VER_22:
3782         case RTL_GIGA_MAC_VER_23:
3783         case RTL_GIGA_MAC_VER_24:
3784                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3785                 break;
3786         default:
3787                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3788                 break;
3789         }
3790 }
3791
3792 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3793 {
3794         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3795 }
3796
3797 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3798 {
3799         void __iomem *ioaddr = tp->mmio_addr;
3800
3801         RTL_W8(Cfg9346, Cfg9346_Unlock);
3802         rtl_generic_op(tp, tp->jumbo_ops.enable);
3803         RTL_W8(Cfg9346, Cfg9346_Lock);
3804 }
3805
3806 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3807 {
3808         void __iomem *ioaddr = tp->mmio_addr;
3809
3810         RTL_W8(Cfg9346, Cfg9346_Unlock);
3811         rtl_generic_op(tp, tp->jumbo_ops.disable);
3812         RTL_W8(Cfg9346, Cfg9346_Lock);
3813 }
3814
3815 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3816 {
3817         void __iomem *ioaddr = tp->mmio_addr;
3818
3819         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3820         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3821         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3822 }
3823
3824 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3825 {
3826         void __iomem *ioaddr = tp->mmio_addr;
3827
3828         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3829         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3830         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3831 }
3832
3833 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3834 {
3835         void __iomem *ioaddr = tp->mmio_addr;
3836
3837         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3838 }
3839
3840 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3841 {
3842         void __iomem *ioaddr = tp->mmio_addr;
3843
3844         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3845 }
3846
3847 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3848 {
3849         void __iomem *ioaddr = tp->mmio_addr;
3850
3851         RTL_W8(MaxTxPacketSize, 0x3f);
3852         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3853         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3854         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3855 }
3856
3857 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3858 {
3859         void __iomem *ioaddr = tp->mmio_addr;
3860
3861         RTL_W8(MaxTxPacketSize, 0x0c);
3862         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3863         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3864         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3865 }
3866
3867 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3868 {
3869         rtl_tx_performance_tweak(tp->pci_dev,
3870                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3871 }
3872
3873 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3874 {
3875         rtl_tx_performance_tweak(tp->pci_dev,
3876                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3877 }
3878
3879 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3880 {
3881         void __iomem *ioaddr = tp->mmio_addr;
3882
3883         r8168b_0_hw_jumbo_enable(tp);
3884
3885         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3886 }
3887
3888 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3889 {
3890         void __iomem *ioaddr = tp->mmio_addr;
3891
3892         r8168b_0_hw_jumbo_disable(tp);
3893
3894         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3895 }
3896
3897 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3898 {
3899         struct jumbo_ops *ops = &tp->jumbo_ops;
3900
3901         switch (tp->mac_version) {
3902         case RTL_GIGA_MAC_VER_11:
3903                 ops->disable    = r8168b_0_hw_jumbo_disable;
3904                 ops->enable     = r8168b_0_hw_jumbo_enable;
3905                 break;
3906         case RTL_GIGA_MAC_VER_12:
3907         case RTL_GIGA_MAC_VER_17:
3908                 ops->disable    = r8168b_1_hw_jumbo_disable;
3909                 ops->enable     = r8168b_1_hw_jumbo_enable;
3910                 break;
3911         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3912         case RTL_GIGA_MAC_VER_19:
3913         case RTL_GIGA_MAC_VER_20:
3914         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3915         case RTL_GIGA_MAC_VER_22:
3916         case RTL_GIGA_MAC_VER_23:
3917         case RTL_GIGA_MAC_VER_24:
3918         case RTL_GIGA_MAC_VER_25:
3919         case RTL_GIGA_MAC_VER_26:
3920                 ops->disable    = r8168c_hw_jumbo_disable;
3921                 ops->enable     = r8168c_hw_jumbo_enable;
3922                 break;
3923         case RTL_GIGA_MAC_VER_27:
3924         case RTL_GIGA_MAC_VER_28:
3925                 ops->disable    = r8168dp_hw_jumbo_disable;
3926                 ops->enable     = r8168dp_hw_jumbo_enable;
3927                 break;
3928         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3929         case RTL_GIGA_MAC_VER_32:
3930         case RTL_GIGA_MAC_VER_33:
3931         case RTL_GIGA_MAC_VER_34:
3932                 ops->disable    = r8168e_hw_jumbo_disable;
3933                 ops->enable     = r8168e_hw_jumbo_enable;
3934                 break;
3935
3936         /*
3937          * No action needed for jumbo frames with 8169.
3938          * No jumbo for 810x at all.
3939          */
3940         default:
3941                 ops->disable    = NULL;
3942                 ops->enable     = NULL;
3943                 break;
3944         }
3945 }
3946
3947 static void rtl_hw_reset(struct rtl8169_private *tp)
3948 {
3949         void __iomem *ioaddr = tp->mmio_addr;
3950         int i;
3951
3952         /* Soft reset the chip. */
3953         RTL_W8(ChipCmd, CmdReset);
3954
3955         /* Check that the chip has finished the reset. */
3956         for (i = 0; i < 100; i++) {
3957                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3958                         break;
3959                 udelay(100);
3960         }
3961 }
3962
3963 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3964 {
3965         struct rtl_fw *rtl_fw;
3966         const char *name;
3967         int rc = -ENOMEM;
3968
3969         name = rtl_lookup_firmware_name(tp);
3970         if (!name)
3971                 goto out_no_firmware;
3972
3973         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3974         if (!rtl_fw)
3975                 goto err_warn;
3976
3977         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3978         if (rc < 0)
3979                 goto err_free;
3980
3981         rc = rtl_check_firmware(tp, rtl_fw);
3982         if (rc < 0)
3983                 goto err_release_firmware;
3984
3985         tp->rtl_fw = rtl_fw;
3986 out:
3987         return;
3988
3989 err_release_firmware:
3990         release_firmware(rtl_fw->fw);
3991 err_free:
3992         kfree(rtl_fw);
3993 err_warn:
3994         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3995                    name, rc);
3996 out_no_firmware:
3997         tp->rtl_fw = NULL;
3998         goto out;
3999 }
4000
4001 static void rtl_request_firmware(struct rtl8169_private *tp)
4002 {
4003         if (IS_ERR(tp->rtl_fw))
4004                 rtl_request_uncached_firmware(tp);
4005 }
4006
4007 static void rtl_rx_close(struct rtl8169_private *tp)
4008 {
4009         void __iomem *ioaddr = tp->mmio_addr;
4010
4011         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4012 }
4013
4014 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4015 {
4016         void __iomem *ioaddr = tp->mmio_addr;
4017
4018         /* Disable interrupts */
4019         rtl8169_irq_mask_and_ack(tp);
4020
4021         rtl_rx_close(tp);
4022
4023         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4024             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4025             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4026                 while (RTL_R8(TxPoll) & NPQ)
4027                         udelay(20);
4028         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4029                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4030                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4031                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4032                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4033                         udelay(100);
4034         } else {
4035                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4036                 udelay(100);
4037         }
4038
4039         rtl_hw_reset(tp);
4040 }
4041
4042 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4043 {
4044         void __iomem *ioaddr = tp->mmio_addr;
4045
4046         /* Set DMA burst size and Interframe Gap Time */
4047         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4048                 (InterFrameGap << TxInterFrameGapShift));
4049 }
4050
4051 static void rtl_hw_start(struct net_device *dev)
4052 {
4053         struct rtl8169_private *tp = netdev_priv(dev);
4054
4055         tp->hw_start(dev);
4056
4057         rtl_irq_enable_all(tp);
4058 }
4059
4060 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4061                                          void __iomem *ioaddr)
4062 {
4063         /*
4064          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4065          * register to be written before TxDescAddrLow to work.
4066          * Switching from MMIO to I/O access fixes the issue as well.
4067          */
4068         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4069         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4070         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4071         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4072 }
4073
4074 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4075 {
4076         u16 cmd;
4077
4078         cmd = RTL_R16(CPlusCmd);
4079         RTL_W16(CPlusCmd, cmd);
4080         return cmd;
4081 }
4082
4083 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4084 {
4085         /* Low hurts. Let's disable the filtering. */
4086         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4087 }
4088
4089 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4090 {
4091         static const struct rtl_cfg2_info {
4092                 u32 mac_version;
4093                 u32 clk;
4094                 u32 val;
4095         } cfg2_info [] = {
4096                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4097                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4098                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4099                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4100         };
4101         const struct rtl_cfg2_info *p = cfg2_info;
4102         unsigned int i;
4103         u32 clk;
4104
4105         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4106         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4107                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4108                         RTL_W32(0x7c, p->val);
4109                         break;
4110                 }
4111         }
4112 }
4113
4114 static void rtl_set_rx_mode(struct net_device *dev)
4115 {
4116         struct rtl8169_private *tp = netdev_priv(dev);
4117         void __iomem *ioaddr = tp->mmio_addr;
4118         u32 mc_filter[2];       /* Multicast hash filter */
4119         int rx_mode;
4120         u32 tmp = 0;
4121
4122         if (dev->flags & IFF_PROMISC) {
4123                 /* Unconditionally log net taps. */
4124                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4125                 rx_mode =
4126                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4127                     AcceptAllPhys;
4128                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4129         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4130                    (dev->flags & IFF_ALLMULTI)) {
4131                 /* Too many to filter perfectly -- accept all multicasts. */
4132                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4133                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4134         } else {
4135                 struct netdev_hw_addr *ha;
4136
4137                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4138                 mc_filter[1] = mc_filter[0] = 0;
4139                 netdev_for_each_mc_addr(ha, dev) {
4140                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4141                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4142                         rx_mode |= AcceptMulticast;
4143                 }
4144         }
4145
4146         if (dev->features & NETIF_F_RXALL)
4147                 rx_mode |= (AcceptErr | AcceptRunt);
4148
4149         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4150
4151         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4152                 u32 data = mc_filter[0];
4153
4154                 mc_filter[0] = swab32(mc_filter[1]);
4155                 mc_filter[1] = swab32(data);
4156         }
4157
4158         RTL_W32(MAR0 + 4, mc_filter[1]);
4159         RTL_W32(MAR0 + 0, mc_filter[0]);
4160
4161         RTL_W32(RxConfig, tmp);
4162 }
4163
4164 static void rtl_hw_start_8169(struct net_device *dev)
4165 {
4166         struct rtl8169_private *tp = netdev_priv(dev);
4167         void __iomem *ioaddr = tp->mmio_addr;
4168         struct pci_dev *pdev = tp->pci_dev;
4169
4170         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4171                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4172                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4173         }
4174
4175         RTL_W8(Cfg9346, Cfg9346_Unlock);
4176         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4177             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4178             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4179             tp->mac_version == RTL_GIGA_MAC_VER_04)
4180                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4181
4182         rtl_init_rxcfg(tp);
4183
4184         RTL_W8(EarlyTxThres, NoEarlyTx);
4185
4186         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4187
4188         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4189             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4190             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4191             tp->mac_version == RTL_GIGA_MAC_VER_04)
4192                 rtl_set_rx_tx_config_registers(tp);
4193
4194         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4195
4196         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4197             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4198                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4199                         "Bit-3 and bit-14 MUST be 1\n");
4200                 tp->cp_cmd |= (1 << 14);
4201         }
4202
4203         RTL_W16(CPlusCmd, tp->cp_cmd);
4204
4205         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4206
4207         /*
4208          * Undocumented corner. Supposedly:
4209          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4210          */
4211         RTL_W16(IntrMitigate, 0x0000);
4212
4213         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4214
4215         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4216             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4217             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4218             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4219                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4220                 rtl_set_rx_tx_config_registers(tp);
4221         }
4222
4223         RTL_W8(Cfg9346, Cfg9346_Lock);
4224
4225         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4226         RTL_R8(IntrMask);
4227
4228         RTL_W32(RxMissed, 0);
4229
4230         rtl_set_rx_mode(dev);
4231
4232         /* no early-rx interrupts */
4233         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4234 }
4235
4236 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4237 {
4238         u32 csi;
4239
4240         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4241         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4242 }
4243
4244 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4245 {
4246         rtl_csi_access_enable(ioaddr, 0x17000000);
4247 }
4248
4249 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4250 {
4251         rtl_csi_access_enable(ioaddr, 0x27000000);
4252 }
4253
4254 struct ephy_info {
4255         unsigned int offset;
4256         u16 mask;
4257         u16 bits;
4258 };
4259
4260 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4261 {
4262         u16 w;
4263
4264         while (len-- > 0) {
4265                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4266                 rtl_ephy_write(ioaddr, e->offset, w);
4267                 e++;
4268         }
4269 }
4270
4271 static void rtl_disable_clock_request(struct pci_dev *pdev)
4272 {
4273         int cap = pci_pcie_cap(pdev);
4274
4275         if (cap) {
4276                 u16 ctl;
4277
4278                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4279                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4280                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4281         }
4282 }
4283
4284 static void rtl_enable_clock_request(struct pci_dev *pdev)
4285 {
4286         int cap = pci_pcie_cap(pdev);
4287
4288         if (cap) {
4289                 u16 ctl;
4290
4291                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4292                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4293                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4294         }
4295 }
4296
4297 #define R8168_CPCMD_QUIRK_MASK (\
4298         EnableBist | \
4299         Mac_dbgo_oe | \
4300         Force_half_dup | \
4301         Force_rxflow_en | \
4302         Force_txflow_en | \
4303         Cxpl_dbg_sel | \
4304         ASF | \
4305         PktCntrDisable | \
4306         Mac_dbgo_sel)
4307
4308 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4309 {
4310         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4311
4312         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4313
4314         rtl_tx_performance_tweak(pdev,
4315                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4316 }
4317
4318 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4319 {
4320         rtl_hw_start_8168bb(ioaddr, pdev);
4321
4322         RTL_W8(MaxTxPacketSize, TxPacketMax);
4323
4324         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4325 }
4326
4327 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4328 {
4329         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4330
4331         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4332
4333         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4334
4335         rtl_disable_clock_request(pdev);
4336
4337         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4338 }
4339
4340 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4341 {
4342         static const struct ephy_info e_info_8168cp[] = {
4343                 { 0x01, 0,      0x0001 },
4344                 { 0x02, 0x0800, 0x1000 },
4345                 { 0x03, 0,      0x0042 },
4346                 { 0x06, 0x0080, 0x0000 },
4347                 { 0x07, 0,      0x2000 }
4348         };
4349
4350         rtl_csi_access_enable_2(ioaddr);
4351
4352         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4353
4354         __rtl_hw_start_8168cp(ioaddr, pdev);
4355 }
4356
4357 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4358 {
4359         rtl_csi_access_enable_2(ioaddr);
4360
4361         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4362
4363         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4364
4365         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4366 }
4367
4368 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4369 {
4370         rtl_csi_access_enable_2(ioaddr);
4371
4372         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4373
4374         /* Magic. */
4375         RTL_W8(DBG_REG, 0x20);
4376
4377         RTL_W8(MaxTxPacketSize, TxPacketMax);
4378
4379         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4380
4381         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4382 }
4383
4384 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4385 {
4386         static const struct ephy_info e_info_8168c_1[] = {
4387                 { 0x02, 0x0800, 0x1000 },
4388                 { 0x03, 0,      0x0002 },
4389                 { 0x06, 0x0080, 0x0000 }
4390         };
4391
4392         rtl_csi_access_enable_2(ioaddr);
4393
4394         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4395
4396         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4397
4398         __rtl_hw_start_8168cp(ioaddr, pdev);
4399 }
4400
4401 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4402 {
4403         static const struct ephy_info e_info_8168c_2[] = {
4404                 { 0x01, 0,      0x0001 },
4405                 { 0x03, 0x0400, 0x0220 }
4406         };
4407
4408         rtl_csi_access_enable_2(ioaddr);
4409
4410         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4411
4412         __rtl_hw_start_8168cp(ioaddr, pdev);
4413 }
4414
4415 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4416 {
4417         rtl_hw_start_8168c_2(ioaddr, pdev);
4418 }
4419
4420 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4421 {
4422         rtl_csi_access_enable_2(ioaddr);
4423
4424         __rtl_hw_start_8168cp(ioaddr, pdev);
4425 }
4426
4427 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4428 {
4429         rtl_csi_access_enable_2(ioaddr);
4430
4431         rtl_disable_clock_request(pdev);
4432
4433         RTL_W8(MaxTxPacketSize, TxPacketMax);
4434
4435         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4436
4437         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4438 }
4439
4440 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4441 {
4442         rtl_csi_access_enable_1(ioaddr);
4443
4444         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4445
4446         RTL_W8(MaxTxPacketSize, TxPacketMax);
4447
4448         rtl_disable_clock_request(pdev);
4449 }
4450
4451 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4452 {
4453         static const struct ephy_info e_info_8168d_4[] = {
4454                 { 0x0b, ~0,     0x48 },
4455                 { 0x19, 0x20,   0x50 },
4456                 { 0x0c, ~0,     0x20 }
4457         };
4458         int i;
4459
4460         rtl_csi_access_enable_1(ioaddr);
4461
4462         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4463
4464         RTL_W8(MaxTxPacketSize, TxPacketMax);
4465
4466         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4467                 const struct ephy_info *e = e_info_8168d_4 + i;
4468                 u16 w;
4469
4470                 w = rtl_ephy_read(ioaddr, e->offset);
4471                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4472         }
4473
4474         rtl_enable_clock_request(pdev);
4475 }
4476
4477 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4478 {
4479         static const struct ephy_info e_info_8168e_1[] = {
4480                 { 0x00, 0x0200, 0x0100 },
4481                 { 0x00, 0x0000, 0x0004 },
4482                 { 0x06, 0x0002, 0x0001 },
4483                 { 0x06, 0x0000, 0x0030 },
4484                 { 0x07, 0x0000, 0x2000 },
4485                 { 0x00, 0x0000, 0x0020 },
4486                 { 0x03, 0x5800, 0x2000 },
4487                 { 0x03, 0x0000, 0x0001 },
4488                 { 0x01, 0x0800, 0x1000 },
4489                 { 0x07, 0x0000, 0x4000 },
4490                 { 0x1e, 0x0000, 0x2000 },
4491                 { 0x19, 0xffff, 0xfe6c },
4492                 { 0x0a, 0x0000, 0x0040 }
4493         };
4494
4495         rtl_csi_access_enable_2(ioaddr);
4496
4497         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4498
4499         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4500
4501         RTL_W8(MaxTxPacketSize, TxPacketMax);
4502
4503         rtl_disable_clock_request(pdev);
4504
4505         /* Reset tx FIFO pointer */
4506         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4507         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4508
4509         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4510 }
4511
4512 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4513 {
4514         static const struct ephy_info e_info_8168e_2[] = {
4515                 { 0x09, 0x0000, 0x0080 },
4516                 { 0x19, 0x0000, 0x0224 }
4517         };
4518
4519         rtl_csi_access_enable_1(ioaddr);
4520
4521         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4522
4523         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4524
4525         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4526         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4527         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4528         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4529         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4530         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4531         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4532         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4533                      ERIAR_EXGMAC);
4534
4535         RTL_W8(MaxTxPacketSize, EarlySize);
4536
4537         rtl_disable_clock_request(pdev);
4538
4539         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4540         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4541
4542         /* Adjust EEE LED frequency */
4543         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4544
4545         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4546         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4547         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4548 }
4549
4550 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4551 {
4552         static const struct ephy_info e_info_8168f_1[] = {
4553                 { 0x06, 0x00c0, 0x0020 },
4554                 { 0x08, 0x0001, 0x0002 },
4555                 { 0x09, 0x0000, 0x0080 },
4556                 { 0x19, 0x0000, 0x0224 }
4557         };
4558
4559         rtl_csi_access_enable_1(ioaddr);
4560
4561         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4562
4563         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4564
4565         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4566         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4567         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4568         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4569         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4570         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4571         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4572         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4573         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4574         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4575         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4576                      ERIAR_EXGMAC);
4577
4578         RTL_W8(MaxTxPacketSize, EarlySize);
4579
4580         rtl_disable_clock_request(pdev);
4581
4582         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4583         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4584
4585         /* Adjust EEE LED frequency */
4586         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4587
4588         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4589         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4590         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4591 }
4592
4593 static void rtl_hw_start_8168(struct net_device *dev)
4594 {
4595         struct rtl8169_private *tp = netdev_priv(dev);
4596         void __iomem *ioaddr = tp->mmio_addr;
4597         struct pci_dev *pdev = tp->pci_dev;
4598
4599         RTL_W8(Cfg9346, Cfg9346_Unlock);
4600
4601         RTL_W8(MaxTxPacketSize, TxPacketMax);
4602
4603         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4604
4605         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4606
4607         RTL_W16(CPlusCmd, tp->cp_cmd);
4608
4609         RTL_W16(IntrMitigate, 0x5151);
4610
4611         /* Work around for RxFIFO overflow. */
4612         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4613                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4614                 tp->event_slow &= ~RxOverflow;
4615         }
4616
4617         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4618
4619         rtl_set_rx_mode(dev);
4620
4621         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4622                 (InterFrameGap << TxInterFrameGapShift));
4623
4624         RTL_R8(IntrMask);
4625
4626         switch (tp->mac_version) {
4627         case RTL_GIGA_MAC_VER_11:
4628                 rtl_hw_start_8168bb(ioaddr, pdev);
4629                 break;
4630
4631         case RTL_GIGA_MAC_VER_12:
4632         case RTL_GIGA_MAC_VER_17:
4633                 rtl_hw_start_8168bef(ioaddr, pdev);
4634                 break;
4635
4636         case RTL_GIGA_MAC_VER_18:
4637                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4638                 break;
4639
4640         case RTL_GIGA_MAC_VER_19:
4641                 rtl_hw_start_8168c_1(ioaddr, pdev);
4642                 break;
4643
4644         case RTL_GIGA_MAC_VER_20:
4645                 rtl_hw_start_8168c_2(ioaddr, pdev);
4646                 break;
4647
4648         case RTL_GIGA_MAC_VER_21:
4649                 rtl_hw_start_8168c_3(ioaddr, pdev);
4650                 break;
4651
4652         case RTL_GIGA_MAC_VER_22:
4653                 rtl_hw_start_8168c_4(ioaddr, pdev);
4654                 break;
4655
4656         case RTL_GIGA_MAC_VER_23:
4657                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4658                 break;
4659
4660         case RTL_GIGA_MAC_VER_24:
4661                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4662                 break;
4663
4664         case RTL_GIGA_MAC_VER_25:
4665         case RTL_GIGA_MAC_VER_26:
4666         case RTL_GIGA_MAC_VER_27:
4667                 rtl_hw_start_8168d(ioaddr, pdev);
4668                 break;
4669
4670         case RTL_GIGA_MAC_VER_28:
4671                 rtl_hw_start_8168d_4(ioaddr, pdev);
4672                 break;
4673
4674         case RTL_GIGA_MAC_VER_31:
4675                 rtl_hw_start_8168dp(ioaddr, pdev);
4676                 break;
4677
4678         case RTL_GIGA_MAC_VER_32:
4679         case RTL_GIGA_MAC_VER_33:
4680                 rtl_hw_start_8168e_1(ioaddr, pdev);
4681                 break;
4682         case RTL_GIGA_MAC_VER_34:
4683                 rtl_hw_start_8168e_2(ioaddr, pdev);
4684                 break;
4685
4686         case RTL_GIGA_MAC_VER_35:
4687         case RTL_GIGA_MAC_VER_36:
4688                 rtl_hw_start_8168f_1(ioaddr, pdev);
4689                 break;
4690
4691         default:
4692                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4693                         dev->name, tp->mac_version);
4694                 break;
4695         }
4696
4697         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4698
4699         RTL_W8(Cfg9346, Cfg9346_Lock);
4700
4701         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4702 }
4703
4704 #define R810X_CPCMD_QUIRK_MASK (\
4705         EnableBist | \
4706         Mac_dbgo_oe | \
4707         Force_half_dup | \
4708         Force_rxflow_en | \
4709         Force_txflow_en | \
4710         Cxpl_dbg_sel | \
4711         ASF | \
4712         PktCntrDisable | \
4713         Mac_dbgo_sel)
4714
4715 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4716 {
4717         static const struct ephy_info e_info_8102e_1[] = {
4718                 { 0x01, 0, 0x6e65 },
4719                 { 0x02, 0, 0x091f },
4720                 { 0x03, 0, 0xc2f9 },
4721                 { 0x06, 0, 0xafb5 },
4722                 { 0x07, 0, 0x0e00 },
4723                 { 0x19, 0, 0xec80 },
4724                 { 0x01, 0, 0x2e65 },
4725                 { 0x01, 0, 0x6e65 }
4726         };
4727         u8 cfg1;
4728
4729         rtl_csi_access_enable_2(ioaddr);
4730
4731         RTL_W8(DBG_REG, FIX_NAK_1);
4732
4733         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4734
4735         RTL_W8(Config1,
4736                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4737         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4738
4739         cfg1 = RTL_R8(Config1);
4740         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4741                 RTL_W8(Config1, cfg1 & ~LEDS0);
4742
4743         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4744 }
4745
4746 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4747 {
4748         rtl_csi_access_enable_2(ioaddr);
4749
4750         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4751
4752         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4753         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4754 }
4755
4756 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4757 {
4758         rtl_hw_start_8102e_2(ioaddr, pdev);
4759
4760         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4761 }
4762
4763 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4764 {
4765         static const struct ephy_info e_info_8105e_1[] = {
4766                 { 0x07, 0, 0x4000 },
4767                 { 0x19, 0, 0x0200 },
4768                 { 0x19, 0, 0x0020 },
4769                 { 0x1e, 0, 0x2000 },
4770                 { 0x03, 0, 0x0001 },
4771                 { 0x19, 0, 0x0100 },
4772                 { 0x19, 0, 0x0004 },
4773                 { 0x0a, 0, 0x0020 }
4774         };
4775
4776         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4777         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4778
4779         /* Disable Early Tally Counter */
4780         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4781
4782         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4783         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4784
4785         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4786 }
4787
4788 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4789 {
4790         rtl_hw_start_8105e_1(ioaddr, pdev);
4791         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4792 }
4793
4794 static void rtl_hw_start_8101(struct net_device *dev)
4795 {
4796         struct rtl8169_private *tp = netdev_priv(dev);
4797         void __iomem *ioaddr = tp->mmio_addr;
4798         struct pci_dev *pdev = tp->pci_dev;
4799
4800         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4801                 tp->event_slow &= ~RxFIFOOver;
4802
4803         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4804             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4805                 int cap = pci_pcie_cap(pdev);
4806
4807                 if (cap) {
4808                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4809                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4810                 }
4811         }
4812
4813         RTL_W8(Cfg9346, Cfg9346_Unlock);
4814
4815         switch (tp->mac_version) {
4816         case RTL_GIGA_MAC_VER_07:
4817                 rtl_hw_start_8102e_1(ioaddr, pdev);
4818                 break;
4819
4820         case RTL_GIGA_MAC_VER_08:
4821                 rtl_hw_start_8102e_3(ioaddr, pdev);
4822                 break;
4823
4824         case RTL_GIGA_MAC_VER_09:
4825                 rtl_hw_start_8102e_2(ioaddr, pdev);
4826                 break;
4827
4828         case RTL_GIGA_MAC_VER_29:
4829                 rtl_hw_start_8105e_1(ioaddr, pdev);
4830                 break;
4831         case RTL_GIGA_MAC_VER_30:
4832                 rtl_hw_start_8105e_2(ioaddr, pdev);
4833                 break;
4834         }
4835
4836         RTL_W8(Cfg9346, Cfg9346_Lock);
4837
4838         RTL_W8(MaxTxPacketSize, TxPacketMax);
4839
4840         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4841
4842         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4843         RTL_W16(CPlusCmd, tp->cp_cmd);
4844
4845         RTL_W16(IntrMitigate, 0x0000);
4846
4847         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4848
4849         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4850         rtl_set_rx_tx_config_registers(tp);
4851
4852         RTL_R8(IntrMask);
4853
4854         rtl_set_rx_mode(dev);
4855
4856         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4857 }
4858
4859 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4860 {
4861         struct rtl8169_private *tp = netdev_priv(dev);
4862
4863         if (new_mtu < ETH_ZLEN ||
4864             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4865                 return -EINVAL;
4866
4867         if (new_mtu > ETH_DATA_LEN)
4868                 rtl_hw_jumbo_enable(tp);
4869         else
4870                 rtl_hw_jumbo_disable(tp);
4871
4872         dev->mtu = new_mtu;
4873         netdev_update_features(dev);
4874
4875         return 0;
4876 }
4877
4878 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4879 {
4880         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4881         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4882 }
4883
4884 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4885                                      void **data_buff, struct RxDesc *desc)
4886 {
4887         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4888                          DMA_FROM_DEVICE);
4889
4890         kfree(*data_buff);
4891         *data_buff = NULL;
4892         rtl8169_make_unusable_by_asic(desc);
4893 }
4894
4895 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4896 {
4897         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4898
4899         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4900 }
4901
4902 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4903                                        u32 rx_buf_sz)
4904 {
4905         desc->addr = cpu_to_le64(mapping);
4906         wmb();
4907         rtl8169_mark_to_asic(desc, rx_buf_sz);
4908 }
4909
4910 static inline void *rtl8169_align(void *data)
4911 {
4912         return (void *)ALIGN((long)data, 16);
4913 }
4914
4915 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4916                                              struct RxDesc *desc)
4917 {
4918         void *data;
4919         dma_addr_t mapping;
4920         struct device *d = &tp->pci_dev->dev;
4921         struct net_device *dev = tp->dev;
4922         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4923
4924         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4925         if (!data)
4926                 return NULL;
4927
4928         if (rtl8169_align(data) != data) {
4929                 kfree(data);
4930                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4931                 if (!data)
4932                         return NULL;
4933         }
4934
4935         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4936                                  DMA_FROM_DEVICE);
4937         if (unlikely(dma_mapping_error(d, mapping))) {
4938                 if (net_ratelimit())
4939                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4940                 goto err_out;
4941         }
4942
4943         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4944         return data;
4945
4946 err_out:
4947         kfree(data);
4948         return NULL;
4949 }
4950
4951 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4952 {
4953         unsigned int i;
4954
4955         for (i = 0; i < NUM_RX_DESC; i++) {
4956                 if (tp->Rx_databuff[i]) {
4957                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4958                                             tp->RxDescArray + i);
4959                 }
4960         }
4961 }
4962
4963 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4964 {
4965         desc->opts1 |= cpu_to_le32(RingEnd);
4966 }
4967
4968 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4969 {
4970         unsigned int i;
4971
4972         for (i = 0; i < NUM_RX_DESC; i++) {
4973                 void *data;
4974
4975                 if (tp->Rx_databuff[i])
4976                         continue;
4977
4978                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4979                 if (!data) {
4980                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4981                         goto err_out;
4982                 }
4983                 tp->Rx_databuff[i] = data;
4984         }
4985
4986         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4987         return 0;
4988
4989 err_out:
4990         rtl8169_rx_clear(tp);
4991         return -ENOMEM;
4992 }
4993
4994 static int rtl8169_init_ring(struct net_device *dev)
4995 {
4996         struct rtl8169_private *tp = netdev_priv(dev);
4997
4998         rtl8169_init_ring_indexes(tp);
4999
5000         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5001         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5002
5003         return rtl8169_rx_fill(tp);
5004 }
5005
5006 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5007                                  struct TxDesc *desc)
5008 {
5009         unsigned int len = tx_skb->len;
5010
5011         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5012
5013         desc->opts1 = 0x00;
5014         desc->opts2 = 0x00;
5015         desc->addr = 0x00;
5016         tx_skb->len = 0;
5017 }
5018
5019 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5020                                    unsigned int n)
5021 {
5022         unsigned int i;
5023
5024         for (i = 0; i < n; i++) {
5025                 unsigned int entry = (start + i) % NUM_TX_DESC;
5026                 struct ring_info *tx_skb = tp->tx_skb + entry;
5027                 unsigned int len = tx_skb->len;
5028
5029                 if (len) {
5030                         struct sk_buff *skb = tx_skb->skb;
5031
5032                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5033                                              tp->TxDescArray + entry);
5034                         if (skb) {
5035                                 tp->dev->stats.tx_dropped++;
5036                                 dev_kfree_skb(skb);
5037                                 tx_skb->skb = NULL;
5038                         }
5039                 }
5040         }
5041 }
5042
5043 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5044 {
5045         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5046         tp->cur_tx = tp->dirty_tx = 0;
5047         netdev_reset_queue(tp->dev);
5048 }
5049
5050 static void rtl_reset_work(struct rtl8169_private *tp)
5051 {
5052         struct net_device *dev = tp->dev;
5053         int i;
5054
5055         napi_disable(&tp->napi);
5056         netif_stop_queue(dev);
5057         synchronize_sched();
5058
5059         rtl8169_hw_reset(tp);
5060
5061         for (i = 0; i < NUM_RX_DESC; i++)
5062                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5063
5064         rtl8169_tx_clear(tp);
5065         rtl8169_init_ring_indexes(tp);
5066
5067         napi_enable(&tp->napi);
5068         rtl_hw_start(dev);
5069         netif_wake_queue(dev);
5070         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5071 }
5072
5073 static void rtl8169_tx_timeout(struct net_device *dev)
5074 {
5075         struct rtl8169_private *tp = netdev_priv(dev);
5076
5077         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5078 }
5079
5080 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5081                               u32 *opts)
5082 {
5083         struct skb_shared_info *info = skb_shinfo(skb);
5084         unsigned int cur_frag, entry;
5085         struct TxDesc * uninitialized_var(txd);
5086         struct device *d = &tp->pci_dev->dev;
5087
5088         entry = tp->cur_tx;
5089         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5090                 const skb_frag_t *frag = info->frags + cur_frag;
5091                 dma_addr_t mapping;
5092                 u32 status, len;
5093                 void *addr;
5094
5095                 entry = (entry + 1) % NUM_TX_DESC;
5096
5097                 txd = tp->TxDescArray + entry;
5098                 len = skb_frag_size(frag);
5099                 addr = skb_frag_address(frag);
5100                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5101                 if (unlikely(dma_mapping_error(d, mapping))) {
5102                         if (net_ratelimit())
5103                                 netif_err(tp, drv, tp->dev,
5104                                           "Failed to map TX fragments DMA!\n");
5105                         goto err_out;
5106                 }
5107
5108                 /* Anti gcc 2.95.3 bugware (sic) */
5109                 status = opts[0] | len |
5110                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5111
5112                 txd->opts1 = cpu_to_le32(status);
5113                 txd->opts2 = cpu_to_le32(opts[1]);
5114                 txd->addr = cpu_to_le64(mapping);
5115
5116                 tp->tx_skb[entry].len = len;
5117         }
5118
5119         if (cur_frag) {
5120                 tp->tx_skb[entry].skb = skb;
5121                 txd->opts1 |= cpu_to_le32(LastFrag);
5122         }
5123
5124         return cur_frag;
5125
5126 err_out:
5127         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5128         return -EIO;
5129 }
5130
5131 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5132                                     struct sk_buff *skb, u32 *opts)
5133 {
5134         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5135         u32 mss = skb_shinfo(skb)->gso_size;
5136         int offset = info->opts_offset;
5137
5138         if (mss) {
5139                 opts[0] |= TD_LSO;
5140                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5141         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5142                 const struct iphdr *ip = ip_hdr(skb);
5143
5144                 if (ip->protocol == IPPROTO_TCP)
5145                         opts[offset] |= info->checksum.tcp;
5146                 else if (ip->protocol == IPPROTO_UDP)
5147                         opts[offset] |= info->checksum.udp;
5148                 else
5149                         WARN_ON_ONCE(1);
5150         }
5151 }
5152
5153 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5154                                       struct net_device *dev)
5155 {
5156         struct rtl8169_private *tp = netdev_priv(dev);
5157         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5158         struct TxDesc *txd = tp->TxDescArray + entry;
5159         void __iomem *ioaddr = tp->mmio_addr;
5160         struct device *d = &tp->pci_dev->dev;
5161         dma_addr_t mapping;
5162         u32 status, len;
5163         u32 opts[2];
5164         int frags;
5165
5166         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5167                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5168                 goto err_stop_0;
5169         }
5170
5171         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5172                 goto err_stop_0;
5173
5174         len = skb_headlen(skb);
5175         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5176         if (unlikely(dma_mapping_error(d, mapping))) {
5177                 if (net_ratelimit())
5178                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5179                 goto err_dma_0;
5180         }
5181
5182         tp->tx_skb[entry].len = len;
5183         txd->addr = cpu_to_le64(mapping);
5184
5185         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5186         opts[0] = DescOwn;
5187
5188         rtl8169_tso_csum(tp, skb, opts);
5189
5190         frags = rtl8169_xmit_frags(tp, skb, opts);
5191         if (frags < 0)
5192                 goto err_dma_1;
5193         else if (frags)
5194                 opts[0] |= FirstFrag;
5195         else {
5196                 opts[0] |= FirstFrag | LastFrag;
5197                 tp->tx_skb[entry].skb = skb;
5198         }
5199
5200         txd->opts2 = cpu_to_le32(opts[1]);
5201
5202         netdev_sent_queue(dev, skb->len);
5203
5204         skb_tx_timestamp(skb);
5205
5206         wmb();
5207
5208         /* Anti gcc 2.95.3 bugware (sic) */
5209         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5210         txd->opts1 = cpu_to_le32(status);
5211
5212         tp->cur_tx += frags + 1;
5213
5214         wmb();
5215
5216         RTL_W8(TxPoll, NPQ);
5217
5218         mmiowb();
5219
5220         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5221                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5222                  * not miss a ring update when it notices a stopped queue.
5223                  */
5224                 smp_wmb();
5225                 netif_stop_queue(dev);
5226                 /* Sync with rtl_tx:
5227                  * - publish queue status and cur_tx ring index (write barrier)
5228                  * - refresh dirty_tx ring index (read barrier).
5229                  * May the current thread have a pessimistic view of the ring
5230                  * status and forget to wake up queue, a racing rtl_tx thread
5231                  * can't.
5232                  */
5233                 smp_mb();
5234                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5235                         netif_wake_queue(dev);
5236         }
5237
5238         return NETDEV_TX_OK;
5239
5240 err_dma_1:
5241         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5242 err_dma_0:
5243         dev_kfree_skb(skb);
5244         dev->stats.tx_dropped++;
5245         return NETDEV_TX_OK;
5246
5247 err_stop_0:
5248         netif_stop_queue(dev);
5249         dev->stats.tx_dropped++;
5250         return NETDEV_TX_BUSY;
5251 }
5252
5253 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5254 {
5255         struct rtl8169_private *tp = netdev_priv(dev);
5256         struct pci_dev *pdev = tp->pci_dev;
5257         u16 pci_status, pci_cmd;
5258
5259         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5260         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5261
5262         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5263                   pci_cmd, pci_status);
5264
5265         /*
5266          * The recovery sequence below admits a very elaborated explanation:
5267          * - it seems to work;
5268          * - I did not see what else could be done;
5269          * - it makes iop3xx happy.
5270          *
5271          * Feel free to adjust to your needs.
5272          */
5273         if (pdev->broken_parity_status)
5274                 pci_cmd &= ~PCI_COMMAND_PARITY;
5275         else
5276                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5277
5278         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5279
5280         pci_write_config_word(pdev, PCI_STATUS,
5281                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5282                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5283                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5284
5285         /* The infamous DAC f*ckup only happens at boot time */
5286         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5287                 void __iomem *ioaddr = tp->mmio_addr;
5288
5289                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5290                 tp->cp_cmd &= ~PCIDAC;
5291                 RTL_W16(CPlusCmd, tp->cp_cmd);
5292                 dev->features &= ~NETIF_F_HIGHDMA;
5293         }
5294
5295         rtl8169_hw_reset(tp);
5296
5297         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5298 }
5299
5300 struct rtl_txc {
5301         int packets;
5302         int bytes;
5303 };
5304
5305 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5306 {
5307         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5308         unsigned int dirty_tx, tx_left;
5309         struct rtl_txc txc = { 0, 0 };
5310
5311         dirty_tx = tp->dirty_tx;
5312         smp_rmb();
5313         tx_left = tp->cur_tx - dirty_tx;
5314
5315         while (tx_left > 0) {
5316                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5317                 struct ring_info *tx_skb = tp->tx_skb + entry;
5318                 u32 status;
5319
5320                 rmb();
5321                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5322                 if (status & DescOwn)
5323                         break;
5324
5325                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5326                                      tp->TxDescArray + entry);
5327                 if (status & LastFrag) {
5328                         struct sk_buff *skb = tx_skb->skb;
5329
5330                         txc.packets++;
5331                         txc.bytes += skb->len;
5332                         dev_kfree_skb(skb);
5333                         tx_skb->skb = NULL;
5334                 }
5335                 dirty_tx++;
5336                 tx_left--;
5337         }
5338
5339         u64_stats_update_begin(&tx_stats->syncp);
5340         tx_stats->packets += txc.packets;
5341         tx_stats->bytes += txc.bytes;
5342         u64_stats_update_end(&tx_stats->syncp);
5343
5344         netdev_completed_queue(dev, txc.packets, txc.bytes);
5345
5346         if (tp->dirty_tx != dirty_tx) {
5347                 tp->dirty_tx = dirty_tx;
5348                 /* Sync with rtl8169_start_xmit:
5349                  * - publish dirty_tx ring index (write barrier)
5350                  * - refresh cur_tx ring index and queue status (read barrier)
5351                  * May the current thread miss the stopped queue condition,
5352                  * a racing xmit thread can only have a right view of the
5353                  * ring status.
5354                  */
5355                 smp_mb();
5356                 if (netif_queue_stopped(dev) &&
5357                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5358                         netif_wake_queue(dev);
5359                 }
5360                 /*
5361                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5362                  * too close. Let's kick an extra TxPoll request when a burst
5363                  * of start_xmit activity is detected (if it is not detected,
5364                  * it is slow enough). -- FR
5365                  */
5366                 if (tp->cur_tx != dirty_tx) {
5367                         void __iomem *ioaddr = tp->mmio_addr;
5368
5369                         RTL_W8(TxPoll, NPQ);
5370                 }
5371         }
5372 }
5373
5374 static inline int rtl8169_fragmented_frame(u32 status)
5375 {
5376         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5377 }
5378
5379 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5380 {
5381         u32 status = opts1 & RxProtoMask;
5382
5383         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5384             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5385                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5386         else
5387                 skb_checksum_none_assert(skb);
5388 }
5389
5390 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5391                                            struct rtl8169_private *tp,
5392                                            int pkt_size,
5393                                            dma_addr_t addr)
5394 {
5395         struct sk_buff *skb;
5396         struct device *d = &tp->pci_dev->dev;
5397
5398         data = rtl8169_align(data);
5399         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5400         prefetch(data);
5401         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5402         if (skb)
5403                 memcpy(skb->data, data, pkt_size);
5404         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5405
5406         return skb;
5407 }
5408
5409 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5410 {
5411         unsigned int cur_rx, rx_left;
5412         unsigned int count;
5413
5414         cur_rx = tp->cur_rx;
5415         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5416         rx_left = min(rx_left, budget);
5417
5418         for (; rx_left > 0; rx_left--, cur_rx++) {
5419                 unsigned int entry = cur_rx % NUM_RX_DESC;
5420                 struct RxDesc *desc = tp->RxDescArray + entry;
5421                 u32 status;
5422
5423                 rmb();
5424                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5425
5426                 if (status & DescOwn)
5427                         break;
5428                 if (unlikely(status & RxRES)) {
5429                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5430                                    status);
5431                         dev->stats.rx_errors++;
5432                         if (status & (RxRWT | RxRUNT))
5433                                 dev->stats.rx_length_errors++;
5434                         if (status & RxCRC)
5435                                 dev->stats.rx_crc_errors++;
5436                         if (status & RxFOVF) {
5437                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5438                                 dev->stats.rx_fifo_errors++;
5439                         }
5440                         if ((status & (RxRUNT | RxCRC)) &&
5441                             !(status & (RxRWT | RxFOVF)) &&
5442                             (dev->features & NETIF_F_RXALL))
5443                                 goto process_pkt;
5444
5445                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5446                 } else {
5447                         struct sk_buff *skb;
5448                         dma_addr_t addr;
5449                         int pkt_size;
5450
5451 process_pkt:
5452                         addr = le64_to_cpu(desc->addr);
5453                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5454                                 pkt_size = (status & 0x00003fff) - 4;
5455                         else
5456                                 pkt_size = status & 0x00003fff;
5457
5458                         /*
5459                          * The driver does not support incoming fragmented
5460                          * frames. They are seen as a symptom of over-mtu
5461                          * sized frames.
5462                          */
5463                         if (unlikely(rtl8169_fragmented_frame(status))) {
5464                                 dev->stats.rx_dropped++;
5465                                 dev->stats.rx_length_errors++;
5466                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5467                                 continue;
5468                         }
5469
5470                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5471                                                   tp, pkt_size, addr);
5472                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5473                         if (!skb) {
5474                                 dev->stats.rx_dropped++;
5475                                 continue;
5476                         }
5477
5478                         rtl8169_rx_csum(skb, status);
5479                         skb_put(skb, pkt_size);
5480                         skb->protocol = eth_type_trans(skb, dev);
5481
5482                         rtl8169_rx_vlan_tag(desc, skb);
5483
5484                         napi_gro_receive(&tp->napi, skb);
5485
5486                         u64_stats_update_begin(&tp->rx_stats.syncp);
5487                         tp->rx_stats.packets++;
5488                         tp->rx_stats.bytes += pkt_size;
5489                         u64_stats_update_end(&tp->rx_stats.syncp);
5490                 }
5491
5492                 /* Work around for AMD plateform. */
5493                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5494                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5495                         desc->opts2 = 0;
5496                         cur_rx++;
5497                 }
5498         }
5499
5500         count = cur_rx - tp->cur_rx;
5501         tp->cur_rx = cur_rx;
5502
5503         tp->dirty_rx += count;
5504
5505         return count;
5506 }
5507
5508 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5509 {
5510         struct net_device *dev = dev_instance;
5511         struct rtl8169_private *tp = netdev_priv(dev);
5512         int handled = 0;
5513         u16 status;
5514
5515         status = rtl_get_events(tp);
5516         if (status && status != 0xffff) {
5517                 status &= RTL_EVENT_NAPI | tp->event_slow;
5518                 if (status) {
5519                         handled = 1;
5520
5521                         rtl_irq_disable(tp);
5522                         napi_schedule(&tp->napi);
5523                 }
5524         }
5525         return IRQ_RETVAL(handled);
5526 }
5527
5528 /*
5529  * Workqueue context.
5530  */
5531 static void rtl_slow_event_work(struct rtl8169_private *tp)
5532 {
5533         struct net_device *dev = tp->dev;
5534         u16 status;
5535
5536         status = rtl_get_events(tp) & tp->event_slow;
5537         rtl_ack_events(tp, status);
5538
5539         if (unlikely(status & RxFIFOOver)) {
5540                 switch (tp->mac_version) {
5541                 /* Work around for rx fifo overflow */
5542                 case RTL_GIGA_MAC_VER_11:
5543                         netif_stop_queue(dev);
5544                         /* XXX - Hack alert. See rtl_task(). */
5545                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5546                 default:
5547                         break;
5548                 }
5549         }
5550
5551         if (unlikely(status & SYSErr))
5552                 rtl8169_pcierr_interrupt(dev);
5553
5554         if (status & LinkChg)
5555                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5556
5557         napi_disable(&tp->napi);
5558         rtl_irq_disable(tp);
5559
5560         napi_enable(&tp->napi);
5561         napi_schedule(&tp->napi);
5562 }
5563
5564 static void rtl_task(struct work_struct *work)
5565 {
5566         static const struct {
5567                 int bitnr;
5568                 void (*action)(struct rtl8169_private *);
5569         } rtl_work[] = {
5570                 /* XXX - keep rtl_slow_event_work() as first element. */
5571                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5572                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5573                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5574         };
5575         struct rtl8169_private *tp =
5576                 container_of(work, struct rtl8169_private, wk.work);
5577         struct net_device *dev = tp->dev;
5578         int i;
5579
5580         rtl_lock_work(tp);
5581
5582         if (!netif_running(dev) ||
5583             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5584                 goto out_unlock;
5585
5586         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5587                 bool pending;
5588
5589                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5590                 if (pending)
5591                         rtl_work[i].action(tp);
5592         }
5593
5594 out_unlock:
5595         rtl_unlock_work(tp);
5596 }
5597
5598 static int rtl8169_poll(struct napi_struct *napi, int budget)
5599 {
5600         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5601         struct net_device *dev = tp->dev;
5602         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5603         int work_done= 0;
5604         u16 status;
5605
5606         status = rtl_get_events(tp);
5607         rtl_ack_events(tp, status & ~tp->event_slow);
5608
5609         if (status & RTL_EVENT_NAPI_RX)
5610                 work_done = rtl_rx(dev, tp, (u32) budget);
5611
5612         if (status & RTL_EVENT_NAPI_TX)
5613                 rtl_tx(dev, tp);
5614
5615         if (status & tp->event_slow) {
5616                 enable_mask &= ~tp->event_slow;
5617
5618                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5619         }
5620
5621         if (work_done < budget) {
5622                 napi_complete(napi);
5623
5624                 rtl_irq_enable(tp, enable_mask);
5625                 mmiowb();
5626         }
5627
5628         return work_done;
5629 }
5630
5631 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5632 {
5633         struct rtl8169_private *tp = netdev_priv(dev);
5634
5635         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5636                 return;
5637
5638         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5639         RTL_W32(RxMissed, 0);
5640 }
5641
5642 static void rtl8169_down(struct net_device *dev)
5643 {
5644         struct rtl8169_private *tp = netdev_priv(dev);
5645         void __iomem *ioaddr = tp->mmio_addr;
5646
5647         del_timer_sync(&tp->timer);
5648
5649         napi_disable(&tp->napi);
5650         netif_stop_queue(dev);
5651
5652         rtl8169_hw_reset(tp);
5653         /*
5654          * At this point device interrupts can not be enabled in any function,
5655          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5656          * and napi is disabled (rtl8169_poll).
5657          */
5658         rtl8169_rx_missed(dev, ioaddr);
5659
5660         /* Give a racing hard_start_xmit a few cycles to complete. */
5661         synchronize_sched();
5662
5663         rtl8169_tx_clear(tp);
5664
5665         rtl8169_rx_clear(tp);
5666
5667         rtl_pll_power_down(tp);
5668 }
5669
5670 static int rtl8169_close(struct net_device *dev)
5671 {
5672         struct rtl8169_private *tp = netdev_priv(dev);
5673         struct pci_dev *pdev = tp->pci_dev;
5674
5675         pm_runtime_get_sync(&pdev->dev);
5676
5677         /* Update counters before going down */
5678         rtl8169_update_counters(dev);
5679
5680         rtl_lock_work(tp);
5681         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5682
5683         rtl8169_down(dev);
5684         rtl_unlock_work(tp);
5685
5686         free_irq(pdev->irq, dev);
5687
5688         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5689                           tp->RxPhyAddr);
5690         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5691                           tp->TxPhyAddr);
5692         tp->TxDescArray = NULL;
5693         tp->RxDescArray = NULL;
5694
5695         pm_runtime_put_sync(&pdev->dev);
5696
5697         return 0;
5698 }
5699
5700 #ifdef CONFIG_NET_POLL_CONTROLLER
5701 static void rtl8169_netpoll(struct net_device *dev)
5702 {
5703         struct rtl8169_private *tp = netdev_priv(dev);
5704
5705         rtl8169_interrupt(tp->pci_dev->irq, dev);
5706 }
5707 #endif
5708
5709 static int rtl_open(struct net_device *dev)
5710 {
5711         struct rtl8169_private *tp = netdev_priv(dev);
5712         void __iomem *ioaddr = tp->mmio_addr;
5713         struct pci_dev *pdev = tp->pci_dev;
5714         int retval = -ENOMEM;
5715
5716         pm_runtime_get_sync(&pdev->dev);
5717
5718         /*
5719          * Rx and Tx desscriptors needs 256 bytes alignment.
5720          * dma_alloc_coherent provides more.
5721          */
5722         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5723                                              &tp->TxPhyAddr, GFP_KERNEL);
5724         if (!tp->TxDescArray)
5725                 goto err_pm_runtime_put;
5726
5727         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5728                                              &tp->RxPhyAddr, GFP_KERNEL);
5729         if (!tp->RxDescArray)
5730                 goto err_free_tx_0;
5731
5732         retval = rtl8169_init_ring(dev);
5733         if (retval < 0)
5734                 goto err_free_rx_1;
5735
5736         INIT_WORK(&tp->wk.work, rtl_task);
5737
5738         smp_mb();
5739
5740         rtl_request_firmware(tp);
5741
5742         retval = request_irq(pdev->irq, rtl8169_interrupt,
5743                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5744                              dev->name, dev);
5745         if (retval < 0)
5746                 goto err_release_fw_2;
5747
5748         rtl_lock_work(tp);
5749
5750         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5751
5752         napi_enable(&tp->napi);
5753
5754         rtl8169_init_phy(dev, tp);
5755
5756         __rtl8169_set_features(dev, dev->features);
5757
5758         rtl_pll_power_up(tp);
5759
5760         rtl_hw_start(dev);
5761
5762         netif_start_queue(dev);
5763
5764         rtl_unlock_work(tp);
5765
5766         tp->saved_wolopts = 0;
5767         tp->runtime_suspended = false;
5768         pm_runtime_put_noidle(&pdev->dev);
5769
5770         rtl8169_check_link_status(dev, tp, ioaddr);
5771 out:
5772         return retval;
5773
5774 err_release_fw_2:
5775         rtl_release_firmware(tp);
5776         rtl8169_rx_clear(tp);
5777 err_free_rx_1:
5778         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5779                           tp->RxPhyAddr);
5780         tp->RxDescArray = NULL;
5781 err_free_tx_0:
5782         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5783                           tp->TxPhyAddr);
5784         tp->TxDescArray = NULL;
5785 err_pm_runtime_put:
5786         pm_runtime_put_noidle(&pdev->dev);
5787         goto out;
5788 }
5789
5790 static struct rtnl_link_stats64 *
5791 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5792 {
5793         struct rtl8169_private *tp = netdev_priv(dev);
5794         void __iomem *ioaddr = tp->mmio_addr;
5795         unsigned int start;
5796
5797         if (netif_running(dev))
5798                 rtl8169_rx_missed(dev, ioaddr);
5799
5800         do {
5801                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5802                 stats->rx_packets = tp->rx_stats.packets;
5803                 stats->rx_bytes = tp->rx_stats.bytes;
5804         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5805
5806
5807         do {
5808                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5809                 stats->tx_packets = tp->tx_stats.packets;
5810                 stats->tx_bytes = tp->tx_stats.bytes;
5811         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5812
5813         stats->rx_dropped       = dev->stats.rx_dropped;
5814         stats->tx_dropped       = dev->stats.tx_dropped;
5815         stats->rx_length_errors = dev->stats.rx_length_errors;
5816         stats->rx_errors        = dev->stats.rx_errors;
5817         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5818         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5819         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5820
5821         return stats;
5822 }
5823
5824 static void rtl8169_net_suspend(struct net_device *dev)
5825 {
5826         struct rtl8169_private *tp = netdev_priv(dev);
5827
5828         if (!netif_running(dev))
5829                 return;
5830
5831         netif_device_detach(dev);
5832         netif_stop_queue(dev);
5833
5834         rtl_lock_work(tp);
5835         napi_disable(&tp->napi);
5836         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5837         rtl_unlock_work(tp);
5838
5839         rtl_pll_power_down(tp);
5840 }
5841
5842 #ifdef CONFIG_PM
5843
5844 static int rtl8169_suspend(struct device *device)
5845 {
5846         struct pci_dev *pdev = to_pci_dev(device);
5847         struct net_device *dev = pci_get_drvdata(pdev);
5848         struct rtl8169_private *tp = netdev_priv(dev);
5849
5850         rtl_lock_work(tp);
5851         tp->saved_wolopts = __rtl8169_get_wol(tp);
5852         rtl_unlock_work(tp);
5853
5854         rtl8169_net_suspend(dev);
5855
5856         return 0;
5857 }
5858
5859 static void __rtl8169_resume(struct net_device *dev)
5860 {
5861         struct rtl8169_private *tp = netdev_priv(dev);
5862
5863         netif_device_attach(dev);
5864
5865         rtl_pll_power_up(tp);
5866
5867         rtl_lock_work(tp);
5868         napi_enable(&tp->napi);
5869         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5870         rtl_unlock_work(tp);
5871
5872         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5873 }
5874
5875 static int rtl8169_resume(struct device *device)
5876 {
5877         struct pci_dev *pdev = to_pci_dev(device);
5878         struct net_device *dev = pci_get_drvdata(pdev);
5879         struct rtl8169_private *tp = netdev_priv(dev);
5880
5881         rtl_lock_work(tp);
5882         __rtl8169_set_wol(tp, tp->saved_wolopts);
5883         rtl_unlock_work(tp);
5884
5885         rtl8169_init_phy(dev, tp);
5886
5887         if (netif_running(dev))
5888                 __rtl8169_resume(dev);
5889
5890         return 0;
5891 }
5892
5893 static int rtl8169_runtime_suspend(struct device *device)
5894 {
5895         struct pci_dev *pdev = to_pci_dev(device);
5896         struct net_device *dev = pci_get_drvdata(pdev);
5897         struct rtl8169_private *tp = netdev_priv(dev);
5898
5899         if (!tp->TxDescArray)
5900                 return 0;
5901
5902         rtl_lock_work(tp);
5903         tp->saved_wolopts = __rtl8169_get_wol(tp);
5904         __rtl8169_set_wol(tp, WAKE_ANY);
5905         tp->runtime_suspended = true;
5906         rtl_unlock_work(tp);
5907
5908         rtl8169_net_suspend(dev);
5909
5910         return 0;
5911 }
5912
5913 static int rtl8169_runtime_resume(struct device *device)
5914 {
5915         struct pci_dev *pdev = to_pci_dev(device);
5916         struct net_device *dev = pci_get_drvdata(pdev);
5917         struct rtl8169_private *tp = netdev_priv(dev);
5918
5919         if (!tp->TxDescArray)
5920                 return 0;
5921
5922         rtl_lock_work(tp);
5923         __rtl8169_set_wol(tp, tp->saved_wolopts);
5924         tp->saved_wolopts = 0;
5925         tp->runtime_suspended = false;
5926         rtl_unlock_work(tp);
5927
5928         rtl8169_init_phy(dev, tp);
5929
5930         __rtl8169_resume(dev);
5931
5932         return 0;
5933 }
5934
5935 static int rtl8169_runtime_idle(struct device *device)
5936 {
5937         struct pci_dev *pdev = to_pci_dev(device);
5938         struct net_device *dev = pci_get_drvdata(pdev);
5939         struct rtl8169_private *tp = netdev_priv(dev);
5940
5941         __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5942         return tp->TxDescArray ? -EBUSY : 0;
5943 }
5944
5945 static const struct dev_pm_ops rtl8169_pm_ops = {
5946         .suspend                = rtl8169_suspend,
5947         .resume                 = rtl8169_resume,
5948         .freeze                 = rtl8169_suspend,
5949         .thaw                   = rtl8169_resume,
5950         .poweroff               = rtl8169_suspend,
5951         .restore                = rtl8169_resume,
5952         .runtime_suspend        = rtl8169_runtime_suspend,
5953         .runtime_resume         = rtl8169_runtime_resume,
5954         .runtime_idle           = rtl8169_runtime_idle,
5955 };
5956
5957 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5958
5959 #else /* !CONFIG_PM */
5960
5961 #define RTL8169_PM_OPS  NULL
5962
5963 #endif /* !CONFIG_PM */
5964
5965 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5966 {
5967         void __iomem *ioaddr = tp->mmio_addr;
5968
5969         /* WoL fails with 8168b when the receiver is disabled. */
5970         switch (tp->mac_version) {
5971         case RTL_GIGA_MAC_VER_11:
5972         case RTL_GIGA_MAC_VER_12:
5973         case RTL_GIGA_MAC_VER_17:
5974                 pci_clear_master(tp->pci_dev);
5975
5976                 RTL_W8(ChipCmd, CmdRxEnb);
5977                 /* PCI commit */
5978                 RTL_R8(ChipCmd);
5979                 break;
5980         default:
5981                 break;
5982         }
5983 }
5984
5985 static void rtl_shutdown(struct pci_dev *pdev)
5986 {
5987         struct net_device *dev = pci_get_drvdata(pdev);
5988         struct rtl8169_private *tp = netdev_priv(dev);
5989         struct device *d = &pdev->dev;
5990
5991         pm_runtime_get_sync(d);
5992
5993         /* Get the device back to D0 state if it was runtime suspended. */
5994         if (tp->runtime_suspended)
5995                 pci_set_power_state(pdev, PCI_D0);
5996
5997         rtl8169_net_suspend(dev);
5998
5999         /* Restore original MAC address */
6000         rtl_rar_set(tp, dev->perm_addr);
6001
6002         rtl8169_hw_reset(tp);
6003
6004         /* Restore WOL flags if they were messed around with. */
6005         if (tp->saved_wolopts)
6006                 __rtl8169_set_wol(tp, tp->saved_wolopts);
6007
6008         if (system_state == SYSTEM_POWER_OFF) {
6009                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6010                         rtl_wol_suspend_quirk(tp);
6011                         rtl_wol_shutdown_quirk(tp);
6012                 }
6013
6014                 pci_wake_from_d3(pdev, true);
6015                 pci_set_power_state(pdev, PCI_D3hot);
6016         }
6017
6018         pm_runtime_put_noidle(d);
6019 }
6020
6021 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6022 {
6023         struct net_device *dev = pci_get_drvdata(pdev);
6024         struct rtl8169_private *tp = netdev_priv(dev);
6025
6026         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6027             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6028             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6029                 rtl8168_driver_stop(tp);
6030         }
6031
6032         cancel_work_sync(&tp->wk.work);
6033
6034         unregister_netdev(dev);
6035
6036         rtl_release_firmware(tp);
6037
6038         if (pci_dev_run_wake(pdev))
6039                 pm_runtime_get_noresume(&pdev->dev);
6040
6041         /* restore original MAC address */
6042         rtl_rar_set(tp, dev->perm_addr);
6043
6044         rtl_disable_msi(pdev, tp);
6045         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6046         pci_set_drvdata(pdev, NULL);
6047 }
6048
6049 static const struct net_device_ops rtl_netdev_ops = {
6050         .ndo_open               = rtl_open,
6051         .ndo_stop               = rtl8169_close,
6052         .ndo_get_stats64        = rtl8169_get_stats64,
6053         .ndo_start_xmit         = rtl8169_start_xmit,
6054         .ndo_tx_timeout         = rtl8169_tx_timeout,
6055         .ndo_validate_addr      = eth_validate_addr,
6056         .ndo_change_mtu         = rtl8169_change_mtu,
6057         .ndo_fix_features       = rtl8169_fix_features,
6058         .ndo_set_features       = rtl8169_set_features,
6059         .ndo_set_mac_address    = rtl_set_mac_address,
6060         .ndo_do_ioctl           = rtl8169_ioctl,
6061         .ndo_set_rx_mode        = rtl_set_rx_mode,
6062 #ifdef CONFIG_NET_POLL_CONTROLLER
6063         .ndo_poll_controller    = rtl8169_netpoll,
6064 #endif
6065
6066 };
6067
6068 static const struct rtl_cfg_info {
6069         void (*hw_start)(struct net_device *);
6070         unsigned int region;
6071         unsigned int align;
6072         u16 event_slow;
6073         unsigned features;
6074         u8 default_ver;
6075 } rtl_cfg_infos [] = {
6076         [RTL_CFG_0] = {
6077                 .hw_start       = rtl_hw_start_8169,
6078                 .region         = 1,
6079                 .align          = 0,
6080                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6081                 .features       = RTL_FEATURE_GMII,
6082                 .default_ver    = RTL_GIGA_MAC_VER_01,
6083         },
6084         [RTL_CFG_1] = {
6085                 .hw_start       = rtl_hw_start_8168,
6086                 .region         = 2,
6087                 .align          = 8,
6088                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6089                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6090                 .default_ver    = RTL_GIGA_MAC_VER_11,
6091         },
6092         [RTL_CFG_2] = {
6093                 .hw_start       = rtl_hw_start_8101,
6094                 .region         = 2,
6095                 .align          = 8,
6096                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6097                                   PCSTimeout,
6098                 .features       = RTL_FEATURE_MSI,
6099                 .default_ver    = RTL_GIGA_MAC_VER_13,
6100         }
6101 };
6102
6103 /* Cfg9346_Unlock assumed. */
6104 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6105                             const struct rtl_cfg_info *cfg)
6106 {
6107         void __iomem *ioaddr = tp->mmio_addr;
6108         unsigned msi = 0;
6109         u8 cfg2;
6110
6111         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6112         if (cfg->features & RTL_FEATURE_MSI) {
6113                 if (pci_enable_msi(tp->pci_dev)) {
6114                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6115                 } else {
6116                         cfg2 |= MSIEnable;
6117                         msi = RTL_FEATURE_MSI;
6118                 }
6119         }
6120         RTL_W8(Config2, cfg2);
6121         return msi;
6122 }
6123
6124 static int __devinit
6125 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6126 {
6127         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6128         const unsigned int region = cfg->region;
6129         struct rtl8169_private *tp;
6130         struct mii_if_info *mii;
6131         struct net_device *dev;
6132         void __iomem *ioaddr;
6133         int chipset, i;
6134         int rc;
6135
6136         if (netif_msg_drv(&debug)) {
6137                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6138                        MODULENAME, RTL8169_VERSION);
6139         }
6140
6141         dev = alloc_etherdev(sizeof (*tp));
6142         if (!dev) {
6143                 rc = -ENOMEM;
6144                 goto out;
6145         }
6146
6147         SET_NETDEV_DEV(dev, &pdev->dev);
6148         dev->netdev_ops = &rtl_netdev_ops;
6149         tp = netdev_priv(dev);
6150         tp->dev = dev;
6151         tp->pci_dev = pdev;
6152         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6153
6154         mii = &tp->mii;
6155         mii->dev = dev;
6156         mii->mdio_read = rtl_mdio_read;
6157         mii->mdio_write = rtl_mdio_write;
6158         mii->phy_id_mask = 0x1f;
6159         mii->reg_num_mask = 0x1f;
6160         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6161
6162         /* disable ASPM completely as that cause random device stop working
6163          * problems as well as full system hangs for some PCIe devices users */
6164         if (aspm_disable) {
6165                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6166                                        PCIE_LINK_STATE_L1 |
6167                                        PCIE_LINK_STATE_CLKPM);
6168                 dprintk("ASPM disabled");
6169         }
6170
6171         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6172         rc = pci_enable_device(pdev);
6173         if (rc < 0) {
6174                 netif_err(tp, probe, dev, "enable failure\n");
6175                 goto err_out_free_dev_1;
6176         }
6177
6178         if (pci_set_mwi(pdev) < 0)
6179                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6180
6181         /* make sure PCI base addr 1 is MMIO */
6182         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6183                 netif_err(tp, probe, dev,
6184                           "region #%d not an MMIO resource, aborting\n",
6185                           region);
6186                 rc = -ENODEV;
6187                 goto err_out_mwi_2;
6188         }
6189
6190         /* check for weird/broken PCI region reporting */
6191         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6192                 netif_err(tp, probe, dev,
6193                           "Invalid PCI region size(s), aborting\n");
6194                 rc = -ENODEV;
6195                 goto err_out_mwi_2;
6196         }
6197
6198         rc = pci_request_regions(pdev, MODULENAME);
6199         if (rc < 0) {
6200                 netif_err(tp, probe, dev, "could not request regions\n");
6201                 goto err_out_mwi_2;
6202         }
6203
6204         tp->cp_cmd = RxChkSum;
6205
6206         if ((sizeof(dma_addr_t) > 4) &&
6207             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6208                 tp->cp_cmd |= PCIDAC;
6209                 dev->features |= NETIF_F_HIGHDMA;
6210         } else {
6211                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6212                 if (rc < 0) {
6213                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6214                         goto err_out_free_res_3;
6215                 }
6216         }
6217
6218         /* ioremap MMIO region */
6219         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6220         if (!ioaddr) {
6221                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6222                 rc = -EIO;
6223                 goto err_out_free_res_3;
6224         }
6225         tp->mmio_addr = ioaddr;
6226
6227         if (!pci_is_pcie(pdev))
6228                 netif_info(tp, probe, dev, "not PCI Express\n");
6229
6230         /* Identify chip attached to board */
6231         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6232
6233         rtl_init_rxcfg(tp);
6234
6235         rtl_irq_disable(tp);
6236
6237         rtl_hw_reset(tp);
6238
6239         rtl_ack_events(tp, 0xffff);
6240
6241         pci_set_master(pdev);
6242
6243         /*
6244          * Pretend we are using VLANs; This bypasses a nasty bug where
6245          * Interrupts stop flowing on high load on 8110SCd controllers.
6246          */
6247         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6248                 tp->cp_cmd |= RxVlan;
6249
6250         rtl_init_mdio_ops(tp);
6251         rtl_init_pll_power_ops(tp);
6252         rtl_init_jumbo_ops(tp);
6253
6254         rtl8169_print_mac_version(tp);
6255
6256         chipset = tp->mac_version;
6257         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6258
6259         RTL_W8(Cfg9346, Cfg9346_Unlock);
6260         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6261         RTL_W8(Config3, 0);
6262         RTL_W8(Config5, PMEStatus);
6263         tp->features |= rtl_try_msi(tp, cfg);
6264         RTL_W8(Cfg9346, Cfg9346_Lock);
6265
6266         if (rtl_tbi_enabled(tp)) {
6267                 tp->set_speed = rtl8169_set_speed_tbi;
6268                 tp->get_settings = rtl8169_gset_tbi;
6269                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6270                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6271                 tp->link_ok = rtl8169_tbi_link_ok;
6272                 tp->do_ioctl = rtl_tbi_ioctl;
6273         } else {
6274                 tp->set_speed = rtl8169_set_speed_xmii;
6275                 tp->get_settings = rtl8169_gset_xmii;
6276                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6277                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6278                 tp->link_ok = rtl8169_xmii_link_ok;
6279                 tp->do_ioctl = rtl_xmii_ioctl;
6280         }
6281
6282         mutex_init(&tp->wk.mutex);
6283
6284         /* Get MAC address */
6285         for (i = 0; i < ETH_ALEN; i++)
6286                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6287         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6288
6289         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6290         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6291
6292         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6293
6294         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6295          * properly for all devices */
6296         dev->features |= NETIF_F_RXCSUM |
6297                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6298
6299         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6300                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6301         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6302                 NETIF_F_HIGHDMA;
6303
6304         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6305                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6306                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6307
6308         dev->hw_features |= NETIF_F_RXALL;
6309         dev->hw_features |= NETIF_F_RXFCS;
6310
6311         tp->hw_start = cfg->hw_start;
6312         tp->event_slow = cfg->event_slow;
6313
6314         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6315                 ~(RxBOVF | RxFOVF) : ~0;
6316
6317         init_timer(&tp->timer);
6318         tp->timer.data = (unsigned long) dev;
6319         tp->timer.function = rtl8169_phy_timer;
6320
6321         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6322
6323         rc = register_netdev(dev);
6324         if (rc < 0)
6325                 goto err_out_msi_4;
6326
6327         pci_set_drvdata(pdev, dev);
6328
6329         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6330                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6331                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6332         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6333                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6334                            "tx checksumming: %s]\n",
6335                            rtl_chip_infos[chipset].jumbo_max,
6336                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6337         }
6338
6339         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6340             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6341             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6342                 rtl8168_driver_start(tp);
6343         }
6344
6345         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6346
6347         if (pci_dev_run_wake(pdev))
6348                 pm_runtime_put_noidle(&pdev->dev);
6349
6350         netif_carrier_off(dev);
6351
6352 out:
6353         return rc;
6354
6355 err_out_msi_4:
6356         rtl_disable_msi(pdev, tp);
6357         iounmap(ioaddr);
6358 err_out_free_res_3:
6359         pci_release_regions(pdev);
6360 err_out_mwi_2:
6361         pci_clear_mwi(pdev);
6362         pci_disable_device(pdev);
6363 err_out_free_dev_1:
6364         free_netdev(dev);
6365         goto out;
6366 }
6367
6368 static struct pci_driver rtl8169_pci_driver = {
6369         .name           = MODULENAME,
6370         .id_table       = rtl8169_pci_tbl,
6371         .probe          = rtl_init_one,
6372         .remove         = __devexit_p(rtl_remove_one),
6373         .shutdown       = rtl_shutdown,
6374         .driver.pm      = RTL8169_PM_OPS,
6375 };
6376
6377 static int __init rtl8169_init_module(void)
6378 {
6379         return pci_register_driver(&rtl8169_pci_driver);
6380 }
6381
6382 static void __exit rtl8169_cleanup_module(void)
6383 {
6384         pci_unregister_driver(&rtl8169_pci_driver);
6385 }
6386
6387 module_init(rtl8169_init_module);
6388 module_exit(rtl8169_cleanup_module);