2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
49 #define assert(expr) \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
52 #expr,__FILE__,__func__,__LINE__); \
54 #define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #define assert(expr) do {} while (0)
58 #define dprintk(fmt, args...) do {} while (0)
59 #endif /* RTL8169_DEBUG */
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64 #define TX_SLOTS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
69 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
72 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
73 static const int multicast_filter_limit = 32;
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01 = 0,
140 RTL_GIGA_MAC_NONE = 0xff,
143 enum rtl_tx_desc_version {
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154 #define _R(NAME,TD,FW,SZ,B) { \
162 static const struct {
164 enum rtl_tx_desc_version txd_version;
168 } rtl_chip_infos[] = {
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
271 { PCI_VENDOR_ID_LINKSYS, 0x1032,
272 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280 static int rx_buf_sz = 16383;
287 MAC0 = 0, /* Ethernet hardware address. */
289 MAR0 = 8, /* Multicast filter. */
290 CounterAddrLow = 0x10,
291 CounterAddrHigh = 0x14,
292 TxDescStartAddrLow = 0x20,
293 TxDescStartAddrHigh = 0x24,
294 TxHDescStartAddrLow = 0x28,
295 TxHDescStartAddrHigh = 0x2c,
304 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
305 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
308 #define RX128_INT_EN (1 << 15) /* 8111c and later */
309 #define RX_MULTI_EN (1 << 14) /* 8111c only */
310 #define RXCFG_FIFO_SHIFT 13
311 /* No threshold before first PCI xfer */
312 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
313 #define RXCFG_DMA_SHIFT 8
314 /* Unlimited maximum PCI burst. */
315 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
322 #define PME_SIGNAL (1 << 5) /* 8168c and later */
333 RxDescAddrLow = 0xe4,
334 RxDescAddrHigh = 0xe8,
335 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
337 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
339 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
341 #define TxPacketMax (8064 >> 7)
342 #define EarlySize 0x27
345 FuncEventMask = 0xf4,
346 FuncPresetState = 0xf8,
347 FuncForceEvent = 0xfc,
350 enum rtl8110_registers {
356 enum rtl8168_8101_registers {
359 #define CSIAR_FLAG 0x80000000
360 #define CSIAR_WRITE_CMD 0x80000000
361 #define CSIAR_BYTE_ENABLE 0x0f
362 #define CSIAR_BYTE_ENABLE_SHIFT 12
363 #define CSIAR_ADDR_MASK 0x0fff
366 #define EPHYAR_FLAG 0x80000000
367 #define EPHYAR_WRITE_CMD 0x80000000
368 #define EPHYAR_REG_MASK 0x1f
369 #define EPHYAR_REG_SHIFT 16
370 #define EPHYAR_DATA_MASK 0xffff
372 #define PFM_EN (1 << 6)
374 #define FIX_NAK_1 (1 << 4)
375 #define FIX_NAK_2 (1 << 3)
378 #define NOW_IS_OOB (1 << 7)
379 #define EN_NDP (1 << 3)
380 #define EN_OOB_RESET (1 << 2)
382 #define EFUSEAR_FLAG 0x80000000
383 #define EFUSEAR_WRITE_CMD 0x80000000
384 #define EFUSEAR_READ_CMD 0x00000000
385 #define EFUSEAR_REG_MASK 0x03ff
386 #define EFUSEAR_REG_SHIFT 8
387 #define EFUSEAR_DATA_MASK 0xff
390 enum rtl8168_registers {
395 #define ERIAR_FLAG 0x80000000
396 #define ERIAR_WRITE_CMD 0x80000000
397 #define ERIAR_READ_CMD 0x00000000
398 #define ERIAR_ADDR_BYTE_ALIGN 4
399 #define ERIAR_TYPE_SHIFT 16
400 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MASK_SHIFT 12
404 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
406 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
407 EPHY_RXER_NUM = 0x7c,
408 OCPDR = 0xb0, /* OCP GPHY access */
409 #define OCPDR_WRITE_CMD 0x80000000
410 #define OCPDR_READ_CMD 0x00000000
411 #define OCPDR_REG_MASK 0x7f
412 #define OCPDR_GPHY_REG_SHIFT 16
413 #define OCPDR_DATA_MASK 0xffff
415 #define OCPAR_FLAG 0x80000000
416 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
417 #define OCPAR_GPHY_READ_CMD 0x0000f060
418 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
419 MISC = 0xf0, /* 8168e only. */
420 #define TXPLA_RST (1 << 29)
421 #define PWM_EN (1 << 22)
424 enum rtl_register_content {
425 /* InterruptStatusBits */
429 TxDescUnavail = 0x0080,
453 /* TXPoll register p.5 */
454 HPQ = 0x80, /* Poll cmd on the high prio queue */
455 NPQ = 0x40, /* Poll cmd on the low prio queue */
456 FSWInt = 0x01, /* Forced software interrupt */
460 Cfg9346_Unlock = 0xc0,
465 AcceptBroadcast = 0x08,
466 AcceptMulticast = 0x04,
468 AcceptAllPhys = 0x01,
469 #define RX_CONFIG_ACCEPT_MASK 0x3f
472 TxInterFrameGapShift = 24,
473 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
475 /* Config1 register p.24 */
478 Speed_down = (1 << 4),
482 PMEnable = (1 << 0), /* Power Management Enable */
484 /* Config2 register p. 25 */
485 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
486 PCI_Clock_66MHz = 0x01,
487 PCI_Clock_33MHz = 0x00,
489 /* Config3 register p.25 */
490 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
491 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
492 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
493 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
495 /* Config4 register */
496 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
498 /* Config5 register p.27 */
499 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
500 MWF = (1 << 5), /* Accept Multicast wakeup frame */
501 UWF = (1 << 4), /* Accept Unicast wakeup frame */
503 LanWake = (1 << 1), /* LanWake enable/disable */
504 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
507 TBIReset = 0x80000000,
508 TBILoopback = 0x40000000,
509 TBINwEnable = 0x20000000,
510 TBINwRestart = 0x10000000,
511 TBILinkOk = 0x02000000,
512 TBINwComplete = 0x01000000,
515 EnableBist = (1 << 15), // 8168 8101
516 Mac_dbgo_oe = (1 << 14), // 8168 8101
517 Normal_mode = (1 << 13), // unused
518 Force_half_dup = (1 << 12), // 8168 8101
519 Force_rxflow_en = (1 << 11), // 8168 8101
520 Force_txflow_en = (1 << 10), // 8168 8101
521 Cxpl_dbg_sel = (1 << 9), // 8168 8101
522 ASF = (1 << 8), // 8168 8101
523 PktCntrDisable = (1 << 7), // 8168 8101
524 Mac_dbgo_sel = 0x001c, // 8168
529 INTT_0 = 0x0000, // 8168
530 INTT_1 = 0x0001, // 8168
531 INTT_2 = 0x0002, // 8168
532 INTT_3 = 0x0003, // 8168
534 /* rtl8169_PHYstatus */
545 TBILinkOK = 0x02000000,
547 /* DumpCounterCommand */
552 /* First doubleword. */
553 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
554 RingEnd = (1 << 30), /* End of descriptor ring */
555 FirstFrag = (1 << 29), /* First segment of a packet */
556 LastFrag = (1 << 28), /* Final segment of a packet */
560 enum rtl_tx_desc_bit {
561 /* First doubleword. */
562 TD_LSO = (1 << 27), /* Large Send Offload */
563 #define TD_MSS_MAX 0x07ffu /* MSS value */
565 /* Second doubleword. */
566 TxVlanTag = (1 << 17), /* Add VLAN tag */
569 /* 8169, 8168b and 810x except 8102e. */
570 enum rtl_tx_desc_bit_0 {
571 /* First doubleword. */
572 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
573 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
574 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
575 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
578 /* 8102e, 8168c and beyond. */
579 enum rtl_tx_desc_bit_1 {
580 /* Second doubleword. */
581 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
582 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
583 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
584 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
587 static const struct rtl_tx_desc_info {
594 } tx_desc_info [] = {
597 .udp = TD0_IP_CS | TD0_UDP_CS,
598 .tcp = TD0_IP_CS | TD0_TCP_CS
600 .mss_shift = TD0_MSS_SHIFT,
605 .udp = TD1_IP_CS | TD1_UDP_CS,
606 .tcp = TD1_IP_CS | TD1_TCP_CS
608 .mss_shift = TD1_MSS_SHIFT,
613 enum rtl_rx_desc_bit {
615 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
616 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
618 #define RxProtoUDP (PID1)
619 #define RxProtoTCP (PID0)
620 #define RxProtoIP (PID1 | PID0)
621 #define RxProtoMask RxProtoIP
623 IPFail = (1 << 16), /* IP checksum failed */
624 UDPFail = (1 << 15), /* UDP/IP checksum failed */
625 TCPFail = (1 << 14), /* TCP/IP checksum failed */
626 RxVlanTag = (1 << 16), /* VLAN tag available */
629 #define RsvdMask 0x3fffc000
646 u8 __pad[sizeof(void *) - sizeof(u32)];
650 RTL_FEATURE_WOL = (1 << 0),
651 RTL_FEATURE_MSI = (1 << 1),
652 RTL_FEATURE_GMII = (1 << 2),
655 struct rtl8169_counters {
662 __le32 tx_one_collision;
663 __le32 tx_multi_collision;
672 RTL_FLAG_TASK_ENABLED,
673 RTL_FLAG_TASK_SLOW_PENDING,
674 RTL_FLAG_TASK_RESET_PENDING,
675 RTL_FLAG_TASK_PHY_PENDING,
679 struct rtl8169_stats {
682 struct u64_stats_sync syncp;
685 struct rtl8169_private {
686 void __iomem *mmio_addr; /* memory map physical address */
687 struct pci_dev *pci_dev;
688 struct net_device *dev;
689 struct napi_struct napi;
693 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
694 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
697 struct rtl8169_stats rx_stats;
698 struct rtl8169_stats tx_stats;
699 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
700 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
701 dma_addr_t TxPhyAddr;
702 dma_addr_t RxPhyAddr;
703 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
704 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
705 struct timer_list timer;
709 bool runtime_suspended;
712 void (*write)(void __iomem *, int, int);
713 int (*read)(void __iomem *, int);
716 struct pll_power_ops {
717 void (*down)(struct rtl8169_private *);
718 void (*up)(struct rtl8169_private *);
722 void (*enable)(struct rtl8169_private *);
723 void (*disable)(struct rtl8169_private *);
726 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
727 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
728 void (*phy_reset_enable)(struct rtl8169_private *tp);
729 void (*hw_start)(struct net_device *);
730 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
731 unsigned int (*link_ok)(void __iomem *);
732 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
735 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
737 struct work_struct work;
742 struct mii_if_info mii;
743 struct rtl8169_counters counters;
748 const struct firmware *fw;
750 #define RTL_VER_SIZE 32
752 char version[RTL_VER_SIZE];
754 struct rtl_fw_phy_action {
759 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
762 static int aspm_disable = 0;
763 module_param(aspm_disable, int, 0444);
764 MODULE_PARM_DESC(aspm_disable, "Disable ASPM completely.");
766 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
767 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
768 module_param(use_dac, int, 0);
769 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
770 module_param_named(debug, debug.msg_enable, int, 0);
771 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
772 MODULE_LICENSE("GPL");
773 MODULE_VERSION(RTL8169_VERSION);
774 MODULE_FIRMWARE(FIRMWARE_8168D_1);
775 MODULE_FIRMWARE(FIRMWARE_8168D_2);
776 MODULE_FIRMWARE(FIRMWARE_8168E_1);
777 MODULE_FIRMWARE(FIRMWARE_8168E_2);
778 MODULE_FIRMWARE(FIRMWARE_8168E_3);
779 MODULE_FIRMWARE(FIRMWARE_8105E_1);
780 MODULE_FIRMWARE(FIRMWARE_8168F_1);
781 MODULE_FIRMWARE(FIRMWARE_8168F_2);
783 static void rtl_lock_work(struct rtl8169_private *tp)
785 mutex_lock(&tp->wk.mutex);
788 static void rtl_unlock_work(struct rtl8169_private *tp)
790 mutex_unlock(&tp->wk.mutex);
793 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
795 int cap = pci_pcie_cap(pdev);
800 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
801 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
802 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
806 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
808 void __iomem *ioaddr = tp->mmio_addr;
811 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
812 for (i = 0; i < 20; i++) {
814 if (RTL_R32(OCPAR) & OCPAR_FLAG)
817 return RTL_R32(OCPDR);
820 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
822 void __iomem *ioaddr = tp->mmio_addr;
825 RTL_W32(OCPDR, data);
826 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
827 for (i = 0; i < 20; i++) {
829 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
834 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
836 void __iomem *ioaddr = tp->mmio_addr;
840 RTL_W32(ERIAR, 0x800010e8);
842 for (i = 0; i < 5; i++) {
844 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
848 ocp_write(tp, 0x1, 0x30, 0x00000001);
851 #define OOB_CMD_RESET 0x00
852 #define OOB_CMD_DRIVER_START 0x05
853 #define OOB_CMD_DRIVER_STOP 0x06
855 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
857 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
860 static void rtl8168_driver_start(struct rtl8169_private *tp)
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
867 reg = rtl8168_get_ocp_reg(tp);
869 for (i = 0; i < 10; i++) {
871 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
876 static void rtl8168_driver_stop(struct rtl8169_private *tp)
881 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
883 reg = rtl8168_get_ocp_reg(tp);
885 for (i = 0; i < 10; i++) {
887 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
892 static int r8168dp_check_dash(struct rtl8169_private *tp)
894 u16 reg = rtl8168_get_ocp_reg(tp);
896 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
899 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
903 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
905 for (i = 20; i > 0; i--) {
907 * Check if the RTL8169 has completed writing to the specified
910 if (!(RTL_R32(PHYAR) & 0x80000000))
915 * According to hardware specs a 20us delay is required after write
916 * complete indication, but before sending next command.
921 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
925 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
927 for (i = 20; i > 0; i--) {
929 * Check if the RTL8169 has completed retrieving data from
930 * the specified MII register.
932 if (RTL_R32(PHYAR) & 0x80000000) {
933 value = RTL_R32(PHYAR) & 0xffff;
939 * According to hardware specs a 20us delay is required after read
940 * complete indication, but before sending next command.
947 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
951 RTL_W32(OCPDR, data |
952 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
953 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
954 RTL_W32(EPHY_RXER_NUM, 0);
956 for (i = 0; i < 100; i++) {
958 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
963 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
965 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
966 (value & OCPDR_DATA_MASK));
969 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
973 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
976 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
977 RTL_W32(EPHY_RXER_NUM, 0);
979 for (i = 0; i < 100; i++) {
981 if (RTL_R32(OCPAR) & OCPAR_FLAG)
985 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
988 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
990 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
992 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
995 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
997 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1000 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1002 r8168dp_2_mdio_start(ioaddr);
1004 r8169_mdio_write(ioaddr, reg_addr, value);
1006 r8168dp_2_mdio_stop(ioaddr);
1009 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1013 r8168dp_2_mdio_start(ioaddr);
1015 value = r8169_mdio_read(ioaddr, reg_addr);
1017 r8168dp_2_mdio_stop(ioaddr);
1022 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1024 tp->mdio_ops.write(tp->mmio_addr, location, val);
1027 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 return tp->mdio_ops.read(tp->mmio_addr, location);
1032 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1034 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1037 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1041 val = rtl_readphy(tp, reg_addr);
1042 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1045 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1048 struct rtl8169_private *tp = netdev_priv(dev);
1050 rtl_writephy(tp, location, val);
1053 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1055 struct rtl8169_private *tp = netdev_priv(dev);
1057 return rtl_readphy(tp, location);
1060 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1064 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1067 for (i = 0; i < 100; i++) {
1068 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1074 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1079 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1081 for (i = 0; i < 100; i++) {
1082 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1092 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1096 RTL_W32(CSIDR, value);
1097 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1100 for (i = 0; i < 100; i++) {
1101 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1107 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1112 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1115 for (i = 0; i < 100; i++) {
1116 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117 value = RTL_R32(CSIDR);
1127 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1131 BUG_ON((addr & 3) || (mask == 0));
1132 RTL_W32(ERIDR, val);
1133 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1135 for (i = 0; i < 100; i++) {
1136 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1142 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1147 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1149 for (i = 0; i < 100; i++) {
1150 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151 value = RTL_R32(ERIDR);
1161 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1165 val = rtl_eri_read(ioaddr, addr, type);
1166 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1175 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176 const struct exgmac_reg *r, int len)
1179 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1184 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1189 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1191 for (i = 0; i < 300; i++) {
1192 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1202 static u16 rtl_get_events(struct rtl8169_private *tp)
1204 void __iomem *ioaddr = tp->mmio_addr;
1206 return RTL_R16(IntrStatus);
1209 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1211 void __iomem *ioaddr = tp->mmio_addr;
1213 RTL_W16(IntrStatus, bits);
1217 static void rtl_irq_disable(struct rtl8169_private *tp)
1219 void __iomem *ioaddr = tp->mmio_addr;
1221 RTL_W16(IntrMask, 0);
1225 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1227 void __iomem *ioaddr = tp->mmio_addr;
1229 RTL_W16(IntrMask, bits);
1232 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1236 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1238 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1243 void __iomem *ioaddr = tp->mmio_addr;
1245 rtl_irq_disable(tp);
1246 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1252 void __iomem *ioaddr = tp->mmio_addr;
1254 return RTL_R32(TBICSR) & TBIReset;
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1259 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1264 return RTL_R32(TBICSR) & TBILinkOk;
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1269 return RTL_R8(PHYstatus) & LinkStatus;
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1274 void __iomem *ioaddr = tp->mmio_addr;
1276 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1283 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1287 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1289 void __iomem *ioaddr = tp->mmio_addr;
1290 struct net_device *dev = tp->dev;
1292 if (!netif_running(dev))
1295 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x00000011, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x00000005, ERIAR_EXGMAC);
1301 } else if (RTL_R8(PHYstatus) & _100bps) {
1302 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303 0x0000001f, ERIAR_EXGMAC);
1304 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305 0x00000005, ERIAR_EXGMAC);
1307 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308 0x0000001f, ERIAR_EXGMAC);
1309 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310 0x0000003f, ERIAR_EXGMAC);
1312 /* Reset packet filter */
1313 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1315 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1317 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321 0x00000011, ERIAR_EXGMAC);
1322 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323 0x00000005, ERIAR_EXGMAC);
1325 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326 0x0000001f, ERIAR_EXGMAC);
1327 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328 0x0000003f, ERIAR_EXGMAC);
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334 struct rtl8169_private *tp,
1335 void __iomem *ioaddr, bool pm)
1337 if (tp->link_ok(ioaddr)) {
1338 rtl_link_chg_patch(tp);
1339 /* This is to cancel a scheduled suspend if there's one. */
1341 pm_request_resume(&tp->pci_dev->dev);
1342 netif_carrier_on(dev);
1343 if (net_ratelimit())
1344 netif_info(tp, ifup, dev, "link up\n");
1346 netif_carrier_off(dev);
1347 netif_info(tp, ifdown, dev, "link down\n");
1349 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354 struct rtl8169_private *tp,
1355 void __iomem *ioaddr)
1357 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1364 void __iomem *ioaddr = tp->mmio_addr;
1368 options = RTL_R8(Config1);
1369 if (!(options & PMEnable))
1372 options = RTL_R8(Config3);
1373 if (options & LinkUp)
1374 wolopts |= WAKE_PHY;
1375 if (options & MagicPacket)
1376 wolopts |= WAKE_MAGIC;
1378 options = RTL_R8(Config5);
1380 wolopts |= WAKE_UCAST;
1382 wolopts |= WAKE_BCAST;
1384 wolopts |= WAKE_MCAST;
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1391 struct rtl8169_private *tp = netdev_priv(dev);
1395 wol->supported = WAKE_ANY;
1396 wol->wolopts = __rtl8169_get_wol(tp);
1398 rtl_unlock_work(tp);
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1403 void __iomem *ioaddr = tp->mmio_addr;
1405 static const struct {
1410 { WAKE_PHY, Config3, LinkUp },
1411 { WAKE_MAGIC, Config3, MagicPacket },
1412 { WAKE_UCAST, Config5, UWF },
1413 { WAKE_BCAST, Config5, BWF },
1414 { WAKE_MCAST, Config5, MWF },
1415 { WAKE_ANY, Config5, LanWake }
1419 RTL_W8(Cfg9346, Cfg9346_Unlock);
1421 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423 if (wolopts & cfg[i].opt)
1424 options |= cfg[i].mask;
1425 RTL_W8(cfg[i].reg, options);
1428 switch (tp->mac_version) {
1429 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1430 options = RTL_R8(Config1) & ~PMEnable;
1432 options |= PMEnable;
1433 RTL_W8(Config1, options);
1436 options = RTL_R8(Config2) & ~PME_SIGNAL;
1438 options |= PME_SIGNAL;
1439 RTL_W8(Config2, options);
1443 RTL_W8(Cfg9346, Cfg9346_Lock);
1446 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1448 struct rtl8169_private *tp = netdev_priv(dev);
1453 tp->features |= RTL_FEATURE_WOL;
1455 tp->features &= ~RTL_FEATURE_WOL;
1456 __rtl8169_set_wol(tp, wol->wolopts);
1458 rtl_unlock_work(tp);
1460 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1465 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1467 return rtl_chip_infos[tp->mac_version].fw_name;
1470 static void rtl8169_get_drvinfo(struct net_device *dev,
1471 struct ethtool_drvinfo *info)
1473 struct rtl8169_private *tp = netdev_priv(dev);
1474 struct rtl_fw *rtl_fw = tp->rtl_fw;
1476 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1478 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1479 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1480 if (!IS_ERR_OR_NULL(rtl_fw))
1481 strlcpy(info->fw_version, rtl_fw->version,
1482 sizeof(info->fw_version));
1485 static int rtl8169_get_regs_len(struct net_device *dev)
1487 return R8169_REGS_SIZE;
1490 static int rtl8169_set_speed_tbi(struct net_device *dev,
1491 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1493 struct rtl8169_private *tp = netdev_priv(dev);
1494 void __iomem *ioaddr = tp->mmio_addr;
1498 reg = RTL_R32(TBICSR);
1499 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1500 (duplex == DUPLEX_FULL)) {
1501 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1502 } else if (autoneg == AUTONEG_ENABLE)
1503 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1505 netif_warn(tp, link, dev,
1506 "incorrect speed setting refused in TBI mode\n");
1513 static int rtl8169_set_speed_xmii(struct net_device *dev,
1514 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1516 struct rtl8169_private *tp = netdev_priv(dev);
1517 int giga_ctrl, bmcr;
1520 rtl_writephy(tp, 0x1f, 0x0000);
1522 if (autoneg == AUTONEG_ENABLE) {
1525 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1526 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1527 ADVERTISE_100HALF | ADVERTISE_100FULL);
1529 if (adv & ADVERTISED_10baseT_Half)
1530 auto_nego |= ADVERTISE_10HALF;
1531 if (adv & ADVERTISED_10baseT_Full)
1532 auto_nego |= ADVERTISE_10FULL;
1533 if (adv & ADVERTISED_100baseT_Half)
1534 auto_nego |= ADVERTISE_100HALF;
1535 if (adv & ADVERTISED_100baseT_Full)
1536 auto_nego |= ADVERTISE_100FULL;
1538 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1540 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1541 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1543 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1544 if (tp->mii.supports_gmii) {
1545 if (adv & ADVERTISED_1000baseT_Half)
1546 giga_ctrl |= ADVERTISE_1000HALF;
1547 if (adv & ADVERTISED_1000baseT_Full)
1548 giga_ctrl |= ADVERTISE_1000FULL;
1549 } else if (adv & (ADVERTISED_1000baseT_Half |
1550 ADVERTISED_1000baseT_Full)) {
1551 netif_info(tp, link, dev,
1552 "PHY does not support 1000Mbps\n");
1556 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1558 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1559 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1563 if (speed == SPEED_10)
1565 else if (speed == SPEED_100)
1566 bmcr = BMCR_SPEED100;
1570 if (duplex == DUPLEX_FULL)
1571 bmcr |= BMCR_FULLDPLX;
1574 rtl_writephy(tp, MII_BMCR, bmcr);
1576 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1577 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1578 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1579 rtl_writephy(tp, 0x17, 0x2138);
1580 rtl_writephy(tp, 0x0e, 0x0260);
1582 rtl_writephy(tp, 0x17, 0x2108);
1583 rtl_writephy(tp, 0x0e, 0x0000);
1592 static int rtl8169_set_speed(struct net_device *dev,
1593 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1595 struct rtl8169_private *tp = netdev_priv(dev);
1598 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1602 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1603 (advertising & ADVERTISED_1000baseT_Full)) {
1604 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1610 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1612 struct rtl8169_private *tp = netdev_priv(dev);
1615 del_timer_sync(&tp->timer);
1618 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1619 cmd->duplex, cmd->advertising);
1620 rtl_unlock_work(tp);
1625 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1626 netdev_features_t features)
1628 struct rtl8169_private *tp = netdev_priv(dev);
1630 if (dev->mtu > TD_MSS_MAX)
1631 features &= ~NETIF_F_ALL_TSO;
1633 if (dev->mtu > JUMBO_1K &&
1634 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1635 features &= ~NETIF_F_IP_CSUM;
1640 static void __rtl8169_set_features(struct net_device *dev,
1641 netdev_features_t features)
1643 struct rtl8169_private *tp = netdev_priv(dev);
1644 netdev_features_t changed = features ^ dev->features;
1645 void __iomem *ioaddr = tp->mmio_addr;
1647 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1650 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1651 if (features & NETIF_F_RXCSUM)
1652 tp->cp_cmd |= RxChkSum;
1654 tp->cp_cmd &= ~RxChkSum;
1656 if (dev->features & NETIF_F_HW_VLAN_RX)
1657 tp->cp_cmd |= RxVlan;
1659 tp->cp_cmd &= ~RxVlan;
1661 RTL_W16(CPlusCmd, tp->cp_cmd);
1664 if (changed & NETIF_F_RXALL) {
1665 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1666 if (features & NETIF_F_RXALL)
1667 tmp |= (AcceptErr | AcceptRunt);
1668 RTL_W32(RxConfig, tmp);
1672 static int rtl8169_set_features(struct net_device *dev,
1673 netdev_features_t features)
1675 struct rtl8169_private *tp = netdev_priv(dev);
1678 __rtl8169_set_features(dev, features);
1679 rtl_unlock_work(tp);
1685 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1686 struct sk_buff *skb)
1688 return (vlan_tx_tag_present(skb)) ?
1689 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1692 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1694 u32 opts2 = le32_to_cpu(desc->opts2);
1696 if (opts2 & RxVlanTag)
1697 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1702 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1704 struct rtl8169_private *tp = netdev_priv(dev);
1705 void __iomem *ioaddr = tp->mmio_addr;
1709 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1710 cmd->port = PORT_FIBRE;
1711 cmd->transceiver = XCVR_INTERNAL;
1713 status = RTL_R32(TBICSR);
1714 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1715 cmd->autoneg = !!(status & TBINwEnable);
1717 ethtool_cmd_speed_set(cmd, SPEED_1000);
1718 cmd->duplex = DUPLEX_FULL; /* Always set */
1723 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1725 struct rtl8169_private *tp = netdev_priv(dev);
1727 return mii_ethtool_gset(&tp->mii, cmd);
1730 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1732 struct rtl8169_private *tp = netdev_priv(dev);
1736 rc = tp->get_settings(dev, cmd);
1737 rtl_unlock_work(tp);
1742 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1745 struct rtl8169_private *tp = netdev_priv(dev);
1747 if (regs->len > R8169_REGS_SIZE)
1748 regs->len = R8169_REGS_SIZE;
1751 memcpy_fromio(p, tp->mmio_addr, regs->len);
1752 rtl_unlock_work(tp);
1755 static u32 rtl8169_get_msglevel(struct net_device *dev)
1757 struct rtl8169_private *tp = netdev_priv(dev);
1759 return tp->msg_enable;
1762 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1764 struct rtl8169_private *tp = netdev_priv(dev);
1766 tp->msg_enable = value;
1769 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1776 "tx_single_collisions",
1777 "tx_multi_collisions",
1785 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1789 return ARRAY_SIZE(rtl8169_gstrings);
1795 static void rtl8169_update_counters(struct net_device *dev)
1797 struct rtl8169_private *tp = netdev_priv(dev);
1798 void __iomem *ioaddr = tp->mmio_addr;
1799 struct device *d = &tp->pci_dev->dev;
1800 struct rtl8169_counters *counters;
1806 * Some chips are unable to dump tally counters when the receiver
1809 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1812 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1816 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1817 cmd = (u64)paddr & DMA_BIT_MASK(32);
1818 RTL_W32(CounterAddrLow, cmd);
1819 RTL_W32(CounterAddrLow, cmd | CounterDump);
1822 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1823 memcpy(&tp->counters, counters, sizeof(*counters));
1829 RTL_W32(CounterAddrLow, 0);
1830 RTL_W32(CounterAddrHigh, 0);
1832 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1835 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1836 struct ethtool_stats *stats, u64 *data)
1838 struct rtl8169_private *tp = netdev_priv(dev);
1842 rtl8169_update_counters(dev);
1844 data[0] = le64_to_cpu(tp->counters.tx_packets);
1845 data[1] = le64_to_cpu(tp->counters.rx_packets);
1846 data[2] = le64_to_cpu(tp->counters.tx_errors);
1847 data[3] = le32_to_cpu(tp->counters.rx_errors);
1848 data[4] = le16_to_cpu(tp->counters.rx_missed);
1849 data[5] = le16_to_cpu(tp->counters.align_errors);
1850 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1851 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1852 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1853 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1854 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1855 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1856 data[12] = le16_to_cpu(tp->counters.tx_underun);
1859 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1863 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1868 static const struct ethtool_ops rtl8169_ethtool_ops = {
1869 .get_drvinfo = rtl8169_get_drvinfo,
1870 .get_regs_len = rtl8169_get_regs_len,
1871 .get_link = ethtool_op_get_link,
1872 .get_settings = rtl8169_get_settings,
1873 .set_settings = rtl8169_set_settings,
1874 .get_msglevel = rtl8169_get_msglevel,
1875 .set_msglevel = rtl8169_set_msglevel,
1876 .get_regs = rtl8169_get_regs,
1877 .get_wol = rtl8169_get_wol,
1878 .set_wol = rtl8169_set_wol,
1879 .get_strings = rtl8169_get_strings,
1880 .get_sset_count = rtl8169_get_sset_count,
1881 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1884 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1885 struct net_device *dev, u8 default_version)
1887 void __iomem *ioaddr = tp->mmio_addr;
1889 * The driver currently handles the 8168Bf and the 8168Be identically
1890 * but they can be identified more specifically through the test below
1893 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1895 * Same thing for the 8101Eb and the 8101Ec:
1897 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1899 static const struct rtl_mac_info {
1905 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1906 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1909 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1910 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1911 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1912 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1915 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1916 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1917 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1919 /* 8168DP family. */
1920 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1921 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1922 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1925 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1926 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1927 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1928 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1929 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1930 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1931 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1932 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1933 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1936 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1937 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1938 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1939 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1942 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1943 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1944 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1945 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1946 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1947 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1948 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1949 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1950 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1951 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1952 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1953 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1954 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1955 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1956 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1957 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1958 /* FIXME: where did these entries come from ? -- FR */
1959 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1960 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1963 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1964 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1965 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1966 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1967 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1968 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1971 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1973 const struct rtl_mac_info *p = mac_info;
1976 reg = RTL_R32(TxConfig);
1977 while ((reg & p->mask) != p->val)
1979 tp->mac_version = p->mac_version;
1981 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1982 netif_notice(tp, probe, dev,
1983 "unknown MAC, using family default\n");
1984 tp->mac_version = default_version;
1988 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1990 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1998 static void rtl_writephy_batch(struct rtl8169_private *tp,
1999 const struct phy_reg *regs, int len)
2002 rtl_writephy(tp, regs->reg, regs->val);
2007 #define PHY_READ 0x00000000
2008 #define PHY_DATA_OR 0x10000000
2009 #define PHY_DATA_AND 0x20000000
2010 #define PHY_BJMPN 0x30000000
2011 #define PHY_READ_EFUSE 0x40000000
2012 #define PHY_READ_MAC_BYTE 0x50000000
2013 #define PHY_WRITE_MAC_BYTE 0x60000000
2014 #define PHY_CLEAR_READCOUNT 0x70000000
2015 #define PHY_WRITE 0x80000000
2016 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2017 #define PHY_COMP_EQ_SKIPN 0xa0000000
2018 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2019 #define PHY_WRITE_PREVIOUS 0xc0000000
2020 #define PHY_SKIPN 0xd0000000
2021 #define PHY_DELAY_MS 0xe0000000
2022 #define PHY_WRITE_ERI_WORD 0xf0000000
2026 char version[RTL_VER_SIZE];
2032 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2034 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2036 const struct firmware *fw = rtl_fw->fw;
2037 struct fw_info *fw_info = (struct fw_info *)fw->data;
2038 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2039 char *version = rtl_fw->version;
2042 if (fw->size < FW_OPCODE_SIZE)
2045 if (!fw_info->magic) {
2046 size_t i, size, start;
2049 if (fw->size < sizeof(*fw_info))
2052 for (i = 0; i < fw->size; i++)
2053 checksum += fw->data[i];
2057 start = le32_to_cpu(fw_info->fw_start);
2058 if (start > fw->size)
2061 size = le32_to_cpu(fw_info->fw_len);
2062 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2065 memcpy(version, fw_info->version, RTL_VER_SIZE);
2067 pa->code = (__le32 *)(fw->data + start);
2070 if (fw->size % FW_OPCODE_SIZE)
2073 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2075 pa->code = (__le32 *)fw->data;
2076 pa->size = fw->size / FW_OPCODE_SIZE;
2078 version[RTL_VER_SIZE - 1] = 0;
2085 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2086 struct rtl_fw_phy_action *pa)
2091 for (index = 0; index < pa->size; index++) {
2092 u32 action = le32_to_cpu(pa->code[index]);
2093 u32 regno = (action & 0x0fff0000) >> 16;
2095 switch(action & 0xf0000000) {
2099 case PHY_READ_EFUSE:
2100 case PHY_CLEAR_READCOUNT:
2102 case PHY_WRITE_PREVIOUS:
2107 if (regno > index) {
2108 netif_err(tp, ifup, tp->dev,
2109 "Out of range of firmware\n");
2113 case PHY_READCOUNT_EQ_SKIP:
2114 if (index + 2 >= pa->size) {
2115 netif_err(tp, ifup, tp->dev,
2116 "Out of range of firmware\n");
2120 case PHY_COMP_EQ_SKIPN:
2121 case PHY_COMP_NEQ_SKIPN:
2123 if (index + 1 + regno >= pa->size) {
2124 netif_err(tp, ifup, tp->dev,
2125 "Out of range of firmware\n");
2130 case PHY_READ_MAC_BYTE:
2131 case PHY_WRITE_MAC_BYTE:
2132 case PHY_WRITE_ERI_WORD:
2134 netif_err(tp, ifup, tp->dev,
2135 "Invalid action 0x%08x\n", action);
2144 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2146 struct net_device *dev = tp->dev;
2149 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2150 netif_err(tp, ifup, dev, "invalid firwmare\n");
2154 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2160 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2162 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2166 predata = count = 0;
2168 for (index = 0; index < pa->size; ) {
2169 u32 action = le32_to_cpu(pa->code[index]);
2170 u32 data = action & 0x0000ffff;
2171 u32 regno = (action & 0x0fff0000) >> 16;
2176 switch(action & 0xf0000000) {
2178 predata = rtl_readphy(tp, regno);
2193 case PHY_READ_EFUSE:
2194 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2197 case PHY_CLEAR_READCOUNT:
2202 rtl_writephy(tp, regno, data);
2205 case PHY_READCOUNT_EQ_SKIP:
2206 index += (count == data) ? 2 : 1;
2208 case PHY_COMP_EQ_SKIPN:
2209 if (predata == data)
2213 case PHY_COMP_NEQ_SKIPN:
2214 if (predata != data)
2218 case PHY_WRITE_PREVIOUS:
2219 rtl_writephy(tp, regno, predata);
2230 case PHY_READ_MAC_BYTE:
2231 case PHY_WRITE_MAC_BYTE:
2232 case PHY_WRITE_ERI_WORD:
2239 static void rtl_release_firmware(struct rtl8169_private *tp)
2241 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2242 release_firmware(tp->rtl_fw->fw);
2245 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2248 static void rtl_apply_firmware(struct rtl8169_private *tp)
2250 struct rtl_fw *rtl_fw = tp->rtl_fw;
2252 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2253 if (!IS_ERR_OR_NULL(rtl_fw))
2254 rtl_phy_write_fw(tp, rtl_fw);
2257 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2259 if (rtl_readphy(tp, reg) != val)
2260 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2262 rtl_apply_firmware(tp);
2265 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2267 static const struct phy_reg phy_reg_init[] = {
2329 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2332 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2334 static const struct phy_reg phy_reg_init[] = {
2340 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2343 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2345 struct pci_dev *pdev = tp->pci_dev;
2347 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2348 (pdev->subsystem_device != 0xe000))
2351 rtl_writephy(tp, 0x1f, 0x0001);
2352 rtl_writephy(tp, 0x10, 0xf01b);
2353 rtl_writephy(tp, 0x1f, 0x0000);
2356 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2358 static const struct phy_reg phy_reg_init[] = {
2398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2400 rtl8169scd_hw_phy_config_quirk(tp);
2403 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2405 static const struct phy_reg phy_reg_init[] = {
2453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2456 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2458 static const struct phy_reg phy_reg_init[] = {
2463 rtl_writephy(tp, 0x1f, 0x0001);
2464 rtl_patchphy(tp, 0x16, 1 << 0);
2466 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2469 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2471 static const struct phy_reg phy_reg_init[] = {
2477 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2480 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2482 static const struct phy_reg phy_reg_init[] = {
2490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2493 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2495 static const struct phy_reg phy_reg_init[] = {
2501 rtl_writephy(tp, 0x1f, 0x0000);
2502 rtl_patchphy(tp, 0x14, 1 << 5);
2503 rtl_patchphy(tp, 0x0d, 1 << 5);
2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2510 static const struct phy_reg phy_reg_init[] = {
2530 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2532 rtl_patchphy(tp, 0x14, 1 << 5);
2533 rtl_patchphy(tp, 0x0d, 1 << 5);
2534 rtl_writephy(tp, 0x1f, 0x0000);
2537 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2539 static const struct phy_reg phy_reg_init[] = {
2557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559 rtl_patchphy(tp, 0x16, 1 << 0);
2560 rtl_patchphy(tp, 0x14, 1 << 5);
2561 rtl_patchphy(tp, 0x0d, 1 << 5);
2562 rtl_writephy(tp, 0x1f, 0x0000);
2565 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2567 static const struct phy_reg phy_reg_init[] = {
2579 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2581 rtl_patchphy(tp, 0x16, 1 << 0);
2582 rtl_patchphy(tp, 0x14, 1 << 5);
2583 rtl_patchphy(tp, 0x0d, 1 << 5);
2584 rtl_writephy(tp, 0x1f, 0x0000);
2587 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2589 rtl8168c_3_hw_phy_config(tp);
2592 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2594 static const struct phy_reg phy_reg_init_0[] = {
2595 /* Channel Estimation */
2616 * Enhance line driver power
2625 * Can not link to 1Gbps with bad cable
2626 * Decrease SNR threshold form 21.07dB to 19.04dB
2634 void __iomem *ioaddr = tp->mmio_addr;
2636 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2640 * Fine Tune Switching regulator parameter
2642 rtl_writephy(tp, 0x1f, 0x0002);
2643 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2644 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2646 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2647 static const struct phy_reg phy_reg_init[] = {
2657 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2659 val = rtl_readphy(tp, 0x0d);
2661 if ((val & 0x00ff) != 0x006c) {
2662 static const u32 set[] = {
2663 0x0065, 0x0066, 0x0067, 0x0068,
2664 0x0069, 0x006a, 0x006b, 0x006c
2668 rtl_writephy(tp, 0x1f, 0x0002);
2671 for (i = 0; i < ARRAY_SIZE(set); i++)
2672 rtl_writephy(tp, 0x0d, val | set[i]);
2675 static const struct phy_reg phy_reg_init[] = {
2683 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2686 /* RSET couple improve */
2687 rtl_writephy(tp, 0x1f, 0x0002);
2688 rtl_patchphy(tp, 0x0d, 0x0300);
2689 rtl_patchphy(tp, 0x0f, 0x0010);
2691 /* Fine tune PLL performance */
2692 rtl_writephy(tp, 0x1f, 0x0002);
2693 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2694 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2696 rtl_writephy(tp, 0x1f, 0x0005);
2697 rtl_writephy(tp, 0x05, 0x001b);
2699 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2701 rtl_writephy(tp, 0x1f, 0x0000);
2704 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2706 static const struct phy_reg phy_reg_init_0[] = {
2707 /* Channel Estimation */
2728 * Enhance line driver power
2737 * Can not link to 1Gbps with bad cable
2738 * Decrease SNR threshold form 21.07dB to 19.04dB
2746 void __iomem *ioaddr = tp->mmio_addr;
2748 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2750 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2751 static const struct phy_reg phy_reg_init[] = {
2762 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2764 val = rtl_readphy(tp, 0x0d);
2765 if ((val & 0x00ff) != 0x006c) {
2766 static const u32 set[] = {
2767 0x0065, 0x0066, 0x0067, 0x0068,
2768 0x0069, 0x006a, 0x006b, 0x006c
2772 rtl_writephy(tp, 0x1f, 0x0002);
2775 for (i = 0; i < ARRAY_SIZE(set); i++)
2776 rtl_writephy(tp, 0x0d, val | set[i]);
2779 static const struct phy_reg phy_reg_init[] = {
2787 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2790 /* Fine tune PLL performance */
2791 rtl_writephy(tp, 0x1f, 0x0002);
2792 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2793 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2795 /* Switching regulator Slew rate */
2796 rtl_writephy(tp, 0x1f, 0x0002);
2797 rtl_patchphy(tp, 0x0f, 0x0017);
2799 rtl_writephy(tp, 0x1f, 0x0005);
2800 rtl_writephy(tp, 0x05, 0x001b);
2802 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2804 rtl_writephy(tp, 0x1f, 0x0000);
2807 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2809 static const struct phy_reg phy_reg_init[] = {
2865 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2868 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2870 static const struct phy_reg phy_reg_init[] = {
2880 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2881 rtl_patchphy(tp, 0x0d, 1 << 5);
2884 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2886 static const struct phy_reg phy_reg_init[] = {
2887 /* Enable Delay cap */
2893 /* Channel estimation fine tune */
2902 /* Update PFM & 10M TX idle timer */
2914 rtl_apply_firmware(tp);
2916 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2918 /* DCO enable for 10M IDLE Power */
2919 rtl_writephy(tp, 0x1f, 0x0007);
2920 rtl_writephy(tp, 0x1e, 0x0023);
2921 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2922 rtl_writephy(tp, 0x1f, 0x0000);
2924 /* For impedance matching */
2925 rtl_writephy(tp, 0x1f, 0x0002);
2926 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2927 rtl_writephy(tp, 0x1f, 0x0000);
2929 /* PHY auto speed down */
2930 rtl_writephy(tp, 0x1f, 0x0007);
2931 rtl_writephy(tp, 0x1e, 0x002d);
2932 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2933 rtl_writephy(tp, 0x1f, 0x0000);
2934 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2936 rtl_writephy(tp, 0x1f, 0x0005);
2937 rtl_writephy(tp, 0x05, 0x8b86);
2938 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2939 rtl_writephy(tp, 0x1f, 0x0000);
2941 rtl_writephy(tp, 0x1f, 0x0005);
2942 rtl_writephy(tp, 0x05, 0x8b85);
2943 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2944 rtl_writephy(tp, 0x1f, 0x0007);
2945 rtl_writephy(tp, 0x1e, 0x0020);
2946 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2947 rtl_writephy(tp, 0x1f, 0x0006);
2948 rtl_writephy(tp, 0x00, 0x5a00);
2949 rtl_writephy(tp, 0x1f, 0x0000);
2950 rtl_writephy(tp, 0x0d, 0x0007);
2951 rtl_writephy(tp, 0x0e, 0x003c);
2952 rtl_writephy(tp, 0x0d, 0x4007);
2953 rtl_writephy(tp, 0x0e, 0x0000);
2954 rtl_writephy(tp, 0x0d, 0x0000);
2957 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2959 static const struct phy_reg phy_reg_init[] = {
2960 /* Enable Delay cap */
2969 /* Channel estimation fine tune */
2986 rtl_apply_firmware(tp);
2988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2990 /* For 4-corner performance improve */
2991 rtl_writephy(tp, 0x1f, 0x0005);
2992 rtl_writephy(tp, 0x05, 0x8b80);
2993 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2994 rtl_writephy(tp, 0x1f, 0x0000);
2996 /* PHY auto speed down */
2997 rtl_writephy(tp, 0x1f, 0x0004);
2998 rtl_writephy(tp, 0x1f, 0x0007);
2999 rtl_writephy(tp, 0x1e, 0x002d);
3000 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3001 rtl_writephy(tp, 0x1f, 0x0002);
3002 rtl_writephy(tp, 0x1f, 0x0000);
3003 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3005 /* improve 10M EEE waveform */
3006 rtl_writephy(tp, 0x1f, 0x0005);
3007 rtl_writephy(tp, 0x05, 0x8b86);
3008 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3009 rtl_writephy(tp, 0x1f, 0x0000);
3011 /* Improve 2-pair detection performance */
3012 rtl_writephy(tp, 0x1f, 0x0005);
3013 rtl_writephy(tp, 0x05, 0x8b85);
3014 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3015 rtl_writephy(tp, 0x1f, 0x0000);
3018 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3020 rtl_writephy(tp, 0x1f, 0x0005);
3021 rtl_writephy(tp, 0x05, 0x8b85);
3022 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3023 rtl_writephy(tp, 0x1f, 0x0004);
3024 rtl_writephy(tp, 0x1f, 0x0007);
3025 rtl_writephy(tp, 0x1e, 0x0020);
3026 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3027 rtl_writephy(tp, 0x1f, 0x0002);
3028 rtl_writephy(tp, 0x1f, 0x0000);
3029 rtl_writephy(tp, 0x0d, 0x0007);
3030 rtl_writephy(tp, 0x0e, 0x003c);
3031 rtl_writephy(tp, 0x0d, 0x4007);
3032 rtl_writephy(tp, 0x0e, 0x0000);
3033 rtl_writephy(tp, 0x0d, 0x0000);
3036 rtl_writephy(tp, 0x1f, 0x0003);
3037 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3038 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3039 rtl_writephy(tp, 0x1f, 0x0000);
3042 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3044 static const struct phy_reg phy_reg_init[] = {
3045 /* Channel estimation fine tune */
3050 /* Modify green table for giga & fnet */
3067 /* Modify green table for 10M */
3073 /* Disable hiimpedance detection (RTCT) */
3079 rtl_apply_firmware(tp);
3081 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3083 /* For 4-corner performance improve */
3084 rtl_writephy(tp, 0x1f, 0x0005);
3085 rtl_writephy(tp, 0x05, 0x8b80);
3086 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3087 rtl_writephy(tp, 0x1f, 0x0000);
3089 /* PHY auto speed down */
3090 rtl_writephy(tp, 0x1f, 0x0007);
3091 rtl_writephy(tp, 0x1e, 0x002d);
3092 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3093 rtl_writephy(tp, 0x1f, 0x0000);
3094 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3096 /* Improve 10M EEE waveform */
3097 rtl_writephy(tp, 0x1f, 0x0005);
3098 rtl_writephy(tp, 0x05, 0x8b86);
3099 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3100 rtl_writephy(tp, 0x1f, 0x0000);
3102 /* Improve 2-pair detection performance */
3103 rtl_writephy(tp, 0x1f, 0x0005);
3104 rtl_writephy(tp, 0x05, 0x8b85);
3105 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3106 rtl_writephy(tp, 0x1f, 0x0000);
3109 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3111 rtl_apply_firmware(tp);
3113 /* For 4-corner performance improve */
3114 rtl_writephy(tp, 0x1f, 0x0005);
3115 rtl_writephy(tp, 0x05, 0x8b80);
3116 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3117 rtl_writephy(tp, 0x1f, 0x0000);
3119 /* PHY auto speed down */
3120 rtl_writephy(tp, 0x1f, 0x0007);
3121 rtl_writephy(tp, 0x1e, 0x002d);
3122 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3123 rtl_writephy(tp, 0x1f, 0x0000);
3124 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3126 /* Improve 10M EEE waveform */
3127 rtl_writephy(tp, 0x1f, 0x0005);
3128 rtl_writephy(tp, 0x05, 0x8b86);
3129 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3130 rtl_writephy(tp, 0x1f, 0x0000);
3133 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3135 static const struct phy_reg phy_reg_init[] = {
3142 rtl_writephy(tp, 0x1f, 0x0000);
3143 rtl_patchphy(tp, 0x11, 1 << 12);
3144 rtl_patchphy(tp, 0x19, 1 << 13);
3145 rtl_patchphy(tp, 0x10, 1 << 15);
3147 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3150 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3152 static const struct phy_reg phy_reg_init[] = {
3166 /* Disable ALDPS before ram code */
3167 rtl_writephy(tp, 0x1f, 0x0000);
3168 rtl_writephy(tp, 0x18, 0x0310);
3171 rtl_apply_firmware(tp);
3173 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3176 static void rtl_hw_phy_config(struct net_device *dev)
3178 struct rtl8169_private *tp = netdev_priv(dev);
3180 rtl8169_print_mac_version(tp);
3182 switch (tp->mac_version) {
3183 case RTL_GIGA_MAC_VER_01:
3185 case RTL_GIGA_MAC_VER_02:
3186 case RTL_GIGA_MAC_VER_03:
3187 rtl8169s_hw_phy_config(tp);
3189 case RTL_GIGA_MAC_VER_04:
3190 rtl8169sb_hw_phy_config(tp);
3192 case RTL_GIGA_MAC_VER_05:
3193 rtl8169scd_hw_phy_config(tp);
3195 case RTL_GIGA_MAC_VER_06:
3196 rtl8169sce_hw_phy_config(tp);
3198 case RTL_GIGA_MAC_VER_07:
3199 case RTL_GIGA_MAC_VER_08:
3200 case RTL_GIGA_MAC_VER_09:
3201 rtl8102e_hw_phy_config(tp);
3203 case RTL_GIGA_MAC_VER_11:
3204 rtl8168bb_hw_phy_config(tp);
3206 case RTL_GIGA_MAC_VER_12:
3207 rtl8168bef_hw_phy_config(tp);
3209 case RTL_GIGA_MAC_VER_17:
3210 rtl8168bef_hw_phy_config(tp);
3212 case RTL_GIGA_MAC_VER_18:
3213 rtl8168cp_1_hw_phy_config(tp);
3215 case RTL_GIGA_MAC_VER_19:
3216 rtl8168c_1_hw_phy_config(tp);
3218 case RTL_GIGA_MAC_VER_20:
3219 rtl8168c_2_hw_phy_config(tp);
3221 case RTL_GIGA_MAC_VER_21:
3222 rtl8168c_3_hw_phy_config(tp);
3224 case RTL_GIGA_MAC_VER_22:
3225 rtl8168c_4_hw_phy_config(tp);
3227 case RTL_GIGA_MAC_VER_23:
3228 case RTL_GIGA_MAC_VER_24:
3229 rtl8168cp_2_hw_phy_config(tp);
3231 case RTL_GIGA_MAC_VER_25:
3232 rtl8168d_1_hw_phy_config(tp);
3234 case RTL_GIGA_MAC_VER_26:
3235 rtl8168d_2_hw_phy_config(tp);
3237 case RTL_GIGA_MAC_VER_27:
3238 rtl8168d_3_hw_phy_config(tp);
3240 case RTL_GIGA_MAC_VER_28:
3241 rtl8168d_4_hw_phy_config(tp);
3243 case RTL_GIGA_MAC_VER_29:
3244 case RTL_GIGA_MAC_VER_30:
3245 rtl8105e_hw_phy_config(tp);
3247 case RTL_GIGA_MAC_VER_31:
3250 case RTL_GIGA_MAC_VER_32:
3251 case RTL_GIGA_MAC_VER_33:
3252 rtl8168e_1_hw_phy_config(tp);
3254 case RTL_GIGA_MAC_VER_34:
3255 rtl8168e_2_hw_phy_config(tp);
3257 case RTL_GIGA_MAC_VER_35:
3258 rtl8168f_1_hw_phy_config(tp);
3260 case RTL_GIGA_MAC_VER_36:
3261 rtl8168f_2_hw_phy_config(tp);
3269 static void rtl_phy_work(struct rtl8169_private *tp)
3271 struct timer_list *timer = &tp->timer;
3272 void __iomem *ioaddr = tp->mmio_addr;
3273 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3275 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3277 if (tp->phy_reset_pending(tp)) {
3279 * A busy loop could burn quite a few cycles on nowadays CPU.
3280 * Let's delay the execution of the timer for a few ticks.
3286 if (tp->link_ok(ioaddr))
3289 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3291 tp->phy_reset_enable(tp);
3294 mod_timer(timer, jiffies + timeout);
3297 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3299 if (!test_and_set_bit(flag, tp->wk.flags))
3300 schedule_work(&tp->wk.work);
3303 static void rtl8169_phy_timer(unsigned long __opaque)
3305 struct net_device *dev = (struct net_device *)__opaque;
3306 struct rtl8169_private *tp = netdev_priv(dev);
3308 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3311 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3312 void __iomem *ioaddr)
3315 pci_release_regions(pdev);
3316 pci_clear_mwi(pdev);
3317 pci_disable_device(pdev);
3321 static void rtl8169_phy_reset(struct net_device *dev,
3322 struct rtl8169_private *tp)
3326 tp->phy_reset_enable(tp);
3327 for (i = 0; i < 100; i++) {
3328 if (!tp->phy_reset_pending(tp))
3332 netif_err(tp, link, dev, "PHY reset failed\n");
3335 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3337 void __iomem *ioaddr = tp->mmio_addr;
3339 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3340 (RTL_R8(PHYstatus) & TBI_Enable);
3343 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3345 void __iomem *ioaddr = tp->mmio_addr;
3347 rtl_hw_phy_config(dev);
3349 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3350 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3354 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3356 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3357 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3359 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3360 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3362 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3363 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3366 rtl8169_phy_reset(dev, tp);
3368 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3369 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3370 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3371 (tp->mii.supports_gmii ?
3372 ADVERTISED_1000baseT_Half |
3373 ADVERTISED_1000baseT_Full : 0));
3375 if (rtl_tbi_enabled(tp))
3376 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3379 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3381 void __iomem *ioaddr = tp->mmio_addr;
3385 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3386 high = addr[4] | (addr[5] << 8);
3390 RTL_W8(Cfg9346, Cfg9346_Unlock);
3392 RTL_W32(MAC4, high);
3398 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3399 const struct exgmac_reg e[] = {
3400 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3401 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3402 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3403 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3407 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3410 RTL_W8(Cfg9346, Cfg9346_Lock);
3412 rtl_unlock_work(tp);
3415 static int rtl_set_mac_address(struct net_device *dev, void *p)
3417 struct rtl8169_private *tp = netdev_priv(dev);
3418 struct sockaddr *addr = p;
3420 if (!is_valid_ether_addr(addr->sa_data))
3421 return -EADDRNOTAVAIL;
3423 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3425 rtl_rar_set(tp, dev->dev_addr);
3430 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3432 struct rtl8169_private *tp = netdev_priv(dev);
3433 struct mii_ioctl_data *data = if_mii(ifr);
3435 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3438 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3439 struct mii_ioctl_data *data, int cmd)
3443 data->phy_id = 32; /* Internal PHY */
3447 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3451 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3457 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3462 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3464 if (tp->features & RTL_FEATURE_MSI) {
3465 pci_disable_msi(pdev);
3466 tp->features &= ~RTL_FEATURE_MSI;
3470 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3472 struct mdio_ops *ops = &tp->mdio_ops;
3474 switch (tp->mac_version) {
3475 case RTL_GIGA_MAC_VER_27:
3476 ops->write = r8168dp_1_mdio_write;
3477 ops->read = r8168dp_1_mdio_read;
3479 case RTL_GIGA_MAC_VER_28:
3480 case RTL_GIGA_MAC_VER_31:
3481 ops->write = r8168dp_2_mdio_write;
3482 ops->read = r8168dp_2_mdio_read;
3485 ops->write = r8169_mdio_write;
3486 ops->read = r8169_mdio_read;
3491 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3493 void __iomem *ioaddr = tp->mmio_addr;
3495 switch (tp->mac_version) {
3496 case RTL_GIGA_MAC_VER_29:
3497 case RTL_GIGA_MAC_VER_30:
3498 case RTL_GIGA_MAC_VER_32:
3499 case RTL_GIGA_MAC_VER_33:
3500 case RTL_GIGA_MAC_VER_34:
3501 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3502 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3509 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3511 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3514 rtl_writephy(tp, 0x1f, 0x0000);
3515 rtl_writephy(tp, MII_BMCR, 0x0000);
3517 rtl_wol_suspend_quirk(tp);
3522 static void r810x_phy_power_down(struct rtl8169_private *tp)
3524 rtl_writephy(tp, 0x1f, 0x0000);
3525 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3528 static void r810x_phy_power_up(struct rtl8169_private *tp)
3530 rtl_writephy(tp, 0x1f, 0x0000);
3531 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3534 static void r810x_pll_power_down(struct rtl8169_private *tp)
3536 if (rtl_wol_pll_power_down(tp))
3539 r810x_phy_power_down(tp);
3542 static void r810x_pll_power_up(struct rtl8169_private *tp)
3544 r810x_phy_power_up(tp);
3547 static void r8168_phy_power_up(struct rtl8169_private *tp)
3549 rtl_writephy(tp, 0x1f, 0x0000);
3550 switch (tp->mac_version) {
3551 case RTL_GIGA_MAC_VER_11:
3552 case RTL_GIGA_MAC_VER_12:
3553 case RTL_GIGA_MAC_VER_17:
3554 case RTL_GIGA_MAC_VER_18:
3555 case RTL_GIGA_MAC_VER_19:
3556 case RTL_GIGA_MAC_VER_20:
3557 case RTL_GIGA_MAC_VER_21:
3558 case RTL_GIGA_MAC_VER_22:
3559 case RTL_GIGA_MAC_VER_23:
3560 case RTL_GIGA_MAC_VER_24:
3561 case RTL_GIGA_MAC_VER_25:
3562 case RTL_GIGA_MAC_VER_26:
3563 case RTL_GIGA_MAC_VER_27:
3564 case RTL_GIGA_MAC_VER_28:
3565 case RTL_GIGA_MAC_VER_31:
3566 rtl_writephy(tp, 0x0e, 0x0000);
3571 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3574 static void r8168_phy_power_down(struct rtl8169_private *tp)
3576 rtl_writephy(tp, 0x1f, 0x0000);
3577 switch (tp->mac_version) {
3578 case RTL_GIGA_MAC_VER_32:
3579 case RTL_GIGA_MAC_VER_33:
3580 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3583 case RTL_GIGA_MAC_VER_11:
3584 case RTL_GIGA_MAC_VER_12:
3585 case RTL_GIGA_MAC_VER_17:
3586 case RTL_GIGA_MAC_VER_18:
3587 case RTL_GIGA_MAC_VER_19:
3588 case RTL_GIGA_MAC_VER_20:
3589 case RTL_GIGA_MAC_VER_21:
3590 case RTL_GIGA_MAC_VER_22:
3591 case RTL_GIGA_MAC_VER_23:
3592 case RTL_GIGA_MAC_VER_24:
3593 case RTL_GIGA_MAC_VER_25:
3594 case RTL_GIGA_MAC_VER_26:
3595 case RTL_GIGA_MAC_VER_27:
3596 case RTL_GIGA_MAC_VER_28:
3597 case RTL_GIGA_MAC_VER_31:
3598 rtl_writephy(tp, 0x0e, 0x0200);
3600 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3605 static void r8168_pll_power_down(struct rtl8169_private *tp)
3607 void __iomem *ioaddr = tp->mmio_addr;
3609 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3610 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3611 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3612 r8168dp_check_dash(tp)) {
3616 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3617 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3618 (RTL_R16(CPlusCmd) & ASF)) {
3622 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3623 tp->mac_version == RTL_GIGA_MAC_VER_33)
3624 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3626 if (rtl_wol_pll_power_down(tp))
3629 r8168_phy_power_down(tp);
3631 switch (tp->mac_version) {
3632 case RTL_GIGA_MAC_VER_25:
3633 case RTL_GIGA_MAC_VER_26:
3634 case RTL_GIGA_MAC_VER_27:
3635 case RTL_GIGA_MAC_VER_28:
3636 case RTL_GIGA_MAC_VER_31:
3637 case RTL_GIGA_MAC_VER_32:
3638 case RTL_GIGA_MAC_VER_33:
3639 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3644 static void r8168_pll_power_up(struct rtl8169_private *tp)
3646 void __iomem *ioaddr = tp->mmio_addr;
3648 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3649 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3650 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3651 r8168dp_check_dash(tp)) {
3655 switch (tp->mac_version) {
3656 case RTL_GIGA_MAC_VER_25:
3657 case RTL_GIGA_MAC_VER_26:
3658 case RTL_GIGA_MAC_VER_27:
3659 case RTL_GIGA_MAC_VER_28:
3660 case RTL_GIGA_MAC_VER_31:
3661 case RTL_GIGA_MAC_VER_32:
3662 case RTL_GIGA_MAC_VER_33:
3663 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3667 r8168_phy_power_up(tp);
3670 static void rtl_generic_op(struct rtl8169_private *tp,
3671 void (*op)(struct rtl8169_private *))
3677 static void rtl_pll_power_down(struct rtl8169_private *tp)
3679 rtl_generic_op(tp, tp->pll_power_ops.down);
3682 static void rtl_pll_power_up(struct rtl8169_private *tp)
3684 rtl_generic_op(tp, tp->pll_power_ops.up);
3687 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3689 struct pll_power_ops *ops = &tp->pll_power_ops;
3691 switch (tp->mac_version) {
3692 case RTL_GIGA_MAC_VER_07:
3693 case RTL_GIGA_MAC_VER_08:
3694 case RTL_GIGA_MAC_VER_09:
3695 case RTL_GIGA_MAC_VER_10:
3696 case RTL_GIGA_MAC_VER_16:
3697 case RTL_GIGA_MAC_VER_29:
3698 case RTL_GIGA_MAC_VER_30:
3699 ops->down = r810x_pll_power_down;
3700 ops->up = r810x_pll_power_up;
3703 case RTL_GIGA_MAC_VER_11:
3704 case RTL_GIGA_MAC_VER_12:
3705 case RTL_GIGA_MAC_VER_17:
3706 case RTL_GIGA_MAC_VER_18:
3707 case RTL_GIGA_MAC_VER_19:
3708 case RTL_GIGA_MAC_VER_20:
3709 case RTL_GIGA_MAC_VER_21:
3710 case RTL_GIGA_MAC_VER_22:
3711 case RTL_GIGA_MAC_VER_23:
3712 case RTL_GIGA_MAC_VER_24:
3713 case RTL_GIGA_MAC_VER_25:
3714 case RTL_GIGA_MAC_VER_26:
3715 case RTL_GIGA_MAC_VER_27:
3716 case RTL_GIGA_MAC_VER_28:
3717 case RTL_GIGA_MAC_VER_31:
3718 case RTL_GIGA_MAC_VER_32:
3719 case RTL_GIGA_MAC_VER_33:
3720 case RTL_GIGA_MAC_VER_34:
3721 case RTL_GIGA_MAC_VER_35:
3722 case RTL_GIGA_MAC_VER_36:
3723 ops->down = r8168_pll_power_down;
3724 ops->up = r8168_pll_power_up;
3734 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3736 void __iomem *ioaddr = tp->mmio_addr;
3738 switch (tp->mac_version) {
3739 case RTL_GIGA_MAC_VER_01:
3740 case RTL_GIGA_MAC_VER_02:
3741 case RTL_GIGA_MAC_VER_03:
3742 case RTL_GIGA_MAC_VER_04:
3743 case RTL_GIGA_MAC_VER_05:
3744 case RTL_GIGA_MAC_VER_06:
3745 case RTL_GIGA_MAC_VER_10:
3746 case RTL_GIGA_MAC_VER_11:
3747 case RTL_GIGA_MAC_VER_12:
3748 case RTL_GIGA_MAC_VER_13:
3749 case RTL_GIGA_MAC_VER_14:
3750 case RTL_GIGA_MAC_VER_15:
3751 case RTL_GIGA_MAC_VER_16:
3752 case RTL_GIGA_MAC_VER_17:
3753 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3755 case RTL_GIGA_MAC_VER_18:
3756 case RTL_GIGA_MAC_VER_19:
3757 case RTL_GIGA_MAC_VER_20:
3758 case RTL_GIGA_MAC_VER_21:
3759 case RTL_GIGA_MAC_VER_22:
3760 case RTL_GIGA_MAC_VER_23:
3761 case RTL_GIGA_MAC_VER_24:
3762 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3765 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3770 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3772 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3775 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3777 void __iomem *ioaddr = tp->mmio_addr;
3779 RTL_W8(Cfg9346, Cfg9346_Unlock);
3780 rtl_generic_op(tp, tp->jumbo_ops.enable);
3781 RTL_W8(Cfg9346, Cfg9346_Lock);
3784 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3786 void __iomem *ioaddr = tp->mmio_addr;
3788 RTL_W8(Cfg9346, Cfg9346_Unlock);
3789 rtl_generic_op(tp, tp->jumbo_ops.disable);
3790 RTL_W8(Cfg9346, Cfg9346_Lock);
3793 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3795 void __iomem *ioaddr = tp->mmio_addr;
3797 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3798 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3799 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3802 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3804 void __iomem *ioaddr = tp->mmio_addr;
3806 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3807 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3808 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3811 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3813 void __iomem *ioaddr = tp->mmio_addr;
3815 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3818 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3820 void __iomem *ioaddr = tp->mmio_addr;
3822 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3825 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3827 void __iomem *ioaddr = tp->mmio_addr;
3829 RTL_W8(MaxTxPacketSize, 0x3f);
3830 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3831 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3832 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3835 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3837 void __iomem *ioaddr = tp->mmio_addr;
3839 RTL_W8(MaxTxPacketSize, 0x0c);
3840 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3841 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3842 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3845 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3847 rtl_tx_performance_tweak(tp->pci_dev,
3848 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3851 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3853 rtl_tx_performance_tweak(tp->pci_dev,
3854 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3857 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3859 void __iomem *ioaddr = tp->mmio_addr;
3861 r8168b_0_hw_jumbo_enable(tp);
3863 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3866 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3868 void __iomem *ioaddr = tp->mmio_addr;
3870 r8168b_0_hw_jumbo_disable(tp);
3872 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3875 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3877 struct jumbo_ops *ops = &tp->jumbo_ops;
3879 switch (tp->mac_version) {
3880 case RTL_GIGA_MAC_VER_11:
3881 ops->disable = r8168b_0_hw_jumbo_disable;
3882 ops->enable = r8168b_0_hw_jumbo_enable;
3884 case RTL_GIGA_MAC_VER_12:
3885 case RTL_GIGA_MAC_VER_17:
3886 ops->disable = r8168b_1_hw_jumbo_disable;
3887 ops->enable = r8168b_1_hw_jumbo_enable;
3889 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3890 case RTL_GIGA_MAC_VER_19:
3891 case RTL_GIGA_MAC_VER_20:
3892 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3893 case RTL_GIGA_MAC_VER_22:
3894 case RTL_GIGA_MAC_VER_23:
3895 case RTL_GIGA_MAC_VER_24:
3896 case RTL_GIGA_MAC_VER_25:
3897 case RTL_GIGA_MAC_VER_26:
3898 ops->disable = r8168c_hw_jumbo_disable;
3899 ops->enable = r8168c_hw_jumbo_enable;
3901 case RTL_GIGA_MAC_VER_27:
3902 case RTL_GIGA_MAC_VER_28:
3903 ops->disable = r8168dp_hw_jumbo_disable;
3904 ops->enable = r8168dp_hw_jumbo_enable;
3906 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3907 case RTL_GIGA_MAC_VER_32:
3908 case RTL_GIGA_MAC_VER_33:
3909 case RTL_GIGA_MAC_VER_34:
3910 ops->disable = r8168e_hw_jumbo_disable;
3911 ops->enable = r8168e_hw_jumbo_enable;
3915 * No action needed for jumbo frames with 8169.
3916 * No jumbo for 810x at all.
3919 ops->disable = NULL;
3925 static void rtl_hw_reset(struct rtl8169_private *tp)
3927 void __iomem *ioaddr = tp->mmio_addr;
3930 /* Soft reset the chip. */
3931 RTL_W8(ChipCmd, CmdReset);
3933 /* Check that the chip has finished the reset. */
3934 for (i = 0; i < 100; i++) {
3935 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3941 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3943 struct rtl_fw *rtl_fw;
3947 name = rtl_lookup_firmware_name(tp);
3949 goto out_no_firmware;
3951 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3955 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3959 rc = rtl_check_firmware(tp, rtl_fw);
3961 goto err_release_firmware;
3963 tp->rtl_fw = rtl_fw;
3967 err_release_firmware:
3968 release_firmware(rtl_fw->fw);
3972 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3979 static void rtl_request_firmware(struct rtl8169_private *tp)
3981 if (IS_ERR(tp->rtl_fw))
3982 rtl_request_uncached_firmware(tp);
3985 static void rtl_rx_close(struct rtl8169_private *tp)
3987 void __iomem *ioaddr = tp->mmio_addr;
3989 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3992 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3994 void __iomem *ioaddr = tp->mmio_addr;
3996 /* Disable interrupts */
3997 rtl8169_irq_mask_and_ack(tp);
4001 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4002 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4003 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4004 while (RTL_R8(TxPoll) & NPQ)
4006 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4007 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4008 tp->mac_version == RTL_GIGA_MAC_VER_36) {
4009 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4010 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4013 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4020 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4022 void __iomem *ioaddr = tp->mmio_addr;
4024 /* Set DMA burst size and Interframe Gap Time */
4025 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4026 (InterFrameGap << TxInterFrameGapShift));
4029 static void rtl_hw_start(struct net_device *dev)
4031 struct rtl8169_private *tp = netdev_priv(dev);
4035 rtl_irq_enable_all(tp);
4038 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4039 void __iomem *ioaddr)
4042 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4043 * register to be written before TxDescAddrLow to work.
4044 * Switching from MMIO to I/O access fixes the issue as well.
4046 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4047 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4048 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4049 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4052 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4056 cmd = RTL_R16(CPlusCmd);
4057 RTL_W16(CPlusCmd, cmd);
4061 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4063 /* Low hurts. Let's disable the filtering. */
4064 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4067 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4069 static const struct rtl_cfg2_info {
4074 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4075 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4076 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4077 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4079 const struct rtl_cfg2_info *p = cfg2_info;
4083 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4084 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4085 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4086 RTL_W32(0x7c, p->val);
4092 static void rtl_set_rx_mode(struct net_device *dev)
4094 struct rtl8169_private *tp = netdev_priv(dev);
4095 void __iomem *ioaddr = tp->mmio_addr;
4096 u32 mc_filter[2]; /* Multicast hash filter */
4100 if (dev->flags & IFF_PROMISC) {
4101 /* Unconditionally log net taps. */
4102 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4104 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4106 mc_filter[1] = mc_filter[0] = 0xffffffff;
4107 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4108 (dev->flags & IFF_ALLMULTI)) {
4109 /* Too many to filter perfectly -- accept all multicasts. */
4110 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4111 mc_filter[1] = mc_filter[0] = 0xffffffff;
4113 struct netdev_hw_addr *ha;
4115 rx_mode = AcceptBroadcast | AcceptMyPhys;
4116 mc_filter[1] = mc_filter[0] = 0;
4117 netdev_for_each_mc_addr(ha, dev) {
4118 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4119 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4120 rx_mode |= AcceptMulticast;
4124 if (dev->features & NETIF_F_RXALL)
4125 rx_mode |= (AcceptErr | AcceptRunt);
4127 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4129 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4130 u32 data = mc_filter[0];
4132 mc_filter[0] = swab32(mc_filter[1]);
4133 mc_filter[1] = swab32(data);
4136 RTL_W32(MAR0 + 4, mc_filter[1]);
4137 RTL_W32(MAR0 + 0, mc_filter[0]);
4139 RTL_W32(RxConfig, tmp);
4142 static void rtl_hw_start_8169(struct net_device *dev)
4144 struct rtl8169_private *tp = netdev_priv(dev);
4145 void __iomem *ioaddr = tp->mmio_addr;
4146 struct pci_dev *pdev = tp->pci_dev;
4148 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4149 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4150 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4153 RTL_W8(Cfg9346, Cfg9346_Unlock);
4154 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4155 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4156 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4157 tp->mac_version == RTL_GIGA_MAC_VER_04)
4158 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4162 RTL_W8(EarlyTxThres, NoEarlyTx);
4164 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4166 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4167 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4168 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4169 tp->mac_version == RTL_GIGA_MAC_VER_04)
4170 rtl_set_rx_tx_config_registers(tp);
4172 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4174 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4175 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4176 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4177 "Bit-3 and bit-14 MUST be 1\n");
4178 tp->cp_cmd |= (1 << 14);
4181 RTL_W16(CPlusCmd, tp->cp_cmd);
4183 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4186 * Undocumented corner. Supposedly:
4187 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4189 RTL_W16(IntrMitigate, 0x0000);
4191 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4193 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4194 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4195 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4196 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4197 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4198 rtl_set_rx_tx_config_registers(tp);
4201 RTL_W8(Cfg9346, Cfg9346_Lock);
4203 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4206 RTL_W32(RxMissed, 0);
4208 rtl_set_rx_mode(dev);
4210 /* no early-rx interrupts */
4211 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4214 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4218 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4219 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4222 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4224 rtl_csi_access_enable(ioaddr, 0x17000000);
4227 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4229 rtl_csi_access_enable(ioaddr, 0x27000000);
4233 unsigned int offset;
4238 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4243 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4244 rtl_ephy_write(ioaddr, e->offset, w);
4249 static void rtl_disable_clock_request(struct pci_dev *pdev)
4251 int cap = pci_pcie_cap(pdev);
4256 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4257 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4258 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4262 static void rtl_enable_clock_request(struct pci_dev *pdev)
4264 int cap = pci_pcie_cap(pdev);
4269 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4270 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4271 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4275 #define R8168_CPCMD_QUIRK_MASK (\
4286 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4288 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4290 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4292 rtl_tx_performance_tweak(pdev,
4293 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4296 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4298 rtl_hw_start_8168bb(ioaddr, pdev);
4300 RTL_W8(MaxTxPacketSize, TxPacketMax);
4302 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4305 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4307 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4309 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4311 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4313 rtl_disable_clock_request(pdev);
4315 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4318 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4320 static const struct ephy_info e_info_8168cp[] = {
4321 { 0x01, 0, 0x0001 },
4322 { 0x02, 0x0800, 0x1000 },
4323 { 0x03, 0, 0x0042 },
4324 { 0x06, 0x0080, 0x0000 },
4328 rtl_csi_access_enable_2(ioaddr);
4330 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4332 __rtl_hw_start_8168cp(ioaddr, pdev);
4335 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4337 rtl_csi_access_enable_2(ioaddr);
4339 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4341 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4343 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4346 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4348 rtl_csi_access_enable_2(ioaddr);
4350 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4353 RTL_W8(DBG_REG, 0x20);
4355 RTL_W8(MaxTxPacketSize, TxPacketMax);
4357 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4359 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4362 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4364 static const struct ephy_info e_info_8168c_1[] = {
4365 { 0x02, 0x0800, 0x1000 },
4366 { 0x03, 0, 0x0002 },
4367 { 0x06, 0x0080, 0x0000 }
4370 rtl_csi_access_enable_2(ioaddr);
4372 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4374 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4376 __rtl_hw_start_8168cp(ioaddr, pdev);
4379 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4381 static const struct ephy_info e_info_8168c_2[] = {
4382 { 0x01, 0, 0x0001 },
4383 { 0x03, 0x0400, 0x0220 }
4386 rtl_csi_access_enable_2(ioaddr);
4388 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4390 __rtl_hw_start_8168cp(ioaddr, pdev);
4393 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4395 rtl_hw_start_8168c_2(ioaddr, pdev);
4398 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4400 rtl_csi_access_enable_2(ioaddr);
4402 __rtl_hw_start_8168cp(ioaddr, pdev);
4405 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4407 rtl_csi_access_enable_2(ioaddr);
4409 rtl_disable_clock_request(pdev);
4411 RTL_W8(MaxTxPacketSize, TxPacketMax);
4413 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4415 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4418 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4420 rtl_csi_access_enable_1(ioaddr);
4422 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4424 RTL_W8(MaxTxPacketSize, TxPacketMax);
4426 rtl_disable_clock_request(pdev);
4429 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4431 static const struct ephy_info e_info_8168d_4[] = {
4433 { 0x19, 0x20, 0x50 },
4438 rtl_csi_access_enable_1(ioaddr);
4440 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4442 RTL_W8(MaxTxPacketSize, TxPacketMax);
4444 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4445 const struct ephy_info *e = e_info_8168d_4 + i;
4448 w = rtl_ephy_read(ioaddr, e->offset);
4449 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4452 rtl_enable_clock_request(pdev);
4455 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4457 static const struct ephy_info e_info_8168e_1[] = {
4458 { 0x00, 0x0200, 0x0100 },
4459 { 0x00, 0x0000, 0x0004 },
4460 { 0x06, 0x0002, 0x0001 },
4461 { 0x06, 0x0000, 0x0030 },
4462 { 0x07, 0x0000, 0x2000 },
4463 { 0x00, 0x0000, 0x0020 },
4464 { 0x03, 0x5800, 0x2000 },
4465 { 0x03, 0x0000, 0x0001 },
4466 { 0x01, 0x0800, 0x1000 },
4467 { 0x07, 0x0000, 0x4000 },
4468 { 0x1e, 0x0000, 0x2000 },
4469 { 0x19, 0xffff, 0xfe6c },
4470 { 0x0a, 0x0000, 0x0040 }
4473 rtl_csi_access_enable_2(ioaddr);
4475 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4477 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4479 RTL_W8(MaxTxPacketSize, TxPacketMax);
4481 rtl_disable_clock_request(pdev);
4483 /* Reset tx FIFO pointer */
4484 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4485 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4487 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4490 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4492 static const struct ephy_info e_info_8168e_2[] = {
4493 { 0x09, 0x0000, 0x0080 },
4494 { 0x19, 0x0000, 0x0224 }
4497 rtl_csi_access_enable_1(ioaddr);
4499 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4501 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4503 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4504 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4505 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4506 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4507 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4508 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4509 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4510 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4513 RTL_W8(MaxTxPacketSize, EarlySize);
4515 rtl_disable_clock_request(pdev);
4517 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4518 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4520 /* Adjust EEE LED frequency */
4521 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4523 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4524 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4525 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4528 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4530 static const struct ephy_info e_info_8168f_1[] = {
4531 { 0x06, 0x00c0, 0x0020 },
4532 { 0x08, 0x0001, 0x0002 },
4533 { 0x09, 0x0000, 0x0080 },
4534 { 0x19, 0x0000, 0x0224 }
4537 rtl_csi_access_enable_1(ioaddr);
4539 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4541 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4543 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4544 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4545 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4546 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4547 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4548 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4549 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4550 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4551 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4552 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4553 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4556 RTL_W8(MaxTxPacketSize, EarlySize);
4558 rtl_disable_clock_request(pdev);
4560 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4561 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4563 /* Adjust EEE LED frequency */
4564 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4566 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4567 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4568 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4571 static void rtl_hw_start_8168(struct net_device *dev)
4573 struct rtl8169_private *tp = netdev_priv(dev);
4574 void __iomem *ioaddr = tp->mmio_addr;
4575 struct pci_dev *pdev = tp->pci_dev;
4577 RTL_W8(Cfg9346, Cfg9346_Unlock);
4579 RTL_W8(MaxTxPacketSize, TxPacketMax);
4581 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4583 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4585 RTL_W16(CPlusCmd, tp->cp_cmd);
4587 RTL_W16(IntrMitigate, 0x5151);
4589 /* Work around for RxFIFO overflow. */
4590 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4591 tp->event_slow |= RxFIFOOver | PCSTimeout;
4592 tp->event_slow &= ~RxOverflow;
4595 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4597 rtl_set_rx_mode(dev);
4599 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4600 (InterFrameGap << TxInterFrameGapShift));
4604 switch (tp->mac_version) {
4605 case RTL_GIGA_MAC_VER_11:
4606 rtl_hw_start_8168bb(ioaddr, pdev);
4609 case RTL_GIGA_MAC_VER_12:
4610 case RTL_GIGA_MAC_VER_17:
4611 rtl_hw_start_8168bef(ioaddr, pdev);
4614 case RTL_GIGA_MAC_VER_18:
4615 rtl_hw_start_8168cp_1(ioaddr, pdev);
4618 case RTL_GIGA_MAC_VER_19:
4619 rtl_hw_start_8168c_1(ioaddr, pdev);
4622 case RTL_GIGA_MAC_VER_20:
4623 rtl_hw_start_8168c_2(ioaddr, pdev);
4626 case RTL_GIGA_MAC_VER_21:
4627 rtl_hw_start_8168c_3(ioaddr, pdev);
4630 case RTL_GIGA_MAC_VER_22:
4631 rtl_hw_start_8168c_4(ioaddr, pdev);
4634 case RTL_GIGA_MAC_VER_23:
4635 rtl_hw_start_8168cp_2(ioaddr, pdev);
4638 case RTL_GIGA_MAC_VER_24:
4639 rtl_hw_start_8168cp_3(ioaddr, pdev);
4642 case RTL_GIGA_MAC_VER_25:
4643 case RTL_GIGA_MAC_VER_26:
4644 case RTL_GIGA_MAC_VER_27:
4645 rtl_hw_start_8168d(ioaddr, pdev);
4648 case RTL_GIGA_MAC_VER_28:
4649 rtl_hw_start_8168d_4(ioaddr, pdev);
4652 case RTL_GIGA_MAC_VER_31:
4653 rtl_hw_start_8168dp(ioaddr, pdev);
4656 case RTL_GIGA_MAC_VER_32:
4657 case RTL_GIGA_MAC_VER_33:
4658 rtl_hw_start_8168e_1(ioaddr, pdev);
4660 case RTL_GIGA_MAC_VER_34:
4661 rtl_hw_start_8168e_2(ioaddr, pdev);
4664 case RTL_GIGA_MAC_VER_35:
4665 case RTL_GIGA_MAC_VER_36:
4666 rtl_hw_start_8168f_1(ioaddr, pdev);
4670 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4671 dev->name, tp->mac_version);
4675 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4677 RTL_W8(Cfg9346, Cfg9346_Lock);
4679 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4682 #define R810X_CPCMD_QUIRK_MASK (\
4693 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4695 static const struct ephy_info e_info_8102e_1[] = {
4696 { 0x01, 0, 0x6e65 },
4697 { 0x02, 0, 0x091f },
4698 { 0x03, 0, 0xc2f9 },
4699 { 0x06, 0, 0xafb5 },
4700 { 0x07, 0, 0x0e00 },
4701 { 0x19, 0, 0xec80 },
4702 { 0x01, 0, 0x2e65 },
4707 rtl_csi_access_enable_2(ioaddr);
4709 RTL_W8(DBG_REG, FIX_NAK_1);
4711 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4714 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4715 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4717 cfg1 = RTL_R8(Config1);
4718 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4719 RTL_W8(Config1, cfg1 & ~LEDS0);
4721 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4724 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4726 rtl_csi_access_enable_2(ioaddr);
4728 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4730 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4731 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4734 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4736 rtl_hw_start_8102e_2(ioaddr, pdev);
4738 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4741 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4743 static const struct ephy_info e_info_8105e_1[] = {
4744 { 0x07, 0, 0x4000 },
4745 { 0x19, 0, 0x0200 },
4746 { 0x19, 0, 0x0020 },
4747 { 0x1e, 0, 0x2000 },
4748 { 0x03, 0, 0x0001 },
4749 { 0x19, 0, 0x0100 },
4750 { 0x19, 0, 0x0004 },
4754 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4755 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4757 /* Disable Early Tally Counter */
4758 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4760 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4761 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4763 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4766 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4768 rtl_hw_start_8105e_1(ioaddr, pdev);
4769 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4772 static void rtl_hw_start_8101(struct net_device *dev)
4774 struct rtl8169_private *tp = netdev_priv(dev);
4775 void __iomem *ioaddr = tp->mmio_addr;
4776 struct pci_dev *pdev = tp->pci_dev;
4778 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4779 tp->event_slow &= ~RxFIFOOver;
4781 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4782 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4783 int cap = pci_pcie_cap(pdev);
4786 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4787 PCI_EXP_DEVCTL_NOSNOOP_EN);
4791 RTL_W8(Cfg9346, Cfg9346_Unlock);
4793 switch (tp->mac_version) {
4794 case RTL_GIGA_MAC_VER_07:
4795 rtl_hw_start_8102e_1(ioaddr, pdev);
4798 case RTL_GIGA_MAC_VER_08:
4799 rtl_hw_start_8102e_3(ioaddr, pdev);
4802 case RTL_GIGA_MAC_VER_09:
4803 rtl_hw_start_8102e_2(ioaddr, pdev);
4806 case RTL_GIGA_MAC_VER_29:
4807 rtl_hw_start_8105e_1(ioaddr, pdev);
4809 case RTL_GIGA_MAC_VER_30:
4810 rtl_hw_start_8105e_2(ioaddr, pdev);
4814 RTL_W8(Cfg9346, Cfg9346_Lock);
4816 RTL_W8(MaxTxPacketSize, TxPacketMax);
4818 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4820 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4821 RTL_W16(CPlusCmd, tp->cp_cmd);
4823 RTL_W16(IntrMitigate, 0x0000);
4825 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4827 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4828 rtl_set_rx_tx_config_registers(tp);
4832 rtl_set_rx_mode(dev);
4834 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4837 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4839 struct rtl8169_private *tp = netdev_priv(dev);
4841 if (new_mtu < ETH_ZLEN ||
4842 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4845 if (new_mtu > ETH_DATA_LEN)
4846 rtl_hw_jumbo_enable(tp);
4848 rtl_hw_jumbo_disable(tp);
4851 netdev_update_features(dev);
4856 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4858 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4859 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4862 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4863 void **data_buff, struct RxDesc *desc)
4865 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4870 rtl8169_make_unusable_by_asic(desc);
4873 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4875 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4877 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4880 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4883 desc->addr = cpu_to_le64(mapping);
4885 rtl8169_mark_to_asic(desc, rx_buf_sz);
4888 static inline void *rtl8169_align(void *data)
4890 return (void *)ALIGN((long)data, 16);
4893 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4894 struct RxDesc *desc)
4898 struct device *d = &tp->pci_dev->dev;
4899 struct net_device *dev = tp->dev;
4900 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4902 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4906 if (rtl8169_align(data) != data) {
4908 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4913 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4915 if (unlikely(dma_mapping_error(d, mapping))) {
4916 if (net_ratelimit())
4917 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4921 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4929 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4933 for (i = 0; i < NUM_RX_DESC; i++) {
4934 if (tp->Rx_databuff[i]) {
4935 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4936 tp->RxDescArray + i);
4941 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4943 desc->opts1 |= cpu_to_le32(RingEnd);
4946 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4950 for (i = 0; i < NUM_RX_DESC; i++) {
4953 if (tp->Rx_databuff[i])
4956 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4958 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4961 tp->Rx_databuff[i] = data;
4964 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4968 rtl8169_rx_clear(tp);
4972 static int rtl8169_init_ring(struct net_device *dev)
4974 struct rtl8169_private *tp = netdev_priv(dev);
4976 rtl8169_init_ring_indexes(tp);
4978 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4979 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4981 return rtl8169_rx_fill(tp);
4984 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4985 struct TxDesc *desc)
4987 unsigned int len = tx_skb->len;
4989 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4997 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5002 for (i = 0; i < n; i++) {
5003 unsigned int entry = (start + i) % NUM_TX_DESC;
5004 struct ring_info *tx_skb = tp->tx_skb + entry;
5005 unsigned int len = tx_skb->len;
5008 struct sk_buff *skb = tx_skb->skb;
5010 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5011 tp->TxDescArray + entry);
5013 tp->dev->stats.tx_dropped++;
5021 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5023 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5024 tp->cur_tx = tp->dirty_tx = 0;
5025 netdev_reset_queue(tp->dev);
5028 static void rtl_reset_work(struct rtl8169_private *tp)
5030 struct net_device *dev = tp->dev;
5033 napi_disable(&tp->napi);
5034 netif_stop_queue(dev);
5035 synchronize_sched();
5037 rtl8169_hw_reset(tp);
5039 for (i = 0; i < NUM_RX_DESC; i++)
5040 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5042 rtl8169_tx_clear(tp);
5043 rtl8169_init_ring_indexes(tp);
5045 napi_enable(&tp->napi);
5047 netif_wake_queue(dev);
5048 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5051 static void rtl8169_tx_timeout(struct net_device *dev)
5053 struct rtl8169_private *tp = netdev_priv(dev);
5055 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5058 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5061 struct skb_shared_info *info = skb_shinfo(skb);
5062 unsigned int cur_frag, entry;
5063 struct TxDesc * uninitialized_var(txd);
5064 struct device *d = &tp->pci_dev->dev;
5067 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5068 const skb_frag_t *frag = info->frags + cur_frag;
5073 entry = (entry + 1) % NUM_TX_DESC;
5075 txd = tp->TxDescArray + entry;
5076 len = skb_frag_size(frag);
5077 addr = skb_frag_address(frag);
5078 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5079 if (unlikely(dma_mapping_error(d, mapping))) {
5080 if (net_ratelimit())
5081 netif_err(tp, drv, tp->dev,
5082 "Failed to map TX fragments DMA!\n");
5086 /* Anti gcc 2.95.3 bugware (sic) */
5087 status = opts[0] | len |
5088 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5090 txd->opts1 = cpu_to_le32(status);
5091 txd->opts2 = cpu_to_le32(opts[1]);
5092 txd->addr = cpu_to_le64(mapping);
5094 tp->tx_skb[entry].len = len;
5098 tp->tx_skb[entry].skb = skb;
5099 txd->opts1 |= cpu_to_le32(LastFrag);
5105 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5109 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5110 struct sk_buff *skb, u32 *opts)
5112 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5113 u32 mss = skb_shinfo(skb)->gso_size;
5114 int offset = info->opts_offset;
5118 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5119 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5120 const struct iphdr *ip = ip_hdr(skb);
5122 if (ip->protocol == IPPROTO_TCP)
5123 opts[offset] |= info->checksum.tcp;
5124 else if (ip->protocol == IPPROTO_UDP)
5125 opts[offset] |= info->checksum.udp;
5131 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5132 struct net_device *dev)
5134 struct rtl8169_private *tp = netdev_priv(dev);
5135 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5136 struct TxDesc *txd = tp->TxDescArray + entry;
5137 void __iomem *ioaddr = tp->mmio_addr;
5138 struct device *d = &tp->pci_dev->dev;
5144 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5145 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5149 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5152 len = skb_headlen(skb);
5153 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5154 if (unlikely(dma_mapping_error(d, mapping))) {
5155 if (net_ratelimit())
5156 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5160 tp->tx_skb[entry].len = len;
5161 txd->addr = cpu_to_le64(mapping);
5163 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5166 rtl8169_tso_csum(tp, skb, opts);
5168 frags = rtl8169_xmit_frags(tp, skb, opts);
5172 opts[0] |= FirstFrag;
5174 opts[0] |= FirstFrag | LastFrag;
5175 tp->tx_skb[entry].skb = skb;
5178 txd->opts2 = cpu_to_le32(opts[1]);
5180 netdev_sent_queue(dev, skb->len);
5182 skb_tx_timestamp(skb);
5186 /* Anti gcc 2.95.3 bugware (sic) */
5187 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5188 txd->opts1 = cpu_to_le32(status);
5190 tp->cur_tx += frags + 1;
5194 RTL_W8(TxPoll, NPQ);
5198 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5199 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5200 * not miss a ring update when it notices a stopped queue.
5203 netif_stop_queue(dev);
5204 /* Sync with rtl_tx:
5205 * - publish queue status and cur_tx ring index (write barrier)
5206 * - refresh dirty_tx ring index (read barrier).
5207 * May the current thread have a pessimistic view of the ring
5208 * status and forget to wake up queue, a racing rtl_tx thread
5212 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5213 netif_wake_queue(dev);
5216 return NETDEV_TX_OK;
5219 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5222 dev->stats.tx_dropped++;
5223 return NETDEV_TX_OK;
5226 netif_stop_queue(dev);
5227 dev->stats.tx_dropped++;
5228 return NETDEV_TX_BUSY;
5231 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5233 struct rtl8169_private *tp = netdev_priv(dev);
5234 struct pci_dev *pdev = tp->pci_dev;
5235 u16 pci_status, pci_cmd;
5237 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5238 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5240 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5241 pci_cmd, pci_status);
5244 * The recovery sequence below admits a very elaborated explanation:
5245 * - it seems to work;
5246 * - I did not see what else could be done;
5247 * - it makes iop3xx happy.
5249 * Feel free to adjust to your needs.
5251 if (pdev->broken_parity_status)
5252 pci_cmd &= ~PCI_COMMAND_PARITY;
5254 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5256 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5258 pci_write_config_word(pdev, PCI_STATUS,
5259 pci_status & (PCI_STATUS_DETECTED_PARITY |
5260 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5261 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5263 /* The infamous DAC f*ckup only happens at boot time */
5264 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5265 void __iomem *ioaddr = tp->mmio_addr;
5267 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5268 tp->cp_cmd &= ~PCIDAC;
5269 RTL_W16(CPlusCmd, tp->cp_cmd);
5270 dev->features &= ~NETIF_F_HIGHDMA;
5273 rtl8169_hw_reset(tp);
5275 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5283 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5285 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5286 unsigned int dirty_tx, tx_left;
5287 struct rtl_txc txc = { 0, 0 };
5289 dirty_tx = tp->dirty_tx;
5291 tx_left = tp->cur_tx - dirty_tx;
5293 while (tx_left > 0) {
5294 unsigned int entry = dirty_tx % NUM_TX_DESC;
5295 struct ring_info *tx_skb = tp->tx_skb + entry;
5299 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5300 if (status & DescOwn)
5303 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5304 tp->TxDescArray + entry);
5305 if (status & LastFrag) {
5306 struct sk_buff *skb = tx_skb->skb;
5309 txc.bytes += skb->len;
5317 u64_stats_update_begin(&tx_stats->syncp);
5318 tx_stats->packets += txc.packets;
5319 tx_stats->bytes += txc.bytes;
5320 u64_stats_update_end(&tx_stats->syncp);
5322 netdev_completed_queue(dev, txc.packets, txc.bytes);
5324 if (tp->dirty_tx != dirty_tx) {
5325 tp->dirty_tx = dirty_tx;
5326 /* Sync with rtl8169_start_xmit:
5327 * - publish dirty_tx ring index (write barrier)
5328 * - refresh cur_tx ring index and queue status (read barrier)
5329 * May the current thread miss the stopped queue condition,
5330 * a racing xmit thread can only have a right view of the
5334 if (netif_queue_stopped(dev) &&
5335 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5336 netif_wake_queue(dev);
5339 * 8168 hack: TxPoll requests are lost when the Tx packets are
5340 * too close. Let's kick an extra TxPoll request when a burst
5341 * of start_xmit activity is detected (if it is not detected,
5342 * it is slow enough). -- FR
5344 if (tp->cur_tx != dirty_tx) {
5345 void __iomem *ioaddr = tp->mmio_addr;
5347 RTL_W8(TxPoll, NPQ);
5352 static inline int rtl8169_fragmented_frame(u32 status)
5354 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5357 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5359 u32 status = opts1 & RxProtoMask;
5361 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5362 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5363 skb->ip_summed = CHECKSUM_UNNECESSARY;
5365 skb_checksum_none_assert(skb);
5368 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5369 struct rtl8169_private *tp,
5373 struct sk_buff *skb;
5374 struct device *d = &tp->pci_dev->dev;
5376 data = rtl8169_align(data);
5377 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5379 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5381 memcpy(skb->data, data, pkt_size);
5382 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5387 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5389 unsigned int cur_rx, rx_left;
5392 cur_rx = tp->cur_rx;
5393 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5394 rx_left = min(rx_left, budget);
5396 for (; rx_left > 0; rx_left--, cur_rx++) {
5397 unsigned int entry = cur_rx % NUM_RX_DESC;
5398 struct RxDesc *desc = tp->RxDescArray + entry;
5402 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5404 if (status & DescOwn)
5406 if (unlikely(status & RxRES)) {
5407 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5409 dev->stats.rx_errors++;
5410 if (status & (RxRWT | RxRUNT))
5411 dev->stats.rx_length_errors++;
5413 dev->stats.rx_crc_errors++;
5414 if (status & RxFOVF) {
5415 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5416 dev->stats.rx_fifo_errors++;
5418 if ((status & (RxRUNT | RxCRC)) &&
5419 !(status & (RxRWT | RxFOVF)) &&
5420 (dev->features & NETIF_F_RXALL))
5423 rtl8169_mark_to_asic(desc, rx_buf_sz);
5425 struct sk_buff *skb;
5430 addr = le64_to_cpu(desc->addr);
5431 if (likely(!(dev->features & NETIF_F_RXFCS)))
5432 pkt_size = (status & 0x00003fff) - 4;
5434 pkt_size = status & 0x00003fff;
5437 * The driver does not support incoming fragmented
5438 * frames. They are seen as a symptom of over-mtu
5441 if (unlikely(rtl8169_fragmented_frame(status))) {
5442 dev->stats.rx_dropped++;
5443 dev->stats.rx_length_errors++;
5444 rtl8169_mark_to_asic(desc, rx_buf_sz);
5448 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5449 tp, pkt_size, addr);
5450 rtl8169_mark_to_asic(desc, rx_buf_sz);
5452 dev->stats.rx_dropped++;
5456 rtl8169_rx_csum(skb, status);
5457 skb_put(skb, pkt_size);
5458 skb->protocol = eth_type_trans(skb, dev);
5460 rtl8169_rx_vlan_tag(desc, skb);
5462 napi_gro_receive(&tp->napi, skb);
5464 u64_stats_update_begin(&tp->rx_stats.syncp);
5465 tp->rx_stats.packets++;
5466 tp->rx_stats.bytes += pkt_size;
5467 u64_stats_update_end(&tp->rx_stats.syncp);
5470 /* Work around for AMD plateform. */
5471 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5472 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5478 count = cur_rx - tp->cur_rx;
5479 tp->cur_rx = cur_rx;
5481 tp->dirty_rx += count;
5486 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5488 struct net_device *dev = dev_instance;
5489 struct rtl8169_private *tp = netdev_priv(dev);
5493 status = rtl_get_events(tp);
5494 if (status && status != 0xffff) {
5495 status &= RTL_EVENT_NAPI | tp->event_slow;
5499 rtl_irq_disable(tp);
5500 napi_schedule(&tp->napi);
5503 return IRQ_RETVAL(handled);
5507 * Workqueue context.
5509 static void rtl_slow_event_work(struct rtl8169_private *tp)
5511 struct net_device *dev = tp->dev;
5514 status = rtl_get_events(tp) & tp->event_slow;
5515 rtl_ack_events(tp, status);
5517 if (unlikely(status & RxFIFOOver)) {
5518 switch (tp->mac_version) {
5519 /* Work around for rx fifo overflow */
5520 case RTL_GIGA_MAC_VER_11:
5521 netif_stop_queue(dev);
5522 /* XXX - Hack alert. See rtl_task(). */
5523 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5529 if (unlikely(status & SYSErr))
5530 rtl8169_pcierr_interrupt(dev);
5532 if (status & LinkChg)
5533 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5535 napi_disable(&tp->napi);
5536 rtl_irq_disable(tp);
5538 napi_enable(&tp->napi);
5539 napi_schedule(&tp->napi);
5542 static void rtl_task(struct work_struct *work)
5544 static const struct {
5546 void (*action)(struct rtl8169_private *);
5548 /* XXX - keep rtl_slow_event_work() as first element. */
5549 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5550 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5551 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5553 struct rtl8169_private *tp =
5554 container_of(work, struct rtl8169_private, wk.work);
5555 struct net_device *dev = tp->dev;
5560 if (!netif_running(dev) ||
5561 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5564 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5567 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5569 rtl_work[i].action(tp);
5573 rtl_unlock_work(tp);
5576 static int rtl8169_poll(struct napi_struct *napi, int budget)
5578 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5579 struct net_device *dev = tp->dev;
5580 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5584 status = rtl_get_events(tp);
5585 rtl_ack_events(tp, status & ~tp->event_slow);
5587 if (status & RTL_EVENT_NAPI_RX)
5588 work_done = rtl_rx(dev, tp, (u32) budget);
5590 if (status & RTL_EVENT_NAPI_TX)
5593 if (status & tp->event_slow) {
5594 enable_mask &= ~tp->event_slow;
5596 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5599 if (work_done < budget) {
5600 napi_complete(napi);
5602 rtl_irq_enable(tp, enable_mask);
5609 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5611 struct rtl8169_private *tp = netdev_priv(dev);
5613 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5616 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5617 RTL_W32(RxMissed, 0);
5620 static void rtl8169_down(struct net_device *dev)
5622 struct rtl8169_private *tp = netdev_priv(dev);
5623 void __iomem *ioaddr = tp->mmio_addr;
5625 del_timer_sync(&tp->timer);
5627 napi_disable(&tp->napi);
5628 netif_stop_queue(dev);
5630 rtl8169_hw_reset(tp);
5632 * At this point device interrupts can not be enabled in any function,
5633 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5634 * and napi is disabled (rtl8169_poll).
5636 rtl8169_rx_missed(dev, ioaddr);
5638 /* Give a racing hard_start_xmit a few cycles to complete. */
5639 synchronize_sched();
5641 rtl8169_tx_clear(tp);
5643 rtl8169_rx_clear(tp);
5645 rtl_pll_power_down(tp);
5648 static int rtl8169_close(struct net_device *dev)
5650 struct rtl8169_private *tp = netdev_priv(dev);
5651 struct pci_dev *pdev = tp->pci_dev;
5653 pm_runtime_get_sync(&pdev->dev);
5655 /* Update counters before going down */
5656 rtl8169_update_counters(dev);
5659 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5662 rtl_unlock_work(tp);
5664 free_irq(pdev->irq, dev);
5666 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5668 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5670 tp->TxDescArray = NULL;
5671 tp->RxDescArray = NULL;
5673 pm_runtime_put_sync(&pdev->dev);
5678 #ifdef CONFIG_NET_POLL_CONTROLLER
5679 static void rtl8169_netpoll(struct net_device *dev)
5681 struct rtl8169_private *tp = netdev_priv(dev);
5683 rtl8169_interrupt(tp->pci_dev->irq, dev);
5687 static int rtl_open(struct net_device *dev)
5689 struct rtl8169_private *tp = netdev_priv(dev);
5690 void __iomem *ioaddr = tp->mmio_addr;
5691 struct pci_dev *pdev = tp->pci_dev;
5692 int retval = -ENOMEM;
5694 pm_runtime_get_sync(&pdev->dev);
5697 * Rx and Tx desscriptors needs 256 bytes alignment.
5698 * dma_alloc_coherent provides more.
5700 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5701 &tp->TxPhyAddr, GFP_KERNEL);
5702 if (!tp->TxDescArray)
5703 goto err_pm_runtime_put;
5705 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5706 &tp->RxPhyAddr, GFP_KERNEL);
5707 if (!tp->RxDescArray)
5710 retval = rtl8169_init_ring(dev);
5714 INIT_WORK(&tp->wk.work, rtl_task);
5718 rtl_request_firmware(tp);
5720 retval = request_irq(pdev->irq, rtl8169_interrupt,
5721 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5724 goto err_release_fw_2;
5728 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5730 napi_enable(&tp->napi);
5732 rtl8169_init_phy(dev, tp);
5734 __rtl8169_set_features(dev, dev->features);
5736 rtl_pll_power_up(tp);
5740 netif_start_queue(dev);
5742 rtl_unlock_work(tp);
5744 tp->saved_wolopts = 0;
5745 tp->runtime_suspended = false;
5746 pm_runtime_put_noidle(&pdev->dev);
5748 rtl8169_check_link_status(dev, tp, ioaddr);
5753 rtl_release_firmware(tp);
5754 rtl8169_rx_clear(tp);
5756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5758 tp->RxDescArray = NULL;
5760 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5762 tp->TxDescArray = NULL;
5764 pm_runtime_put_noidle(&pdev->dev);
5768 static struct rtnl_link_stats64 *
5769 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5771 struct rtl8169_private *tp = netdev_priv(dev);
5772 void __iomem *ioaddr = tp->mmio_addr;
5775 if (netif_running(dev))
5776 rtl8169_rx_missed(dev, ioaddr);
5779 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5780 stats->rx_packets = tp->rx_stats.packets;
5781 stats->rx_bytes = tp->rx_stats.bytes;
5782 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5786 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5787 stats->tx_packets = tp->tx_stats.packets;
5788 stats->tx_bytes = tp->tx_stats.bytes;
5789 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5791 stats->rx_dropped = dev->stats.rx_dropped;
5792 stats->tx_dropped = dev->stats.tx_dropped;
5793 stats->rx_length_errors = dev->stats.rx_length_errors;
5794 stats->rx_errors = dev->stats.rx_errors;
5795 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5796 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5797 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5802 static void rtl8169_net_suspend(struct net_device *dev)
5804 struct rtl8169_private *tp = netdev_priv(dev);
5806 if (!netif_running(dev))
5809 netif_device_detach(dev);
5810 netif_stop_queue(dev);
5813 napi_disable(&tp->napi);
5814 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5815 rtl_unlock_work(tp);
5817 rtl_pll_power_down(tp);
5822 static int rtl8169_suspend(struct device *device)
5824 struct pci_dev *pdev = to_pci_dev(device);
5825 struct net_device *dev = pci_get_drvdata(pdev);
5826 struct rtl8169_private *tp = netdev_priv(dev);
5829 tp->saved_wolopts = __rtl8169_get_wol(tp);
5830 rtl_unlock_work(tp);
5832 rtl8169_net_suspend(dev);
5837 static void __rtl8169_resume(struct net_device *dev)
5839 struct rtl8169_private *tp = netdev_priv(dev);
5841 netif_device_attach(dev);
5843 rtl_pll_power_up(tp);
5846 napi_enable(&tp->napi);
5847 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5848 rtl_unlock_work(tp);
5850 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5853 static int rtl8169_resume(struct device *device)
5855 struct pci_dev *pdev = to_pci_dev(device);
5856 struct net_device *dev = pci_get_drvdata(pdev);
5857 struct rtl8169_private *tp = netdev_priv(dev);
5860 __rtl8169_set_wol(tp, tp->saved_wolopts);
5861 rtl_unlock_work(tp);
5863 rtl8169_init_phy(dev, tp);
5865 if (netif_running(dev))
5866 __rtl8169_resume(dev);
5871 static int rtl8169_runtime_suspend(struct device *device)
5873 struct pci_dev *pdev = to_pci_dev(device);
5874 struct net_device *dev = pci_get_drvdata(pdev);
5875 struct rtl8169_private *tp = netdev_priv(dev);
5877 if (!tp->TxDescArray)
5881 tp->saved_wolopts = __rtl8169_get_wol(tp);
5882 __rtl8169_set_wol(tp, WAKE_ANY);
5883 tp->runtime_suspended = true;
5884 rtl_unlock_work(tp);
5886 rtl8169_net_suspend(dev);
5891 static int rtl8169_runtime_resume(struct device *device)
5893 struct pci_dev *pdev = to_pci_dev(device);
5894 struct net_device *dev = pci_get_drvdata(pdev);
5895 struct rtl8169_private *tp = netdev_priv(dev);
5897 if (!tp->TxDescArray)
5901 __rtl8169_set_wol(tp, tp->saved_wolopts);
5902 tp->saved_wolopts = 0;
5903 tp->runtime_suspended = false;
5904 rtl_unlock_work(tp);
5906 rtl8169_init_phy(dev, tp);
5908 __rtl8169_resume(dev);
5913 static int rtl8169_runtime_idle(struct device *device)
5915 struct pci_dev *pdev = to_pci_dev(device);
5916 struct net_device *dev = pci_get_drvdata(pdev);
5917 struct rtl8169_private *tp = netdev_priv(dev);
5919 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5920 return tp->TxDescArray ? -EBUSY : 0;
5923 static const struct dev_pm_ops rtl8169_pm_ops = {
5924 .suspend = rtl8169_suspend,
5925 .resume = rtl8169_resume,
5926 .freeze = rtl8169_suspend,
5927 .thaw = rtl8169_resume,
5928 .poweroff = rtl8169_suspend,
5929 .restore = rtl8169_resume,
5930 .runtime_suspend = rtl8169_runtime_suspend,
5931 .runtime_resume = rtl8169_runtime_resume,
5932 .runtime_idle = rtl8169_runtime_idle,
5935 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5937 #else /* !CONFIG_PM */
5939 #define RTL8169_PM_OPS NULL
5941 #endif /* !CONFIG_PM */
5943 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5945 void __iomem *ioaddr = tp->mmio_addr;
5947 /* WoL fails with 8168b when the receiver is disabled. */
5948 switch (tp->mac_version) {
5949 case RTL_GIGA_MAC_VER_11:
5950 case RTL_GIGA_MAC_VER_12:
5951 case RTL_GIGA_MAC_VER_17:
5952 pci_clear_master(tp->pci_dev);
5954 RTL_W8(ChipCmd, CmdRxEnb);
5963 static void rtl_shutdown(struct pci_dev *pdev)
5965 struct net_device *dev = pci_get_drvdata(pdev);
5966 struct rtl8169_private *tp = netdev_priv(dev);
5967 struct device *d = &pdev->dev;
5969 pm_runtime_get_sync(d);
5971 /* Get the device back to D0 state if it was runtime suspended. */
5972 if (tp->runtime_suspended)
5973 pci_set_power_state(pdev, PCI_D0);
5975 rtl8169_net_suspend(dev);
5977 /* Restore original MAC address */
5978 rtl_rar_set(tp, dev->perm_addr);
5980 rtl8169_hw_reset(tp);
5982 /* Restore WOL flags if they were messed around with. */
5983 if (tp->saved_wolopts)
5984 __rtl8169_set_wol(tp, tp->saved_wolopts);
5986 if (system_state == SYSTEM_POWER_OFF) {
5987 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5988 rtl_wol_suspend_quirk(tp);
5989 rtl_wol_shutdown_quirk(tp);
5992 pci_wake_from_d3(pdev, true);
5993 pci_set_power_state(pdev, PCI_D3hot);
5996 pm_runtime_put_noidle(d);
5999 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6001 struct net_device *dev = pci_get_drvdata(pdev);
6002 struct rtl8169_private *tp = netdev_priv(dev);
6004 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6005 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6006 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6007 rtl8168_driver_stop(tp);
6010 cancel_work_sync(&tp->wk.work);
6012 unregister_netdev(dev);
6014 rtl_release_firmware(tp);
6016 if (pci_dev_run_wake(pdev))
6017 pm_runtime_get_noresume(&pdev->dev);
6019 /* restore original MAC address */
6020 rtl_rar_set(tp, dev->perm_addr);
6022 rtl_disable_msi(pdev, tp);
6023 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6024 pci_set_drvdata(pdev, NULL);
6027 static const struct net_device_ops rtl_netdev_ops = {
6028 .ndo_open = rtl_open,
6029 .ndo_stop = rtl8169_close,
6030 .ndo_get_stats64 = rtl8169_get_stats64,
6031 .ndo_start_xmit = rtl8169_start_xmit,
6032 .ndo_tx_timeout = rtl8169_tx_timeout,
6033 .ndo_validate_addr = eth_validate_addr,
6034 .ndo_change_mtu = rtl8169_change_mtu,
6035 .ndo_fix_features = rtl8169_fix_features,
6036 .ndo_set_features = rtl8169_set_features,
6037 .ndo_set_mac_address = rtl_set_mac_address,
6038 .ndo_do_ioctl = rtl8169_ioctl,
6039 .ndo_set_rx_mode = rtl_set_rx_mode,
6040 #ifdef CONFIG_NET_POLL_CONTROLLER
6041 .ndo_poll_controller = rtl8169_netpoll,
6046 static const struct rtl_cfg_info {
6047 void (*hw_start)(struct net_device *);
6048 unsigned int region;
6053 } rtl_cfg_infos [] = {
6055 .hw_start = rtl_hw_start_8169,
6058 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6059 .features = RTL_FEATURE_GMII,
6060 .default_ver = RTL_GIGA_MAC_VER_01,
6063 .hw_start = rtl_hw_start_8168,
6066 .event_slow = SYSErr | LinkChg | RxOverflow,
6067 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6068 .default_ver = RTL_GIGA_MAC_VER_11,
6071 .hw_start = rtl_hw_start_8101,
6074 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6076 .features = RTL_FEATURE_MSI,
6077 .default_ver = RTL_GIGA_MAC_VER_13,
6081 /* Cfg9346_Unlock assumed. */
6082 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6083 const struct rtl_cfg_info *cfg)
6085 void __iomem *ioaddr = tp->mmio_addr;
6089 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6090 if (cfg->features & RTL_FEATURE_MSI) {
6091 if (pci_enable_msi(tp->pci_dev)) {
6092 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6095 msi = RTL_FEATURE_MSI;
6098 RTL_W8(Config2, cfg2);
6102 static int __devinit
6103 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6105 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6106 const unsigned int region = cfg->region;
6107 struct rtl8169_private *tp;
6108 struct mii_if_info *mii;
6109 struct net_device *dev;
6110 void __iomem *ioaddr;
6114 if (netif_msg_drv(&debug)) {
6115 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6116 MODULENAME, RTL8169_VERSION);
6119 dev = alloc_etherdev(sizeof (*tp));
6125 SET_NETDEV_DEV(dev, &pdev->dev);
6126 dev->netdev_ops = &rtl_netdev_ops;
6127 tp = netdev_priv(dev);
6130 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6134 mii->mdio_read = rtl_mdio_read;
6135 mii->mdio_write = rtl_mdio_write;
6136 mii->phy_id_mask = 0x1f;
6137 mii->reg_num_mask = 0x1f;
6138 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6140 /* disable ASPM completely as that cause random device stop working
6141 * problems as well as full system hangs for some PCIe devices users */
6143 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6144 PCIE_LINK_STATE_L1 |
6145 PCIE_LINK_STATE_CLKPM);
6146 dprintk("ASPM disabled");
6149 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6150 rc = pci_enable_device(pdev);
6152 netif_err(tp, probe, dev, "enable failure\n");
6153 goto err_out_free_dev_1;
6156 if (pci_set_mwi(pdev) < 0)
6157 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6159 /* make sure PCI base addr 1 is MMIO */
6160 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6161 netif_err(tp, probe, dev,
6162 "region #%d not an MMIO resource, aborting\n",
6168 /* check for weird/broken PCI region reporting */
6169 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6170 netif_err(tp, probe, dev,
6171 "Invalid PCI region size(s), aborting\n");
6176 rc = pci_request_regions(pdev, MODULENAME);
6178 netif_err(tp, probe, dev, "could not request regions\n");
6182 tp->cp_cmd = RxChkSum;
6184 if ((sizeof(dma_addr_t) > 4) &&
6185 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6186 tp->cp_cmd |= PCIDAC;
6187 dev->features |= NETIF_F_HIGHDMA;
6189 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6191 netif_err(tp, probe, dev, "DMA configuration failed\n");
6192 goto err_out_free_res_3;
6196 /* ioremap MMIO region */
6197 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6199 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6201 goto err_out_free_res_3;
6203 tp->mmio_addr = ioaddr;
6205 if (!pci_is_pcie(pdev))
6206 netif_info(tp, probe, dev, "not PCI Express\n");
6208 /* Identify chip attached to board */
6209 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6213 rtl_irq_disable(tp);
6217 rtl_ack_events(tp, 0xffff);
6219 pci_set_master(pdev);
6222 * Pretend we are using VLANs; This bypasses a nasty bug where
6223 * Interrupts stop flowing on high load on 8110SCd controllers.
6225 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6226 tp->cp_cmd |= RxVlan;
6228 rtl_init_mdio_ops(tp);
6229 rtl_init_pll_power_ops(tp);
6230 rtl_init_jumbo_ops(tp);
6232 rtl8169_print_mac_version(tp);
6234 chipset = tp->mac_version;
6235 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6237 RTL_W8(Cfg9346, Cfg9346_Unlock);
6238 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6240 RTL_W8(Config5, PMEStatus);
6241 tp->features |= rtl_try_msi(tp, cfg);
6242 RTL_W8(Cfg9346, Cfg9346_Lock);
6244 if (rtl_tbi_enabled(tp)) {
6245 tp->set_speed = rtl8169_set_speed_tbi;
6246 tp->get_settings = rtl8169_gset_tbi;
6247 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6248 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6249 tp->link_ok = rtl8169_tbi_link_ok;
6250 tp->do_ioctl = rtl_tbi_ioctl;
6252 tp->set_speed = rtl8169_set_speed_xmii;
6253 tp->get_settings = rtl8169_gset_xmii;
6254 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6255 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6256 tp->link_ok = rtl8169_xmii_link_ok;
6257 tp->do_ioctl = rtl_xmii_ioctl;
6260 mutex_init(&tp->wk.mutex);
6262 /* Get MAC address */
6263 for (i = 0; i < ETH_ALEN; i++)
6264 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6265 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6267 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6268 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6270 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6272 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6273 * properly for all devices */
6274 dev->features |= NETIF_F_RXCSUM |
6275 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6277 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6278 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6279 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6282 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6283 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6284 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6286 dev->hw_features |= NETIF_F_RXALL;
6287 dev->hw_features |= NETIF_F_RXFCS;
6289 tp->hw_start = cfg->hw_start;
6290 tp->event_slow = cfg->event_slow;
6292 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6293 ~(RxBOVF | RxFOVF) : ~0;
6295 init_timer(&tp->timer);
6296 tp->timer.data = (unsigned long) dev;
6297 tp->timer.function = rtl8169_phy_timer;
6299 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6301 rc = register_netdev(dev);
6305 pci_set_drvdata(pdev, dev);
6307 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6308 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6309 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6310 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6311 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6312 "tx checksumming: %s]\n",
6313 rtl_chip_infos[chipset].jumbo_max,
6314 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6317 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6318 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6319 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6320 rtl8168_driver_start(tp);
6323 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6325 if (pci_dev_run_wake(pdev))
6326 pm_runtime_put_noidle(&pdev->dev);
6328 netif_carrier_off(dev);
6334 rtl_disable_msi(pdev, tp);
6337 pci_release_regions(pdev);
6339 pci_clear_mwi(pdev);
6340 pci_disable_device(pdev);
6346 static struct pci_driver rtl8169_pci_driver = {
6348 .id_table = rtl8169_pci_tbl,
6349 .probe = rtl_init_one,
6350 .remove = __devexit_p(rtl_remove_one),
6351 .shutdown = rtl_shutdown,
6352 .driver.pm = RTL8169_PM_OPS,
6355 static int __init rtl8169_init_module(void)
6357 return pci_register_driver(&rtl8169_pci_driver);
6360 static void __exit rtl8169_cleanup_module(void)
6362 pci_unregister_driver(&rtl8169_pci_driver);
6365 module_init(rtl8169_init_module);
6366 module_exit(rtl8169_cleanup_module);