2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
49 #define assert(expr) \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
52 #expr,__FILE__,__func__,__LINE__); \
54 #define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #define assert(expr) do {} while (0)
58 #define dprintk(fmt, args...) do {} while (0)
59 #endif /* RTL8169_DEBUG */
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64 #define TX_SLOTS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
69 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
72 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
73 static const int multicast_filter_limit = 32;
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01 = 0,
140 RTL_GIGA_MAC_NONE = 0xff,
143 enum rtl_tx_desc_version {
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154 #define _R(NAME,TD,FW,SZ,B) { \
162 static const struct {
164 enum rtl_tx_desc_version txd_version;
168 } rtl_chip_infos[] = {
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
271 { PCI_VENDOR_ID_LINKSYS, 0x1032,
272 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280 static int rx_buf_sz = 16383;
287 MAC0 = 0, /* Ethernet hardware address. */
289 MAR0 = 8, /* Multicast filter. */
290 CounterAddrLow = 0x10,
291 CounterAddrHigh = 0x14,
292 TxDescStartAddrLow = 0x20,
293 TxDescStartAddrHigh = 0x24,
294 TxHDescStartAddrLow = 0x28,
295 TxHDescStartAddrHigh = 0x2c,
304 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
305 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
308 #define RX128_INT_EN (1 << 15) /* 8111c and later */
309 #define RX_MULTI_EN (1 << 14) /* 8111c only */
310 #define RXCFG_FIFO_SHIFT 13
311 /* No threshold before first PCI xfer */
312 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
313 #define RXCFG_DMA_SHIFT 8
314 /* Unlimited maximum PCI burst. */
315 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
331 RxDescAddrLow = 0xe4,
332 RxDescAddrHigh = 0xe8,
333 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
337 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339 #define TxPacketMax (8064 >> 7)
340 #define EarlySize 0x27
343 FuncEventMask = 0xf4,
344 FuncPresetState = 0xf8,
345 FuncForceEvent = 0xfc,
348 enum rtl8110_registers {
354 enum rtl8168_8101_registers {
357 #define CSIAR_FLAG 0x80000000
358 #define CSIAR_WRITE_CMD 0x80000000
359 #define CSIAR_BYTE_ENABLE 0x0f
360 #define CSIAR_BYTE_ENABLE_SHIFT 12
361 #define CSIAR_ADDR_MASK 0x0fff
364 #define EPHYAR_FLAG 0x80000000
365 #define EPHYAR_WRITE_CMD 0x80000000
366 #define EPHYAR_REG_MASK 0x1f
367 #define EPHYAR_REG_SHIFT 16
368 #define EPHYAR_DATA_MASK 0xffff
370 #define PFM_EN (1 << 6)
372 #define FIX_NAK_1 (1 << 4)
373 #define FIX_NAK_2 (1 << 3)
376 #define NOW_IS_OOB (1 << 7)
377 #define EN_NDP (1 << 3)
378 #define EN_OOB_RESET (1 << 2)
380 #define EFUSEAR_FLAG 0x80000000
381 #define EFUSEAR_WRITE_CMD 0x80000000
382 #define EFUSEAR_READ_CMD 0x00000000
383 #define EFUSEAR_REG_MASK 0x03ff
384 #define EFUSEAR_REG_SHIFT 8
385 #define EFUSEAR_DATA_MASK 0xff
388 enum rtl8168_registers {
393 #define ERIAR_FLAG 0x80000000
394 #define ERIAR_WRITE_CMD 0x80000000
395 #define ERIAR_READ_CMD 0x00000000
396 #define ERIAR_ADDR_BYTE_ALIGN 4
397 #define ERIAR_TYPE_SHIFT 16
398 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
399 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_MASK_SHIFT 12
402 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
403 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
405 EPHY_RXER_NUM = 0x7c,
406 OCPDR = 0xb0, /* OCP GPHY access */
407 #define OCPDR_WRITE_CMD 0x80000000
408 #define OCPDR_READ_CMD 0x00000000
409 #define OCPDR_REG_MASK 0x7f
410 #define OCPDR_GPHY_REG_SHIFT 16
411 #define OCPDR_DATA_MASK 0xffff
413 #define OCPAR_FLAG 0x80000000
414 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
415 #define OCPAR_GPHY_READ_CMD 0x0000f060
416 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
417 MISC = 0xf0, /* 8168e only. */
418 #define TXPLA_RST (1 << 29)
419 #define PWM_EN (1 << 22)
422 enum rtl_register_content {
423 /* InterruptStatusBits */
427 TxDescUnavail = 0x0080,
451 /* TXPoll register p.5 */
452 HPQ = 0x80, /* Poll cmd on the high prio queue */
453 NPQ = 0x40, /* Poll cmd on the low prio queue */
454 FSWInt = 0x01, /* Forced software interrupt */
458 Cfg9346_Unlock = 0xc0,
463 AcceptBroadcast = 0x08,
464 AcceptMulticast = 0x04,
466 AcceptAllPhys = 0x01,
467 #define RX_CONFIG_ACCEPT_MASK 0x3f
470 TxInterFrameGapShift = 24,
471 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473 /* Config1 register p.24 */
476 Speed_down = (1 << 4),
480 PMEnable = (1 << 0), /* Power Management Enable */
482 /* Config2 register p. 25 */
483 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
484 PCI_Clock_66MHz = 0x01,
485 PCI_Clock_33MHz = 0x00,
487 /* Config3 register p.25 */
488 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
489 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
490 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
491 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
493 /* Config4 register */
494 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496 /* Config5 register p.27 */
497 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
498 MWF = (1 << 5), /* Accept Multicast wakeup frame */
499 UWF = (1 << 4), /* Accept Unicast wakeup frame */
501 LanWake = (1 << 1), /* LanWake enable/disable */
502 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
505 TBIReset = 0x80000000,
506 TBILoopback = 0x40000000,
507 TBINwEnable = 0x20000000,
508 TBINwRestart = 0x10000000,
509 TBILinkOk = 0x02000000,
510 TBINwComplete = 0x01000000,
513 EnableBist = (1 << 15), // 8168 8101
514 Mac_dbgo_oe = (1 << 14), // 8168 8101
515 Normal_mode = (1 << 13), // unused
516 Force_half_dup = (1 << 12), // 8168 8101
517 Force_rxflow_en = (1 << 11), // 8168 8101
518 Force_txflow_en = (1 << 10), // 8168 8101
519 Cxpl_dbg_sel = (1 << 9), // 8168 8101
520 ASF = (1 << 8), // 8168 8101
521 PktCntrDisable = (1 << 7), // 8168 8101
522 Mac_dbgo_sel = 0x001c, // 8168
527 INTT_0 = 0x0000, // 8168
528 INTT_1 = 0x0001, // 8168
529 INTT_2 = 0x0002, // 8168
530 INTT_3 = 0x0003, // 8168
532 /* rtl8169_PHYstatus */
543 TBILinkOK = 0x02000000,
545 /* DumpCounterCommand */
550 /* First doubleword. */
551 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
552 RingEnd = (1 << 30), /* End of descriptor ring */
553 FirstFrag = (1 << 29), /* First segment of a packet */
554 LastFrag = (1 << 28), /* Final segment of a packet */
558 enum rtl_tx_desc_bit {
559 /* First doubleword. */
560 TD_LSO = (1 << 27), /* Large Send Offload */
561 #define TD_MSS_MAX 0x07ffu /* MSS value */
563 /* Second doubleword. */
564 TxVlanTag = (1 << 17), /* Add VLAN tag */
567 /* 8169, 8168b and 810x except 8102e. */
568 enum rtl_tx_desc_bit_0 {
569 /* First doubleword. */
570 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
571 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
572 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
573 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
576 /* 8102e, 8168c and beyond. */
577 enum rtl_tx_desc_bit_1 {
578 /* Second doubleword. */
579 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
580 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
581 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
582 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
585 static const struct rtl_tx_desc_info {
592 } tx_desc_info [] = {
595 .udp = TD0_IP_CS | TD0_UDP_CS,
596 .tcp = TD0_IP_CS | TD0_TCP_CS
598 .mss_shift = TD0_MSS_SHIFT,
603 .udp = TD1_IP_CS | TD1_UDP_CS,
604 .tcp = TD1_IP_CS | TD1_TCP_CS
606 .mss_shift = TD1_MSS_SHIFT,
611 enum rtl_rx_desc_bit {
613 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
614 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616 #define RxProtoUDP (PID1)
617 #define RxProtoTCP (PID0)
618 #define RxProtoIP (PID1 | PID0)
619 #define RxProtoMask RxProtoIP
621 IPFail = (1 << 16), /* IP checksum failed */
622 UDPFail = (1 << 15), /* UDP/IP checksum failed */
623 TCPFail = (1 << 14), /* TCP/IP checksum failed */
624 RxVlanTag = (1 << 16), /* VLAN tag available */
627 #define RsvdMask 0x3fffc000
644 u8 __pad[sizeof(void *) - sizeof(u32)];
648 RTL_FEATURE_WOL = (1 << 0),
649 RTL_FEATURE_MSI = (1 << 1),
650 RTL_FEATURE_GMII = (1 << 2),
653 struct rtl8169_counters {
660 __le32 tx_one_collision;
661 __le32 tx_multi_collision;
670 RTL_FLAG_TASK_ENABLED,
671 RTL_FLAG_TASK_SLOW_PENDING,
672 RTL_FLAG_TASK_RESET_PENDING,
673 RTL_FLAG_TASK_PHY_PENDING,
677 struct rtl8169_stats {
680 struct u64_stats_sync syncp;
683 struct rtl8169_private {
684 void __iomem *mmio_addr; /* memory map physical address */
685 struct pci_dev *pci_dev;
686 struct net_device *dev;
687 struct napi_struct napi;
691 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
692 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
695 struct rtl8169_stats rx_stats;
696 struct rtl8169_stats tx_stats;
697 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
698 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
699 dma_addr_t TxPhyAddr;
700 dma_addr_t RxPhyAddr;
701 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
702 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
703 struct timer_list timer;
707 bool runtime_suspended;
710 void (*write)(void __iomem *, int, int);
711 int (*read)(void __iomem *, int);
714 struct pll_power_ops {
715 void (*down)(struct rtl8169_private *);
716 void (*up)(struct rtl8169_private *);
720 void (*enable)(struct rtl8169_private *);
721 void (*disable)(struct rtl8169_private *);
724 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
725 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
726 void (*phy_reset_enable)(struct rtl8169_private *tp);
727 void (*hw_start)(struct net_device *);
728 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
729 unsigned int (*link_ok)(void __iomem *);
730 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
733 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
735 struct work_struct work;
740 struct mii_if_info mii;
741 struct rtl8169_counters counters;
746 const struct firmware *fw;
748 #define RTL_VER_SIZE 32
750 char version[RTL_VER_SIZE];
752 struct rtl_fw_phy_action {
757 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
760 static int aspm_disable = 0;
761 module_param(aspm_disable, bool, 0444);
762 MODULE_PARM_DESC(aspm_disable, "Disable ASPM completely.");
764 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
765 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
766 module_param(use_dac, int, 0);
767 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
768 module_param_named(debug, debug.msg_enable, int, 0);
769 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
770 MODULE_LICENSE("GPL");
771 MODULE_VERSION(RTL8169_VERSION);
772 MODULE_FIRMWARE(FIRMWARE_8168D_1);
773 MODULE_FIRMWARE(FIRMWARE_8168D_2);
774 MODULE_FIRMWARE(FIRMWARE_8168E_1);
775 MODULE_FIRMWARE(FIRMWARE_8168E_2);
776 MODULE_FIRMWARE(FIRMWARE_8168E_3);
777 MODULE_FIRMWARE(FIRMWARE_8105E_1);
778 MODULE_FIRMWARE(FIRMWARE_8168F_1);
779 MODULE_FIRMWARE(FIRMWARE_8168F_2);
781 static void rtl_lock_work(struct rtl8169_private *tp)
783 mutex_lock(&tp->wk.mutex);
786 static void rtl_unlock_work(struct rtl8169_private *tp)
788 mutex_unlock(&tp->wk.mutex);
791 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
793 int cap = pci_pcie_cap(pdev);
798 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
799 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
800 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
804 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
806 void __iomem *ioaddr = tp->mmio_addr;
809 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
810 for (i = 0; i < 20; i++) {
812 if (RTL_R32(OCPAR) & OCPAR_FLAG)
815 return RTL_R32(OCPDR);
818 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
820 void __iomem *ioaddr = tp->mmio_addr;
823 RTL_W32(OCPDR, data);
824 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
825 for (i = 0; i < 20; i++) {
827 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
832 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
834 void __iomem *ioaddr = tp->mmio_addr;
838 RTL_W32(ERIAR, 0x800010e8);
840 for (i = 0; i < 5; i++) {
842 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
846 ocp_write(tp, 0x1, 0x30, 0x00000001);
849 #define OOB_CMD_RESET 0x00
850 #define OOB_CMD_DRIVER_START 0x05
851 #define OOB_CMD_DRIVER_STOP 0x06
853 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
855 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
858 static void rtl8168_driver_start(struct rtl8169_private *tp)
863 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
865 reg = rtl8168_get_ocp_reg(tp);
867 for (i = 0; i < 10; i++) {
869 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
874 static void rtl8168_driver_stop(struct rtl8169_private *tp)
879 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
881 reg = rtl8168_get_ocp_reg(tp);
883 for (i = 0; i < 10; i++) {
885 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
890 static int r8168dp_check_dash(struct rtl8169_private *tp)
892 u16 reg = rtl8168_get_ocp_reg(tp);
894 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
897 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
901 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
903 for (i = 20; i > 0; i--) {
905 * Check if the RTL8169 has completed writing to the specified
908 if (!(RTL_R32(PHYAR) & 0x80000000))
913 * According to hardware specs a 20us delay is required after write
914 * complete indication, but before sending next command.
919 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
923 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
925 for (i = 20; i > 0; i--) {
927 * Check if the RTL8169 has completed retrieving data from
928 * the specified MII register.
930 if (RTL_R32(PHYAR) & 0x80000000) {
931 value = RTL_R32(PHYAR) & 0xffff;
937 * According to hardware specs a 20us delay is required after read
938 * complete indication, but before sending next command.
945 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
949 RTL_W32(OCPDR, data |
950 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
951 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
952 RTL_W32(EPHY_RXER_NUM, 0);
954 for (i = 0; i < 100; i++) {
956 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
961 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
963 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
964 (value & OCPDR_DATA_MASK));
967 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
971 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
974 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
975 RTL_W32(EPHY_RXER_NUM, 0);
977 for (i = 0; i < 100; i++) {
979 if (RTL_R32(OCPAR) & OCPAR_FLAG)
983 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
986 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
988 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
990 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
993 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
995 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
998 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1000 r8168dp_2_mdio_start(ioaddr);
1002 r8169_mdio_write(ioaddr, reg_addr, value);
1004 r8168dp_2_mdio_stop(ioaddr);
1007 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1011 r8168dp_2_mdio_start(ioaddr);
1013 value = r8169_mdio_read(ioaddr, reg_addr);
1015 r8168dp_2_mdio_stop(ioaddr);
1020 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1022 tp->mdio_ops.write(tp->mmio_addr, location, val);
1025 static int rtl_readphy(struct rtl8169_private *tp, int location)
1027 return tp->mdio_ops.read(tp->mmio_addr, location);
1030 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1032 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1039 val = rtl_readphy(tp, reg_addr);
1040 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1043 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1046 struct rtl8169_private *tp = netdev_priv(dev);
1048 rtl_writephy(tp, location, val);
1051 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1053 struct rtl8169_private *tp = netdev_priv(dev);
1055 return rtl_readphy(tp, location);
1058 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1062 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1063 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065 for (i = 0; i < 100; i++) {
1066 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1072 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1077 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1079 for (i = 0; i < 100; i++) {
1080 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1081 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1090 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1094 RTL_W32(CSIDR, value);
1095 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1096 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1098 for (i = 0; i < 100; i++) {
1099 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1105 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1110 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1111 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1113 for (i = 0; i < 100; i++) {
1114 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1115 value = RTL_R32(CSIDR);
1125 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1129 BUG_ON((addr & 3) || (mask == 0));
1130 RTL_W32(ERIDR, val);
1131 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1133 for (i = 0; i < 100; i++) {
1134 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1140 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1145 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1147 for (i = 0; i < 100; i++) {
1148 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1149 value = RTL_R32(ERIDR);
1159 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1163 val = rtl_eri_read(ioaddr, addr, type);
1164 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1173 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1174 const struct exgmac_reg *r, int len)
1177 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1182 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1187 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1189 for (i = 0; i < 300; i++) {
1190 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1191 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1200 static u16 rtl_get_events(struct rtl8169_private *tp)
1202 void __iomem *ioaddr = tp->mmio_addr;
1204 return RTL_R16(IntrStatus);
1207 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1209 void __iomem *ioaddr = tp->mmio_addr;
1211 RTL_W16(IntrStatus, bits);
1215 static void rtl_irq_disable(struct rtl8169_private *tp)
1217 void __iomem *ioaddr = tp->mmio_addr;
1219 RTL_W16(IntrMask, 0);
1223 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1225 void __iomem *ioaddr = tp->mmio_addr;
1227 RTL_W16(IntrMask, bits);
1230 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1231 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1232 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1234 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1236 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1239 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1241 void __iomem *ioaddr = tp->mmio_addr;
1243 rtl_irq_disable(tp);
1244 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1248 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1250 void __iomem *ioaddr = tp->mmio_addr;
1252 return RTL_R32(TBICSR) & TBIReset;
1255 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1257 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1260 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1262 return RTL_R32(TBICSR) & TBILinkOk;
1265 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1267 return RTL_R8(PHYstatus) & LinkStatus;
1270 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1272 void __iomem *ioaddr = tp->mmio_addr;
1274 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1277 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1281 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1282 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1285 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1287 void __iomem *ioaddr = tp->mmio_addr;
1288 struct net_device *dev = tp->dev;
1290 if (!netif_running(dev))
1293 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1294 if (RTL_R8(PHYstatus) & _1000bpsF) {
1295 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1296 0x00000011, ERIAR_EXGMAC);
1297 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1298 0x00000005, ERIAR_EXGMAC);
1299 } else if (RTL_R8(PHYstatus) & _100bps) {
1300 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1301 0x0000001f, ERIAR_EXGMAC);
1302 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1303 0x00000005, ERIAR_EXGMAC);
1305 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1306 0x0000001f, ERIAR_EXGMAC);
1307 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1308 0x0000003f, ERIAR_EXGMAC);
1310 /* Reset packet filter */
1311 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1313 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1315 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1316 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1317 if (RTL_R8(PHYstatus) & _1000bpsF) {
1318 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1319 0x00000011, ERIAR_EXGMAC);
1320 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1321 0x00000005, ERIAR_EXGMAC);
1323 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1324 0x0000001f, ERIAR_EXGMAC);
1325 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1326 0x0000003f, ERIAR_EXGMAC);
1331 static void __rtl8169_check_link_status(struct net_device *dev,
1332 struct rtl8169_private *tp,
1333 void __iomem *ioaddr, bool pm)
1335 if (tp->link_ok(ioaddr)) {
1336 rtl_link_chg_patch(tp);
1337 /* This is to cancel a scheduled suspend if there's one. */
1339 pm_request_resume(&tp->pci_dev->dev);
1340 netif_carrier_on(dev);
1341 if (net_ratelimit())
1342 netif_info(tp, ifup, dev, "link up\n");
1344 netif_carrier_off(dev);
1345 netif_info(tp, ifdown, dev, "link down\n");
1347 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1351 static void rtl8169_check_link_status(struct net_device *dev,
1352 struct rtl8169_private *tp,
1353 void __iomem *ioaddr)
1355 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1360 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1362 void __iomem *ioaddr = tp->mmio_addr;
1366 options = RTL_R8(Config1);
1367 if (!(options & PMEnable))
1370 options = RTL_R8(Config3);
1371 if (options & LinkUp)
1372 wolopts |= WAKE_PHY;
1373 if (options & MagicPacket)
1374 wolopts |= WAKE_MAGIC;
1376 options = RTL_R8(Config5);
1378 wolopts |= WAKE_UCAST;
1380 wolopts |= WAKE_BCAST;
1382 wolopts |= WAKE_MCAST;
1387 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1389 struct rtl8169_private *tp = netdev_priv(dev);
1393 wol->supported = WAKE_ANY;
1394 wol->wolopts = __rtl8169_get_wol(tp);
1396 rtl_unlock_work(tp);
1399 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1401 void __iomem *ioaddr = tp->mmio_addr;
1403 static const struct {
1408 { WAKE_ANY, Config1, PMEnable },
1409 { WAKE_PHY, Config3, LinkUp },
1410 { WAKE_MAGIC, Config3, MagicPacket },
1411 { WAKE_UCAST, Config5, UWF },
1412 { WAKE_BCAST, Config5, BWF },
1413 { WAKE_MCAST, Config5, MWF },
1414 { WAKE_ANY, Config5, LanWake }
1417 RTL_W8(Cfg9346, Cfg9346_Unlock);
1419 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1420 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1421 if (wolopts & cfg[i].opt)
1422 options |= cfg[i].mask;
1423 RTL_W8(cfg[i].reg, options);
1426 RTL_W8(Cfg9346, Cfg9346_Lock);
1429 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1431 struct rtl8169_private *tp = netdev_priv(dev);
1436 tp->features |= RTL_FEATURE_WOL;
1438 tp->features &= ~RTL_FEATURE_WOL;
1439 __rtl8169_set_wol(tp, wol->wolopts);
1441 rtl_unlock_work(tp);
1443 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1448 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1450 return rtl_chip_infos[tp->mac_version].fw_name;
1453 static void rtl8169_get_drvinfo(struct net_device *dev,
1454 struct ethtool_drvinfo *info)
1456 struct rtl8169_private *tp = netdev_priv(dev);
1457 struct rtl_fw *rtl_fw = tp->rtl_fw;
1459 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1460 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1461 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1462 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1463 if (!IS_ERR_OR_NULL(rtl_fw))
1464 strlcpy(info->fw_version, rtl_fw->version,
1465 sizeof(info->fw_version));
1468 static int rtl8169_get_regs_len(struct net_device *dev)
1470 return R8169_REGS_SIZE;
1473 static int rtl8169_set_speed_tbi(struct net_device *dev,
1474 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1476 struct rtl8169_private *tp = netdev_priv(dev);
1477 void __iomem *ioaddr = tp->mmio_addr;
1481 reg = RTL_R32(TBICSR);
1482 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1483 (duplex == DUPLEX_FULL)) {
1484 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1485 } else if (autoneg == AUTONEG_ENABLE)
1486 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1488 netif_warn(tp, link, dev,
1489 "incorrect speed setting refused in TBI mode\n");
1496 static int rtl8169_set_speed_xmii(struct net_device *dev,
1497 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1499 struct rtl8169_private *tp = netdev_priv(dev);
1500 int giga_ctrl, bmcr;
1503 rtl_writephy(tp, 0x1f, 0x0000);
1505 if (autoneg == AUTONEG_ENABLE) {
1508 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1509 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1510 ADVERTISE_100HALF | ADVERTISE_100FULL);
1512 if (adv & ADVERTISED_10baseT_Half)
1513 auto_nego |= ADVERTISE_10HALF;
1514 if (adv & ADVERTISED_10baseT_Full)
1515 auto_nego |= ADVERTISE_10FULL;
1516 if (adv & ADVERTISED_100baseT_Half)
1517 auto_nego |= ADVERTISE_100HALF;
1518 if (adv & ADVERTISED_100baseT_Full)
1519 auto_nego |= ADVERTISE_100FULL;
1521 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1523 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1524 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1526 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1527 if (tp->mii.supports_gmii) {
1528 if (adv & ADVERTISED_1000baseT_Half)
1529 giga_ctrl |= ADVERTISE_1000HALF;
1530 if (adv & ADVERTISED_1000baseT_Full)
1531 giga_ctrl |= ADVERTISE_1000FULL;
1532 } else if (adv & (ADVERTISED_1000baseT_Half |
1533 ADVERTISED_1000baseT_Full)) {
1534 netif_info(tp, link, dev,
1535 "PHY does not support 1000Mbps\n");
1539 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1541 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1542 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1546 if (speed == SPEED_10)
1548 else if (speed == SPEED_100)
1549 bmcr = BMCR_SPEED100;
1553 if (duplex == DUPLEX_FULL)
1554 bmcr |= BMCR_FULLDPLX;
1557 rtl_writephy(tp, MII_BMCR, bmcr);
1559 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1560 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1561 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1562 rtl_writephy(tp, 0x17, 0x2138);
1563 rtl_writephy(tp, 0x0e, 0x0260);
1565 rtl_writephy(tp, 0x17, 0x2108);
1566 rtl_writephy(tp, 0x0e, 0x0000);
1575 static int rtl8169_set_speed(struct net_device *dev,
1576 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1578 struct rtl8169_private *tp = netdev_priv(dev);
1581 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1585 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1586 (advertising & ADVERTISED_1000baseT_Full)) {
1587 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1593 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1595 struct rtl8169_private *tp = netdev_priv(dev);
1598 del_timer_sync(&tp->timer);
1601 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1602 cmd->duplex, cmd->advertising);
1603 rtl_unlock_work(tp);
1608 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1609 netdev_features_t features)
1611 struct rtl8169_private *tp = netdev_priv(dev);
1613 if (dev->mtu > TD_MSS_MAX)
1614 features &= ~NETIF_F_ALL_TSO;
1616 if (dev->mtu > JUMBO_1K &&
1617 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1618 features &= ~NETIF_F_IP_CSUM;
1623 static void __rtl8169_set_features(struct net_device *dev,
1624 netdev_features_t features)
1626 struct rtl8169_private *tp = netdev_priv(dev);
1627 netdev_features_t changed = features ^ dev->features;
1628 void __iomem *ioaddr = tp->mmio_addr;
1630 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1633 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1634 if (features & NETIF_F_RXCSUM)
1635 tp->cp_cmd |= RxChkSum;
1637 tp->cp_cmd &= ~RxChkSum;
1639 if (dev->features & NETIF_F_HW_VLAN_RX)
1640 tp->cp_cmd |= RxVlan;
1642 tp->cp_cmd &= ~RxVlan;
1644 RTL_W16(CPlusCmd, tp->cp_cmd);
1647 if (changed & NETIF_F_RXALL) {
1648 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1649 if (features & NETIF_F_RXALL)
1650 tmp |= (AcceptErr | AcceptRunt);
1651 RTL_W32(RxConfig, tmp);
1655 static int rtl8169_set_features(struct net_device *dev,
1656 netdev_features_t features)
1658 struct rtl8169_private *tp = netdev_priv(dev);
1661 __rtl8169_set_features(dev, features);
1662 rtl_unlock_work(tp);
1668 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1669 struct sk_buff *skb)
1671 return (vlan_tx_tag_present(skb)) ?
1672 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1675 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1677 u32 opts2 = le32_to_cpu(desc->opts2);
1679 if (opts2 & RxVlanTag)
1680 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1685 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1687 struct rtl8169_private *tp = netdev_priv(dev);
1688 void __iomem *ioaddr = tp->mmio_addr;
1692 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1693 cmd->port = PORT_FIBRE;
1694 cmd->transceiver = XCVR_INTERNAL;
1696 status = RTL_R32(TBICSR);
1697 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1698 cmd->autoneg = !!(status & TBINwEnable);
1700 ethtool_cmd_speed_set(cmd, SPEED_1000);
1701 cmd->duplex = DUPLEX_FULL; /* Always set */
1706 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1708 struct rtl8169_private *tp = netdev_priv(dev);
1710 return mii_ethtool_gset(&tp->mii, cmd);
1713 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1715 struct rtl8169_private *tp = netdev_priv(dev);
1719 rc = tp->get_settings(dev, cmd);
1720 rtl_unlock_work(tp);
1725 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1728 struct rtl8169_private *tp = netdev_priv(dev);
1730 if (regs->len > R8169_REGS_SIZE)
1731 regs->len = R8169_REGS_SIZE;
1734 memcpy_fromio(p, tp->mmio_addr, regs->len);
1735 rtl_unlock_work(tp);
1738 static u32 rtl8169_get_msglevel(struct net_device *dev)
1740 struct rtl8169_private *tp = netdev_priv(dev);
1742 return tp->msg_enable;
1745 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1747 struct rtl8169_private *tp = netdev_priv(dev);
1749 tp->msg_enable = value;
1752 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1759 "tx_single_collisions",
1760 "tx_multi_collisions",
1768 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1772 return ARRAY_SIZE(rtl8169_gstrings);
1778 static void rtl8169_update_counters(struct net_device *dev)
1780 struct rtl8169_private *tp = netdev_priv(dev);
1781 void __iomem *ioaddr = tp->mmio_addr;
1782 struct device *d = &tp->pci_dev->dev;
1783 struct rtl8169_counters *counters;
1789 * Some chips are unable to dump tally counters when the receiver
1792 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1795 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1799 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1800 cmd = (u64)paddr & DMA_BIT_MASK(32);
1801 RTL_W32(CounterAddrLow, cmd);
1802 RTL_W32(CounterAddrLow, cmd | CounterDump);
1805 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1806 memcpy(&tp->counters, counters, sizeof(*counters));
1812 RTL_W32(CounterAddrLow, 0);
1813 RTL_W32(CounterAddrHigh, 0);
1815 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1818 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1819 struct ethtool_stats *stats, u64 *data)
1821 struct rtl8169_private *tp = netdev_priv(dev);
1825 rtl8169_update_counters(dev);
1827 data[0] = le64_to_cpu(tp->counters.tx_packets);
1828 data[1] = le64_to_cpu(tp->counters.rx_packets);
1829 data[2] = le64_to_cpu(tp->counters.tx_errors);
1830 data[3] = le32_to_cpu(tp->counters.rx_errors);
1831 data[4] = le16_to_cpu(tp->counters.rx_missed);
1832 data[5] = le16_to_cpu(tp->counters.align_errors);
1833 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1834 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1835 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1836 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1837 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1838 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1839 data[12] = le16_to_cpu(tp->counters.tx_underun);
1842 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1846 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1851 static const struct ethtool_ops rtl8169_ethtool_ops = {
1852 .get_drvinfo = rtl8169_get_drvinfo,
1853 .get_regs_len = rtl8169_get_regs_len,
1854 .get_link = ethtool_op_get_link,
1855 .get_settings = rtl8169_get_settings,
1856 .set_settings = rtl8169_set_settings,
1857 .get_msglevel = rtl8169_get_msglevel,
1858 .set_msglevel = rtl8169_set_msglevel,
1859 .get_regs = rtl8169_get_regs,
1860 .get_wol = rtl8169_get_wol,
1861 .set_wol = rtl8169_set_wol,
1862 .get_strings = rtl8169_get_strings,
1863 .get_sset_count = rtl8169_get_sset_count,
1864 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1867 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1868 struct net_device *dev, u8 default_version)
1870 void __iomem *ioaddr = tp->mmio_addr;
1872 * The driver currently handles the 8168Bf and the 8168Be identically
1873 * but they can be identified more specifically through the test below
1876 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1878 * Same thing for the 8101Eb and the 8101Ec:
1880 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1882 static const struct rtl_mac_info {
1888 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1889 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1892 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1893 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1894 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1895 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1898 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1899 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1900 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1902 /* 8168DP family. */
1903 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1904 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1905 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1908 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1909 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1910 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1911 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1912 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1913 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1914 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1915 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1916 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1919 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1920 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1921 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1922 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1925 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1926 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1927 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1928 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1929 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1930 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1931 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1932 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1933 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1934 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1935 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1936 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1937 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1938 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1939 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1940 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1941 /* FIXME: where did these entries come from ? -- FR */
1942 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1943 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1946 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1947 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1948 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1949 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1950 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1951 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1954 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1956 const struct rtl_mac_info *p = mac_info;
1959 reg = RTL_R32(TxConfig);
1960 while ((reg & p->mask) != p->val)
1962 tp->mac_version = p->mac_version;
1964 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1965 netif_notice(tp, probe, dev,
1966 "unknown MAC, using family default\n");
1967 tp->mac_version = default_version;
1971 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1973 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1981 static void rtl_writephy_batch(struct rtl8169_private *tp,
1982 const struct phy_reg *regs, int len)
1985 rtl_writephy(tp, regs->reg, regs->val);
1990 #define PHY_READ 0x00000000
1991 #define PHY_DATA_OR 0x10000000
1992 #define PHY_DATA_AND 0x20000000
1993 #define PHY_BJMPN 0x30000000
1994 #define PHY_READ_EFUSE 0x40000000
1995 #define PHY_READ_MAC_BYTE 0x50000000
1996 #define PHY_WRITE_MAC_BYTE 0x60000000
1997 #define PHY_CLEAR_READCOUNT 0x70000000
1998 #define PHY_WRITE 0x80000000
1999 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2000 #define PHY_COMP_EQ_SKIPN 0xa0000000
2001 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2002 #define PHY_WRITE_PREVIOUS 0xc0000000
2003 #define PHY_SKIPN 0xd0000000
2004 #define PHY_DELAY_MS 0xe0000000
2005 #define PHY_WRITE_ERI_WORD 0xf0000000
2009 char version[RTL_VER_SIZE];
2015 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2017 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2019 const struct firmware *fw = rtl_fw->fw;
2020 struct fw_info *fw_info = (struct fw_info *)fw->data;
2021 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2022 char *version = rtl_fw->version;
2025 if (fw->size < FW_OPCODE_SIZE)
2028 if (!fw_info->magic) {
2029 size_t i, size, start;
2032 if (fw->size < sizeof(*fw_info))
2035 for (i = 0; i < fw->size; i++)
2036 checksum += fw->data[i];
2040 start = le32_to_cpu(fw_info->fw_start);
2041 if (start > fw->size)
2044 size = le32_to_cpu(fw_info->fw_len);
2045 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2048 memcpy(version, fw_info->version, RTL_VER_SIZE);
2050 pa->code = (__le32 *)(fw->data + start);
2053 if (fw->size % FW_OPCODE_SIZE)
2056 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2058 pa->code = (__le32 *)fw->data;
2059 pa->size = fw->size / FW_OPCODE_SIZE;
2061 version[RTL_VER_SIZE - 1] = 0;
2068 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2069 struct rtl_fw_phy_action *pa)
2074 for (index = 0; index < pa->size; index++) {
2075 u32 action = le32_to_cpu(pa->code[index]);
2076 u32 regno = (action & 0x0fff0000) >> 16;
2078 switch(action & 0xf0000000) {
2082 case PHY_READ_EFUSE:
2083 case PHY_CLEAR_READCOUNT:
2085 case PHY_WRITE_PREVIOUS:
2090 if (regno > index) {
2091 netif_err(tp, ifup, tp->dev,
2092 "Out of range of firmware\n");
2096 case PHY_READCOUNT_EQ_SKIP:
2097 if (index + 2 >= pa->size) {
2098 netif_err(tp, ifup, tp->dev,
2099 "Out of range of firmware\n");
2103 case PHY_COMP_EQ_SKIPN:
2104 case PHY_COMP_NEQ_SKIPN:
2106 if (index + 1 + regno >= pa->size) {
2107 netif_err(tp, ifup, tp->dev,
2108 "Out of range of firmware\n");
2113 case PHY_READ_MAC_BYTE:
2114 case PHY_WRITE_MAC_BYTE:
2115 case PHY_WRITE_ERI_WORD:
2117 netif_err(tp, ifup, tp->dev,
2118 "Invalid action 0x%08x\n", action);
2127 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2129 struct net_device *dev = tp->dev;
2132 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2133 netif_err(tp, ifup, dev, "invalid firwmare\n");
2137 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2143 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2145 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2149 predata = count = 0;
2151 for (index = 0; index < pa->size; ) {
2152 u32 action = le32_to_cpu(pa->code[index]);
2153 u32 data = action & 0x0000ffff;
2154 u32 regno = (action & 0x0fff0000) >> 16;
2159 switch(action & 0xf0000000) {
2161 predata = rtl_readphy(tp, regno);
2176 case PHY_READ_EFUSE:
2177 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2180 case PHY_CLEAR_READCOUNT:
2185 rtl_writephy(tp, regno, data);
2188 case PHY_READCOUNT_EQ_SKIP:
2189 index += (count == data) ? 2 : 1;
2191 case PHY_COMP_EQ_SKIPN:
2192 if (predata == data)
2196 case PHY_COMP_NEQ_SKIPN:
2197 if (predata != data)
2201 case PHY_WRITE_PREVIOUS:
2202 rtl_writephy(tp, regno, predata);
2213 case PHY_READ_MAC_BYTE:
2214 case PHY_WRITE_MAC_BYTE:
2215 case PHY_WRITE_ERI_WORD:
2222 static void rtl_release_firmware(struct rtl8169_private *tp)
2224 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2225 release_firmware(tp->rtl_fw->fw);
2228 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2231 static void rtl_apply_firmware(struct rtl8169_private *tp)
2233 struct rtl_fw *rtl_fw = tp->rtl_fw;
2235 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2236 if (!IS_ERR_OR_NULL(rtl_fw))
2237 rtl_phy_write_fw(tp, rtl_fw);
2240 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2242 if (rtl_readphy(tp, reg) != val)
2243 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2245 rtl_apply_firmware(tp);
2248 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2250 static const struct phy_reg phy_reg_init[] = {
2312 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2317 static const struct phy_reg phy_reg_init[] = {
2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2328 struct pci_dev *pdev = tp->pci_dev;
2330 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2331 (pdev->subsystem_device != 0xe000))
2334 rtl_writephy(tp, 0x1f, 0x0001);
2335 rtl_writephy(tp, 0x10, 0xf01b);
2336 rtl_writephy(tp, 0x1f, 0x0000);
2339 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2341 static const struct phy_reg phy_reg_init[] = {
2381 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2383 rtl8169scd_hw_phy_config_quirk(tp);
2386 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2388 static const struct phy_reg phy_reg_init[] = {
2436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2439 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2441 static const struct phy_reg phy_reg_init[] = {
2446 rtl_writephy(tp, 0x1f, 0x0001);
2447 rtl_patchphy(tp, 0x16, 1 << 0);
2449 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2452 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2454 static const struct phy_reg phy_reg_init[] = {
2460 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2463 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2465 static const struct phy_reg phy_reg_init[] = {
2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2476 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2478 static const struct phy_reg phy_reg_init[] = {
2484 rtl_writephy(tp, 0x1f, 0x0000);
2485 rtl_patchphy(tp, 0x14, 1 << 5);
2486 rtl_patchphy(tp, 0x0d, 1 << 5);
2488 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2491 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2493 static const struct phy_reg phy_reg_init[] = {
2513 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2515 rtl_patchphy(tp, 0x14, 1 << 5);
2516 rtl_patchphy(tp, 0x0d, 1 << 5);
2517 rtl_writephy(tp, 0x1f, 0x0000);
2520 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2522 static const struct phy_reg phy_reg_init[] = {
2540 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2542 rtl_patchphy(tp, 0x16, 1 << 0);
2543 rtl_patchphy(tp, 0x14, 1 << 5);
2544 rtl_patchphy(tp, 0x0d, 1 << 5);
2545 rtl_writephy(tp, 0x1f, 0x0000);
2548 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2550 static const struct phy_reg phy_reg_init[] = {
2562 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564 rtl_patchphy(tp, 0x16, 1 << 0);
2565 rtl_patchphy(tp, 0x14, 1 << 5);
2566 rtl_patchphy(tp, 0x0d, 1 << 5);
2567 rtl_writephy(tp, 0x1f, 0x0000);
2570 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2572 rtl8168c_3_hw_phy_config(tp);
2575 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2577 static const struct phy_reg phy_reg_init_0[] = {
2578 /* Channel Estimation */
2599 * Enhance line driver power
2608 * Can not link to 1Gbps with bad cable
2609 * Decrease SNR threshold form 21.07dB to 19.04dB
2617 void __iomem *ioaddr = tp->mmio_addr;
2619 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2623 * Fine Tune Switching regulator parameter
2625 rtl_writephy(tp, 0x1f, 0x0002);
2626 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2627 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2629 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2630 static const struct phy_reg phy_reg_init[] = {
2640 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642 val = rtl_readphy(tp, 0x0d);
2644 if ((val & 0x00ff) != 0x006c) {
2645 static const u32 set[] = {
2646 0x0065, 0x0066, 0x0067, 0x0068,
2647 0x0069, 0x006a, 0x006b, 0x006c
2651 rtl_writephy(tp, 0x1f, 0x0002);
2654 for (i = 0; i < ARRAY_SIZE(set); i++)
2655 rtl_writephy(tp, 0x0d, val | set[i]);
2658 static const struct phy_reg phy_reg_init[] = {
2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2669 /* RSET couple improve */
2670 rtl_writephy(tp, 0x1f, 0x0002);
2671 rtl_patchphy(tp, 0x0d, 0x0300);
2672 rtl_patchphy(tp, 0x0f, 0x0010);
2674 /* Fine tune PLL performance */
2675 rtl_writephy(tp, 0x1f, 0x0002);
2676 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2677 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2679 rtl_writephy(tp, 0x1f, 0x0005);
2680 rtl_writephy(tp, 0x05, 0x001b);
2682 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2684 rtl_writephy(tp, 0x1f, 0x0000);
2687 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2689 static const struct phy_reg phy_reg_init_0[] = {
2690 /* Channel Estimation */
2711 * Enhance line driver power
2720 * Can not link to 1Gbps with bad cable
2721 * Decrease SNR threshold form 21.07dB to 19.04dB
2729 void __iomem *ioaddr = tp->mmio_addr;
2731 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2733 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2734 static const struct phy_reg phy_reg_init[] = {
2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2747 val = rtl_readphy(tp, 0x0d);
2748 if ((val & 0x00ff) != 0x006c) {
2749 static const u32 set[] = {
2750 0x0065, 0x0066, 0x0067, 0x0068,
2751 0x0069, 0x006a, 0x006b, 0x006c
2755 rtl_writephy(tp, 0x1f, 0x0002);
2758 for (i = 0; i < ARRAY_SIZE(set); i++)
2759 rtl_writephy(tp, 0x0d, val | set[i]);
2762 static const struct phy_reg phy_reg_init[] = {
2770 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2773 /* Fine tune PLL performance */
2774 rtl_writephy(tp, 0x1f, 0x0002);
2775 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2776 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2778 /* Switching regulator Slew rate */
2779 rtl_writephy(tp, 0x1f, 0x0002);
2780 rtl_patchphy(tp, 0x0f, 0x0017);
2782 rtl_writephy(tp, 0x1f, 0x0005);
2783 rtl_writephy(tp, 0x05, 0x001b);
2785 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2787 rtl_writephy(tp, 0x1f, 0x0000);
2790 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2792 static const struct phy_reg phy_reg_init[] = {
2848 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2853 static const struct phy_reg phy_reg_init[] = {
2863 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2864 rtl_patchphy(tp, 0x0d, 1 << 5);
2867 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2869 static const struct phy_reg phy_reg_init[] = {
2870 /* Enable Delay cap */
2876 /* Channel estimation fine tune */
2885 /* Update PFM & 10M TX idle timer */
2897 rtl_apply_firmware(tp);
2899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2901 /* DCO enable for 10M IDLE Power */
2902 rtl_writephy(tp, 0x1f, 0x0007);
2903 rtl_writephy(tp, 0x1e, 0x0023);
2904 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2905 rtl_writephy(tp, 0x1f, 0x0000);
2907 /* For impedance matching */
2908 rtl_writephy(tp, 0x1f, 0x0002);
2909 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2912 /* PHY auto speed down */
2913 rtl_writephy(tp, 0x1f, 0x0007);
2914 rtl_writephy(tp, 0x1e, 0x002d);
2915 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2916 rtl_writephy(tp, 0x1f, 0x0000);
2917 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2919 rtl_writephy(tp, 0x1f, 0x0005);
2920 rtl_writephy(tp, 0x05, 0x8b86);
2921 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2922 rtl_writephy(tp, 0x1f, 0x0000);
2924 rtl_writephy(tp, 0x1f, 0x0005);
2925 rtl_writephy(tp, 0x05, 0x8b85);
2926 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2927 rtl_writephy(tp, 0x1f, 0x0007);
2928 rtl_writephy(tp, 0x1e, 0x0020);
2929 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2930 rtl_writephy(tp, 0x1f, 0x0006);
2931 rtl_writephy(tp, 0x00, 0x5a00);
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933 rtl_writephy(tp, 0x0d, 0x0007);
2934 rtl_writephy(tp, 0x0e, 0x003c);
2935 rtl_writephy(tp, 0x0d, 0x4007);
2936 rtl_writephy(tp, 0x0e, 0x0000);
2937 rtl_writephy(tp, 0x0d, 0x0000);
2940 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2942 static const struct phy_reg phy_reg_init[] = {
2943 /* Enable Delay cap */
2952 /* Channel estimation fine tune */
2969 rtl_apply_firmware(tp);
2971 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2973 /* For 4-corner performance improve */
2974 rtl_writephy(tp, 0x1f, 0x0005);
2975 rtl_writephy(tp, 0x05, 0x8b80);
2976 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2977 rtl_writephy(tp, 0x1f, 0x0000);
2979 /* PHY auto speed down */
2980 rtl_writephy(tp, 0x1f, 0x0004);
2981 rtl_writephy(tp, 0x1f, 0x0007);
2982 rtl_writephy(tp, 0x1e, 0x002d);
2983 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2984 rtl_writephy(tp, 0x1f, 0x0002);
2985 rtl_writephy(tp, 0x1f, 0x0000);
2986 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2988 /* improve 10M EEE waveform */
2989 rtl_writephy(tp, 0x1f, 0x0005);
2990 rtl_writephy(tp, 0x05, 0x8b86);
2991 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2992 rtl_writephy(tp, 0x1f, 0x0000);
2994 /* Improve 2-pair detection performance */
2995 rtl_writephy(tp, 0x1f, 0x0005);
2996 rtl_writephy(tp, 0x05, 0x8b85);
2997 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2998 rtl_writephy(tp, 0x1f, 0x0000);
3001 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3003 rtl_writephy(tp, 0x1f, 0x0005);
3004 rtl_writephy(tp, 0x05, 0x8b85);
3005 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3006 rtl_writephy(tp, 0x1f, 0x0004);
3007 rtl_writephy(tp, 0x1f, 0x0007);
3008 rtl_writephy(tp, 0x1e, 0x0020);
3009 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3010 rtl_writephy(tp, 0x1f, 0x0002);
3011 rtl_writephy(tp, 0x1f, 0x0000);
3012 rtl_writephy(tp, 0x0d, 0x0007);
3013 rtl_writephy(tp, 0x0e, 0x003c);
3014 rtl_writephy(tp, 0x0d, 0x4007);
3015 rtl_writephy(tp, 0x0e, 0x0000);
3016 rtl_writephy(tp, 0x0d, 0x0000);
3019 rtl_writephy(tp, 0x1f, 0x0003);
3020 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3021 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3025 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3027 static const struct phy_reg phy_reg_init[] = {
3028 /* Channel estimation fine tune */
3033 /* Modify green table for giga & fnet */
3050 /* Modify green table for 10M */
3056 /* Disable hiimpedance detection (RTCT) */
3062 rtl_apply_firmware(tp);
3064 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3066 /* For 4-corner performance improve */
3067 rtl_writephy(tp, 0x1f, 0x0005);
3068 rtl_writephy(tp, 0x05, 0x8b80);
3069 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3070 rtl_writephy(tp, 0x1f, 0x0000);
3072 /* PHY auto speed down */
3073 rtl_writephy(tp, 0x1f, 0x0007);
3074 rtl_writephy(tp, 0x1e, 0x002d);
3075 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3076 rtl_writephy(tp, 0x1f, 0x0000);
3077 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3079 /* Improve 10M EEE waveform */
3080 rtl_writephy(tp, 0x1f, 0x0005);
3081 rtl_writephy(tp, 0x05, 0x8b86);
3082 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3083 rtl_writephy(tp, 0x1f, 0x0000);
3085 /* Improve 2-pair detection performance */
3086 rtl_writephy(tp, 0x1f, 0x0005);
3087 rtl_writephy(tp, 0x05, 0x8b85);
3088 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3089 rtl_writephy(tp, 0x1f, 0x0000);
3092 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3094 rtl_apply_firmware(tp);
3096 /* For 4-corner performance improve */
3097 rtl_writephy(tp, 0x1f, 0x0005);
3098 rtl_writephy(tp, 0x05, 0x8b80);
3099 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3100 rtl_writephy(tp, 0x1f, 0x0000);
3102 /* PHY auto speed down */
3103 rtl_writephy(tp, 0x1f, 0x0007);
3104 rtl_writephy(tp, 0x1e, 0x002d);
3105 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3106 rtl_writephy(tp, 0x1f, 0x0000);
3107 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3109 /* Improve 10M EEE waveform */
3110 rtl_writephy(tp, 0x1f, 0x0005);
3111 rtl_writephy(tp, 0x05, 0x8b86);
3112 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3113 rtl_writephy(tp, 0x1f, 0x0000);
3116 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3118 static const struct phy_reg phy_reg_init[] = {
3125 rtl_writephy(tp, 0x1f, 0x0000);
3126 rtl_patchphy(tp, 0x11, 1 << 12);
3127 rtl_patchphy(tp, 0x19, 1 << 13);
3128 rtl_patchphy(tp, 0x10, 1 << 15);
3130 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3133 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3135 static const struct phy_reg phy_reg_init[] = {
3149 /* Disable ALDPS before ram code */
3150 rtl_writephy(tp, 0x1f, 0x0000);
3151 rtl_writephy(tp, 0x18, 0x0310);
3154 rtl_apply_firmware(tp);
3156 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159 static void rtl_hw_phy_config(struct net_device *dev)
3161 struct rtl8169_private *tp = netdev_priv(dev);
3163 rtl8169_print_mac_version(tp);
3165 switch (tp->mac_version) {
3166 case RTL_GIGA_MAC_VER_01:
3168 case RTL_GIGA_MAC_VER_02:
3169 case RTL_GIGA_MAC_VER_03:
3170 rtl8169s_hw_phy_config(tp);
3172 case RTL_GIGA_MAC_VER_04:
3173 rtl8169sb_hw_phy_config(tp);
3175 case RTL_GIGA_MAC_VER_05:
3176 rtl8169scd_hw_phy_config(tp);
3178 case RTL_GIGA_MAC_VER_06:
3179 rtl8169sce_hw_phy_config(tp);
3181 case RTL_GIGA_MAC_VER_07:
3182 case RTL_GIGA_MAC_VER_08:
3183 case RTL_GIGA_MAC_VER_09:
3184 rtl8102e_hw_phy_config(tp);
3186 case RTL_GIGA_MAC_VER_11:
3187 rtl8168bb_hw_phy_config(tp);
3189 case RTL_GIGA_MAC_VER_12:
3190 rtl8168bef_hw_phy_config(tp);
3192 case RTL_GIGA_MAC_VER_17:
3193 rtl8168bef_hw_phy_config(tp);
3195 case RTL_GIGA_MAC_VER_18:
3196 rtl8168cp_1_hw_phy_config(tp);
3198 case RTL_GIGA_MAC_VER_19:
3199 rtl8168c_1_hw_phy_config(tp);
3201 case RTL_GIGA_MAC_VER_20:
3202 rtl8168c_2_hw_phy_config(tp);
3204 case RTL_GIGA_MAC_VER_21:
3205 rtl8168c_3_hw_phy_config(tp);
3207 case RTL_GIGA_MAC_VER_22:
3208 rtl8168c_4_hw_phy_config(tp);
3210 case RTL_GIGA_MAC_VER_23:
3211 case RTL_GIGA_MAC_VER_24:
3212 rtl8168cp_2_hw_phy_config(tp);
3214 case RTL_GIGA_MAC_VER_25:
3215 rtl8168d_1_hw_phy_config(tp);
3217 case RTL_GIGA_MAC_VER_26:
3218 rtl8168d_2_hw_phy_config(tp);
3220 case RTL_GIGA_MAC_VER_27:
3221 rtl8168d_3_hw_phy_config(tp);
3223 case RTL_GIGA_MAC_VER_28:
3224 rtl8168d_4_hw_phy_config(tp);
3226 case RTL_GIGA_MAC_VER_29:
3227 case RTL_GIGA_MAC_VER_30:
3228 rtl8105e_hw_phy_config(tp);
3230 case RTL_GIGA_MAC_VER_31:
3233 case RTL_GIGA_MAC_VER_32:
3234 case RTL_GIGA_MAC_VER_33:
3235 rtl8168e_1_hw_phy_config(tp);
3237 case RTL_GIGA_MAC_VER_34:
3238 rtl8168e_2_hw_phy_config(tp);
3240 case RTL_GIGA_MAC_VER_35:
3241 rtl8168f_1_hw_phy_config(tp);
3243 case RTL_GIGA_MAC_VER_36:
3244 rtl8168f_2_hw_phy_config(tp);
3252 static void rtl_phy_work(struct rtl8169_private *tp)
3254 struct timer_list *timer = &tp->timer;
3255 void __iomem *ioaddr = tp->mmio_addr;
3256 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3258 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3260 if (tp->phy_reset_pending(tp)) {
3262 * A busy loop could burn quite a few cycles on nowadays CPU.
3263 * Let's delay the execution of the timer for a few ticks.
3269 if (tp->link_ok(ioaddr))
3272 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3274 tp->phy_reset_enable(tp);
3277 mod_timer(timer, jiffies + timeout);
3280 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3282 if (!test_and_set_bit(flag, tp->wk.flags))
3283 schedule_work(&tp->wk.work);
3286 static void rtl8169_phy_timer(unsigned long __opaque)
3288 struct net_device *dev = (struct net_device *)__opaque;
3289 struct rtl8169_private *tp = netdev_priv(dev);
3291 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3294 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3295 void __iomem *ioaddr)
3298 pci_release_regions(pdev);
3299 pci_clear_mwi(pdev);
3300 pci_disable_device(pdev);
3304 static void rtl8169_phy_reset(struct net_device *dev,
3305 struct rtl8169_private *tp)
3309 tp->phy_reset_enable(tp);
3310 for (i = 0; i < 100; i++) {
3311 if (!tp->phy_reset_pending(tp))
3315 netif_err(tp, link, dev, "PHY reset failed\n");
3318 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3320 void __iomem *ioaddr = tp->mmio_addr;
3322 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3323 (RTL_R8(PHYstatus) & TBI_Enable);
3326 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3328 void __iomem *ioaddr = tp->mmio_addr;
3330 rtl_hw_phy_config(dev);
3332 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3333 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3337 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3339 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3340 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3342 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3343 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3345 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3346 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3349 rtl8169_phy_reset(dev, tp);
3351 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3352 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3353 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3354 (tp->mii.supports_gmii ?
3355 ADVERTISED_1000baseT_Half |
3356 ADVERTISED_1000baseT_Full : 0));
3358 if (rtl_tbi_enabled(tp))
3359 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3362 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3364 void __iomem *ioaddr = tp->mmio_addr;
3368 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3369 high = addr[4] | (addr[5] << 8);
3373 RTL_W8(Cfg9346, Cfg9346_Unlock);
3375 RTL_W32(MAC4, high);
3381 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3382 const struct exgmac_reg e[] = {
3383 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3384 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3385 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3386 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3390 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3393 RTL_W8(Cfg9346, Cfg9346_Lock);
3395 rtl_unlock_work(tp);
3398 static int rtl_set_mac_address(struct net_device *dev, void *p)
3400 struct rtl8169_private *tp = netdev_priv(dev);
3401 struct sockaddr *addr = p;
3403 if (!is_valid_ether_addr(addr->sa_data))
3404 return -EADDRNOTAVAIL;
3406 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3408 rtl_rar_set(tp, dev->dev_addr);
3413 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3415 struct rtl8169_private *tp = netdev_priv(dev);
3416 struct mii_ioctl_data *data = if_mii(ifr);
3418 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3421 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3422 struct mii_ioctl_data *data, int cmd)
3426 data->phy_id = 32; /* Internal PHY */
3430 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3434 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3440 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3445 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3447 if (tp->features & RTL_FEATURE_MSI) {
3448 pci_disable_msi(pdev);
3449 tp->features &= ~RTL_FEATURE_MSI;
3453 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3455 struct mdio_ops *ops = &tp->mdio_ops;
3457 switch (tp->mac_version) {
3458 case RTL_GIGA_MAC_VER_27:
3459 ops->write = r8168dp_1_mdio_write;
3460 ops->read = r8168dp_1_mdio_read;
3462 case RTL_GIGA_MAC_VER_28:
3463 case RTL_GIGA_MAC_VER_31:
3464 ops->write = r8168dp_2_mdio_write;
3465 ops->read = r8168dp_2_mdio_read;
3468 ops->write = r8169_mdio_write;
3469 ops->read = r8169_mdio_read;
3474 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3476 void __iomem *ioaddr = tp->mmio_addr;
3478 switch (tp->mac_version) {
3479 case RTL_GIGA_MAC_VER_29:
3480 case RTL_GIGA_MAC_VER_30:
3481 case RTL_GIGA_MAC_VER_32:
3482 case RTL_GIGA_MAC_VER_33:
3483 case RTL_GIGA_MAC_VER_34:
3484 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3485 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3492 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3494 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3497 rtl_writephy(tp, 0x1f, 0x0000);
3498 rtl_writephy(tp, MII_BMCR, 0x0000);
3500 rtl_wol_suspend_quirk(tp);
3505 static void r810x_phy_power_down(struct rtl8169_private *tp)
3507 rtl_writephy(tp, 0x1f, 0x0000);
3508 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3511 static void r810x_phy_power_up(struct rtl8169_private *tp)
3513 rtl_writephy(tp, 0x1f, 0x0000);
3514 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3517 static void r810x_pll_power_down(struct rtl8169_private *tp)
3519 if (rtl_wol_pll_power_down(tp))
3522 r810x_phy_power_down(tp);
3525 static void r810x_pll_power_up(struct rtl8169_private *tp)
3527 r810x_phy_power_up(tp);
3530 static void r8168_phy_power_up(struct rtl8169_private *tp)
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533 switch (tp->mac_version) {
3534 case RTL_GIGA_MAC_VER_11:
3535 case RTL_GIGA_MAC_VER_12:
3536 case RTL_GIGA_MAC_VER_17:
3537 case RTL_GIGA_MAC_VER_18:
3538 case RTL_GIGA_MAC_VER_19:
3539 case RTL_GIGA_MAC_VER_20:
3540 case RTL_GIGA_MAC_VER_21:
3541 case RTL_GIGA_MAC_VER_22:
3542 case RTL_GIGA_MAC_VER_23:
3543 case RTL_GIGA_MAC_VER_24:
3544 case RTL_GIGA_MAC_VER_25:
3545 case RTL_GIGA_MAC_VER_26:
3546 case RTL_GIGA_MAC_VER_27:
3547 case RTL_GIGA_MAC_VER_28:
3548 case RTL_GIGA_MAC_VER_31:
3549 rtl_writephy(tp, 0x0e, 0x0000);
3554 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3557 static void r8168_phy_power_down(struct rtl8169_private *tp)
3559 rtl_writephy(tp, 0x1f, 0x0000);
3560 switch (tp->mac_version) {
3561 case RTL_GIGA_MAC_VER_32:
3562 case RTL_GIGA_MAC_VER_33:
3563 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3566 case RTL_GIGA_MAC_VER_11:
3567 case RTL_GIGA_MAC_VER_12:
3568 case RTL_GIGA_MAC_VER_17:
3569 case RTL_GIGA_MAC_VER_18:
3570 case RTL_GIGA_MAC_VER_19:
3571 case RTL_GIGA_MAC_VER_20:
3572 case RTL_GIGA_MAC_VER_21:
3573 case RTL_GIGA_MAC_VER_22:
3574 case RTL_GIGA_MAC_VER_23:
3575 case RTL_GIGA_MAC_VER_24:
3576 case RTL_GIGA_MAC_VER_25:
3577 case RTL_GIGA_MAC_VER_26:
3578 case RTL_GIGA_MAC_VER_27:
3579 case RTL_GIGA_MAC_VER_28:
3580 case RTL_GIGA_MAC_VER_31:
3581 rtl_writephy(tp, 0x0e, 0x0200);
3583 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3588 static void r8168_pll_power_down(struct rtl8169_private *tp)
3590 void __iomem *ioaddr = tp->mmio_addr;
3592 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3593 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3594 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3595 r8168dp_check_dash(tp)) {
3599 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3600 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3601 (RTL_R16(CPlusCmd) & ASF)) {
3605 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3606 tp->mac_version == RTL_GIGA_MAC_VER_33)
3607 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3609 if (rtl_wol_pll_power_down(tp))
3612 r8168_phy_power_down(tp);
3614 switch (tp->mac_version) {
3615 case RTL_GIGA_MAC_VER_25:
3616 case RTL_GIGA_MAC_VER_26:
3617 case RTL_GIGA_MAC_VER_27:
3618 case RTL_GIGA_MAC_VER_28:
3619 case RTL_GIGA_MAC_VER_31:
3620 case RTL_GIGA_MAC_VER_32:
3621 case RTL_GIGA_MAC_VER_33:
3622 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3627 static void r8168_pll_power_up(struct rtl8169_private *tp)
3629 void __iomem *ioaddr = tp->mmio_addr;
3631 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3632 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3633 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3634 r8168dp_check_dash(tp)) {
3638 switch (tp->mac_version) {
3639 case RTL_GIGA_MAC_VER_25:
3640 case RTL_GIGA_MAC_VER_26:
3641 case RTL_GIGA_MAC_VER_27:
3642 case RTL_GIGA_MAC_VER_28:
3643 case RTL_GIGA_MAC_VER_31:
3644 case RTL_GIGA_MAC_VER_32:
3645 case RTL_GIGA_MAC_VER_33:
3646 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3650 r8168_phy_power_up(tp);
3653 static void rtl_generic_op(struct rtl8169_private *tp,
3654 void (*op)(struct rtl8169_private *))
3660 static void rtl_pll_power_down(struct rtl8169_private *tp)
3662 rtl_generic_op(tp, tp->pll_power_ops.down);
3665 static void rtl_pll_power_up(struct rtl8169_private *tp)
3667 rtl_generic_op(tp, tp->pll_power_ops.up);
3670 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3672 struct pll_power_ops *ops = &tp->pll_power_ops;
3674 switch (tp->mac_version) {
3675 case RTL_GIGA_MAC_VER_07:
3676 case RTL_GIGA_MAC_VER_08:
3677 case RTL_GIGA_MAC_VER_09:
3678 case RTL_GIGA_MAC_VER_10:
3679 case RTL_GIGA_MAC_VER_16:
3680 case RTL_GIGA_MAC_VER_29:
3681 case RTL_GIGA_MAC_VER_30:
3682 ops->down = r810x_pll_power_down;
3683 ops->up = r810x_pll_power_up;
3686 case RTL_GIGA_MAC_VER_11:
3687 case RTL_GIGA_MAC_VER_12:
3688 case RTL_GIGA_MAC_VER_17:
3689 case RTL_GIGA_MAC_VER_18:
3690 case RTL_GIGA_MAC_VER_19:
3691 case RTL_GIGA_MAC_VER_20:
3692 case RTL_GIGA_MAC_VER_21:
3693 case RTL_GIGA_MAC_VER_22:
3694 case RTL_GIGA_MAC_VER_23:
3695 case RTL_GIGA_MAC_VER_24:
3696 case RTL_GIGA_MAC_VER_25:
3697 case RTL_GIGA_MAC_VER_26:
3698 case RTL_GIGA_MAC_VER_27:
3699 case RTL_GIGA_MAC_VER_28:
3700 case RTL_GIGA_MAC_VER_31:
3701 case RTL_GIGA_MAC_VER_32:
3702 case RTL_GIGA_MAC_VER_33:
3703 case RTL_GIGA_MAC_VER_34:
3704 case RTL_GIGA_MAC_VER_35:
3705 case RTL_GIGA_MAC_VER_36:
3706 ops->down = r8168_pll_power_down;
3707 ops->up = r8168_pll_power_up;
3717 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3719 void __iomem *ioaddr = tp->mmio_addr;
3721 switch (tp->mac_version) {
3722 case RTL_GIGA_MAC_VER_01:
3723 case RTL_GIGA_MAC_VER_02:
3724 case RTL_GIGA_MAC_VER_03:
3725 case RTL_GIGA_MAC_VER_04:
3726 case RTL_GIGA_MAC_VER_05:
3727 case RTL_GIGA_MAC_VER_06:
3728 case RTL_GIGA_MAC_VER_10:
3729 case RTL_GIGA_MAC_VER_11:
3730 case RTL_GIGA_MAC_VER_12:
3731 case RTL_GIGA_MAC_VER_13:
3732 case RTL_GIGA_MAC_VER_14:
3733 case RTL_GIGA_MAC_VER_15:
3734 case RTL_GIGA_MAC_VER_16:
3735 case RTL_GIGA_MAC_VER_17:
3736 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3738 case RTL_GIGA_MAC_VER_18:
3739 case RTL_GIGA_MAC_VER_19:
3740 case RTL_GIGA_MAC_VER_20:
3741 case RTL_GIGA_MAC_VER_21:
3742 case RTL_GIGA_MAC_VER_22:
3743 case RTL_GIGA_MAC_VER_23:
3744 case RTL_GIGA_MAC_VER_24:
3745 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3748 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3753 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3755 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3758 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3760 void __iomem *ioaddr = tp->mmio_addr;
3762 RTL_W8(Cfg9346, Cfg9346_Unlock);
3763 rtl_generic_op(tp, tp->jumbo_ops.enable);
3764 RTL_W8(Cfg9346, Cfg9346_Lock);
3767 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3769 void __iomem *ioaddr = tp->mmio_addr;
3771 RTL_W8(Cfg9346, Cfg9346_Unlock);
3772 rtl_generic_op(tp, tp->jumbo_ops.disable);
3773 RTL_W8(Cfg9346, Cfg9346_Lock);
3776 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3778 void __iomem *ioaddr = tp->mmio_addr;
3780 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3781 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3782 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3785 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3787 void __iomem *ioaddr = tp->mmio_addr;
3789 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3790 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3791 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3794 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3796 void __iomem *ioaddr = tp->mmio_addr;
3798 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3801 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3803 void __iomem *ioaddr = tp->mmio_addr;
3805 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3808 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3810 void __iomem *ioaddr = tp->mmio_addr;
3812 RTL_W8(MaxTxPacketSize, 0x3f);
3813 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3814 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3815 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3818 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3820 void __iomem *ioaddr = tp->mmio_addr;
3822 RTL_W8(MaxTxPacketSize, 0x0c);
3823 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3824 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3825 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3828 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3830 rtl_tx_performance_tweak(tp->pci_dev,
3831 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3834 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3836 rtl_tx_performance_tweak(tp->pci_dev,
3837 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3840 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3842 void __iomem *ioaddr = tp->mmio_addr;
3844 r8168b_0_hw_jumbo_enable(tp);
3846 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3849 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3851 void __iomem *ioaddr = tp->mmio_addr;
3853 r8168b_0_hw_jumbo_disable(tp);
3855 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3858 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3860 struct jumbo_ops *ops = &tp->jumbo_ops;
3862 switch (tp->mac_version) {
3863 case RTL_GIGA_MAC_VER_11:
3864 ops->disable = r8168b_0_hw_jumbo_disable;
3865 ops->enable = r8168b_0_hw_jumbo_enable;
3867 case RTL_GIGA_MAC_VER_12:
3868 case RTL_GIGA_MAC_VER_17:
3869 ops->disable = r8168b_1_hw_jumbo_disable;
3870 ops->enable = r8168b_1_hw_jumbo_enable;
3872 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3873 case RTL_GIGA_MAC_VER_19:
3874 case RTL_GIGA_MAC_VER_20:
3875 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3876 case RTL_GIGA_MAC_VER_22:
3877 case RTL_GIGA_MAC_VER_23:
3878 case RTL_GIGA_MAC_VER_24:
3879 case RTL_GIGA_MAC_VER_25:
3880 case RTL_GIGA_MAC_VER_26:
3881 ops->disable = r8168c_hw_jumbo_disable;
3882 ops->enable = r8168c_hw_jumbo_enable;
3884 case RTL_GIGA_MAC_VER_27:
3885 case RTL_GIGA_MAC_VER_28:
3886 ops->disable = r8168dp_hw_jumbo_disable;
3887 ops->enable = r8168dp_hw_jumbo_enable;
3889 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3890 case RTL_GIGA_MAC_VER_32:
3891 case RTL_GIGA_MAC_VER_33:
3892 case RTL_GIGA_MAC_VER_34:
3893 ops->disable = r8168e_hw_jumbo_disable;
3894 ops->enable = r8168e_hw_jumbo_enable;
3898 * No action needed for jumbo frames with 8169.
3899 * No jumbo for 810x at all.
3902 ops->disable = NULL;
3908 static void rtl_hw_reset(struct rtl8169_private *tp)
3910 void __iomem *ioaddr = tp->mmio_addr;
3913 /* Soft reset the chip. */
3914 RTL_W8(ChipCmd, CmdReset);
3916 /* Check that the chip has finished the reset. */
3917 for (i = 0; i < 100; i++) {
3918 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3924 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3926 struct rtl_fw *rtl_fw;
3930 name = rtl_lookup_firmware_name(tp);
3932 goto out_no_firmware;
3934 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3938 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3942 rc = rtl_check_firmware(tp, rtl_fw);
3944 goto err_release_firmware;
3946 tp->rtl_fw = rtl_fw;
3950 err_release_firmware:
3951 release_firmware(rtl_fw->fw);
3955 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3962 static void rtl_request_firmware(struct rtl8169_private *tp)
3964 if (IS_ERR(tp->rtl_fw))
3965 rtl_request_uncached_firmware(tp);
3968 static void rtl_rx_close(struct rtl8169_private *tp)
3970 void __iomem *ioaddr = tp->mmio_addr;
3972 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3975 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3977 void __iomem *ioaddr = tp->mmio_addr;
3979 /* Disable interrupts */
3980 rtl8169_irq_mask_and_ack(tp);
3984 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3985 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3986 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3987 while (RTL_R8(TxPoll) & NPQ)
3989 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3990 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3991 tp->mac_version == RTL_GIGA_MAC_VER_36) {
3992 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3993 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3996 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4003 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4005 void __iomem *ioaddr = tp->mmio_addr;
4007 /* Set DMA burst size and Interframe Gap Time */
4008 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4009 (InterFrameGap << TxInterFrameGapShift));
4012 static void rtl_hw_start(struct net_device *dev)
4014 struct rtl8169_private *tp = netdev_priv(dev);
4018 rtl_irq_enable_all(tp);
4021 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4022 void __iomem *ioaddr)
4025 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4026 * register to be written before TxDescAddrLow to work.
4027 * Switching from MMIO to I/O access fixes the issue as well.
4029 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4030 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4031 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4032 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4035 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4039 cmd = RTL_R16(CPlusCmd);
4040 RTL_W16(CPlusCmd, cmd);
4044 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4046 /* Low hurts. Let's disable the filtering. */
4047 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4050 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4052 static const struct rtl_cfg2_info {
4057 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4058 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4059 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4060 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4062 const struct rtl_cfg2_info *p = cfg2_info;
4066 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4067 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4068 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4069 RTL_W32(0x7c, p->val);
4075 static void rtl_set_rx_mode(struct net_device *dev)
4077 struct rtl8169_private *tp = netdev_priv(dev);
4078 void __iomem *ioaddr = tp->mmio_addr;
4079 u32 mc_filter[2]; /* Multicast hash filter */
4083 if (dev->flags & IFF_PROMISC) {
4084 /* Unconditionally log net taps. */
4085 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4087 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4089 mc_filter[1] = mc_filter[0] = 0xffffffff;
4090 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4091 (dev->flags & IFF_ALLMULTI)) {
4092 /* Too many to filter perfectly -- accept all multicasts. */
4093 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4094 mc_filter[1] = mc_filter[0] = 0xffffffff;
4096 struct netdev_hw_addr *ha;
4098 rx_mode = AcceptBroadcast | AcceptMyPhys;
4099 mc_filter[1] = mc_filter[0] = 0;
4100 netdev_for_each_mc_addr(ha, dev) {
4101 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4102 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4103 rx_mode |= AcceptMulticast;
4107 if (dev->features & NETIF_F_RXALL)
4108 rx_mode |= (AcceptErr | AcceptRunt);
4110 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4112 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4113 u32 data = mc_filter[0];
4115 mc_filter[0] = swab32(mc_filter[1]);
4116 mc_filter[1] = swab32(data);
4119 RTL_W32(MAR0 + 4, mc_filter[1]);
4120 RTL_W32(MAR0 + 0, mc_filter[0]);
4122 RTL_W32(RxConfig, tmp);
4125 static void rtl_hw_start_8169(struct net_device *dev)
4127 struct rtl8169_private *tp = netdev_priv(dev);
4128 void __iomem *ioaddr = tp->mmio_addr;
4129 struct pci_dev *pdev = tp->pci_dev;
4131 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4132 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4133 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4136 RTL_W8(Cfg9346, Cfg9346_Unlock);
4137 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4138 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4139 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4140 tp->mac_version == RTL_GIGA_MAC_VER_04)
4141 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4145 RTL_W8(EarlyTxThres, NoEarlyTx);
4147 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4149 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4150 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4151 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4152 tp->mac_version == RTL_GIGA_MAC_VER_04)
4153 rtl_set_rx_tx_config_registers(tp);
4155 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4157 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4158 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4159 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4160 "Bit-3 and bit-14 MUST be 1\n");
4161 tp->cp_cmd |= (1 << 14);
4164 RTL_W16(CPlusCmd, tp->cp_cmd);
4166 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4169 * Undocumented corner. Supposedly:
4170 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4172 RTL_W16(IntrMitigate, 0x0000);
4174 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4176 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4177 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4178 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4179 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4180 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4181 rtl_set_rx_tx_config_registers(tp);
4184 RTL_W8(Cfg9346, Cfg9346_Lock);
4186 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4189 RTL_W32(RxMissed, 0);
4191 rtl_set_rx_mode(dev);
4193 /* no early-rx interrupts */
4194 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4197 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4201 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4202 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4205 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4207 rtl_csi_access_enable(ioaddr, 0x17000000);
4210 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4212 rtl_csi_access_enable(ioaddr, 0x27000000);
4216 unsigned int offset;
4221 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4226 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4227 rtl_ephy_write(ioaddr, e->offset, w);
4232 static void rtl_disable_clock_request(struct pci_dev *pdev)
4234 int cap = pci_pcie_cap(pdev);
4239 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4240 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4241 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4245 static void rtl_enable_clock_request(struct pci_dev *pdev)
4247 int cap = pci_pcie_cap(pdev);
4252 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4253 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4254 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4258 #define R8168_CPCMD_QUIRK_MASK (\
4269 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4271 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4273 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4275 rtl_tx_performance_tweak(pdev,
4276 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4279 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4281 rtl_hw_start_8168bb(ioaddr, pdev);
4283 RTL_W8(MaxTxPacketSize, TxPacketMax);
4285 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4288 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4290 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4292 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4294 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4296 rtl_disable_clock_request(pdev);
4298 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4301 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4303 static const struct ephy_info e_info_8168cp[] = {
4304 { 0x01, 0, 0x0001 },
4305 { 0x02, 0x0800, 0x1000 },
4306 { 0x03, 0, 0x0042 },
4307 { 0x06, 0x0080, 0x0000 },
4311 rtl_csi_access_enable_2(ioaddr);
4313 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4315 __rtl_hw_start_8168cp(ioaddr, pdev);
4318 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4320 rtl_csi_access_enable_2(ioaddr);
4322 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4324 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4326 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4329 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4331 rtl_csi_access_enable_2(ioaddr);
4333 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4336 RTL_W8(DBG_REG, 0x20);
4338 RTL_W8(MaxTxPacketSize, TxPacketMax);
4340 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4342 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4345 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4347 static const struct ephy_info e_info_8168c_1[] = {
4348 { 0x02, 0x0800, 0x1000 },
4349 { 0x03, 0, 0x0002 },
4350 { 0x06, 0x0080, 0x0000 }
4353 rtl_csi_access_enable_2(ioaddr);
4355 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4357 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4359 __rtl_hw_start_8168cp(ioaddr, pdev);
4362 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4364 static const struct ephy_info e_info_8168c_2[] = {
4365 { 0x01, 0, 0x0001 },
4366 { 0x03, 0x0400, 0x0220 }
4369 rtl_csi_access_enable_2(ioaddr);
4371 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4373 __rtl_hw_start_8168cp(ioaddr, pdev);
4376 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4378 rtl_hw_start_8168c_2(ioaddr, pdev);
4381 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4383 rtl_csi_access_enable_2(ioaddr);
4385 __rtl_hw_start_8168cp(ioaddr, pdev);
4388 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4390 rtl_csi_access_enable_2(ioaddr);
4392 rtl_disable_clock_request(pdev);
4394 RTL_W8(MaxTxPacketSize, TxPacketMax);
4396 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4398 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4401 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4403 rtl_csi_access_enable_1(ioaddr);
4405 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4407 RTL_W8(MaxTxPacketSize, TxPacketMax);
4409 rtl_disable_clock_request(pdev);
4412 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4414 static const struct ephy_info e_info_8168d_4[] = {
4416 { 0x19, 0x20, 0x50 },
4421 rtl_csi_access_enable_1(ioaddr);
4423 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4425 RTL_W8(MaxTxPacketSize, TxPacketMax);
4427 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4428 const struct ephy_info *e = e_info_8168d_4 + i;
4431 w = rtl_ephy_read(ioaddr, e->offset);
4432 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4435 rtl_enable_clock_request(pdev);
4438 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4440 static const struct ephy_info e_info_8168e_1[] = {
4441 { 0x00, 0x0200, 0x0100 },
4442 { 0x00, 0x0000, 0x0004 },
4443 { 0x06, 0x0002, 0x0001 },
4444 { 0x06, 0x0000, 0x0030 },
4445 { 0x07, 0x0000, 0x2000 },
4446 { 0x00, 0x0000, 0x0020 },
4447 { 0x03, 0x5800, 0x2000 },
4448 { 0x03, 0x0000, 0x0001 },
4449 { 0x01, 0x0800, 0x1000 },
4450 { 0x07, 0x0000, 0x4000 },
4451 { 0x1e, 0x0000, 0x2000 },
4452 { 0x19, 0xffff, 0xfe6c },
4453 { 0x0a, 0x0000, 0x0040 }
4456 rtl_csi_access_enable_2(ioaddr);
4458 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4460 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4462 RTL_W8(MaxTxPacketSize, TxPacketMax);
4464 rtl_disable_clock_request(pdev);
4466 /* Reset tx FIFO pointer */
4467 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4468 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4470 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4473 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4475 static const struct ephy_info e_info_8168e_2[] = {
4476 { 0x09, 0x0000, 0x0080 },
4477 { 0x19, 0x0000, 0x0224 }
4480 rtl_csi_access_enable_1(ioaddr);
4482 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4484 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4486 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4487 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4488 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4489 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4490 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4491 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4492 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4493 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4496 RTL_W8(MaxTxPacketSize, EarlySize);
4498 rtl_disable_clock_request(pdev);
4500 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4501 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4503 /* Adjust EEE LED frequency */
4504 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4506 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4507 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4508 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4511 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4513 static const struct ephy_info e_info_8168f_1[] = {
4514 { 0x06, 0x00c0, 0x0020 },
4515 { 0x08, 0x0001, 0x0002 },
4516 { 0x09, 0x0000, 0x0080 },
4517 { 0x19, 0x0000, 0x0224 }
4520 rtl_csi_access_enable_1(ioaddr);
4522 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4524 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4526 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4527 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4528 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4529 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4530 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4531 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4532 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4533 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4534 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4535 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4536 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4539 RTL_W8(MaxTxPacketSize, EarlySize);
4541 rtl_disable_clock_request(pdev);
4543 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4544 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4546 /* Adjust EEE LED frequency */
4547 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4549 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4550 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4551 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4554 static void rtl_hw_start_8168(struct net_device *dev)
4556 struct rtl8169_private *tp = netdev_priv(dev);
4557 void __iomem *ioaddr = tp->mmio_addr;
4558 struct pci_dev *pdev = tp->pci_dev;
4560 RTL_W8(Cfg9346, Cfg9346_Unlock);
4562 RTL_W8(MaxTxPacketSize, TxPacketMax);
4564 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4566 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4568 RTL_W16(CPlusCmd, tp->cp_cmd);
4570 RTL_W16(IntrMitigate, 0x5151);
4572 /* Work around for RxFIFO overflow. */
4573 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4574 tp->event_slow |= RxFIFOOver | PCSTimeout;
4575 tp->event_slow &= ~RxOverflow;
4578 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4580 rtl_set_rx_mode(dev);
4582 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4583 (InterFrameGap << TxInterFrameGapShift));
4587 switch (tp->mac_version) {
4588 case RTL_GIGA_MAC_VER_11:
4589 rtl_hw_start_8168bb(ioaddr, pdev);
4592 case RTL_GIGA_MAC_VER_12:
4593 case RTL_GIGA_MAC_VER_17:
4594 rtl_hw_start_8168bef(ioaddr, pdev);
4597 case RTL_GIGA_MAC_VER_18:
4598 rtl_hw_start_8168cp_1(ioaddr, pdev);
4601 case RTL_GIGA_MAC_VER_19:
4602 rtl_hw_start_8168c_1(ioaddr, pdev);
4605 case RTL_GIGA_MAC_VER_20:
4606 rtl_hw_start_8168c_2(ioaddr, pdev);
4609 case RTL_GIGA_MAC_VER_21:
4610 rtl_hw_start_8168c_3(ioaddr, pdev);
4613 case RTL_GIGA_MAC_VER_22:
4614 rtl_hw_start_8168c_4(ioaddr, pdev);
4617 case RTL_GIGA_MAC_VER_23:
4618 rtl_hw_start_8168cp_2(ioaddr, pdev);
4621 case RTL_GIGA_MAC_VER_24:
4622 rtl_hw_start_8168cp_3(ioaddr, pdev);
4625 case RTL_GIGA_MAC_VER_25:
4626 case RTL_GIGA_MAC_VER_26:
4627 case RTL_GIGA_MAC_VER_27:
4628 rtl_hw_start_8168d(ioaddr, pdev);
4631 case RTL_GIGA_MAC_VER_28:
4632 rtl_hw_start_8168d_4(ioaddr, pdev);
4635 case RTL_GIGA_MAC_VER_31:
4636 rtl_hw_start_8168dp(ioaddr, pdev);
4639 case RTL_GIGA_MAC_VER_32:
4640 case RTL_GIGA_MAC_VER_33:
4641 rtl_hw_start_8168e_1(ioaddr, pdev);
4643 case RTL_GIGA_MAC_VER_34:
4644 rtl_hw_start_8168e_2(ioaddr, pdev);
4647 case RTL_GIGA_MAC_VER_35:
4648 case RTL_GIGA_MAC_VER_36:
4649 rtl_hw_start_8168f_1(ioaddr, pdev);
4653 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4654 dev->name, tp->mac_version);
4658 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4660 RTL_W8(Cfg9346, Cfg9346_Lock);
4662 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4665 #define R810X_CPCMD_QUIRK_MASK (\
4676 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4678 static const struct ephy_info e_info_8102e_1[] = {
4679 { 0x01, 0, 0x6e65 },
4680 { 0x02, 0, 0x091f },
4681 { 0x03, 0, 0xc2f9 },
4682 { 0x06, 0, 0xafb5 },
4683 { 0x07, 0, 0x0e00 },
4684 { 0x19, 0, 0xec80 },
4685 { 0x01, 0, 0x2e65 },
4690 rtl_csi_access_enable_2(ioaddr);
4692 RTL_W8(DBG_REG, FIX_NAK_1);
4694 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4697 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4698 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4700 cfg1 = RTL_R8(Config1);
4701 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4702 RTL_W8(Config1, cfg1 & ~LEDS0);
4704 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4707 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4709 rtl_csi_access_enable_2(ioaddr);
4711 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4713 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4714 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4717 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4719 rtl_hw_start_8102e_2(ioaddr, pdev);
4721 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4724 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4726 static const struct ephy_info e_info_8105e_1[] = {
4727 { 0x07, 0, 0x4000 },
4728 { 0x19, 0, 0x0200 },
4729 { 0x19, 0, 0x0020 },
4730 { 0x1e, 0, 0x2000 },
4731 { 0x03, 0, 0x0001 },
4732 { 0x19, 0, 0x0100 },
4733 { 0x19, 0, 0x0004 },
4737 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4738 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4740 /* Disable Early Tally Counter */
4741 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4743 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4744 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4746 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4749 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4751 rtl_hw_start_8105e_1(ioaddr, pdev);
4752 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4755 static void rtl_hw_start_8101(struct net_device *dev)
4757 struct rtl8169_private *tp = netdev_priv(dev);
4758 void __iomem *ioaddr = tp->mmio_addr;
4759 struct pci_dev *pdev = tp->pci_dev;
4761 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4762 tp->event_slow &= ~RxFIFOOver;
4764 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4765 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4766 int cap = pci_pcie_cap(pdev);
4769 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4770 PCI_EXP_DEVCTL_NOSNOOP_EN);
4774 RTL_W8(Cfg9346, Cfg9346_Unlock);
4776 switch (tp->mac_version) {
4777 case RTL_GIGA_MAC_VER_07:
4778 rtl_hw_start_8102e_1(ioaddr, pdev);
4781 case RTL_GIGA_MAC_VER_08:
4782 rtl_hw_start_8102e_3(ioaddr, pdev);
4785 case RTL_GIGA_MAC_VER_09:
4786 rtl_hw_start_8102e_2(ioaddr, pdev);
4789 case RTL_GIGA_MAC_VER_29:
4790 rtl_hw_start_8105e_1(ioaddr, pdev);
4792 case RTL_GIGA_MAC_VER_30:
4793 rtl_hw_start_8105e_2(ioaddr, pdev);
4797 RTL_W8(Cfg9346, Cfg9346_Lock);
4799 RTL_W8(MaxTxPacketSize, TxPacketMax);
4801 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4803 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4804 RTL_W16(CPlusCmd, tp->cp_cmd);
4806 RTL_W16(IntrMitigate, 0x0000);
4808 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4810 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4811 rtl_set_rx_tx_config_registers(tp);
4815 rtl_set_rx_mode(dev);
4817 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4820 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4822 struct rtl8169_private *tp = netdev_priv(dev);
4824 if (new_mtu < ETH_ZLEN ||
4825 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4828 if (new_mtu > ETH_DATA_LEN)
4829 rtl_hw_jumbo_enable(tp);
4831 rtl_hw_jumbo_disable(tp);
4834 netdev_update_features(dev);
4839 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4841 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4842 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4845 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4846 void **data_buff, struct RxDesc *desc)
4848 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4853 rtl8169_make_unusable_by_asic(desc);
4856 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4858 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4860 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4863 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4866 desc->addr = cpu_to_le64(mapping);
4868 rtl8169_mark_to_asic(desc, rx_buf_sz);
4871 static inline void *rtl8169_align(void *data)
4873 return (void *)ALIGN((long)data, 16);
4876 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4877 struct RxDesc *desc)
4881 struct device *d = &tp->pci_dev->dev;
4882 struct net_device *dev = tp->dev;
4883 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4885 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4889 if (rtl8169_align(data) != data) {
4891 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4896 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4898 if (unlikely(dma_mapping_error(d, mapping))) {
4899 if (net_ratelimit())
4900 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4904 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4912 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4916 for (i = 0; i < NUM_RX_DESC; i++) {
4917 if (tp->Rx_databuff[i]) {
4918 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4919 tp->RxDescArray + i);
4924 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4926 desc->opts1 |= cpu_to_le32(RingEnd);
4929 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4933 for (i = 0; i < NUM_RX_DESC; i++) {
4936 if (tp->Rx_databuff[i])
4939 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4941 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4944 tp->Rx_databuff[i] = data;
4947 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4951 rtl8169_rx_clear(tp);
4955 static int rtl8169_init_ring(struct net_device *dev)
4957 struct rtl8169_private *tp = netdev_priv(dev);
4959 rtl8169_init_ring_indexes(tp);
4961 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4962 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4964 return rtl8169_rx_fill(tp);
4967 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4968 struct TxDesc *desc)
4970 unsigned int len = tx_skb->len;
4972 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4980 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4985 for (i = 0; i < n; i++) {
4986 unsigned int entry = (start + i) % NUM_TX_DESC;
4987 struct ring_info *tx_skb = tp->tx_skb + entry;
4988 unsigned int len = tx_skb->len;
4991 struct sk_buff *skb = tx_skb->skb;
4993 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4994 tp->TxDescArray + entry);
4996 tp->dev->stats.tx_dropped++;
5004 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5006 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5007 tp->cur_tx = tp->dirty_tx = 0;
5008 netdev_reset_queue(tp->dev);
5011 static void rtl_reset_work(struct rtl8169_private *tp)
5013 struct net_device *dev = tp->dev;
5016 napi_disable(&tp->napi);
5017 netif_stop_queue(dev);
5018 synchronize_sched();
5020 rtl8169_hw_reset(tp);
5022 for (i = 0; i < NUM_RX_DESC; i++)
5023 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5025 rtl8169_tx_clear(tp);
5026 rtl8169_init_ring_indexes(tp);
5028 napi_enable(&tp->napi);
5030 netif_wake_queue(dev);
5031 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5034 static void rtl8169_tx_timeout(struct net_device *dev)
5036 struct rtl8169_private *tp = netdev_priv(dev);
5038 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5041 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5044 struct skb_shared_info *info = skb_shinfo(skb);
5045 unsigned int cur_frag, entry;
5046 struct TxDesc * uninitialized_var(txd);
5047 struct device *d = &tp->pci_dev->dev;
5050 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5051 const skb_frag_t *frag = info->frags + cur_frag;
5056 entry = (entry + 1) % NUM_TX_DESC;
5058 txd = tp->TxDescArray + entry;
5059 len = skb_frag_size(frag);
5060 addr = skb_frag_address(frag);
5061 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5062 if (unlikely(dma_mapping_error(d, mapping))) {
5063 if (net_ratelimit())
5064 netif_err(tp, drv, tp->dev,
5065 "Failed to map TX fragments DMA!\n");
5069 /* Anti gcc 2.95.3 bugware (sic) */
5070 status = opts[0] | len |
5071 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5073 txd->opts1 = cpu_to_le32(status);
5074 txd->opts2 = cpu_to_le32(opts[1]);
5075 txd->addr = cpu_to_le64(mapping);
5077 tp->tx_skb[entry].len = len;
5081 tp->tx_skb[entry].skb = skb;
5082 txd->opts1 |= cpu_to_le32(LastFrag);
5088 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5092 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5093 struct sk_buff *skb, u32 *opts)
5095 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5096 u32 mss = skb_shinfo(skb)->gso_size;
5097 int offset = info->opts_offset;
5101 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5102 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5103 const struct iphdr *ip = ip_hdr(skb);
5105 if (ip->protocol == IPPROTO_TCP)
5106 opts[offset] |= info->checksum.tcp;
5107 else if (ip->protocol == IPPROTO_UDP)
5108 opts[offset] |= info->checksum.udp;
5114 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5115 struct net_device *dev)
5117 struct rtl8169_private *tp = netdev_priv(dev);
5118 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5119 struct TxDesc *txd = tp->TxDescArray + entry;
5120 void __iomem *ioaddr = tp->mmio_addr;
5121 struct device *d = &tp->pci_dev->dev;
5127 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5128 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5132 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5135 len = skb_headlen(skb);
5136 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5137 if (unlikely(dma_mapping_error(d, mapping))) {
5138 if (net_ratelimit())
5139 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5143 tp->tx_skb[entry].len = len;
5144 txd->addr = cpu_to_le64(mapping);
5146 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5149 rtl8169_tso_csum(tp, skb, opts);
5151 frags = rtl8169_xmit_frags(tp, skb, opts);
5155 opts[0] |= FirstFrag;
5157 opts[0] |= FirstFrag | LastFrag;
5158 tp->tx_skb[entry].skb = skb;
5161 txd->opts2 = cpu_to_le32(opts[1]);
5163 netdev_sent_queue(dev, skb->len);
5165 skb_tx_timestamp(skb);
5169 /* Anti gcc 2.95.3 bugware (sic) */
5170 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5171 txd->opts1 = cpu_to_le32(status);
5173 tp->cur_tx += frags + 1;
5177 RTL_W8(TxPoll, NPQ);
5181 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5182 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5183 * not miss a ring update when it notices a stopped queue.
5186 netif_stop_queue(dev);
5187 /* Sync with rtl_tx:
5188 * - publish queue status and cur_tx ring index (write barrier)
5189 * - refresh dirty_tx ring index (read barrier).
5190 * May the current thread have a pessimistic view of the ring
5191 * status and forget to wake up queue, a racing rtl_tx thread
5195 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5196 netif_wake_queue(dev);
5199 return NETDEV_TX_OK;
5202 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5205 dev->stats.tx_dropped++;
5206 return NETDEV_TX_OK;
5209 netif_stop_queue(dev);
5210 dev->stats.tx_dropped++;
5211 return NETDEV_TX_BUSY;
5214 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5216 struct rtl8169_private *tp = netdev_priv(dev);
5217 struct pci_dev *pdev = tp->pci_dev;
5218 u16 pci_status, pci_cmd;
5220 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5221 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5223 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5224 pci_cmd, pci_status);
5227 * The recovery sequence below admits a very elaborated explanation:
5228 * - it seems to work;
5229 * - I did not see what else could be done;
5230 * - it makes iop3xx happy.
5232 * Feel free to adjust to your needs.
5234 if (pdev->broken_parity_status)
5235 pci_cmd &= ~PCI_COMMAND_PARITY;
5237 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5239 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5241 pci_write_config_word(pdev, PCI_STATUS,
5242 pci_status & (PCI_STATUS_DETECTED_PARITY |
5243 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5244 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5246 /* The infamous DAC f*ckup only happens at boot time */
5247 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5248 void __iomem *ioaddr = tp->mmio_addr;
5250 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5251 tp->cp_cmd &= ~PCIDAC;
5252 RTL_W16(CPlusCmd, tp->cp_cmd);
5253 dev->features &= ~NETIF_F_HIGHDMA;
5256 rtl8169_hw_reset(tp);
5258 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5266 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5268 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5269 unsigned int dirty_tx, tx_left;
5270 struct rtl_txc txc = { 0, 0 };
5272 dirty_tx = tp->dirty_tx;
5274 tx_left = tp->cur_tx - dirty_tx;
5276 while (tx_left > 0) {
5277 unsigned int entry = dirty_tx % NUM_TX_DESC;
5278 struct ring_info *tx_skb = tp->tx_skb + entry;
5282 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5283 if (status & DescOwn)
5286 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5287 tp->TxDescArray + entry);
5288 if (status & LastFrag) {
5289 struct sk_buff *skb = tx_skb->skb;
5292 txc.bytes += skb->len;
5300 u64_stats_update_begin(&tx_stats->syncp);
5301 tx_stats->packets += txc.packets;
5302 tx_stats->bytes += txc.bytes;
5303 u64_stats_update_end(&tx_stats->syncp);
5305 netdev_completed_queue(dev, txc.packets, txc.bytes);
5307 if (tp->dirty_tx != dirty_tx) {
5308 tp->dirty_tx = dirty_tx;
5309 /* Sync with rtl8169_start_xmit:
5310 * - publish dirty_tx ring index (write barrier)
5311 * - refresh cur_tx ring index and queue status (read barrier)
5312 * May the current thread miss the stopped queue condition,
5313 * a racing xmit thread can only have a right view of the
5317 if (netif_queue_stopped(dev) &&
5318 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5319 netif_wake_queue(dev);
5322 * 8168 hack: TxPoll requests are lost when the Tx packets are
5323 * too close. Let's kick an extra TxPoll request when a burst
5324 * of start_xmit activity is detected (if it is not detected,
5325 * it is slow enough). -- FR
5327 if (tp->cur_tx != dirty_tx) {
5328 void __iomem *ioaddr = tp->mmio_addr;
5330 RTL_W8(TxPoll, NPQ);
5335 static inline int rtl8169_fragmented_frame(u32 status)
5337 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5340 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5342 u32 status = opts1 & RxProtoMask;
5344 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5345 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5346 skb->ip_summed = CHECKSUM_UNNECESSARY;
5348 skb_checksum_none_assert(skb);
5351 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5352 struct rtl8169_private *tp,
5356 struct sk_buff *skb;
5357 struct device *d = &tp->pci_dev->dev;
5359 data = rtl8169_align(data);
5360 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5362 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5364 memcpy(skb->data, data, pkt_size);
5365 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5370 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5372 unsigned int cur_rx, rx_left;
5375 cur_rx = tp->cur_rx;
5376 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5377 rx_left = min(rx_left, budget);
5379 for (; rx_left > 0; rx_left--, cur_rx++) {
5380 unsigned int entry = cur_rx % NUM_RX_DESC;
5381 struct RxDesc *desc = tp->RxDescArray + entry;
5385 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5387 if (status & DescOwn)
5389 if (unlikely(status & RxRES)) {
5390 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5392 dev->stats.rx_errors++;
5393 if (status & (RxRWT | RxRUNT))
5394 dev->stats.rx_length_errors++;
5396 dev->stats.rx_crc_errors++;
5397 if (status & RxFOVF) {
5398 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5399 dev->stats.rx_fifo_errors++;
5401 if ((status & (RxRUNT | RxCRC)) &&
5402 !(status & (RxRWT | RxFOVF)) &&
5403 (dev->features & NETIF_F_RXALL))
5406 rtl8169_mark_to_asic(desc, rx_buf_sz);
5408 struct sk_buff *skb;
5413 addr = le64_to_cpu(desc->addr);
5414 if (likely(!(dev->features & NETIF_F_RXFCS)))
5415 pkt_size = (status & 0x00003fff) - 4;
5417 pkt_size = status & 0x00003fff;
5420 * The driver does not support incoming fragmented
5421 * frames. They are seen as a symptom of over-mtu
5424 if (unlikely(rtl8169_fragmented_frame(status))) {
5425 dev->stats.rx_dropped++;
5426 dev->stats.rx_length_errors++;
5427 rtl8169_mark_to_asic(desc, rx_buf_sz);
5431 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5432 tp, pkt_size, addr);
5433 rtl8169_mark_to_asic(desc, rx_buf_sz);
5435 dev->stats.rx_dropped++;
5439 rtl8169_rx_csum(skb, status);
5440 skb_put(skb, pkt_size);
5441 skb->protocol = eth_type_trans(skb, dev);
5443 rtl8169_rx_vlan_tag(desc, skb);
5445 napi_gro_receive(&tp->napi, skb);
5447 u64_stats_update_begin(&tp->rx_stats.syncp);
5448 tp->rx_stats.packets++;
5449 tp->rx_stats.bytes += pkt_size;
5450 u64_stats_update_end(&tp->rx_stats.syncp);
5453 /* Work around for AMD plateform. */
5454 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5455 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5461 count = cur_rx - tp->cur_rx;
5462 tp->cur_rx = cur_rx;
5464 tp->dirty_rx += count;
5469 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5471 struct net_device *dev = dev_instance;
5472 struct rtl8169_private *tp = netdev_priv(dev);
5476 status = rtl_get_events(tp);
5477 if (status && status != 0xffff) {
5478 status &= RTL_EVENT_NAPI | tp->event_slow;
5482 rtl_irq_disable(tp);
5483 napi_schedule(&tp->napi);
5486 return IRQ_RETVAL(handled);
5490 * Workqueue context.
5492 static void rtl_slow_event_work(struct rtl8169_private *tp)
5494 struct net_device *dev = tp->dev;
5497 status = rtl_get_events(tp) & tp->event_slow;
5498 rtl_ack_events(tp, status);
5500 if (unlikely(status & RxFIFOOver)) {
5501 switch (tp->mac_version) {
5502 /* Work around for rx fifo overflow */
5503 case RTL_GIGA_MAC_VER_11:
5504 netif_stop_queue(dev);
5505 /* XXX - Hack alert. See rtl_task(). */
5506 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5512 if (unlikely(status & SYSErr))
5513 rtl8169_pcierr_interrupt(dev);
5515 if (status & LinkChg)
5516 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5518 napi_disable(&tp->napi);
5519 rtl_irq_disable(tp);
5521 napi_enable(&tp->napi);
5522 napi_schedule(&tp->napi);
5525 static void rtl_task(struct work_struct *work)
5527 static const struct {
5529 void (*action)(struct rtl8169_private *);
5531 /* XXX - keep rtl_slow_event_work() as first element. */
5532 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5533 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5534 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5536 struct rtl8169_private *tp =
5537 container_of(work, struct rtl8169_private, wk.work);
5538 struct net_device *dev = tp->dev;
5543 if (!netif_running(dev) ||
5544 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5547 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5550 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5552 rtl_work[i].action(tp);
5556 rtl_unlock_work(tp);
5559 static int rtl8169_poll(struct napi_struct *napi, int budget)
5561 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5562 struct net_device *dev = tp->dev;
5563 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5567 status = rtl_get_events(tp);
5568 rtl_ack_events(tp, status & ~tp->event_slow);
5570 if (status & RTL_EVENT_NAPI_RX)
5571 work_done = rtl_rx(dev, tp, (u32) budget);
5573 if (status & RTL_EVENT_NAPI_TX)
5576 if (status & tp->event_slow) {
5577 enable_mask &= ~tp->event_slow;
5579 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5582 if (work_done < budget) {
5583 napi_complete(napi);
5585 rtl_irq_enable(tp, enable_mask);
5592 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5594 struct rtl8169_private *tp = netdev_priv(dev);
5596 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5599 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5600 RTL_W32(RxMissed, 0);
5603 static void rtl8169_down(struct net_device *dev)
5605 struct rtl8169_private *tp = netdev_priv(dev);
5606 void __iomem *ioaddr = tp->mmio_addr;
5608 del_timer_sync(&tp->timer);
5610 napi_disable(&tp->napi);
5611 netif_stop_queue(dev);
5613 rtl8169_hw_reset(tp);
5615 * At this point device interrupts can not be enabled in any function,
5616 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5617 * and napi is disabled (rtl8169_poll).
5619 rtl8169_rx_missed(dev, ioaddr);
5621 /* Give a racing hard_start_xmit a few cycles to complete. */
5622 synchronize_sched();
5624 rtl8169_tx_clear(tp);
5626 rtl8169_rx_clear(tp);
5628 rtl_pll_power_down(tp);
5631 static int rtl8169_close(struct net_device *dev)
5633 struct rtl8169_private *tp = netdev_priv(dev);
5634 struct pci_dev *pdev = tp->pci_dev;
5636 pm_runtime_get_sync(&pdev->dev);
5638 /* Update counters before going down */
5639 rtl8169_update_counters(dev);
5642 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5645 rtl_unlock_work(tp);
5647 free_irq(pdev->irq, dev);
5649 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5651 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5653 tp->TxDescArray = NULL;
5654 tp->RxDescArray = NULL;
5656 pm_runtime_put_sync(&pdev->dev);
5661 #ifdef CONFIG_NET_POLL_CONTROLLER
5662 static void rtl8169_netpoll(struct net_device *dev)
5664 struct rtl8169_private *tp = netdev_priv(dev);
5666 rtl8169_interrupt(tp->pci_dev->irq, dev);
5670 static int rtl_open(struct net_device *dev)
5672 struct rtl8169_private *tp = netdev_priv(dev);
5673 void __iomem *ioaddr = tp->mmio_addr;
5674 struct pci_dev *pdev = tp->pci_dev;
5675 int retval = -ENOMEM;
5677 pm_runtime_get_sync(&pdev->dev);
5680 * Rx and Tx desscriptors needs 256 bytes alignment.
5681 * dma_alloc_coherent provides more.
5683 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5684 &tp->TxPhyAddr, GFP_KERNEL);
5685 if (!tp->TxDescArray)
5686 goto err_pm_runtime_put;
5688 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5689 &tp->RxPhyAddr, GFP_KERNEL);
5690 if (!tp->RxDescArray)
5693 retval = rtl8169_init_ring(dev);
5697 INIT_WORK(&tp->wk.work, rtl_task);
5701 rtl_request_firmware(tp);
5703 retval = request_irq(pdev->irq, rtl8169_interrupt,
5704 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5707 goto err_release_fw_2;
5711 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5713 napi_enable(&tp->napi);
5715 rtl8169_init_phy(dev, tp);
5717 __rtl8169_set_features(dev, dev->features);
5719 rtl_pll_power_up(tp);
5723 netif_start_queue(dev);
5725 rtl_unlock_work(tp);
5727 tp->saved_wolopts = 0;
5728 tp->runtime_suspended = false;
5729 pm_runtime_put_noidle(&pdev->dev);
5731 rtl8169_check_link_status(dev, tp, ioaddr);
5736 rtl_release_firmware(tp);
5737 rtl8169_rx_clear(tp);
5739 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5741 tp->RxDescArray = NULL;
5743 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5745 tp->TxDescArray = NULL;
5747 pm_runtime_put_noidle(&pdev->dev);
5751 static struct rtnl_link_stats64 *
5752 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5754 struct rtl8169_private *tp = netdev_priv(dev);
5755 void __iomem *ioaddr = tp->mmio_addr;
5758 if (netif_running(dev))
5759 rtl8169_rx_missed(dev, ioaddr);
5762 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5763 stats->rx_packets = tp->rx_stats.packets;
5764 stats->rx_bytes = tp->rx_stats.bytes;
5765 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5769 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5770 stats->tx_packets = tp->tx_stats.packets;
5771 stats->tx_bytes = tp->tx_stats.bytes;
5772 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5774 stats->rx_dropped = dev->stats.rx_dropped;
5775 stats->tx_dropped = dev->stats.tx_dropped;
5776 stats->rx_length_errors = dev->stats.rx_length_errors;
5777 stats->rx_errors = dev->stats.rx_errors;
5778 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5779 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5780 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5785 static void rtl8169_net_suspend(struct net_device *dev)
5787 struct rtl8169_private *tp = netdev_priv(dev);
5789 if (!netif_running(dev))
5792 netif_device_detach(dev);
5793 netif_stop_queue(dev);
5796 napi_disable(&tp->napi);
5797 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5798 rtl_unlock_work(tp);
5800 rtl_pll_power_down(tp);
5805 static int rtl8169_suspend(struct device *device)
5807 struct pci_dev *pdev = to_pci_dev(device);
5808 struct net_device *dev = pci_get_drvdata(pdev);
5810 rtl8169_net_suspend(dev);
5815 static void __rtl8169_resume(struct net_device *dev)
5817 struct rtl8169_private *tp = netdev_priv(dev);
5819 netif_device_attach(dev);
5821 rtl_pll_power_up(tp);
5824 napi_enable(&tp->napi);
5825 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5826 rtl_unlock_work(tp);
5828 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5831 static int rtl8169_resume(struct device *device)
5833 struct pci_dev *pdev = to_pci_dev(device);
5834 struct net_device *dev = pci_get_drvdata(pdev);
5835 struct rtl8169_private *tp = netdev_priv(dev);
5837 rtl8169_init_phy(dev, tp);
5839 if (netif_running(dev))
5840 __rtl8169_resume(dev);
5845 static int rtl8169_runtime_suspend(struct device *device)
5847 struct pci_dev *pdev = to_pci_dev(device);
5848 struct net_device *dev = pci_get_drvdata(pdev);
5849 struct rtl8169_private *tp = netdev_priv(dev);
5851 if (!tp->TxDescArray)
5855 tp->saved_wolopts = __rtl8169_get_wol(tp);
5856 __rtl8169_set_wol(tp, WAKE_ANY);
5857 tp->runtime_suspended = true;
5858 rtl_unlock_work(tp);
5860 rtl8169_net_suspend(dev);
5865 static int rtl8169_runtime_resume(struct device *device)
5867 struct pci_dev *pdev = to_pci_dev(device);
5868 struct net_device *dev = pci_get_drvdata(pdev);
5869 struct rtl8169_private *tp = netdev_priv(dev);
5871 if (!tp->TxDescArray)
5875 __rtl8169_set_wol(tp, tp->saved_wolopts);
5876 tp->saved_wolopts = 0;
5877 tp->runtime_suspended = false;
5878 rtl_unlock_work(tp);
5880 rtl8169_init_phy(dev, tp);
5882 __rtl8169_resume(dev);
5887 static int rtl8169_runtime_idle(struct device *device)
5889 struct pci_dev *pdev = to_pci_dev(device);
5890 struct net_device *dev = pci_get_drvdata(pdev);
5891 struct rtl8169_private *tp = netdev_priv(dev);
5893 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5894 return tp->TxDescArray ? -EBUSY : 0;
5897 static const struct dev_pm_ops rtl8169_pm_ops = {
5898 .suspend = rtl8169_suspend,
5899 .resume = rtl8169_resume,
5900 .freeze = rtl8169_suspend,
5901 .thaw = rtl8169_resume,
5902 .poweroff = rtl8169_suspend,
5903 .restore = rtl8169_resume,
5904 .runtime_suspend = rtl8169_runtime_suspend,
5905 .runtime_resume = rtl8169_runtime_resume,
5906 .runtime_idle = rtl8169_runtime_idle,
5909 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5911 #else /* !CONFIG_PM */
5913 #define RTL8169_PM_OPS NULL
5915 #endif /* !CONFIG_PM */
5917 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5919 void __iomem *ioaddr = tp->mmio_addr;
5921 /* WoL fails with 8168b when the receiver is disabled. */
5922 switch (tp->mac_version) {
5923 case RTL_GIGA_MAC_VER_11:
5924 case RTL_GIGA_MAC_VER_12:
5925 case RTL_GIGA_MAC_VER_17:
5926 pci_clear_master(tp->pci_dev);
5928 RTL_W8(ChipCmd, CmdRxEnb);
5937 static void rtl_shutdown(struct pci_dev *pdev)
5939 struct net_device *dev = pci_get_drvdata(pdev);
5940 struct rtl8169_private *tp = netdev_priv(dev);
5941 struct device *d = &pdev->dev;
5943 pm_runtime_get_sync(d);
5945 /* Get the device back to D0 state if it was runtime suspended. */
5946 if (tp->runtime_suspended)
5947 pci_set_power_state(pdev, PCI_D0);
5949 rtl8169_net_suspend(dev);
5951 /* Restore original MAC address */
5952 rtl_rar_set(tp, dev->perm_addr);
5954 rtl8169_hw_reset(tp);
5956 /* Restore WOL flags if they were messed around with. */
5957 if (tp->saved_wolopts)
5958 __rtl8169_set_wol(tp, tp->saved_wolopts);
5960 if (system_state == SYSTEM_POWER_OFF) {
5961 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5962 rtl_wol_suspend_quirk(tp);
5963 rtl_wol_shutdown_quirk(tp);
5966 pci_wake_from_d3(pdev, true);
5967 pci_set_power_state(pdev, PCI_D3hot);
5970 pm_runtime_put_noidle(d);
5973 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5975 struct net_device *dev = pci_get_drvdata(pdev);
5976 struct rtl8169_private *tp = netdev_priv(dev);
5978 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5979 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5980 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5981 rtl8168_driver_stop(tp);
5984 cancel_work_sync(&tp->wk.work);
5986 unregister_netdev(dev);
5988 rtl_release_firmware(tp);
5990 if (pci_dev_run_wake(pdev))
5991 pm_runtime_get_noresume(&pdev->dev);
5993 /* restore original MAC address */
5994 rtl_rar_set(tp, dev->perm_addr);
5996 rtl_disable_msi(pdev, tp);
5997 rtl8169_release_board(pdev, dev, tp->mmio_addr);
5998 pci_set_drvdata(pdev, NULL);
6001 static const struct net_device_ops rtl_netdev_ops = {
6002 .ndo_open = rtl_open,
6003 .ndo_stop = rtl8169_close,
6004 .ndo_get_stats64 = rtl8169_get_stats64,
6005 .ndo_start_xmit = rtl8169_start_xmit,
6006 .ndo_tx_timeout = rtl8169_tx_timeout,
6007 .ndo_validate_addr = eth_validate_addr,
6008 .ndo_change_mtu = rtl8169_change_mtu,
6009 .ndo_fix_features = rtl8169_fix_features,
6010 .ndo_set_features = rtl8169_set_features,
6011 .ndo_set_mac_address = rtl_set_mac_address,
6012 .ndo_do_ioctl = rtl8169_ioctl,
6013 .ndo_set_rx_mode = rtl_set_rx_mode,
6014 #ifdef CONFIG_NET_POLL_CONTROLLER
6015 .ndo_poll_controller = rtl8169_netpoll,
6020 static const struct rtl_cfg_info {
6021 void (*hw_start)(struct net_device *);
6022 unsigned int region;
6027 } rtl_cfg_infos [] = {
6029 .hw_start = rtl_hw_start_8169,
6032 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6033 .features = RTL_FEATURE_GMII,
6034 .default_ver = RTL_GIGA_MAC_VER_01,
6037 .hw_start = rtl_hw_start_8168,
6040 .event_slow = SYSErr | LinkChg | RxOverflow,
6041 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6042 .default_ver = RTL_GIGA_MAC_VER_11,
6045 .hw_start = rtl_hw_start_8101,
6048 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6050 .features = RTL_FEATURE_MSI,
6051 .default_ver = RTL_GIGA_MAC_VER_13,
6055 /* Cfg9346_Unlock assumed. */
6056 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6057 const struct rtl_cfg_info *cfg)
6059 void __iomem *ioaddr = tp->mmio_addr;
6063 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6064 if (cfg->features & RTL_FEATURE_MSI) {
6065 if (pci_enable_msi(tp->pci_dev)) {
6066 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6069 msi = RTL_FEATURE_MSI;
6072 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6073 RTL_W8(Config2, cfg2);
6077 static int __devinit
6078 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6080 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6081 const unsigned int region = cfg->region;
6082 struct rtl8169_private *tp;
6083 struct mii_if_info *mii;
6084 struct net_device *dev;
6085 void __iomem *ioaddr;
6089 if (netif_msg_drv(&debug)) {
6090 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6091 MODULENAME, RTL8169_VERSION);
6094 dev = alloc_etherdev(sizeof (*tp));
6100 SET_NETDEV_DEV(dev, &pdev->dev);
6101 dev->netdev_ops = &rtl_netdev_ops;
6102 tp = netdev_priv(dev);
6105 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6109 mii->mdio_read = rtl_mdio_read;
6110 mii->mdio_write = rtl_mdio_write;
6111 mii->phy_id_mask = 0x1f;
6112 mii->reg_num_mask = 0x1f;
6113 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6115 /* disable ASPM completely as that cause random device stop working
6116 * problems as well as full system hangs for some PCIe devices users */
6118 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6119 PCIE_LINK_STATE_L1 |
6120 PCIE_LINK_STATE_CLKPM);
6121 dprintk("ASPM disabled");
6124 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6125 rc = pci_enable_device(pdev);
6127 netif_err(tp, probe, dev, "enable failure\n");
6128 goto err_out_free_dev_1;
6131 if (pci_set_mwi(pdev) < 0)
6132 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6134 /* make sure PCI base addr 1 is MMIO */
6135 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6136 netif_err(tp, probe, dev,
6137 "region #%d not an MMIO resource, aborting\n",
6143 /* check for weird/broken PCI region reporting */
6144 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6145 netif_err(tp, probe, dev,
6146 "Invalid PCI region size(s), aborting\n");
6151 rc = pci_request_regions(pdev, MODULENAME);
6153 netif_err(tp, probe, dev, "could not request regions\n");
6157 tp->cp_cmd = RxChkSum;
6159 if ((sizeof(dma_addr_t) > 4) &&
6160 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6161 tp->cp_cmd |= PCIDAC;
6162 dev->features |= NETIF_F_HIGHDMA;
6164 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6166 netif_err(tp, probe, dev, "DMA configuration failed\n");
6167 goto err_out_free_res_3;
6171 /* ioremap MMIO region */
6172 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6174 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6176 goto err_out_free_res_3;
6178 tp->mmio_addr = ioaddr;
6180 if (!pci_is_pcie(pdev))
6181 netif_info(tp, probe, dev, "not PCI Express\n");
6183 /* Identify chip attached to board */
6184 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6188 rtl_irq_disable(tp);
6192 rtl_ack_events(tp, 0xffff);
6194 pci_set_master(pdev);
6197 * Pretend we are using VLANs; This bypasses a nasty bug where
6198 * Interrupts stop flowing on high load on 8110SCd controllers.
6200 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6201 tp->cp_cmd |= RxVlan;
6203 rtl_init_mdio_ops(tp);
6204 rtl_init_pll_power_ops(tp);
6205 rtl_init_jumbo_ops(tp);
6207 rtl8169_print_mac_version(tp);
6209 chipset = tp->mac_version;
6210 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6212 RTL_W8(Cfg9346, Cfg9346_Unlock);
6213 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6214 RTL_W8(Config3, MagicPacket);
6215 RTL_W8(Config5, PMEStatus);
6216 tp->features |= RTL_FEATURE_WOL;
6217 tp->features |= rtl_try_msi(tp, cfg);
6218 RTL_W8(Cfg9346, Cfg9346_Lock);
6220 if (rtl_tbi_enabled(tp)) {
6221 tp->set_speed = rtl8169_set_speed_tbi;
6222 tp->get_settings = rtl8169_gset_tbi;
6223 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6224 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6225 tp->link_ok = rtl8169_tbi_link_ok;
6226 tp->do_ioctl = rtl_tbi_ioctl;
6228 tp->set_speed = rtl8169_set_speed_xmii;
6229 tp->get_settings = rtl8169_gset_xmii;
6230 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6231 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6232 tp->link_ok = rtl8169_xmii_link_ok;
6233 tp->do_ioctl = rtl_xmii_ioctl;
6236 mutex_init(&tp->wk.mutex);
6238 /* Get MAC address */
6239 for (i = 0; i < ETH_ALEN; i++)
6240 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6241 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6243 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6244 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6246 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6248 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6249 * properly for all devices */
6250 dev->features |= NETIF_F_RXCSUM |
6251 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6253 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6254 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6255 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6258 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6259 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6260 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6262 dev->hw_features |= NETIF_F_RXALL;
6263 dev->hw_features |= NETIF_F_RXFCS;
6265 tp->hw_start = cfg->hw_start;
6266 tp->event_slow = cfg->event_slow;
6268 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6269 ~(RxBOVF | RxFOVF) : ~0;
6271 init_timer(&tp->timer);
6272 tp->timer.data = (unsigned long) dev;
6273 tp->timer.function = rtl8169_phy_timer;
6275 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6277 rc = register_netdev(dev);
6281 pci_set_drvdata(pdev, dev);
6283 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6284 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6285 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6286 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6287 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6288 "tx checksumming: %s]\n",
6289 rtl_chip_infos[chipset].jumbo_max,
6290 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6293 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6294 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6295 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6296 rtl8168_driver_start(tp);
6299 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6301 if (pci_dev_run_wake(pdev))
6302 pm_runtime_put_noidle(&pdev->dev);
6304 netif_carrier_off(dev);
6310 rtl_disable_msi(pdev, tp);
6313 pci_release_regions(pdev);
6315 pci_clear_mwi(pdev);
6316 pci_disable_device(pdev);
6322 static struct pci_driver rtl8169_pci_driver = {
6324 .id_table = rtl8169_pci_tbl,
6325 .probe = rtl_init_one,
6326 .remove = __devexit_p(rtl_remove_one),
6327 .shutdown = rtl_shutdown,
6328 .driver.pm = RTL8169_PM_OPS,
6331 static int __init rtl8169_init_module(void)
6333 return pci_register_driver(&rtl8169_pci_driver);
6336 static void __exit rtl8169_cleanup_module(void)
6338 pci_unregister_driver(&rtl8169_pci_driver);
6341 module_init(rtl8169_init_module);
6342 module_exit(rtl8169_cleanup_module);