drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46
  47 #ifdef RTL8169_DEBUG
  48 #define assert(expr) \
  49         if (!(expr)) {                                  \
  50                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  51                 #expr,__FILE__,__func__,__LINE__);              \
  52         }
  53 #define dprintk(fmt, args...) \
  54         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  55 #else
  56 #define assert(expr) do {} while (0)
  57 #define dprintk(fmt, args...)   do {} while (0)
  58 #endif /* RTL8169_DEBUG */
  59
  60 #define R8169_MSG_DEFAULT \
  61         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  62
  63 #define TX_BUFFS_AVAIL(tp) \
  64         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 /* MAC address length */
  71 #define MAC_ADDR_LEN    6
  72
  73 #define MAX_READ_REQUEST_SHIFT  12
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define _R(NAME,TD,FW) \
 145         { .name = NAME, .txd_version = TD, .fw_name = FW }
 146
 147 static const struct {
 148         const char *name;
 149         enum rtl_tx_desc_version txd_version;
 150         const char *fw_name;
 151 } rtl_chip_infos[] = {
 152         /* PCI devices. */
 153         [RTL_GIGA_MAC_VER_01] =
 154                 _R("RTL8169",           RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_02] =
 156                 _R("RTL8169s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_03] =
 158                 _R("RTL8110s",          RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_04] =
 160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_05] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_06] =
 164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 165         /* PCI-E devices. */
 166         [RTL_GIGA_MAC_VER_07] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_08] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_09] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_10] =
 173                 _R("RTL8101e",          RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_11] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_12] =
 177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_13] =
 179                 _R("RTL8101e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_14] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_15] =
 183                 _R("RTL8100e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_16] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_17] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_18] =
 189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_19] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_20] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_21] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_22] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_23] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_24] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_25] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 204         [RTL_GIGA_MAC_VER_26] =
 205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 206         [RTL_GIGA_MAC_VER_27] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_28] =
 209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 210         [RTL_GIGA_MAC_VER_29] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_30] =
 213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 214         [RTL_GIGA_MAC_VER_31] =
 215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 216         [RTL_GIGA_MAC_VER_32] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 218         [RTL_GIGA_MAC_VER_33] =
 219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2),
 220         [RTL_GIGA_MAC_VER_34] =
 221                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
 222 };
 223 #undef _R
 224
 225 enum cfg_version {
 226         RTL_CFG_0 = 0x00,
 227         RTL_CFG_1,
 228         RTL_CFG_2
 229 };
 230
 231 static void rtl_hw_start_8169(struct net_device *);
 232 static void rtl_hw_start_8168(struct net_device *);
 233 static void rtl_hw_start_8101(struct net_device *);
 234
 235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 242         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 243         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 244         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 245         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 246                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 247         { 0x0001,                               0x8168,
 248                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 249         {0,},
 250 };
 251
 252 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 253
 254 static int rx_buf_sz = 16383;
 255 static int use_dac;
 256 static struct {
 257         u32 msg_enable;
 258 } debug = { -1 };
 259
 260 enum rtl_registers {
 261         MAC0            = 0,    /* Ethernet hardware address. */
 262         MAC4            = 4,
 263         MAR0            = 8,    /* Multicast filter. */
 264         CounterAddrLow          = 0x10,
 265         CounterAddrHigh         = 0x14,
 266         TxDescStartAddrLow      = 0x20,
 267         TxDescStartAddrHigh     = 0x24,
 268         TxHDescStartAddrLow     = 0x28,
 269         TxHDescStartAddrHigh    = 0x2c,
 270         FLASH           = 0x30,
 271         ERSR            = 0x36,
 272         ChipCmd         = 0x37,
 273         TxPoll          = 0x38,
 274         IntrMask        = 0x3c,
 275         IntrStatus      = 0x3e,
 276
 277         TxConfig        = 0x40,
 278 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 279 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 280
 281         RxConfig        = 0x44,
 282 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 283 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 284 #define RXCFG_FIFO_SHIFT                13
 285                                         /* No threshold before first PCI xfer */
 286 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 287 #define RXCFG_DMA_SHIFT                 8
 288                                         /* Unlimited maximum PCI burst. */
 289 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 290
 291         RxMissed        = 0x4c,
 292         Cfg9346         = 0x50,
 293         Config0         = 0x51,
 294         Config1         = 0x52,
 295         Config2         = 0x53,
 296         Config3         = 0x54,
 297         Config4         = 0x55,
 298         Config5         = 0x56,
 299         MultiIntr       = 0x5c,
 300         PHYAR           = 0x60,
 301         PHYstatus       = 0x6c,
 302         RxMaxSize       = 0xda,
 303         CPlusCmd        = 0xe0,
 304         IntrMitigate    = 0xe2,
 305         RxDescAddrLow   = 0xe4,
 306         RxDescAddrHigh  = 0xe8,
 307         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 308
 309 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 310
 311         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 312
 313 #define TxPacketMax     (8064 >> 7)
 314 #define EarlySize       0x27
 315
 316         FuncEvent       = 0xf0,
 317         FuncEventMask   = 0xf4,
 318         FuncPresetState = 0xf8,
 319         FuncForceEvent  = 0xfc,
 320 };
 321
 322 enum rtl8110_registers {
 323         TBICSR                  = 0x64,
 324         TBI_ANAR                = 0x68,
 325         TBI_LPAR                = 0x6a,
 326 };
 327
 328 enum rtl8168_8101_registers {
 329         CSIDR                   = 0x64,
 330         CSIAR                   = 0x68,
 331 #define CSIAR_FLAG                      0x80000000
 332 #define CSIAR_WRITE_CMD                 0x80000000
 333 #define CSIAR_BYTE_ENABLE               0x0f
 334 #define CSIAR_BYTE_ENABLE_SHIFT         12
 335 #define CSIAR_ADDR_MASK                 0x0fff
 336         PMCH                    = 0x6f,
 337         EPHYAR                  = 0x80,
 338 #define EPHYAR_FLAG                     0x80000000
 339 #define EPHYAR_WRITE_CMD                0x80000000
 340 #define EPHYAR_REG_MASK                 0x1f
 341 #define EPHYAR_REG_SHIFT                16
 342 #define EPHYAR_DATA_MASK                0xffff
 343         DLLPR                   = 0xd0,
 344 #define PFM_EN                          (1 << 6)
 345         DBG_REG                 = 0xd1,
 346 #define FIX_NAK_1                       (1 << 4)
 347 #define FIX_NAK_2                       (1 << 3)
 348         TWSI                    = 0xd2,
 349         MCU                     = 0xd3,
 350 #define NOW_IS_OOB                      (1 << 7)
 351 #define EN_NDP                          (1 << 3)
 352 #define EN_OOB_RESET                    (1 << 2)
 353         EFUSEAR                 = 0xdc,
 354 #define EFUSEAR_FLAG                    0x80000000
 355 #define EFUSEAR_WRITE_CMD               0x80000000
 356 #define EFUSEAR_READ_CMD                0x00000000
 357 #define EFUSEAR_REG_MASK                0x03ff
 358 #define EFUSEAR_REG_SHIFT               8
 359 #define EFUSEAR_DATA_MASK               0xff
 360 };
 361
 362 enum rtl8168_registers {
 363         LED_FREQ                = 0x1a,
 364         EEE_LED                 = 0x1b,
 365         ERIDR                   = 0x70,
 366         ERIAR                   = 0x74,
 367 #define ERIAR_FLAG                      0x80000000
 368 #define ERIAR_WRITE_CMD                 0x80000000
 369 #define ERIAR_READ_CMD                  0x00000000
 370 #define ERIAR_ADDR_BYTE_ALIGN           4
 371 #define ERIAR_TYPE_SHIFT                16
 372 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 373 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 374 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 375 #define ERIAR_MASK_SHIFT                12
 376 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 377 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 378 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 379         EPHY_RXER_NUM           = 0x7c,
 380         OCPDR                   = 0xb0, /* OCP GPHY access */
 381 #define OCPDR_WRITE_CMD                 0x80000000
 382 #define OCPDR_READ_CMD                  0x00000000
 383 #define OCPDR_REG_MASK                  0x7f
 384 #define OCPDR_GPHY_REG_SHIFT            16
 385 #define OCPDR_DATA_MASK                 0xffff
 386         OCPAR                   = 0xb4,
 387 #define OCPAR_FLAG                      0x80000000
 388 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 389 #define OCPAR_GPHY_READ_CMD             0x0000f060
 390         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 391         MISC                    = 0xf0, /* 8168e only. */
 392 #define TXPLA_RST                       (1 << 29)
 393 #define PWM_EN                          (1 << 22)
 394 };
 395
 396 enum rtl_register_content {
 397         /* InterruptStatusBits */
 398         SYSErr          = 0x8000,
 399         PCSTimeout      = 0x4000,
 400         SWInt           = 0x0100,
 401         TxDescUnavail   = 0x0080,
 402         RxFIFOOver      = 0x0040,
 403         LinkChg         = 0x0020,
 404         RxOverflow      = 0x0010,
 405         TxErr           = 0x0008,
 406         TxOK            = 0x0004,
 407         RxErr           = 0x0002,
 408         RxOK            = 0x0001,
 409
 410         /* RxStatusDesc */
 411         RxBOVF  = (1 << 24),
 412         RxFOVF  = (1 << 23),
 413         RxRWT   = (1 << 22),
 414         RxRES   = (1 << 21),
 415         RxRUNT  = (1 << 20),
 416         RxCRC   = (1 << 19),
 417
 418         /* ChipCmdBits */
 419         StopReq         = 0x80,
 420         CmdReset        = 0x10,
 421         CmdRxEnb        = 0x08,
 422         CmdTxEnb        = 0x04,
 423         RxBufEmpty      = 0x01,
 424
 425         /* TXPoll register p.5 */
 426         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 427         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 428         FSWInt          = 0x01,         /* Forced software interrupt */
 429
 430         /* Cfg9346Bits */
 431         Cfg9346_Lock    = 0x00,
 432         Cfg9346_Unlock  = 0xc0,
 433
 434         /* rx_mode_bits */
 435         AcceptErr       = 0x20,
 436         AcceptRunt      = 0x10,
 437         AcceptBroadcast = 0x08,
 438         AcceptMulticast = 0x04,
 439         AcceptMyPhys    = 0x02,
 440         AcceptAllPhys   = 0x01,
 441 #define RX_CONFIG_ACCEPT_MASK           0x3f
 442
 443         /* TxConfigBits */
 444         TxInterFrameGapShift = 24,
 445         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 446
 447         /* Config1 register p.24 */
 448         LEDS1           = (1 << 7),
 449         LEDS0           = (1 << 6),
 450         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 451         Speed_down      = (1 << 4),
 452         MEMMAP          = (1 << 3),
 453         IOMAP           = (1 << 2),
 454         VPD             = (1 << 1),
 455         PMEnable        = (1 << 0),     /* Power Management Enable */
 456
 457         /* Config2 register p. 25 */
 458         PCI_Clock_66MHz = 0x01,
 459         PCI_Clock_33MHz = 0x00,
 460
 461         /* Config3 register p.25 */
 462         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 463         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 464         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 465
 466         /* Config5 register p.27 */
 467         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 468         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 469         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 470         Spi_en          = (1 << 3),
 471         LanWake         = (1 << 1),     /* LanWake enable/disable */
 472         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 473
 474         /* TBICSR p.28 */
 475         TBIReset        = 0x80000000,
 476         TBILoopback     = 0x40000000,
 477         TBINwEnable     = 0x20000000,
 478         TBINwRestart    = 0x10000000,
 479         TBILinkOk       = 0x02000000,
 480         TBINwComplete   = 0x01000000,
 481
 482         /* CPlusCmd p.31 */
 483         EnableBist      = (1 << 15),    // 8168 8101
 484         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 485         Normal_mode     = (1 << 13),    // unused
 486         Force_half_dup  = (1 << 12),    // 8168 8101
 487         Force_rxflow_en = (1 << 11),    // 8168 8101
 488         Force_txflow_en = (1 << 10),    // 8168 8101
 489         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 490         ASF             = (1 << 8),     // 8168 8101
 491         PktCntrDisable  = (1 << 7),     // 8168 8101
 492         Mac_dbgo_sel    = 0x001c,       // 8168
 493         RxVlan          = (1 << 6),
 494         RxChkSum        = (1 << 5),
 495         PCIDAC          = (1 << 4),
 496         PCIMulRW        = (1 << 3),
 497         INTT_0          = 0x0000,       // 8168
 498         INTT_1          = 0x0001,       // 8168
 499         INTT_2          = 0x0002,       // 8168
 500         INTT_3          = 0x0003,       // 8168
 501
 502         /* rtl8169_PHYstatus */
 503         TBI_Enable      = 0x80,
 504         TxFlowCtrl      = 0x40,
 505         RxFlowCtrl      = 0x20,
 506         _1000bpsF       = 0x10,
 507         _100bps         = 0x08,
 508         _10bps          = 0x04,
 509         LinkStatus      = 0x02,
 510         FullDup         = 0x01,
 511
 512         /* _TBICSRBit */
 513         TBILinkOK       = 0x02000000,
 514
 515         /* DumpCounterCommand */
 516         CounterDump     = 0x8,
 517 };
 518
 519 enum rtl_desc_bit {
 520         /* First doubleword. */
 521         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 522         RingEnd         = (1 << 30), /* End of descriptor ring */
 523         FirstFrag       = (1 << 29), /* First segment of a packet */
 524         LastFrag        = (1 << 28), /* Final segment of a packet */
 525 };
 526
 527 /* Generic case. */
 528 enum rtl_tx_desc_bit {
 529         /* First doubleword. */
 530         TD_LSO          = (1 << 27),            /* Large Send Offload */
 531 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 532
 533         /* Second doubleword. */
 534         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 535 };
 536
 537 /* 8169, 8168b and 810x except 8102e. */
 538 enum rtl_tx_desc_bit_0 {
 539         /* First doubleword. */
 540 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 541         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 542         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 543         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 544 };
 545
 546 /* 8102e, 8168c and beyond. */
 547 enum rtl_tx_desc_bit_1 {
 548         /* Second doubleword. */
 549 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 550         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 551         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 552         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 553 };
 554
 555 static const struct rtl_tx_desc_info {
 556         struct {
 557                 u32 udp;
 558                 u32 tcp;
 559         } checksum;
 560         u16 mss_shift;
 561         u16 opts_offset;
 562 } tx_desc_info [] = {
 563         [RTL_TD_0] = {
 564                 .checksum = {
 565                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 566                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 567                 },
 568                 .mss_shift      = TD0_MSS_SHIFT,
 569                 .opts_offset    = 0
 570         },
 571         [RTL_TD_1] = {
 572                 .checksum = {
 573                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 574                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 575                 },
 576                 .mss_shift      = TD1_MSS_SHIFT,
 577                 .opts_offset    = 1
 578         }
 579 };
 580
 581 enum rtl_rx_desc_bit {
 582         /* Rx private */
 583         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 584         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 585
 586 #define RxProtoUDP      (PID1)
 587 #define RxProtoTCP      (PID0)
 588 #define RxProtoIP       (PID1 | PID0)
 589 #define RxProtoMask     RxProtoIP
 590
 591         IPFail          = (1 << 16), /* IP checksum failed */
 592         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 593         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 594         RxVlanTag       = (1 << 16), /* VLAN tag available */
 595 };
 596
 597 #define RsvdMask        0x3fffc000
 598
 599 struct TxDesc {
 600         __le32 opts1;
 601         __le32 opts2;
 602         __le64 addr;
 603 };
 604
 605 struct RxDesc {
 606         __le32 opts1;
 607         __le32 opts2;
 608         __le64 addr;
 609 };
 610
 611 struct ring_info {
 612         struct sk_buff  *skb;
 613         u32             len;
 614         u8              __pad[sizeof(void *) - sizeof(u32)];
 615 };
 616
 617 enum features {
 618         RTL_FEATURE_WOL         = (1 << 0),
 619         RTL_FEATURE_MSI         = (1 << 1),
 620         RTL_FEATURE_GMII        = (1 << 2),
 621 };
 622
 623 struct rtl8169_counters {
 624         __le64  tx_packets;
 625         __le64  rx_packets;
 626         __le64  tx_errors;
 627         __le32  rx_errors;
 628         __le16  rx_missed;
 629         __le16  align_errors;
 630         __le32  tx_one_collision;
 631         __le32  tx_multi_collision;
 632         __le64  rx_unicast;
 633         __le64  rx_broadcast;
 634         __le32  rx_multicast;
 635         __le16  tx_aborted;
 636         __le16  tx_underun;
 637 };
 638
 639 struct rtl8169_private {
 640         void __iomem *mmio_addr;        /* memory map physical address */
 641         struct pci_dev *pci_dev;
 642         struct net_device *dev;
 643         struct napi_struct napi;
 644         spinlock_t lock;
 645         u32 msg_enable;
 646         u16 txd_version;
 647         u16 mac_version;
 648         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 649         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 650         u32 dirty_rx;
 651         u32 dirty_tx;
 652         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 653         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 654         dma_addr_t TxPhyAddr;
 655         dma_addr_t RxPhyAddr;
 656         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 657         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 658         struct timer_list timer;
 659         u16 cp_cmd;
 660         u16 intr_event;
 661         u16 napi_event;
 662         u16 intr_mask;
 663
 664         struct mdio_ops {
 665                 void (*write)(void __iomem *, int, int);
 666                 int (*read)(void __iomem *, int);
 667         } mdio_ops;
 668
 669         struct pll_power_ops {
 670                 void (*down)(struct rtl8169_private *);
 671                 void (*up)(struct rtl8169_private *);
 672         } pll_power_ops;
 673
 674         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 675         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 676         void (*phy_reset_enable)(struct rtl8169_private *tp);
 677         void (*hw_start)(struct net_device *);
 678         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 679         unsigned int (*link_ok)(void __iomem *);
 680         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 681         struct delayed_work task;
 682         unsigned features;
 683
 684         struct mii_if_info mii;
 685         struct rtl8169_counters counters;
 686         u32 saved_wolopts;
 687         u32 opts1_mask;
 688
 689         struct rtl_fw {
 690                 const struct firmware *fw;
 691
 692 #define RTL_VER_SIZE            32
 693
 694                 char version[RTL_VER_SIZE];
 695
 696                 struct rtl_fw_phy_action {
 697                         __le32 *code;
 698                         size_t size;
 699                 } phy_action;
 700         } *rtl_fw;
 701 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 702 };
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param(use_dac, int, 0);
 707 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 708 module_param_named(debug, debug.msg_enable, int, 0);
 709 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 710 MODULE_LICENSE("GPL");
 711 MODULE_VERSION(RTL8169_VERSION);
 712 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 716 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 717 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 718
 719 static int rtl8169_open(struct net_device *dev);
 720 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 721                                       struct net_device *dev);
 722 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 723 static int rtl8169_init_ring(struct net_device *dev);
 724 static void rtl_hw_start(struct net_device *dev);
 725 static int rtl8169_close(struct net_device *dev);
 726 static void rtl_set_rx_mode(struct net_device *dev);
 727 static void rtl8169_tx_timeout(struct net_device *dev);
 728 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 729 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 730                                 void __iomem *, u32 budget);
 731 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 732 static void rtl8169_down(struct net_device *dev);
 733 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 734 static int rtl8169_poll(struct napi_struct *napi, int budget);
 735
 736 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 737 {
 738         void __iomem *ioaddr = tp->mmio_addr;
 739         int i;
 740
 741         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 742         for (i = 0; i < 20; i++) {
 743                 udelay(100);
 744                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 745                         break;
 746         }
 747         return RTL_R32(OCPDR);
 748 }
 749
 750 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 751 {
 752         void __iomem *ioaddr = tp->mmio_addr;
 753         int i;
 754
 755         RTL_W32(OCPDR, data);
 756         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 757         for (i = 0; i < 20; i++) {
 758                 udelay(100);
 759                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 760                         break;
 761         }
 762 }
 763
 764 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 765 {
 766         void __iomem *ioaddr = tp->mmio_addr;
 767         int i;
 768
 769         RTL_W8(ERIDR, cmd);
 770         RTL_W32(ERIAR, 0x800010e8);
 771         msleep(2);
 772         for (i = 0; i < 5; i++) {
 773                 udelay(100);
 774                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 775                         break;
 776         }
 777
 778         ocp_write(tp, 0x1, 0x30, 0x00000001);
 779 }
 780
 781 #define OOB_CMD_RESET           0x00
 782 #define OOB_CMD_DRIVER_START    0x05
 783 #define OOB_CMD_DRIVER_STOP     0x06
 784
 785 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 786 {
 787         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 788 }
 789
 790 static void rtl8168_driver_start(struct rtl8169_private *tp)
 791 {
 792         u16 reg;
 793         int i;
 794
 795         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 796
 797         reg = rtl8168_get_ocp_reg(tp);
 798
 799         for (i = 0; i < 10; i++) {
 800                 msleep(10);
 801                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 802                         break;
 803         }
 804 }
 805
 806 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 807 {
 808         u16 reg;
 809         int i;
 810
 811         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 812
 813         reg = rtl8168_get_ocp_reg(tp);
 814
 815         for (i = 0; i < 10; i++) {
 816                 msleep(10);
 817                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 818                         break;
 819         }
 820 }
 821
 822 static int r8168dp_check_dash(struct rtl8169_private *tp)
 823 {
 824         u16 reg = rtl8168_get_ocp_reg(tp);
 825
 826         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 827 }
 828
 829 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 830 {
 831         int i;
 832
 833         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 834
 835         for (i = 20; i > 0; i--) {
 836                 /*
 837                  * Check if the RTL8169 has completed writing to the specified
 838                  * MII register.
 839                  */
 840                 if (!(RTL_R32(PHYAR) & 0x80000000))
 841                         break;
 842                 udelay(25);
 843         }
 844         /*
 845          * According to hardware specs a 20us delay is required after write
 846          * complete indication, but before sending next command.
 847          */
 848         udelay(20);
 849 }
 850
 851 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 852 {
 853         int i, value = -1;
 854
 855         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 856
 857         for (i = 20; i > 0; i--) {
 858                 /*
 859                  * Check if the RTL8169 has completed retrieving data from
 860                  * the specified MII register.
 861                  */
 862                 if (RTL_R32(PHYAR) & 0x80000000) {
 863                         value = RTL_R32(PHYAR) & 0xffff;
 864                         break;
 865                 }
 866                 udelay(25);
 867         }
 868         /*
 869          * According to hardware specs a 20us delay is required after read
 870          * complete indication, but before sending next command.
 871          */
 872         udelay(20);
 873
 874         return value;
 875 }
 876
 877 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 878 {
 879         int i;
 880
 881         RTL_W32(OCPDR, data |
 882                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 883         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 884         RTL_W32(EPHY_RXER_NUM, 0);
 885
 886         for (i = 0; i < 100; i++) {
 887                 mdelay(1);
 888                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 889                         break;
 890         }
 891 }
 892
 893 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 894 {
 895         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 896                 (value & OCPDR_DATA_MASK));
 897 }
 898
 899 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 900 {
 901         int i;
 902
 903         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 904
 905         mdelay(1);
 906         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 907         RTL_W32(EPHY_RXER_NUM, 0);
 908
 909         for (i = 0; i < 100; i++) {
 910                 mdelay(1);
 911                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 912                         break;
 913         }
 914
 915         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 916 }
 917
 918 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 919
 920 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 921 {
 922         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 923 }
 924
 925 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 926 {
 927         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 928 }
 929
 930 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 931 {
 932         r8168dp_2_mdio_start(ioaddr);
 933
 934         r8169_mdio_write(ioaddr, reg_addr, value);
 935
 936         r8168dp_2_mdio_stop(ioaddr);
 937 }
 938
 939 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 940 {
 941         int value;
 942
 943         r8168dp_2_mdio_start(ioaddr);
 944
 945         value = r8169_mdio_read(ioaddr, reg_addr);
 946
 947         r8168dp_2_mdio_stop(ioaddr);
 948
 949         return value;
 950 }
 951
 952 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 953 {
 954         tp->mdio_ops.write(tp->mmio_addr, location, val);
 955 }
 956
 957 static int rtl_readphy(struct rtl8169_private *tp, int location)
 958 {
 959         return tp->mdio_ops.read(tp->mmio_addr, location);
 960 }
 961
 962 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 963 {
 964         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 965 }
 966
 967 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 968 {
 969         int val;
 970
 971         val = rtl_readphy(tp, reg_addr);
 972         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 973 }
 974
 975 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 976                            int val)
 977 {
 978         struct rtl8169_private *tp = netdev_priv(dev);
 979
 980         rtl_writephy(tp, location, val);
 981 }
 982
 983 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 984 {
 985         struct rtl8169_private *tp = netdev_priv(dev);
 986
 987         return rtl_readphy(tp, location);
 988 }
 989
 990 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 991 {
 992         unsigned int i;
 993
 994         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 995                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 996
 997         for (i = 0; i < 100; i++) {
 998                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 999                         break;
1000                 udelay(10);
1001         }
1002 }
1003
1004 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1005 {
1006         u16 value = 0xffff;
1007         unsigned int i;
1008
1009         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1010
1011         for (i = 0; i < 100; i++) {
1012                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1013                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1014                         break;
1015                 }
1016                 udelay(10);
1017         }
1018
1019         return value;
1020 }
1021
1022 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1023 {
1024         unsigned int i;
1025
1026         RTL_W32(CSIDR, value);
1027         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1028                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1029
1030         for (i = 0; i < 100; i++) {
1031                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1032                         break;
1033                 udelay(10);
1034         }
1035 }
1036
1037 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1038 {
1039         u32 value = ~0x00;
1040         unsigned int i;
1041
1042         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1043                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1044
1045         for (i = 0; i < 100; i++) {
1046                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1047                         value = RTL_R32(CSIDR);
1048                         break;
1049                 }
1050                 udelay(10);
1051         }
1052
1053         return value;
1054 }
1055
1056 static
1057 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1058 {
1059         unsigned int i;
1060
1061         BUG_ON((addr & 3) || (mask == 0));
1062         RTL_W32(ERIDR, val);
1063         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1064
1065         for (i = 0; i < 100; i++) {
1066                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1067                         break;
1068                 udelay(100);
1069         }
1070 }
1071
1072 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1073 {
1074         u32 value = ~0x00;
1075         unsigned int i;
1076
1077         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1078
1079         for (i = 0; i < 100; i++) {
1080                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1081                         value = RTL_R32(ERIDR);
1082                         break;
1083                 }
1084                 udelay(100);
1085         }
1086
1087         return value;
1088 }
1089
1090 static void
1091 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1092 {
1093         u32 val;
1094
1095         val = rtl_eri_read(ioaddr, addr, type);
1096         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1097 }
1098
1099 struct exgmac_reg {
1100         u16 addr;
1101         u16 mask;
1102         u32 val;
1103 };
1104
1105 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1106                                    const struct exgmac_reg *r, int len)
1107 {
1108         while (len-- > 0) {
1109                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1110                 r++;
1111         }
1112 }
1113
1114 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1115 {
1116         u8 value = 0xff;
1117         unsigned int i;
1118
1119         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1120
1121         for (i = 0; i < 300; i++) {
1122                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1123                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1124                         break;
1125                 }
1126                 udelay(100);
1127         }
1128
1129         return value;
1130 }
1131
1132 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1133 {
1134         RTL_W16(IntrMask, 0x0000);
1135
1136         RTL_W16(IntrStatus, 0xffff);
1137 }
1138
1139 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1140 {
1141         void __iomem *ioaddr = tp->mmio_addr;
1142
1143         return RTL_R32(TBICSR) & TBIReset;
1144 }
1145
1146 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1147 {
1148         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1149 }
1150
1151 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1152 {
1153         return RTL_R32(TBICSR) & TBILinkOk;
1154 }
1155
1156 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1157 {
1158         return RTL_R8(PHYstatus) & LinkStatus;
1159 }
1160
1161 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1162 {
1163         void __iomem *ioaddr = tp->mmio_addr;
1164
1165         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1166 }
1167
1168 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1169 {
1170         unsigned int val;
1171
1172         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1173         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1174 }
1175
1176 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1177 {
1178         void __iomem *ioaddr = tp->mmio_addr;
1179         struct net_device *dev = tp->dev;
1180
1181         if (!netif_running(dev))
1182                 return;
1183
1184         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1185                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1186                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1187                                       0x00000011, ERIAR_EXGMAC);
1188                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1189                                       0x00000005, ERIAR_EXGMAC);
1190                 } else if (RTL_R8(PHYstatus) & _100bps) {
1191                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1192                                       0x0000001f, ERIAR_EXGMAC);
1193                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1194                                       0x00000005, ERIAR_EXGMAC);
1195                 } else {
1196                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1197                                       0x0000001f, ERIAR_EXGMAC);
1198                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1199                                       0x0000003f, ERIAR_EXGMAC);
1200                 }
1201                 /* Reset packet filter */
1202                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1203                              ERIAR_EXGMAC);
1204                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1205                              ERIAR_EXGMAC);
1206         }
1207 }
1208
1209 static void __rtl8169_check_link_status(struct net_device *dev,
1210                                         struct rtl8169_private *tp,
1211                                         void __iomem *ioaddr, bool pm)
1212 {
1213         unsigned long flags;
1214
1215         spin_lock_irqsave(&tp->lock, flags);
1216         if (tp->link_ok(ioaddr)) {
1217                 rtl_link_chg_patch(tp);
1218                 /* This is to cancel a scheduled suspend if there's one. */
1219                 if (pm)
1220                         pm_request_resume(&tp->pci_dev->dev);
1221                 netif_carrier_on(dev);
1222                 if (net_ratelimit())
1223                         netif_info(tp, ifup, dev, "link up\n");
1224         } else {
1225                 netif_carrier_off(dev);
1226                 netif_info(tp, ifdown, dev, "link down\n");
1227                 if (pm)
1228                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1229         }
1230         spin_unlock_irqrestore(&tp->lock, flags);
1231 }
1232
1233 static void rtl8169_check_link_status(struct net_device *dev,
1234                                       struct rtl8169_private *tp,
1235                                       void __iomem *ioaddr)
1236 {
1237         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1238 }
1239
1240 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1241
1242 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1243 {
1244         void __iomem *ioaddr = tp->mmio_addr;
1245         u8 options;
1246         u32 wolopts = 0;
1247
1248         options = RTL_R8(Config1);
1249         if (!(options & PMEnable))
1250                 return 0;
1251
1252         options = RTL_R8(Config3);
1253         if (options & LinkUp)
1254                 wolopts |= WAKE_PHY;
1255         if (options & MagicPacket)
1256                 wolopts |= WAKE_MAGIC;
1257
1258         options = RTL_R8(Config5);
1259         if (options & UWF)
1260                 wolopts |= WAKE_UCAST;
1261         if (options & BWF)
1262                 wolopts |= WAKE_BCAST;
1263         if (options & MWF)
1264                 wolopts |= WAKE_MCAST;
1265
1266         return wolopts;
1267 }
1268
1269 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1270 {
1271         struct rtl8169_private *tp = netdev_priv(dev);
1272
1273         spin_lock_irq(&tp->lock);
1274
1275         wol->supported = WAKE_ANY;
1276         wol->wolopts = __rtl8169_get_wol(tp);
1277
1278         spin_unlock_irq(&tp->lock);
1279 }
1280
1281 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1282 {
1283         void __iomem *ioaddr = tp->mmio_addr;
1284         unsigned int i;
1285         static const struct {
1286                 u32 opt;
1287                 u16 reg;
1288                 u8  mask;
1289         } cfg[] = {
1290                 { WAKE_ANY,   Config1, PMEnable },
1291                 { WAKE_PHY,   Config3, LinkUp },
1292                 { WAKE_MAGIC, Config3, MagicPacket },
1293                 { WAKE_UCAST, Config5, UWF },
1294                 { WAKE_BCAST, Config5, BWF },
1295                 { WAKE_MCAST, Config5, MWF },
1296                 { WAKE_ANY,   Config5, LanWake }
1297         };
1298
1299         RTL_W8(Cfg9346, Cfg9346_Unlock);
1300
1301         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1302                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1303                 if (wolopts & cfg[i].opt)
1304                         options |= cfg[i].mask;
1305                 RTL_W8(cfg[i].reg, options);
1306         }
1307
1308         RTL_W8(Cfg9346, Cfg9346_Lock);
1309 }
1310
1311 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1312 {
1313         struct rtl8169_private *tp = netdev_priv(dev);
1314
1315         spin_lock_irq(&tp->lock);
1316
1317         if (wol->wolopts)
1318                 tp->features |= RTL_FEATURE_WOL;
1319         else
1320                 tp->features &= ~RTL_FEATURE_WOL;
1321         __rtl8169_set_wol(tp, wol->wolopts);
1322         spin_unlock_irq(&tp->lock);
1323
1324         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1325
1326         return 0;
1327 }
1328
1329 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1330 {
1331         return rtl_chip_infos[tp->mac_version].fw_name;
1332 }
1333
1334 static void rtl8169_get_drvinfo(struct net_device *dev,
1335                                 struct ethtool_drvinfo *info)
1336 {
1337         struct rtl8169_private *tp = netdev_priv(dev);
1338         struct rtl_fw *rtl_fw = tp->rtl_fw;
1339
1340         strcpy(info->driver, MODULENAME);
1341         strcpy(info->version, RTL8169_VERSION);
1342         strcpy(info->bus_info, pci_name(tp->pci_dev));
1343         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1344         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1345                rtl_fw->version);
1346 }
1347
1348 static int rtl8169_get_regs_len(struct net_device *dev)
1349 {
1350         return R8169_REGS_SIZE;
1351 }
1352
1353 static int rtl8169_set_speed_tbi(struct net_device *dev,
1354                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1355 {
1356         struct rtl8169_private *tp = netdev_priv(dev);
1357         void __iomem *ioaddr = tp->mmio_addr;
1358         int ret = 0;
1359         u32 reg;
1360
1361         reg = RTL_R32(TBICSR);
1362         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1363             (duplex == DUPLEX_FULL)) {
1364                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1365         } else if (autoneg == AUTONEG_ENABLE)
1366                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1367         else {
1368                 netif_warn(tp, link, dev,
1369                            "incorrect speed setting refused in TBI mode\n");
1370                 ret = -EOPNOTSUPP;
1371         }
1372
1373         return ret;
1374 }
1375
1376 static int rtl8169_set_speed_xmii(struct net_device *dev,
1377                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1378 {
1379         struct rtl8169_private *tp = netdev_priv(dev);
1380         int giga_ctrl, bmcr;
1381         int rc = -EINVAL;
1382
1383         rtl_writephy(tp, 0x1f, 0x0000);
1384
1385         if (autoneg == AUTONEG_ENABLE) {
1386                 int auto_nego;
1387
1388                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1389                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1390                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1391
1392                 if (adv & ADVERTISED_10baseT_Half)
1393                         auto_nego |= ADVERTISE_10HALF;
1394                 if (adv & ADVERTISED_10baseT_Full)
1395                         auto_nego |= ADVERTISE_10FULL;
1396                 if (adv & ADVERTISED_100baseT_Half)
1397                         auto_nego |= ADVERTISE_100HALF;
1398                 if (adv & ADVERTISED_100baseT_Full)
1399                         auto_nego |= ADVERTISE_100FULL;
1400
1401                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1402
1403                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1404                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1405
1406                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1407                 if (tp->mii.supports_gmii) {
1408                         if (adv & ADVERTISED_1000baseT_Half)
1409                                 giga_ctrl |= ADVERTISE_1000HALF;
1410                         if (adv & ADVERTISED_1000baseT_Full)
1411                                 giga_ctrl |= ADVERTISE_1000FULL;
1412                 } else if (adv & (ADVERTISED_1000baseT_Half |
1413                                   ADVERTISED_1000baseT_Full)) {
1414                         netif_info(tp, link, dev,
1415                                    "PHY does not support 1000Mbps\n");
1416                         goto out;
1417                 }
1418
1419                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1420
1421                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1422                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1423         } else {
1424                 giga_ctrl = 0;
1425
1426                 if (speed == SPEED_10)
1427                         bmcr = 0;
1428                 else if (speed == SPEED_100)
1429                         bmcr = BMCR_SPEED100;
1430                 else
1431                         goto out;
1432
1433                 if (duplex == DUPLEX_FULL)
1434                         bmcr |= BMCR_FULLDPLX;
1435         }
1436
1437         rtl_writephy(tp, MII_BMCR, bmcr);
1438
1439         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1440             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1441                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1442                         rtl_writephy(tp, 0x17, 0x2138);
1443                         rtl_writephy(tp, 0x0e, 0x0260);
1444                 } else {
1445                         rtl_writephy(tp, 0x17, 0x2108);
1446                         rtl_writephy(tp, 0x0e, 0x0000);
1447                 }
1448         }
1449
1450         rc = 0;
1451 out:
1452         return rc;
1453 }
1454
1455 static int rtl8169_set_speed(struct net_device *dev,
1456                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1457 {
1458         struct rtl8169_private *tp = netdev_priv(dev);
1459         int ret;
1460
1461         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1462         if (ret < 0)
1463                 goto out;
1464
1465         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1466             (advertising & ADVERTISED_1000baseT_Full)) {
1467                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1468         }
1469 out:
1470         return ret;
1471 }
1472
1473 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1474 {
1475         struct rtl8169_private *tp = netdev_priv(dev);
1476         unsigned long flags;
1477         int ret;
1478
1479         del_timer_sync(&tp->timer);
1480
1481         spin_lock_irqsave(&tp->lock, flags);
1482         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1483                                 cmd->duplex, cmd->advertising);
1484         spin_unlock_irqrestore(&tp->lock, flags);
1485
1486         return ret;
1487 }
1488
1489 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1490 {
1491         if (dev->mtu > TD_MSS_MAX)
1492                 features &= ~NETIF_F_ALL_TSO;
1493
1494         return features;
1495 }
1496
1497 static int rtl8169_set_features(struct net_device *dev, u32 features)
1498 {
1499         struct rtl8169_private *tp = netdev_priv(dev);
1500         void __iomem *ioaddr = tp->mmio_addr;
1501         unsigned long flags;
1502
1503         spin_lock_irqsave(&tp->lock, flags);
1504
1505         if (features & NETIF_F_RXCSUM)
1506                 tp->cp_cmd |= RxChkSum;
1507         else
1508                 tp->cp_cmd &= ~RxChkSum;
1509
1510         if (dev->features & NETIF_F_HW_VLAN_RX)
1511                 tp->cp_cmd |= RxVlan;
1512         else
1513                 tp->cp_cmd &= ~RxVlan;
1514
1515         RTL_W16(CPlusCmd, tp->cp_cmd);
1516         RTL_R16(CPlusCmd);
1517
1518         spin_unlock_irqrestore(&tp->lock, flags);
1519
1520         return 0;
1521 }
1522
1523 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1524                                       struct sk_buff *skb)
1525 {
1526         return (vlan_tx_tag_present(skb)) ?
1527                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1528 }
1529
1530 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1531 {
1532         u32 opts2 = le32_to_cpu(desc->opts2);
1533
1534         if (opts2 & RxVlanTag)
1535                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1536
1537         desc->opts2 = 0;
1538 }
1539
1540 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1541 {
1542         struct rtl8169_private *tp = netdev_priv(dev);
1543         void __iomem *ioaddr = tp->mmio_addr;
1544         u32 status;
1545
1546         cmd->supported =
1547                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1548         cmd->port = PORT_FIBRE;
1549         cmd->transceiver = XCVR_INTERNAL;
1550
1551         status = RTL_R32(TBICSR);
1552         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1553         cmd->autoneg = !!(status & TBINwEnable);
1554
1555         ethtool_cmd_speed_set(cmd, SPEED_1000);
1556         cmd->duplex = DUPLEX_FULL; /* Always set */
1557
1558         return 0;
1559 }
1560
1561 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1562 {
1563         struct rtl8169_private *tp = netdev_priv(dev);
1564
1565         return mii_ethtool_gset(&tp->mii, cmd);
1566 }
1567
1568 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1569 {
1570         struct rtl8169_private *tp = netdev_priv(dev);
1571         unsigned long flags;
1572         int rc;
1573
1574         spin_lock_irqsave(&tp->lock, flags);
1575
1576         rc = tp->get_settings(dev, cmd);
1577
1578         spin_unlock_irqrestore(&tp->lock, flags);
1579         return rc;
1580 }
1581
1582 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1583                              void *p)
1584 {
1585         struct rtl8169_private *tp = netdev_priv(dev);
1586         unsigned long flags;
1587
1588         if (regs->len > R8169_REGS_SIZE)
1589                 regs->len = R8169_REGS_SIZE;
1590
1591         spin_lock_irqsave(&tp->lock, flags);
1592         memcpy_fromio(p, tp->mmio_addr, regs->len);
1593         spin_unlock_irqrestore(&tp->lock, flags);
1594 }
1595
1596 static u32 rtl8169_get_msglevel(struct net_device *dev)
1597 {
1598         struct rtl8169_private *tp = netdev_priv(dev);
1599
1600         return tp->msg_enable;
1601 }
1602
1603 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1604 {
1605         struct rtl8169_private *tp = netdev_priv(dev);
1606
1607         tp->msg_enable = value;
1608 }
1609
1610 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1611         "tx_packets",
1612         "rx_packets",
1613         "tx_errors",
1614         "rx_errors",
1615         "rx_missed",
1616         "align_errors",
1617         "tx_single_collisions",
1618         "tx_multi_collisions",
1619         "unicast",
1620         "broadcast",
1621         "multicast",
1622         "tx_aborted",
1623         "tx_underrun",
1624 };
1625
1626 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1627 {
1628         switch (sset) {
1629         case ETH_SS_STATS:
1630                 return ARRAY_SIZE(rtl8169_gstrings);
1631         default:
1632                 return -EOPNOTSUPP;
1633         }
1634 }
1635
1636 static void rtl8169_update_counters(struct net_device *dev)
1637 {
1638         struct rtl8169_private *tp = netdev_priv(dev);
1639         void __iomem *ioaddr = tp->mmio_addr;
1640         struct device *d = &tp->pci_dev->dev;
1641         struct rtl8169_counters *counters;
1642         dma_addr_t paddr;
1643         u32 cmd;
1644         int wait = 1000;
1645
1646         /*
1647          * Some chips are unable to dump tally counters when the receiver
1648          * is disabled.
1649          */
1650         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1651                 return;
1652
1653         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1654         if (!counters)
1655                 return;
1656
1657         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1658         cmd = (u64)paddr & DMA_BIT_MASK(32);
1659         RTL_W32(CounterAddrLow, cmd);
1660         RTL_W32(CounterAddrLow, cmd | CounterDump);
1661
1662         while (wait--) {
1663                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1664                         memcpy(&tp->counters, counters, sizeof(*counters));
1665                         break;
1666                 }
1667                 udelay(10);
1668         }
1669
1670         RTL_W32(CounterAddrLow, 0);
1671         RTL_W32(CounterAddrHigh, 0);
1672
1673         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1674 }
1675
1676 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1677                                       struct ethtool_stats *stats, u64 *data)
1678 {
1679         struct rtl8169_private *tp = netdev_priv(dev);
1680
1681         ASSERT_RTNL();
1682
1683         rtl8169_update_counters(dev);
1684
1685         data[0] = le64_to_cpu(tp->counters.tx_packets);
1686         data[1] = le64_to_cpu(tp->counters.rx_packets);
1687         data[2] = le64_to_cpu(tp->counters.tx_errors);
1688         data[3] = le32_to_cpu(tp->counters.rx_errors);
1689         data[4] = le16_to_cpu(tp->counters.rx_missed);
1690         data[5] = le16_to_cpu(tp->counters.align_errors);
1691         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1692         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1693         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1694         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1695         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1696         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1697         data[12] = le16_to_cpu(tp->counters.tx_underun);
1698 }
1699
1700 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1701 {
1702         switch(stringset) {
1703         case ETH_SS_STATS:
1704                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1705                 break;
1706         }
1707 }
1708
1709 static const struct ethtool_ops rtl8169_ethtool_ops = {
1710         .get_drvinfo            = rtl8169_get_drvinfo,
1711         .get_regs_len           = rtl8169_get_regs_len,
1712         .get_link               = ethtool_op_get_link,
1713         .get_settings           = rtl8169_get_settings,
1714         .set_settings           = rtl8169_set_settings,
1715         .get_msglevel           = rtl8169_get_msglevel,
1716         .set_msglevel           = rtl8169_set_msglevel,
1717         .get_regs               = rtl8169_get_regs,
1718         .get_wol                = rtl8169_get_wol,
1719         .set_wol                = rtl8169_set_wol,
1720         .get_strings            = rtl8169_get_strings,
1721         .get_sset_count         = rtl8169_get_sset_count,
1722         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1723 };
1724
1725 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1726                                     struct net_device *dev, u8 default_version)
1727 {
1728         void __iomem *ioaddr = tp->mmio_addr;
1729         /*
1730          * The driver currently handles the 8168Bf and the 8168Be identically
1731          * but they can be identified more specifically through the test below
1732          * if needed:
1733          *
1734          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1735          *
1736          * Same thing for the 8101Eb and the 8101Ec:
1737          *
1738          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1739          */
1740         static const struct rtl_mac_info {
1741                 u32 mask;
1742                 u32 val;
1743                 int mac_version;
1744         } mac_info[] = {
1745                 /* 8168E family. */
1746                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1747                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1748                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1749                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1750
1751                 /* 8168D family. */
1752                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1753                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1754                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1755
1756                 /* 8168DP family. */
1757                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1758                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1759                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1760
1761                 /* 8168C family. */
1762                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1763                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1764                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1765                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1766                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1767                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1768                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1769                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1770                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1771
1772                 /* 8168B family. */
1773                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1774                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1775                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1776                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1777
1778                 /* 8101 family. */
1779                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1780                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1781                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1782                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1783                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1784                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1785                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1786                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1787                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1788                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1789                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1790                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1791                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1792                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1793                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1794                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1795                 /* FIXME: where did these entries come from ? -- FR */
1796                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1797                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1798
1799                 /* 8110 family. */
1800                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1801                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1802                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1803                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1804                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1805                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1806
1807                 /* Catch-all */
1808                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1809         };
1810         const struct rtl_mac_info *p = mac_info;
1811         u32 reg;
1812
1813         reg = RTL_R32(TxConfig);
1814         while ((reg & p->mask) != p->val)
1815                 p++;
1816         tp->mac_version = p->mac_version;
1817
1818         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1819                 netif_notice(tp, probe, dev,
1820                              "unknown MAC, using family default\n");
1821                 tp->mac_version = default_version;
1822         }
1823 }
1824
1825 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1826 {
1827         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1828 }
1829
1830 struct phy_reg {
1831         u16 reg;
1832         u16 val;
1833 };
1834
1835 static void rtl_writephy_batch(struct rtl8169_private *tp,
1836                                const struct phy_reg *regs, int len)
1837 {
1838         while (len-- > 0) {
1839                 rtl_writephy(tp, regs->reg, regs->val);
1840                 regs++;
1841         }
1842 }
1843
1844 #define PHY_READ                0x00000000
1845 #define PHY_DATA_OR             0x10000000
1846 #define PHY_DATA_AND            0x20000000
1847 #define PHY_BJMPN               0x30000000
1848 #define PHY_READ_EFUSE          0x40000000
1849 #define PHY_READ_MAC_BYTE       0x50000000
1850 #define PHY_WRITE_MAC_BYTE      0x60000000
1851 #define PHY_CLEAR_READCOUNT     0x70000000
1852 #define PHY_WRITE               0x80000000
1853 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1854 #define PHY_COMP_EQ_SKIPN       0xa0000000
1855 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1856 #define PHY_WRITE_PREVIOUS      0xc0000000
1857 #define PHY_SKIPN               0xd0000000
1858 #define PHY_DELAY_MS            0xe0000000
1859 #define PHY_WRITE_ERI_WORD      0xf0000000
1860
1861 struct fw_info {
1862         u32     magic;
1863         char    version[RTL_VER_SIZE];
1864         __le32  fw_start;
1865         __le32  fw_len;
1866         u8      chksum;
1867 } __packed;
1868
1869 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1870
1871 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1872 {
1873         const struct firmware *fw = rtl_fw->fw;
1874         struct fw_info *fw_info = (struct fw_info *)fw->data;
1875         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1876         char *version = rtl_fw->version;
1877         bool rc = false;
1878
1879         if (fw->size < FW_OPCODE_SIZE)
1880                 goto out;
1881
1882         if (!fw_info->magic) {
1883                 size_t i, size, start;
1884                 u8 checksum = 0;
1885
1886                 if (fw->size < sizeof(*fw_info))
1887                         goto out;
1888
1889                 for (i = 0; i < fw->size; i++)
1890                         checksum += fw->data[i];
1891                 if (checksum != 0)
1892                         goto out;
1893
1894                 start = le32_to_cpu(fw_info->fw_start);
1895                 if (start > fw->size)
1896                         goto out;
1897
1898                 size = le32_to_cpu(fw_info->fw_len);
1899                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1900                         goto out;
1901
1902                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1903
1904                 pa->code = (__le32 *)(fw->data + start);
1905                 pa->size = size;
1906         } else {
1907                 if (fw->size % FW_OPCODE_SIZE)
1908                         goto out;
1909
1910                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1911
1912                 pa->code = (__le32 *)fw->data;
1913                 pa->size = fw->size / FW_OPCODE_SIZE;
1914         }
1915         version[RTL_VER_SIZE - 1] = 0;
1916
1917         rc = true;
1918 out:
1919         return rc;
1920 }
1921
1922 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1923                            struct rtl_fw_phy_action *pa)
1924 {
1925         bool rc = false;
1926         size_t index;
1927
1928         for (index = 0; index < pa->size; index++) {
1929                 u32 action = le32_to_cpu(pa->code[index]);
1930                 u32 regno = (action & 0x0fff0000) >> 16;
1931
1932                 switch(action & 0xf0000000) {
1933                 case PHY_READ:
1934                 case PHY_DATA_OR:
1935                 case PHY_DATA_AND:
1936                 case PHY_READ_EFUSE:
1937                 case PHY_CLEAR_READCOUNT:
1938                 case PHY_WRITE:
1939                 case PHY_WRITE_PREVIOUS:
1940                 case PHY_DELAY_MS:
1941                         break;
1942
1943                 case PHY_BJMPN:
1944                         if (regno > index) {
1945                                 netif_err(tp, ifup, tp->dev,
1946                                           "Out of range of firmware\n");
1947                                 goto out;
1948                         }
1949                         break;
1950                 case PHY_READCOUNT_EQ_SKIP:
1951                         if (index + 2 >= pa->size) {
1952                                 netif_err(tp, ifup, tp->dev,
1953                                           "Out of range of firmware\n");
1954                                 goto out;
1955                         }
1956                         break;
1957                 case PHY_COMP_EQ_SKIPN:
1958                 case PHY_COMP_NEQ_SKIPN:
1959                 case PHY_SKIPN:
1960                         if (index + 1 + regno >= pa->size) {
1961                                 netif_err(tp, ifup, tp->dev,
1962                                           "Out of range of firmware\n");
1963                                 goto out;
1964                         }
1965                         break;
1966
1967                 case PHY_READ_MAC_BYTE:
1968                 case PHY_WRITE_MAC_BYTE:
1969                 case PHY_WRITE_ERI_WORD:
1970                 default:
1971                         netif_err(tp, ifup, tp->dev,
1972                                   "Invalid action 0x%08x\n", action);
1973                         goto out;
1974                 }
1975         }
1976         rc = true;
1977 out:
1978         return rc;
1979 }
1980
1981 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1982 {
1983         struct net_device *dev = tp->dev;
1984         int rc = -EINVAL;
1985
1986         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1987                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1988                 goto out;
1989         }
1990
1991         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1992                 rc = 0;
1993 out:
1994         return rc;
1995 }
1996
1997 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1998 {
1999         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2000         u32 predata, count;
2001         size_t index;
2002
2003         predata = count = 0;
2004
2005         for (index = 0; index < pa->size; ) {
2006                 u32 action = le32_to_cpu(pa->code[index]);
2007                 u32 data = action & 0x0000ffff;
2008                 u32 regno = (action & 0x0fff0000) >> 16;
2009
2010                 if (!action)
2011                         break;
2012
2013                 switch(action & 0xf0000000) {
2014                 case PHY_READ:
2015                         predata = rtl_readphy(tp, regno);
2016                         count++;
2017                         index++;
2018                         break;
2019                 case PHY_DATA_OR:
2020                         predata |= data;
2021                         index++;
2022                         break;
2023                 case PHY_DATA_AND:
2024                         predata &= data;
2025                         index++;
2026                         break;
2027                 case PHY_BJMPN:
2028                         index -= regno;
2029                         break;
2030                 case PHY_READ_EFUSE:
2031                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2032                         index++;
2033                         break;
2034                 case PHY_CLEAR_READCOUNT:
2035                         count = 0;
2036                         index++;
2037                         break;
2038                 case PHY_WRITE:
2039                         rtl_writephy(tp, regno, data);
2040                         index++;
2041                         break;
2042                 case PHY_READCOUNT_EQ_SKIP:
2043                         index += (count == data) ? 2 : 1;
2044                         break;
2045                 case PHY_COMP_EQ_SKIPN:
2046                         if (predata == data)
2047                                 index += regno;
2048                         index++;
2049                         break;
2050                 case PHY_COMP_NEQ_SKIPN:
2051                         if (predata != data)
2052                                 index += regno;
2053                         index++;
2054                         break;
2055                 case PHY_WRITE_PREVIOUS:
2056                         rtl_writephy(tp, regno, predata);
2057                         index++;
2058                         break;
2059                 case PHY_SKIPN:
2060                         index += regno + 1;
2061                         break;
2062                 case PHY_DELAY_MS:
2063                         mdelay(data);
2064                         index++;
2065                         break;
2066
2067                 case PHY_READ_MAC_BYTE:
2068                 case PHY_WRITE_MAC_BYTE:
2069                 case PHY_WRITE_ERI_WORD:
2070                 default:
2071                         BUG();
2072                 }
2073         }
2074 }
2075
2076 static void rtl_release_firmware(struct rtl8169_private *tp)
2077 {
2078         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2079                 release_firmware(tp->rtl_fw->fw);
2080                 kfree(tp->rtl_fw);
2081         }
2082         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2083 }
2084
2085 static void rtl_apply_firmware(struct rtl8169_private *tp)
2086 {
2087         struct rtl_fw *rtl_fw = tp->rtl_fw;
2088
2089         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2090         if (!IS_ERR_OR_NULL(rtl_fw))
2091                 rtl_phy_write_fw(tp, rtl_fw);
2092 }
2093
2094 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2095 {
2096         if (rtl_readphy(tp, reg) != val)
2097                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2098         else
2099                 rtl_apply_firmware(tp);
2100 }
2101
2102 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2103 {
2104         static const struct phy_reg phy_reg_init[] = {
2105                 { 0x1f, 0x0001 },
2106                 { 0x06, 0x006e },
2107                 { 0x08, 0x0708 },
2108                 { 0x15, 0x4000 },
2109                 { 0x18, 0x65c7 },
2110
2111                 { 0x1f, 0x0001 },
2112                 { 0x03, 0x00a1 },
2113                 { 0x02, 0x0008 },
2114                 { 0x01, 0x0120 },
2115                 { 0x00, 0x1000 },
2116                 { 0x04, 0x0800 },
2117                 { 0x04, 0x0000 },
2118
2119                 { 0x03, 0xff41 },
2120                 { 0x02, 0xdf60 },
2121                 { 0x01, 0x0140 },
2122                 { 0x00, 0x0077 },
2123                 { 0x04, 0x7800 },
2124                 { 0x04, 0x7000 },
2125
2126                 { 0x03, 0x802f },
2127                 { 0x02, 0x4f02 },
2128                 { 0x01, 0x0409 },
2129                 { 0x00, 0xf0f9 },
2130                 { 0x04, 0x9800 },
2131                 { 0x04, 0x9000 },
2132
2133                 { 0x03, 0xdf01 },
2134                 { 0x02, 0xdf20 },
2135                 { 0x01, 0xff95 },
2136                 { 0x00, 0xba00 },
2137                 { 0x04, 0xa800 },
2138                 { 0x04, 0xa000 },
2139
2140                 { 0x03, 0xff41 },
2141                 { 0x02, 0xdf20 },
2142                 { 0x01, 0x0140 },
2143                 { 0x00, 0x00bb },
2144                 { 0x04, 0xb800 },
2145                 { 0x04, 0xb000 },
2146
2147                 { 0x03, 0xdf41 },
2148                 { 0x02, 0xdc60 },
2149                 { 0x01, 0x6340 },
2150                 { 0x00, 0x007d },
2151                 { 0x04, 0xd800 },
2152                 { 0x04, 0xd000 },
2153
2154                 { 0x03, 0xdf01 },
2155                 { 0x02, 0xdf20 },
2156                 { 0x01, 0x100a },
2157                 { 0x00, 0xa0ff },
2158                 { 0x04, 0xf800 },
2159                 { 0x04, 0xf000 },
2160
2161                 { 0x1f, 0x0000 },
2162                 { 0x0b, 0x0000 },
2163                 { 0x00, 0x9200 }
2164         };
2165
2166         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2167 }
2168
2169 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2170 {
2171         static const struct phy_reg phy_reg_init[] = {
2172                 { 0x1f, 0x0002 },
2173                 { 0x01, 0x90d0 },
2174                 { 0x1f, 0x0000 }
2175         };
2176
2177         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2178 }
2179
2180 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2181 {
2182         struct pci_dev *pdev = tp->pci_dev;
2183
2184         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2185             (pdev->subsystem_device != 0xe000))
2186                 return;
2187
2188         rtl_writephy(tp, 0x1f, 0x0001);
2189         rtl_writephy(tp, 0x10, 0xf01b);
2190         rtl_writephy(tp, 0x1f, 0x0000);
2191 }
2192
2193 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2194 {
2195         static const struct phy_reg phy_reg_init[] = {
2196                 { 0x1f, 0x0001 },
2197                 { 0x04, 0x0000 },
2198                 { 0x03, 0x00a1 },
2199                 { 0x02, 0x0008 },
2200                 { 0x01, 0x0120 },
2201                 { 0x00, 0x1000 },
2202                 { 0x04, 0x0800 },
2203                 { 0x04, 0x9000 },
2204                 { 0x03, 0x802f },
2205                 { 0x02, 0x4f02 },
2206                 { 0x01, 0x0409 },
2207                 { 0x00, 0xf099 },
2208                 { 0x04, 0x9800 },
2209                 { 0x04, 0xa000 },
2210                 { 0x03, 0xdf01 },
2211                 { 0x02, 0xdf20 },
2212                 { 0x01, 0xff95 },
2213                 { 0x00, 0xba00 },
2214                 { 0x04, 0xa800 },
2215                 { 0x04, 0xf000 },
2216                 { 0x03, 0xdf01 },
2217                 { 0x02, 0xdf20 },
2218                 { 0x01, 0x101a },
2219                 { 0x00, 0xa0ff },
2220                 { 0x04, 0xf800 },
2221                 { 0x04, 0x0000 },
2222                 { 0x1f, 0x0000 },
2223
2224                 { 0x1f, 0x0001 },
2225                 { 0x10, 0xf41b },
2226                 { 0x14, 0xfb54 },
2227                 { 0x18, 0xf5c7 },
2228                 { 0x1f, 0x0000 },
2229
2230                 { 0x1f, 0x0001 },
2231                 { 0x17, 0x0cc0 },
2232                 { 0x1f, 0x0000 }
2233         };
2234
2235         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2236
2237         rtl8169scd_hw_phy_config_quirk(tp);
2238 }
2239
2240 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2241 {
2242         static const struct phy_reg phy_reg_init[] = {
2243                 { 0x1f, 0x0001 },
2244                 { 0x04, 0x0000 },
2245                 { 0x03, 0x00a1 },
2246                 { 0x02, 0x0008 },
2247                 { 0x01, 0x0120 },
2248                 { 0x00, 0x1000 },
2249                 { 0x04, 0x0800 },
2250                 { 0x04, 0x9000 },
2251                 { 0x03, 0x802f },
2252                 { 0x02, 0x4f02 },
2253                 { 0x01, 0x0409 },
2254                 { 0x00, 0xf099 },
2255                 { 0x04, 0x9800 },
2256                 { 0x04, 0xa000 },
2257                 { 0x03, 0xdf01 },
2258                 { 0x02, 0xdf20 },
2259                 { 0x01, 0xff95 },
2260                 { 0x00, 0xba00 },
2261                 { 0x04, 0xa800 },
2262                 { 0x04, 0xf000 },
2263                 { 0x03, 0xdf01 },
2264                 { 0x02, 0xdf20 },
2265                 { 0x01, 0x101a },
2266                 { 0x00, 0xa0ff },
2267                 { 0x04, 0xf800 },
2268                 { 0x04, 0x0000 },
2269                 { 0x1f, 0x0000 },
2270
2271                 { 0x1f, 0x0001 },
2272                 { 0x0b, 0x8480 },
2273                 { 0x1f, 0x0000 },
2274
2275                 { 0x1f, 0x0001 },
2276                 { 0x18, 0x67c7 },
2277                 { 0x04, 0x2000 },
2278                 { 0x03, 0x002f },
2279                 { 0x02, 0x4360 },
2280                 { 0x01, 0x0109 },
2281                 { 0x00, 0x3022 },
2282                 { 0x04, 0x2800 },
2283                 { 0x1f, 0x0000 },
2284
2285                 { 0x1f, 0x0001 },
2286                 { 0x17, 0x0cc0 },
2287                 { 0x1f, 0x0000 }
2288         };
2289
2290         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2291 }
2292
2293 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2294 {
2295         static const struct phy_reg phy_reg_init[] = {
2296                 { 0x10, 0xf41b },
2297                 { 0x1f, 0x0000 }
2298         };
2299
2300         rtl_writephy(tp, 0x1f, 0x0001);
2301         rtl_patchphy(tp, 0x16, 1 << 0);
2302
2303         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2304 }
2305
2306 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2307 {
2308         static const struct phy_reg phy_reg_init[] = {
2309                 { 0x1f, 0x0001 },
2310                 { 0x10, 0xf41b },
2311                 { 0x1f, 0x0000 }
2312         };
2313
2314         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 }
2316
2317 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2318 {
2319         static const struct phy_reg phy_reg_init[] = {
2320                 { 0x1f, 0x0000 },
2321                 { 0x1d, 0x0f00 },
2322                 { 0x1f, 0x0002 },
2323                 { 0x0c, 0x1ec8 },
2324                 { 0x1f, 0x0000 }
2325         };
2326
2327         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2328 }
2329
2330 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2331 {
2332         static const struct phy_reg phy_reg_init[] = {
2333                 { 0x1f, 0x0001 },
2334                 { 0x1d, 0x3d98 },
2335                 { 0x1f, 0x0000 }
2336         };
2337
2338         rtl_writephy(tp, 0x1f, 0x0000);
2339         rtl_patchphy(tp, 0x14, 1 << 5);
2340         rtl_patchphy(tp, 0x0d, 1 << 5);
2341
2342         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2343 }
2344
2345 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2346 {
2347         static const struct phy_reg phy_reg_init[] = {
2348                 { 0x1f, 0x0001 },
2349                 { 0x12, 0x2300 },
2350                 { 0x1f, 0x0002 },
2351                 { 0x00, 0x88d4 },
2352                 { 0x01, 0x82b1 },
2353                 { 0x03, 0x7002 },
2354                 { 0x08, 0x9e30 },
2355                 { 0x09, 0x01f0 },
2356                 { 0x0a, 0x5500 },
2357                 { 0x0c, 0x00c8 },
2358                 { 0x1f, 0x0003 },
2359                 { 0x12, 0xc096 },
2360                 { 0x16, 0x000a },
2361                 { 0x1f, 0x0000 },
2362                 { 0x1f, 0x0000 },
2363                 { 0x09, 0x2000 },
2364                 { 0x09, 0x0000 }
2365         };
2366
2367         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2368
2369         rtl_patchphy(tp, 0x14, 1 << 5);
2370         rtl_patchphy(tp, 0x0d, 1 << 5);
2371         rtl_writephy(tp, 0x1f, 0x0000);
2372 }
2373
2374 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2375 {
2376         static const struct phy_reg phy_reg_init[] = {
2377                 { 0x1f, 0x0001 },
2378                 { 0x12, 0x2300 },
2379                 { 0x03, 0x802f },
2380                 { 0x02, 0x4f02 },
2381                 { 0x01, 0x0409 },
2382                 { 0x00, 0xf099 },
2383                 { 0x04, 0x9800 },
2384                 { 0x04, 0x9000 },
2385                 { 0x1d, 0x3d98 },
2386                 { 0x1f, 0x0002 },
2387                 { 0x0c, 0x7eb8 },
2388                 { 0x06, 0x0761 },
2389                 { 0x1f, 0x0003 },
2390                 { 0x16, 0x0f0a },
2391                 { 0x1f, 0x0000 }
2392         };
2393
2394         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2395
2396         rtl_patchphy(tp, 0x16, 1 << 0);
2397         rtl_patchphy(tp, 0x14, 1 << 5);
2398         rtl_patchphy(tp, 0x0d, 1 << 5);
2399         rtl_writephy(tp, 0x1f, 0x0000);
2400 }
2401
2402 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2403 {
2404         static const struct phy_reg phy_reg_init[] = {
2405                 { 0x1f, 0x0001 },
2406                 { 0x12, 0x2300 },
2407                 { 0x1d, 0x3d98 },
2408                 { 0x1f, 0x0002 },
2409                 { 0x0c, 0x7eb8 },
2410                 { 0x06, 0x5461 },
2411                 { 0x1f, 0x0003 },
2412                 { 0x16, 0x0f0a },
2413                 { 0x1f, 0x0000 }
2414         };
2415
2416         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2417
2418         rtl_patchphy(tp, 0x16, 1 << 0);
2419         rtl_patchphy(tp, 0x14, 1 << 5);
2420         rtl_patchphy(tp, 0x0d, 1 << 5);
2421         rtl_writephy(tp, 0x1f, 0x0000);
2422 }
2423
2424 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2425 {
2426         rtl8168c_3_hw_phy_config(tp);
2427 }
2428
2429 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2430 {
2431         static const struct phy_reg phy_reg_init_0[] = {
2432                 /* Channel Estimation */
2433                 { 0x1f, 0x0001 },
2434                 { 0x06, 0x4064 },
2435                 { 0x07, 0x2863 },
2436                 { 0x08, 0x059c },
2437                 { 0x09, 0x26b4 },
2438                 { 0x0a, 0x6a19 },
2439                 { 0x0b, 0xdcc8 },
2440                 { 0x10, 0xf06d },
2441                 { 0x14, 0x7f68 },
2442                 { 0x18, 0x7fd9 },
2443                 { 0x1c, 0xf0ff },
2444                 { 0x1d, 0x3d9c },
2445                 { 0x1f, 0x0003 },
2446                 { 0x12, 0xf49f },
2447                 { 0x13, 0x070b },
2448                 { 0x1a, 0x05ad },
2449                 { 0x14, 0x94c0 },
2450
2451                 /*
2452                  * Tx Error Issue
2453                  * Enhance line driver power
2454                  */
2455                 { 0x1f, 0x0002 },
2456                 { 0x06, 0x5561 },
2457                 { 0x1f, 0x0005 },
2458                 { 0x05, 0x8332 },
2459                 { 0x06, 0x5561 },
2460
2461                 /*
2462                  * Can not link to 1Gbps with bad cable
2463                  * Decrease SNR threshold form 21.07dB to 19.04dB
2464                  */
2465                 { 0x1f, 0x0001 },
2466                 { 0x17, 0x0cc0 },
2467
2468                 { 0x1f, 0x0000 },
2469                 { 0x0d, 0xf880 }
2470         };
2471         void __iomem *ioaddr = tp->mmio_addr;
2472
2473         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2474
2475         /*
2476          * Rx Error Issue
2477          * Fine Tune Switching regulator parameter
2478          */
2479         rtl_writephy(tp, 0x1f, 0x0002);
2480         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2481         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2482
2483         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2484                 static const struct phy_reg phy_reg_init[] = {
2485                         { 0x1f, 0x0002 },
2486                         { 0x05, 0x669a },
2487                         { 0x1f, 0x0005 },
2488                         { 0x05, 0x8330 },
2489                         { 0x06, 0x669a },
2490                         { 0x1f, 0x0002 }
2491                 };
2492                 int val;
2493
2494                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2495
2496                 val = rtl_readphy(tp, 0x0d);
2497
2498                 if ((val & 0x00ff) != 0x006c) {
2499                         static const u32 set[] = {
2500                                 0x0065, 0x0066, 0x0067, 0x0068,
2501                                 0x0069, 0x006a, 0x006b, 0x006c
2502                         };
2503                         int i;
2504
2505                         rtl_writephy(tp, 0x1f, 0x0002);
2506
2507                         val &= 0xff00;
2508                         for (i = 0; i < ARRAY_SIZE(set); i++)
2509                                 rtl_writephy(tp, 0x0d, val | set[i]);
2510                 }
2511         } else {
2512                 static const struct phy_reg phy_reg_init[] = {
2513                         { 0x1f, 0x0002 },
2514                         { 0x05, 0x6662 },
2515                         { 0x1f, 0x0005 },
2516                         { 0x05, 0x8330 },
2517                         { 0x06, 0x6662 }
2518                 };
2519
2520                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2521         }
2522
2523         /* RSET couple improve */
2524         rtl_writephy(tp, 0x1f, 0x0002);
2525         rtl_patchphy(tp, 0x0d, 0x0300);
2526         rtl_patchphy(tp, 0x0f, 0x0010);
2527
2528         /* Fine tune PLL performance */
2529         rtl_writephy(tp, 0x1f, 0x0002);
2530         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2531         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2532
2533         rtl_writephy(tp, 0x1f, 0x0005);
2534         rtl_writephy(tp, 0x05, 0x001b);
2535
2536         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2537
2538         rtl_writephy(tp, 0x1f, 0x0000);
2539 }
2540
2541 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2542 {
2543         static const struct phy_reg phy_reg_init_0[] = {
2544                 /* Channel Estimation */
2545                 { 0x1f, 0x0001 },
2546                 { 0x06, 0x4064 },
2547                 { 0x07, 0x2863 },
2548                 { 0x08, 0x059c },
2549                 { 0x09, 0x26b4 },
2550                 { 0x0a, 0x6a19 },
2551                 { 0x0b, 0xdcc8 },
2552                 { 0x10, 0xf06d },
2553                 { 0x14, 0x7f68 },
2554                 { 0x18, 0x7fd9 },
2555                 { 0x1c, 0xf0ff },
2556                 { 0x1d, 0x3d9c },
2557                 { 0x1f, 0x0003 },
2558                 { 0x12, 0xf49f },
2559                 { 0x13, 0x070b },
2560                 { 0x1a, 0x05ad },
2561                 { 0x14, 0x94c0 },
2562
2563                 /*
2564                  * Tx Error Issue
2565                  * Enhance line driver power
2566                  */
2567                 { 0x1f, 0x0002 },
2568                 { 0x06, 0x5561 },
2569                 { 0x1f, 0x0005 },
2570                 { 0x05, 0x8332 },
2571                 { 0x06, 0x5561 },
2572
2573                 /*
2574                  * Can not link to 1Gbps with bad cable
2575                  * Decrease SNR threshold form 21.07dB to 19.04dB
2576                  */
2577                 { 0x1f, 0x0001 },
2578                 { 0x17, 0x0cc0 },
2579
2580                 { 0x1f, 0x0000 },
2581                 { 0x0d, 0xf880 }
2582         };
2583         void __iomem *ioaddr = tp->mmio_addr;
2584
2585         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2586
2587         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2588                 static const struct phy_reg phy_reg_init[] = {
2589                         { 0x1f, 0x0002 },
2590                         { 0x05, 0x669a },
2591                         { 0x1f, 0x0005 },
2592                         { 0x05, 0x8330 },
2593                         { 0x06, 0x669a },
2594
2595                         { 0x1f, 0x0002 }
2596                 };
2597                 int val;
2598
2599                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600
2601                 val = rtl_readphy(tp, 0x0d);
2602                 if ((val & 0x00ff) != 0x006c) {
2603                         static const u32 set[] = {
2604                                 0x0065, 0x0066, 0x0067, 0x0068,
2605                                 0x0069, 0x006a, 0x006b, 0x006c
2606                         };
2607                         int i;
2608
2609                         rtl_writephy(tp, 0x1f, 0x0002);
2610
2611                         val &= 0xff00;
2612                         for (i = 0; i < ARRAY_SIZE(set); i++)
2613                                 rtl_writephy(tp, 0x0d, val | set[i]);
2614                 }
2615         } else {
2616                 static const struct phy_reg phy_reg_init[] = {
2617                         { 0x1f, 0x0002 },
2618                         { 0x05, 0x2642 },
2619                         { 0x1f, 0x0005 },
2620                         { 0x05, 0x8330 },
2621                         { 0x06, 0x2642 }
2622                 };
2623
2624                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2625         }
2626
2627         /* Fine tune PLL performance */
2628         rtl_writephy(tp, 0x1f, 0x0002);
2629         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2630         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2631
2632         /* Switching regulator Slew rate */
2633         rtl_writephy(tp, 0x1f, 0x0002);
2634         rtl_patchphy(tp, 0x0f, 0x0017);
2635
2636         rtl_writephy(tp, 0x1f, 0x0005);
2637         rtl_writephy(tp, 0x05, 0x001b);
2638
2639         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2640
2641         rtl_writephy(tp, 0x1f, 0x0000);
2642 }
2643
2644 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2645 {
2646         static const struct phy_reg phy_reg_init[] = {
2647                 { 0x1f, 0x0002 },
2648                 { 0x10, 0x0008 },
2649                 { 0x0d, 0x006c },
2650
2651                 { 0x1f, 0x0000 },
2652                 { 0x0d, 0xf880 },
2653
2654                 { 0x1f, 0x0001 },
2655                 { 0x17, 0x0cc0 },
2656
2657                 { 0x1f, 0x0001 },
2658                 { 0x0b, 0xa4d8 },
2659                 { 0x09, 0x281c },
2660                 { 0x07, 0x2883 },
2661                 { 0x0a, 0x6b35 },
2662                 { 0x1d, 0x3da4 },
2663                 { 0x1c, 0xeffd },
2664                 { 0x14, 0x7f52 },
2665                 { 0x18, 0x7fc6 },
2666                 { 0x08, 0x0601 },
2667                 { 0x06, 0x4063 },
2668                 { 0x10, 0xf074 },
2669                 { 0x1f, 0x0003 },
2670                 { 0x13, 0x0789 },
2671                 { 0x12, 0xf4bd },
2672                 { 0x1a, 0x04fd },
2673                 { 0x14, 0x84b0 },
2674                 { 0x1f, 0x0000 },
2675                 { 0x00, 0x9200 },
2676
2677                 { 0x1f, 0x0005 },
2678                 { 0x01, 0x0340 },
2679                 { 0x1f, 0x0001 },
2680                 { 0x04, 0x4000 },
2681                 { 0x03, 0x1d21 },
2682                 { 0x02, 0x0c32 },
2683                 { 0x01, 0x0200 },
2684                 { 0x00, 0x5554 },
2685                 { 0x04, 0x4800 },
2686                 { 0x04, 0x4000 },
2687                 { 0x04, 0xf000 },
2688                 { 0x03, 0xdf01 },
2689                 { 0x02, 0xdf20 },
2690                 { 0x01, 0x101a },
2691                 { 0x00, 0xa0ff },
2692                 { 0x04, 0xf800 },
2693                 { 0x04, 0xf000 },
2694                 { 0x1f, 0x0000 },
2695
2696                 { 0x1f, 0x0007 },
2697                 { 0x1e, 0x0023 },
2698                 { 0x16, 0x0000 },
2699                 { 0x1f, 0x0000 }
2700         };
2701
2702         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2703 }
2704
2705 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2706 {
2707         static const struct phy_reg phy_reg_init[] = {
2708                 { 0x1f, 0x0001 },
2709                 { 0x17, 0x0cc0 },
2710
2711                 { 0x1f, 0x0007 },
2712                 { 0x1e, 0x002d },
2713                 { 0x18, 0x0040 },
2714                 { 0x1f, 0x0000 }
2715         };
2716
2717         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2718         rtl_patchphy(tp, 0x0d, 1 << 5);
2719 }
2720
2721 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2722 {
2723         static const struct phy_reg phy_reg_init[] = {
2724                 /* Enable Delay cap */
2725                 { 0x1f, 0x0005 },
2726                 { 0x05, 0x8b80 },
2727                 { 0x06, 0xc896 },
2728                 { 0x1f, 0x0000 },
2729
2730                 /* Channel estimation fine tune */
2731                 { 0x1f, 0x0001 },
2732                 { 0x0b, 0x6c20 },
2733                 { 0x07, 0x2872 },
2734                 { 0x1c, 0xefff },
2735                 { 0x1f, 0x0003 },
2736                 { 0x14, 0x6420 },
2737                 { 0x1f, 0x0000 },
2738
2739                 /* Update PFM & 10M TX idle timer */
2740                 { 0x1f, 0x0007 },
2741                 { 0x1e, 0x002f },
2742                 { 0x15, 0x1919 },
2743                 { 0x1f, 0x0000 },
2744
2745                 { 0x1f, 0x0007 },
2746                 { 0x1e, 0x00ac },
2747                 { 0x18, 0x0006 },
2748                 { 0x1f, 0x0000 }
2749         };
2750
2751         rtl_apply_firmware(tp);
2752
2753         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755         /* DCO enable for 10M IDLE Power */
2756         rtl_writephy(tp, 0x1f, 0x0007);
2757         rtl_writephy(tp, 0x1e, 0x0023);
2758         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2759         rtl_writephy(tp, 0x1f, 0x0000);
2760
2761         /* For impedance matching */
2762         rtl_writephy(tp, 0x1f, 0x0002);
2763         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2764         rtl_writephy(tp, 0x1f, 0x0000);
2765
2766         /* PHY auto speed down */
2767         rtl_writephy(tp, 0x1f, 0x0007);
2768         rtl_writephy(tp, 0x1e, 0x002d);
2769         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2770         rtl_writephy(tp, 0x1f, 0x0000);
2771         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2772
2773         rtl_writephy(tp, 0x1f, 0x0005);
2774         rtl_writephy(tp, 0x05, 0x8b86);
2775         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2776         rtl_writephy(tp, 0x1f, 0x0000);
2777
2778         rtl_writephy(tp, 0x1f, 0x0005);
2779         rtl_writephy(tp, 0x05, 0x8b85);
2780         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2781         rtl_writephy(tp, 0x1f, 0x0007);
2782         rtl_writephy(tp, 0x1e, 0x0020);
2783         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2784         rtl_writephy(tp, 0x1f, 0x0006);
2785         rtl_writephy(tp, 0x00, 0x5a00);
2786         rtl_writephy(tp, 0x1f, 0x0000);
2787         rtl_writephy(tp, 0x0d, 0x0007);
2788         rtl_writephy(tp, 0x0e, 0x003c);
2789         rtl_writephy(tp, 0x0d, 0x4007);
2790         rtl_writephy(tp, 0x0e, 0x0000);
2791         rtl_writephy(tp, 0x0d, 0x0000);
2792 }
2793
2794 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2795 {
2796         static const struct phy_reg phy_reg_init[] = {
2797                 /* Enable Delay cap */
2798                 { 0x1f, 0x0004 },
2799                 { 0x1f, 0x0007 },
2800                 { 0x1e, 0x00ac },
2801                 { 0x18, 0x0006 },
2802                 { 0x1f, 0x0002 },
2803                 { 0x1f, 0x0000 },
2804                 { 0x1f, 0x0000 },
2805
2806                 /* Channel estimation fine tune */
2807                 { 0x1f, 0x0003 },
2808                 { 0x09, 0xa20f },
2809                 { 0x1f, 0x0000 },
2810                 { 0x1f, 0x0000 },
2811
2812                 /* Green Setting */
2813                 { 0x1f, 0x0005 },
2814                 { 0x05, 0x8b5b },
2815                 { 0x06, 0x9222 },
2816                 { 0x05, 0x8b6d },
2817                 { 0x06, 0x8000 },
2818                 { 0x05, 0x8b76 },
2819                 { 0x06, 0x8000 },
2820                 { 0x1f, 0x0000 }
2821         };
2822
2823         rtl_apply_firmware(tp);
2824
2825         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2826
2827         /* For 4-corner performance improve */
2828         rtl_writephy(tp, 0x1f, 0x0005);
2829         rtl_writephy(tp, 0x05, 0x8b80);
2830         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2831         rtl_writephy(tp, 0x1f, 0x0000);
2832
2833         /* PHY auto speed down */
2834         rtl_writephy(tp, 0x1f, 0x0004);
2835         rtl_writephy(tp, 0x1f, 0x0007);
2836         rtl_writephy(tp, 0x1e, 0x002d);
2837         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2838         rtl_writephy(tp, 0x1f, 0x0002);
2839         rtl_writephy(tp, 0x1f, 0x0000);
2840         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2841
2842         /* improve 10M EEE waveform */
2843         rtl_writephy(tp, 0x1f, 0x0005);
2844         rtl_writephy(tp, 0x05, 0x8b86);
2845         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2846         rtl_writephy(tp, 0x1f, 0x0000);
2847
2848         /* Improve 2-pair detection performance */
2849         rtl_writephy(tp, 0x1f, 0x0005);
2850         rtl_writephy(tp, 0x05, 0x8b85);
2851         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2852         rtl_writephy(tp, 0x1f, 0x0000);
2853
2854         /* EEE setting */
2855         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2856                      ERIAR_EXGMAC);
2857         rtl_writephy(tp, 0x1f, 0x0005);
2858         rtl_writephy(tp, 0x05, 0x8b85);
2859         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2860         rtl_writephy(tp, 0x1f, 0x0004);
2861         rtl_writephy(tp, 0x1f, 0x0007);
2862         rtl_writephy(tp, 0x1e, 0x0020);
2863         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2864         rtl_writephy(tp, 0x1f, 0x0002);
2865         rtl_writephy(tp, 0x1f, 0x0000);
2866         rtl_writephy(tp, 0x0d, 0x0007);
2867         rtl_writephy(tp, 0x0e, 0x003c);
2868         rtl_writephy(tp, 0x0d, 0x4007);
2869         rtl_writephy(tp, 0x0e, 0x0000);
2870         rtl_writephy(tp, 0x0d, 0x0000);
2871
2872         /* Green feature */
2873         rtl_writephy(tp, 0x1f, 0x0003);
2874         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2875         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2876         rtl_writephy(tp, 0x1f, 0x0000);
2877 }
2878
2879 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881         static const struct phy_reg phy_reg_init[] = {
2882                 { 0x1f, 0x0003 },
2883                 { 0x08, 0x441d },
2884                 { 0x01, 0x9100 },
2885                 { 0x1f, 0x0000 }
2886         };
2887
2888         rtl_writephy(tp, 0x1f, 0x0000);
2889         rtl_patchphy(tp, 0x11, 1 << 12);
2890         rtl_patchphy(tp, 0x19, 1 << 13);
2891         rtl_patchphy(tp, 0x10, 1 << 15);
2892
2893         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2894 }
2895
2896 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2897 {
2898         static const struct phy_reg phy_reg_init[] = {
2899                 { 0x1f, 0x0005 },
2900                 { 0x1a, 0x0000 },
2901                 { 0x1f, 0x0000 },
2902
2903                 { 0x1f, 0x0004 },
2904                 { 0x1c, 0x0000 },
2905                 { 0x1f, 0x0000 },
2906
2907                 { 0x1f, 0x0001 },
2908                 { 0x15, 0x7701 },
2909                 { 0x1f, 0x0000 }
2910         };
2911
2912         /* Disable ALDPS before ram code */
2913         rtl_writephy(tp, 0x1f, 0x0000);
2914         rtl_writephy(tp, 0x18, 0x0310);
2915         msleep(100);
2916
2917         rtl_apply_firmware(tp);
2918
2919         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2920 }
2921
2922 static void rtl_hw_phy_config(struct net_device *dev)
2923 {
2924         struct rtl8169_private *tp = netdev_priv(dev);
2925
2926         rtl8169_print_mac_version(tp);
2927
2928         switch (tp->mac_version) {
2929         case RTL_GIGA_MAC_VER_01:
2930                 break;
2931         case RTL_GIGA_MAC_VER_02:
2932         case RTL_GIGA_MAC_VER_03:
2933                 rtl8169s_hw_phy_config(tp);
2934                 break;
2935         case RTL_GIGA_MAC_VER_04:
2936                 rtl8169sb_hw_phy_config(tp);
2937                 break;
2938         case RTL_GIGA_MAC_VER_05:
2939                 rtl8169scd_hw_phy_config(tp);
2940                 break;
2941         case RTL_GIGA_MAC_VER_06:
2942                 rtl8169sce_hw_phy_config(tp);
2943                 break;
2944         case RTL_GIGA_MAC_VER_07:
2945         case RTL_GIGA_MAC_VER_08:
2946         case RTL_GIGA_MAC_VER_09:
2947                 rtl8102e_hw_phy_config(tp);
2948                 break;
2949         case RTL_GIGA_MAC_VER_11:
2950                 rtl8168bb_hw_phy_config(tp);
2951                 break;
2952         case RTL_GIGA_MAC_VER_12:
2953                 rtl8168bef_hw_phy_config(tp);
2954                 break;
2955         case RTL_GIGA_MAC_VER_17:
2956                 rtl8168bef_hw_phy_config(tp);
2957                 break;
2958         case RTL_GIGA_MAC_VER_18:
2959                 rtl8168cp_1_hw_phy_config(tp);
2960                 break;
2961         case RTL_GIGA_MAC_VER_19:
2962                 rtl8168c_1_hw_phy_config(tp);
2963                 break;
2964         case RTL_GIGA_MAC_VER_20:
2965                 rtl8168c_2_hw_phy_config(tp);
2966                 break;
2967         case RTL_GIGA_MAC_VER_21:
2968                 rtl8168c_3_hw_phy_config(tp);
2969                 break;
2970         case RTL_GIGA_MAC_VER_22:
2971                 rtl8168c_4_hw_phy_config(tp);
2972                 break;
2973         case RTL_GIGA_MAC_VER_23:
2974         case RTL_GIGA_MAC_VER_24:
2975                 rtl8168cp_2_hw_phy_config(tp);
2976                 break;
2977         case RTL_GIGA_MAC_VER_25:
2978                 rtl8168d_1_hw_phy_config(tp);
2979                 break;
2980         case RTL_GIGA_MAC_VER_26:
2981                 rtl8168d_2_hw_phy_config(tp);
2982                 break;
2983         case RTL_GIGA_MAC_VER_27:
2984                 rtl8168d_3_hw_phy_config(tp);
2985                 break;
2986         case RTL_GIGA_MAC_VER_28:
2987                 rtl8168d_4_hw_phy_config(tp);
2988                 break;
2989         case RTL_GIGA_MAC_VER_29:
2990         case RTL_GIGA_MAC_VER_30:
2991                 rtl8105e_hw_phy_config(tp);
2992                 break;
2993         case RTL_GIGA_MAC_VER_31:
2994                 /* None. */
2995                 break;
2996         case RTL_GIGA_MAC_VER_32:
2997         case RTL_GIGA_MAC_VER_33:
2998                 rtl8168e_1_hw_phy_config(tp);
2999                 break;
3000         case RTL_GIGA_MAC_VER_34:
3001                 rtl8168e_2_hw_phy_config(tp);
3002                 break;
3003
3004         default:
3005                 break;
3006         }
3007 }
3008
3009 static void rtl8169_phy_timer(unsigned long __opaque)
3010 {
3011         struct net_device *dev = (struct net_device *)__opaque;
3012         struct rtl8169_private *tp = netdev_priv(dev);
3013         struct timer_list *timer = &tp->timer;
3014         void __iomem *ioaddr = tp->mmio_addr;
3015         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3016
3017         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3018
3019         spin_lock_irq(&tp->lock);
3020
3021         if (tp->phy_reset_pending(tp)) {
3022                 /*
3023                  * A busy loop could burn quite a few cycles on nowadays CPU.
3024                  * Let's delay the execution of the timer for a few ticks.
3025                  */
3026                 timeout = HZ/10;
3027                 goto out_mod_timer;
3028         }
3029
3030         if (tp->link_ok(ioaddr))
3031                 goto out_unlock;
3032
3033         netif_warn(tp, link, dev, "PHY reset until link up\n");
3034
3035         tp->phy_reset_enable(tp);
3036
3037 out_mod_timer:
3038         mod_timer(timer, jiffies + timeout);
3039 out_unlock:
3040         spin_unlock_irq(&tp->lock);
3041 }
3042
3043 #ifdef CONFIG_NET_POLL_CONTROLLER
3044 /*
3045  * Polling 'interrupt' - used by things like netconsole to send skbs
3046  * without having to re-enable interrupts. It's not called while
3047  * the interrupt routine is executing.
3048  */
3049 static void rtl8169_netpoll(struct net_device *dev)
3050 {
3051         struct rtl8169_private *tp = netdev_priv(dev);
3052         struct pci_dev *pdev = tp->pci_dev;
3053
3054         disable_irq(pdev->irq);
3055         rtl8169_interrupt(pdev->irq, dev);
3056         enable_irq(pdev->irq);
3057 }
3058 #endif
3059
3060 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3061                                   void __iomem *ioaddr)
3062 {
3063         iounmap(ioaddr);
3064         pci_release_regions(pdev);
3065         pci_clear_mwi(pdev);
3066         pci_disable_device(pdev);
3067         free_netdev(dev);
3068 }
3069
3070 static void rtl8169_phy_reset(struct net_device *dev,
3071                               struct rtl8169_private *tp)
3072 {
3073         unsigned int i;
3074
3075         tp->phy_reset_enable(tp);
3076         for (i = 0; i < 100; i++) {
3077                 if (!tp->phy_reset_pending(tp))
3078                         return;
3079                 msleep(1);
3080         }
3081         netif_err(tp, link, dev, "PHY reset failed\n");
3082 }
3083
3084 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3085 {
3086         void __iomem *ioaddr = tp->mmio_addr;
3087
3088         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3089             (RTL_R8(PHYstatus) & TBI_Enable);
3090 }
3091
3092 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3093 {
3094         void __iomem *ioaddr = tp->mmio_addr;
3095
3096         rtl_hw_phy_config(dev);
3097
3098         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3099                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3100                 RTL_W8(0x82, 0x01);
3101         }
3102
3103         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3104
3105         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3106                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3107
3108         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3109                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3110                 RTL_W8(0x82, 0x01);
3111                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3112                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3113         }
3114
3115         rtl8169_phy_reset(dev, tp);
3116
3117         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3118                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3119                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3120                           (tp->mii.supports_gmii ?
3121                            ADVERTISED_1000baseT_Half |
3122                            ADVERTISED_1000baseT_Full : 0));
3123
3124         if (rtl_tbi_enabled(tp))
3125                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3126 }
3127
3128 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3129 {
3130         void __iomem *ioaddr = tp->mmio_addr;
3131         u32 high;
3132         u32 low;
3133
3134         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3135         high = addr[4] | (addr[5] << 8);
3136
3137         spin_lock_irq(&tp->lock);
3138
3139         RTL_W8(Cfg9346, Cfg9346_Unlock);
3140
3141         RTL_W32(MAC4, high);
3142         RTL_R32(MAC4);
3143
3144         RTL_W32(MAC0, low);
3145         RTL_R32(MAC0);
3146
3147         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3148                 const struct exgmac_reg e[] = {
3149                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3150                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3151                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3152                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3153                                                                 low  >> 16 },
3154                 };
3155
3156                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3157         }
3158
3159         RTL_W8(Cfg9346, Cfg9346_Lock);
3160
3161         spin_unlock_irq(&tp->lock);
3162 }
3163
3164 static int rtl_set_mac_address(struct net_device *dev, void *p)
3165 {
3166         struct rtl8169_private *tp = netdev_priv(dev);
3167         struct sockaddr *addr = p;
3168
3169         if (!is_valid_ether_addr(addr->sa_data))
3170                 return -EADDRNOTAVAIL;
3171
3172         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3173
3174         rtl_rar_set(tp, dev->dev_addr);
3175
3176         return 0;
3177 }
3178
3179 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3180 {
3181         struct rtl8169_private *tp = netdev_priv(dev);
3182         struct mii_ioctl_data *data = if_mii(ifr);
3183
3184         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3185 }
3186
3187 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3188                           struct mii_ioctl_data *data, int cmd)
3189 {
3190         switch (cmd) {
3191         case SIOCGMIIPHY:
3192                 data->phy_id = 32; /* Internal PHY */
3193                 return 0;
3194
3195         case SIOCGMIIREG:
3196                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3197                 return 0;
3198
3199         case SIOCSMIIREG:
3200                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3201                 return 0;
3202         }
3203         return -EOPNOTSUPP;
3204 }
3205
3206 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3207 {
3208         return -EOPNOTSUPP;
3209 }
3210
3211 static const struct rtl_cfg_info {
3212         void (*hw_start)(struct net_device *);
3213         unsigned int region;
3214         unsigned int align;
3215         u16 intr_event;
3216         u16 napi_event;
3217         unsigned features;
3218         u8 default_ver;
3219 } rtl_cfg_infos [] = {
3220         [RTL_CFG_0] = {
3221                 .hw_start       = rtl_hw_start_8169,
3222                 .region         = 1,
3223                 .align          = 0,
3224                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3225                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3226                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3227                 .features       = RTL_FEATURE_GMII,
3228                 .default_ver    = RTL_GIGA_MAC_VER_01,
3229         },
3230         [RTL_CFG_1] = {
3231                 .hw_start       = rtl_hw_start_8168,
3232                 .region         = 2,
3233                 .align          = 8,
3234                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3235                                   TxErr | TxOK | RxOK | RxErr,
3236                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3237                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3238                 .default_ver    = RTL_GIGA_MAC_VER_11,
3239         },
3240         [RTL_CFG_2] = {
3241                 .hw_start       = rtl_hw_start_8101,
3242                 .region         = 2,
3243                 .align          = 8,
3244                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3245                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3246                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3247                 .features       = RTL_FEATURE_MSI,
3248                 .default_ver    = RTL_GIGA_MAC_VER_13,
3249         }
3250 };
3251
3252 /* Cfg9346_Unlock assumed. */
3253 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3254                             const struct rtl_cfg_info *cfg)
3255 {
3256         unsigned msi = 0;
3257         u8 cfg2;
3258
3259         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3260         if (cfg->features & RTL_FEATURE_MSI) {
3261                 if (pci_enable_msi(pdev)) {
3262                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3263                 } else {
3264                         cfg2 |= MSIEnable;
3265                         msi = RTL_FEATURE_MSI;
3266                 }
3267         }
3268         RTL_W8(Config2, cfg2);
3269         return msi;
3270 }
3271
3272 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3273 {
3274         if (tp->features & RTL_FEATURE_MSI) {
3275                 pci_disable_msi(pdev);
3276                 tp->features &= ~RTL_FEATURE_MSI;
3277         }
3278 }
3279
3280 static const struct net_device_ops rtl8169_netdev_ops = {
3281         .ndo_open               = rtl8169_open,
3282         .ndo_stop               = rtl8169_close,
3283         .ndo_get_stats          = rtl8169_get_stats,
3284         .ndo_start_xmit         = rtl8169_start_xmit,
3285         .ndo_tx_timeout         = rtl8169_tx_timeout,
3286         .ndo_validate_addr      = eth_validate_addr,
3287         .ndo_change_mtu         = rtl8169_change_mtu,
3288         .ndo_fix_features       = rtl8169_fix_features,
3289         .ndo_set_features       = rtl8169_set_features,
3290         .ndo_set_mac_address    = rtl_set_mac_address,
3291         .ndo_do_ioctl           = rtl8169_ioctl,
3292         .ndo_set_rx_mode        = rtl_set_rx_mode,
3293 #ifdef CONFIG_NET_POLL_CONTROLLER
3294         .ndo_poll_controller    = rtl8169_netpoll,
3295 #endif
3296
3297 };
3298
3299 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3300 {
3301         struct mdio_ops *ops = &tp->mdio_ops;
3302
3303         switch (tp->mac_version) {
3304         case RTL_GIGA_MAC_VER_27:
3305                 ops->write      = r8168dp_1_mdio_write;
3306                 ops->read       = r8168dp_1_mdio_read;
3307                 break;
3308         case RTL_GIGA_MAC_VER_28:
3309         case RTL_GIGA_MAC_VER_31:
3310                 ops->write      = r8168dp_2_mdio_write;
3311                 ops->read       = r8168dp_2_mdio_read;
3312                 break;
3313         default:
3314                 ops->write      = r8169_mdio_write;
3315                 ops->read       = r8169_mdio_read;
3316                 break;
3317         }
3318 }
3319
3320 static void r810x_phy_power_down(struct rtl8169_private *tp)
3321 {
3322         rtl_writephy(tp, 0x1f, 0x0000);
3323         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3324 }
3325
3326 static void r810x_phy_power_up(struct rtl8169_private *tp)
3327 {
3328         rtl_writephy(tp, 0x1f, 0x0000);
3329         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3330 }
3331
3332 static void r810x_pll_power_down(struct rtl8169_private *tp)
3333 {
3334         void __iomem *ioaddr = tp->mmio_addr;
3335
3336         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3337                 rtl_writephy(tp, 0x1f, 0x0000);
3338                 rtl_writephy(tp, MII_BMCR, 0x0000);
3339
3340                 if (tp->mac_version == RTL_GIGA_MAC_VER_29 ||
3341                     tp->mac_version == RTL_GIGA_MAC_VER_30)
3342                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3343                                 AcceptMulticast | AcceptMyPhys);
3344                 return;
3345         }
3346
3347         r810x_phy_power_down(tp);
3348 }
3349
3350 static void r810x_pll_power_up(struct rtl8169_private *tp)
3351 {
3352         r810x_phy_power_up(tp);
3353 }
3354
3355 static void r8168_phy_power_up(struct rtl8169_private *tp)
3356 {
3357         rtl_writephy(tp, 0x1f, 0x0000);
3358         switch (tp->mac_version) {
3359         case RTL_GIGA_MAC_VER_11:
3360         case RTL_GIGA_MAC_VER_12:
3361         case RTL_GIGA_MAC_VER_17:
3362         case RTL_GIGA_MAC_VER_18:
3363         case RTL_GIGA_MAC_VER_19:
3364         case RTL_GIGA_MAC_VER_20:
3365         case RTL_GIGA_MAC_VER_21:
3366         case RTL_GIGA_MAC_VER_22:
3367         case RTL_GIGA_MAC_VER_23:
3368         case RTL_GIGA_MAC_VER_24:
3369         case RTL_GIGA_MAC_VER_25:
3370         case RTL_GIGA_MAC_VER_26:
3371         case RTL_GIGA_MAC_VER_27:
3372         case RTL_GIGA_MAC_VER_28:
3373         case RTL_GIGA_MAC_VER_31:
3374                 rtl_writephy(tp, 0x0e, 0x0000);
3375                 break;
3376         default:
3377                 break;
3378         }
3379         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3380 }
3381
3382 static void r8168_phy_power_down(struct rtl8169_private *tp)
3383 {
3384         rtl_writephy(tp, 0x1f, 0x0000);
3385         switch (tp->mac_version) {
3386         case RTL_GIGA_MAC_VER_32:
3387         case RTL_GIGA_MAC_VER_33:
3388                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3389                 break;
3390
3391         case RTL_GIGA_MAC_VER_11:
3392         case RTL_GIGA_MAC_VER_12:
3393         case RTL_GIGA_MAC_VER_17:
3394         case RTL_GIGA_MAC_VER_18:
3395         case RTL_GIGA_MAC_VER_19:
3396         case RTL_GIGA_MAC_VER_20:
3397         case RTL_GIGA_MAC_VER_21:
3398         case RTL_GIGA_MAC_VER_22:
3399         case RTL_GIGA_MAC_VER_23:
3400         case RTL_GIGA_MAC_VER_24:
3401         case RTL_GIGA_MAC_VER_25:
3402         case RTL_GIGA_MAC_VER_26:
3403         case RTL_GIGA_MAC_VER_27:
3404         case RTL_GIGA_MAC_VER_28:
3405         case RTL_GIGA_MAC_VER_31:
3406                 rtl_writephy(tp, 0x0e, 0x0200);
3407         default:
3408                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3409                 break;
3410         }
3411 }
3412
3413 static void r8168_pll_power_down(struct rtl8169_private *tp)
3414 {
3415         void __iomem *ioaddr = tp->mmio_addr;
3416
3417         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3418              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3419              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3420             r8168dp_check_dash(tp)) {
3421                 return;
3422         }
3423
3424         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3425              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3426             (RTL_R16(CPlusCmd) & ASF)) {
3427                 return;
3428         }
3429
3430         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3431             tp->mac_version == RTL_GIGA_MAC_VER_33)
3432                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3433
3434         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3435                 rtl_writephy(tp, 0x1f, 0x0000);
3436                 rtl_writephy(tp, MII_BMCR, 0x0000);
3437
3438                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3439                     tp->mac_version == RTL_GIGA_MAC_VER_33 ||
3440                     tp->mac_version == RTL_GIGA_MAC_VER_34)
3441                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3442                                 AcceptMulticast | AcceptMyPhys);
3443                 return;
3444         }
3445
3446         r8168_phy_power_down(tp);
3447
3448         switch (tp->mac_version) {
3449         case RTL_GIGA_MAC_VER_25:
3450         case RTL_GIGA_MAC_VER_26:
3451         case RTL_GIGA_MAC_VER_27:
3452         case RTL_GIGA_MAC_VER_28:
3453         case RTL_GIGA_MAC_VER_31:
3454         case RTL_GIGA_MAC_VER_32:
3455         case RTL_GIGA_MAC_VER_33:
3456                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3457                 break;
3458         }
3459 }
3460
3461 static void r8168_pll_power_up(struct rtl8169_private *tp)
3462 {
3463         void __iomem *ioaddr = tp->mmio_addr;
3464
3465         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3466              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3467              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3468             r8168dp_check_dash(tp)) {
3469                 return;
3470         }
3471
3472         switch (tp->mac_version) {
3473         case RTL_GIGA_MAC_VER_25:
3474         case RTL_GIGA_MAC_VER_26:
3475         case RTL_GIGA_MAC_VER_27:
3476         case RTL_GIGA_MAC_VER_28:
3477         case RTL_GIGA_MAC_VER_31:
3478         case RTL_GIGA_MAC_VER_32:
3479         case RTL_GIGA_MAC_VER_33:
3480                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3481                 break;
3482         }
3483
3484         r8168_phy_power_up(tp);
3485 }
3486
3487 static void rtl_pll_power_op(struct rtl8169_private *tp,
3488                              void (*op)(struct rtl8169_private *))
3489 {
3490         if (op)
3491                 op(tp);
3492 }
3493
3494 static void rtl_pll_power_down(struct rtl8169_private *tp)
3495 {
3496         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3497 }
3498
3499 static void rtl_pll_power_up(struct rtl8169_private *tp)
3500 {
3501         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3502 }
3503
3504 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3505 {
3506         struct pll_power_ops *ops = &tp->pll_power_ops;
3507
3508         switch (tp->mac_version) {
3509         case RTL_GIGA_MAC_VER_07:
3510         case RTL_GIGA_MAC_VER_08:
3511         case RTL_GIGA_MAC_VER_09:
3512         case RTL_GIGA_MAC_VER_10:
3513         case RTL_GIGA_MAC_VER_16:
3514         case RTL_GIGA_MAC_VER_29:
3515         case RTL_GIGA_MAC_VER_30:
3516                 ops->down       = r810x_pll_power_down;
3517                 ops->up         = r810x_pll_power_up;
3518                 break;
3519
3520         case RTL_GIGA_MAC_VER_11:
3521         case RTL_GIGA_MAC_VER_12:
3522         case RTL_GIGA_MAC_VER_17:
3523         case RTL_GIGA_MAC_VER_18:
3524         case RTL_GIGA_MAC_VER_19:
3525         case RTL_GIGA_MAC_VER_20:
3526         case RTL_GIGA_MAC_VER_21:
3527         case RTL_GIGA_MAC_VER_22:
3528         case RTL_GIGA_MAC_VER_23:
3529         case RTL_GIGA_MAC_VER_24:
3530         case RTL_GIGA_MAC_VER_25:
3531         case RTL_GIGA_MAC_VER_26:
3532         case RTL_GIGA_MAC_VER_27:
3533         case RTL_GIGA_MAC_VER_28:
3534         case RTL_GIGA_MAC_VER_31:
3535         case RTL_GIGA_MAC_VER_32:
3536         case RTL_GIGA_MAC_VER_33:
3537         case RTL_GIGA_MAC_VER_34:
3538                 ops->down       = r8168_pll_power_down;
3539                 ops->up         = r8168_pll_power_up;
3540                 break;
3541
3542         default:
3543                 ops->down       = NULL;
3544                 ops->up         = NULL;
3545                 break;
3546         }
3547 }
3548
3549 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3550 {
3551         void __iomem *ioaddr = tp->mmio_addr;
3552
3553         switch (tp->mac_version) {
3554         case RTL_GIGA_MAC_VER_01:
3555         case RTL_GIGA_MAC_VER_02:
3556         case RTL_GIGA_MAC_VER_03:
3557         case RTL_GIGA_MAC_VER_04:
3558         case RTL_GIGA_MAC_VER_05:
3559         case RTL_GIGA_MAC_VER_06:
3560         case RTL_GIGA_MAC_VER_10:
3561         case RTL_GIGA_MAC_VER_11:
3562         case RTL_GIGA_MAC_VER_12:
3563         case RTL_GIGA_MAC_VER_13:
3564         case RTL_GIGA_MAC_VER_14:
3565         case RTL_GIGA_MAC_VER_15:
3566         case RTL_GIGA_MAC_VER_16:
3567         case RTL_GIGA_MAC_VER_17:
3568                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3569                 break;
3570         case RTL_GIGA_MAC_VER_18:
3571         case RTL_GIGA_MAC_VER_19:
3572         case RTL_GIGA_MAC_VER_20:
3573         case RTL_GIGA_MAC_VER_21:
3574         case RTL_GIGA_MAC_VER_22:
3575         case RTL_GIGA_MAC_VER_23:
3576         case RTL_GIGA_MAC_VER_24:
3577                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3578                 break;
3579         default:
3580                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3581                 break;
3582         }
3583 }
3584
3585 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3586 {
3587         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3588 }
3589
3590 static void rtl_hw_reset(struct rtl8169_private *tp)
3591 {
3592         void __iomem *ioaddr = tp->mmio_addr;
3593         int i;
3594
3595         /* Soft reset the chip. */
3596         RTL_W8(ChipCmd, CmdReset);
3597
3598         /* Check that the chip has finished the reset. */
3599         for (i = 0; i < 100; i++) {
3600                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3601                         break;
3602                 udelay(100);
3603         }
3604
3605         rtl8169_init_ring_indexes(tp);
3606 }
3607
3608 static int __devinit
3609 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3610 {
3611         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3612         const unsigned int region = cfg->region;
3613         struct rtl8169_private *tp;
3614         struct mii_if_info *mii;
3615         struct net_device *dev;
3616         void __iomem *ioaddr;
3617         int chipset, i;
3618         int rc;
3619
3620         if (netif_msg_drv(&debug)) {
3621                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3622                        MODULENAME, RTL8169_VERSION);
3623         }
3624
3625         dev = alloc_etherdev(sizeof (*tp));
3626         if (!dev) {
3627                 if (netif_msg_drv(&debug))
3628                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3629                 rc = -ENOMEM;
3630                 goto out;
3631         }
3632
3633         SET_NETDEV_DEV(dev, &pdev->dev);
3634         dev->netdev_ops = &rtl8169_netdev_ops;
3635         tp = netdev_priv(dev);
3636         tp->dev = dev;
3637         tp->pci_dev = pdev;
3638         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3639
3640         mii = &tp->mii;
3641         mii->dev = dev;
3642         mii->mdio_read = rtl_mdio_read;
3643         mii->mdio_write = rtl_mdio_write;
3644         mii->phy_id_mask = 0x1f;
3645         mii->reg_num_mask = 0x1f;
3646         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3647
3648         /* disable ASPM completely as that cause random device stop working
3649          * problems as well as full system hangs for some PCIe devices users */
3650         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3651                                      PCIE_LINK_STATE_CLKPM);
3652
3653         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3654         rc = pci_enable_device(pdev);
3655         if (rc < 0) {
3656                 netif_err(tp, probe, dev, "enable failure\n");
3657                 goto err_out_free_dev_1;
3658         }
3659
3660         if (pci_set_mwi(pdev) < 0)
3661                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3662
3663         /* make sure PCI base addr 1 is MMIO */
3664         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3665                 netif_err(tp, probe, dev,
3666                           "region #%d not an MMIO resource, aborting\n",
3667                           region);
3668                 rc = -ENODEV;
3669                 goto err_out_mwi_2;
3670         }
3671
3672         /* check for weird/broken PCI region reporting */
3673         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3674                 netif_err(tp, probe, dev,
3675                           "Invalid PCI region size(s), aborting\n");
3676                 rc = -ENODEV;
3677                 goto err_out_mwi_2;
3678         }
3679
3680         rc = pci_request_regions(pdev, MODULENAME);
3681         if (rc < 0) {
3682                 netif_err(tp, probe, dev, "could not request regions\n");
3683                 goto err_out_mwi_2;
3684         }
3685
3686         tp->cp_cmd = RxChkSum;
3687
3688         if ((sizeof(dma_addr_t) > 4) &&
3689             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3690                 tp->cp_cmd |= PCIDAC;
3691                 dev->features |= NETIF_F_HIGHDMA;
3692         } else {
3693                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3694                 if (rc < 0) {
3695                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3696                         goto err_out_free_res_3;
3697                 }
3698         }
3699
3700         /* ioremap MMIO region */
3701         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3702         if (!ioaddr) {
3703                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3704                 rc = -EIO;
3705                 goto err_out_free_res_3;
3706         }
3707         tp->mmio_addr = ioaddr;
3708
3709         if (!pci_is_pcie(pdev))
3710                 netif_info(tp, probe, dev, "not PCI Express\n");
3711
3712         /* Identify chip attached to board */
3713         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3714
3715         rtl_init_rxcfg(tp);
3716
3717         RTL_W16(IntrMask, 0x0000);
3718
3719         rtl_hw_reset(tp);
3720
3721         RTL_W16(IntrStatus, 0xffff);
3722
3723         pci_set_master(pdev);
3724
3725         /*
3726          * Pretend we are using VLANs; This bypasses a nasty bug where
3727          * Interrupts stop flowing on high load on 8110SCd controllers.
3728          */
3729         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3730                 tp->cp_cmd |= RxVlan;
3731
3732         rtl_init_mdio_ops(tp);
3733         rtl_init_pll_power_ops(tp);
3734
3735         rtl8169_print_mac_version(tp);
3736
3737         chipset = tp->mac_version;
3738         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3739
3740         RTL_W8(Cfg9346, Cfg9346_Unlock);
3741         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3742         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3743         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3744                 tp->features |= RTL_FEATURE_WOL;
3745         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3746                 tp->features |= RTL_FEATURE_WOL;
3747         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3748         RTL_W8(Cfg9346, Cfg9346_Lock);
3749
3750         if (rtl_tbi_enabled(tp)) {
3751                 tp->set_speed = rtl8169_set_speed_tbi;
3752                 tp->get_settings = rtl8169_gset_tbi;
3753                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3754                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3755                 tp->link_ok = rtl8169_tbi_link_ok;
3756                 tp->do_ioctl = rtl_tbi_ioctl;
3757         } else {
3758                 tp->set_speed = rtl8169_set_speed_xmii;
3759                 tp->get_settings = rtl8169_gset_xmii;
3760                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3761                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3762                 tp->link_ok = rtl8169_xmii_link_ok;
3763                 tp->do_ioctl = rtl_xmii_ioctl;
3764         }
3765
3766         spin_lock_init(&tp->lock);
3767
3768         /* Get MAC address */
3769         for (i = 0; i < MAC_ADDR_LEN; i++)
3770                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3771         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3772
3773         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3774         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3775         dev->irq = pdev->irq;
3776         dev->base_addr = (unsigned long) ioaddr;
3777
3778         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3779
3780         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3781          * properly for all devices */
3782         dev->features |= NETIF_F_RXCSUM |
3783                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3784
3785         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3786                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3787         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3788                 NETIF_F_HIGHDMA;
3789
3790         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3791                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3792                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3793
3794         tp->intr_mask = 0xffff;
3795         tp->hw_start = cfg->hw_start;
3796         tp->intr_event = cfg->intr_event;
3797         tp->napi_event = cfg->napi_event;
3798
3799         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3800                 ~(RxBOVF | RxFOVF) : ~0;
3801
3802         init_timer(&tp->timer);
3803         tp->timer.data = (unsigned long) dev;
3804         tp->timer.function = rtl8169_phy_timer;
3805
3806         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3807
3808         rc = register_netdev(dev);
3809         if (rc < 0)
3810                 goto err_out_msi_4;
3811
3812         pci_set_drvdata(pdev, dev);
3813
3814         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3815                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3816                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3817
3818         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3819             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3820             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3821                 rtl8168_driver_start(tp);
3822         }
3823
3824         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3825
3826         if (pci_dev_run_wake(pdev))
3827                 pm_runtime_put_noidle(&pdev->dev);
3828
3829         netif_carrier_off(dev);
3830
3831 out:
3832         return rc;
3833
3834 err_out_msi_4:
3835         rtl_disable_msi(pdev, tp);
3836         iounmap(ioaddr);
3837 err_out_free_res_3:
3838         pci_release_regions(pdev);
3839 err_out_mwi_2:
3840         pci_clear_mwi(pdev);
3841         pci_disable_device(pdev);
3842 err_out_free_dev_1:
3843         free_netdev(dev);
3844         goto out;
3845 }
3846
3847 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3848 {
3849         struct net_device *dev = pci_get_drvdata(pdev);
3850         struct rtl8169_private *tp = netdev_priv(dev);
3851
3852         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3853             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3854             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3855                 rtl8168_driver_stop(tp);
3856         }
3857
3858         cancel_delayed_work_sync(&tp->task);
3859
3860         unregister_netdev(dev);
3861
3862         rtl_release_firmware(tp);
3863
3864         if (pci_dev_run_wake(pdev))
3865                 pm_runtime_get_noresume(&pdev->dev);
3866
3867         /* restore original MAC address */
3868         rtl_rar_set(tp, dev->perm_addr);
3869
3870         rtl_disable_msi(pdev, tp);
3871         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3872         pci_set_drvdata(pdev, NULL);
3873 }
3874
3875 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3876 {
3877         struct rtl_fw *rtl_fw;
3878         const char *name;
3879         int rc = -ENOMEM;
3880
3881         name = rtl_lookup_firmware_name(tp);
3882         if (!name)
3883                 goto out_no_firmware;
3884
3885         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3886         if (!rtl_fw)
3887                 goto err_warn;
3888
3889         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3890         if (rc < 0)
3891                 goto err_free;
3892
3893         rc = rtl_check_firmware(tp, rtl_fw);
3894         if (rc < 0)
3895                 goto err_release_firmware;
3896
3897         tp->rtl_fw = rtl_fw;
3898 out:
3899         return;
3900
3901 err_release_firmware:
3902         release_firmware(rtl_fw->fw);
3903 err_free:
3904         kfree(rtl_fw);
3905 err_warn:
3906         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3907                    name, rc);
3908 out_no_firmware:
3909         tp->rtl_fw = NULL;
3910         goto out;
3911 }
3912
3913 static void rtl_request_firmware(struct rtl8169_private *tp)
3914 {
3915         if (IS_ERR(tp->rtl_fw))
3916                 rtl_request_uncached_firmware(tp);
3917 }
3918
3919 static int rtl8169_open(struct net_device *dev)
3920 {
3921         struct rtl8169_private *tp = netdev_priv(dev);
3922         void __iomem *ioaddr = tp->mmio_addr;
3923         struct pci_dev *pdev = tp->pci_dev;
3924         int retval = -ENOMEM;
3925
3926         pm_runtime_get_sync(&pdev->dev);
3927
3928         /*
3929          * Rx and Tx desscriptors needs 256 bytes alignment.
3930          * dma_alloc_coherent provides more.
3931          */
3932         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3933                                              &tp->TxPhyAddr, GFP_KERNEL);
3934         if (!tp->TxDescArray)
3935                 goto err_pm_runtime_put;
3936
3937         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3938                                              &tp->RxPhyAddr, GFP_KERNEL);
3939         if (!tp->RxDescArray)
3940                 goto err_free_tx_0;
3941
3942         retval = rtl8169_init_ring(dev);
3943         if (retval < 0)
3944                 goto err_free_rx_1;
3945
3946         INIT_DELAYED_WORK(&tp->task, NULL);
3947
3948         smp_mb();
3949
3950         rtl_request_firmware(tp);
3951
3952         retval = request_irq(dev->irq, rtl8169_interrupt,
3953                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3954                              dev->name, dev);
3955         if (retval < 0)
3956                 goto err_release_fw_2;
3957
3958         napi_enable(&tp->napi);
3959
3960         rtl8169_init_phy(dev, tp);
3961
3962         rtl8169_set_features(dev, dev->features);
3963
3964         rtl_pll_power_up(tp);
3965
3966         rtl_hw_start(dev);
3967
3968         tp->saved_wolopts = 0;
3969         pm_runtime_put_noidle(&pdev->dev);
3970
3971         rtl8169_check_link_status(dev, tp, ioaddr);
3972 out:
3973         return retval;
3974
3975 err_release_fw_2:
3976         rtl_release_firmware(tp);
3977         rtl8169_rx_clear(tp);
3978 err_free_rx_1:
3979         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3980                           tp->RxPhyAddr);
3981         tp->RxDescArray = NULL;
3982 err_free_tx_0:
3983         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3984                           tp->TxPhyAddr);
3985         tp->TxDescArray = NULL;
3986 err_pm_runtime_put:
3987         pm_runtime_put_noidle(&pdev->dev);
3988         goto out;
3989 }
3990
3991 static void rtl_rx_close(struct rtl8169_private *tp)
3992 {
3993         void __iomem *ioaddr = tp->mmio_addr;
3994
3995         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3996 }
3997
3998 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3999 {
4000         void __iomem *ioaddr = tp->mmio_addr;
4001
4002         /* Disable interrupts */
4003         rtl8169_irq_mask_and_ack(ioaddr);
4004
4005         rtl_rx_close(tp);
4006
4007         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4008             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4009             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4010                 while (RTL_R8(TxPoll) & NPQ)
4011                         udelay(20);
4012         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
4013                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4014                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4015                         udelay(100);
4016         } else {
4017                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4018                 udelay(100);
4019         }
4020
4021         rtl_hw_reset(tp);
4022 }
4023
4024 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4025 {
4026         void __iomem *ioaddr = tp->mmio_addr;
4027
4028         /* Set DMA burst size and Interframe Gap Time */
4029         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4030                 (InterFrameGap << TxInterFrameGapShift));
4031 }
4032
4033 static void rtl_hw_start(struct net_device *dev)
4034 {
4035         struct rtl8169_private *tp = netdev_priv(dev);
4036
4037         tp->hw_start(dev);
4038
4039         netif_start_queue(dev);
4040 }
4041
4042 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4043                                          void __iomem *ioaddr)
4044 {
4045         /*
4046          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4047          * register to be written before TxDescAddrLow to work.
4048          * Switching from MMIO to I/O access fixes the issue as well.
4049          */
4050         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4051         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4052         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4053         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4054 }
4055
4056 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4057 {
4058         u16 cmd;
4059
4060         cmd = RTL_R16(CPlusCmd);
4061         RTL_W16(CPlusCmd, cmd);
4062         return cmd;
4063 }
4064
4065 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4066 {
4067         /* Low hurts. Let's disable the filtering. */
4068         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4069 }
4070
4071 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4072 {
4073         static const struct rtl_cfg2_info {
4074                 u32 mac_version;
4075                 u32 clk;
4076                 u32 val;
4077         } cfg2_info [] = {
4078                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4079                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4080                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4081                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4082         };
4083         const struct rtl_cfg2_info *p = cfg2_info;
4084         unsigned int i;
4085         u32 clk;
4086
4087         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4088         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4089                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4090                         RTL_W32(0x7c, p->val);
4091                         break;
4092                 }
4093         }
4094 }
4095
4096 static void rtl_hw_start_8169(struct net_device *dev)
4097 {
4098         struct rtl8169_private *tp = netdev_priv(dev);
4099         void __iomem *ioaddr = tp->mmio_addr;
4100         struct pci_dev *pdev = tp->pci_dev;
4101
4102         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4103                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4104                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4105         }
4106
4107         RTL_W8(Cfg9346, Cfg9346_Unlock);
4108         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4109             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4110             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4111             tp->mac_version == RTL_GIGA_MAC_VER_04)
4112                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4113
4114         rtl_init_rxcfg(tp);
4115
4116         RTL_W8(EarlyTxThres, NoEarlyTx);
4117
4118         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4119
4120         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4121             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4122             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4123             tp->mac_version == RTL_GIGA_MAC_VER_04)
4124                 rtl_set_rx_tx_config_registers(tp);
4125
4126         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4127
4128         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4129             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4130                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4131                         "Bit-3 and bit-14 MUST be 1\n");
4132                 tp->cp_cmd |= (1 << 14);
4133         }
4134
4135         RTL_W16(CPlusCmd, tp->cp_cmd);
4136
4137         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4138
4139         /*
4140          * Undocumented corner. Supposedly:
4141          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4142          */
4143         RTL_W16(IntrMitigate, 0x0000);
4144
4145         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4146
4147         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4148             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4149             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4150             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4151                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4152                 rtl_set_rx_tx_config_registers(tp);
4153         }
4154
4155         RTL_W8(Cfg9346, Cfg9346_Lock);
4156
4157         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4158         RTL_R8(IntrMask);
4159
4160         RTL_W32(RxMissed, 0);
4161
4162         rtl_set_rx_mode(dev);
4163
4164         /* no early-rx interrupts */
4165         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4166
4167         /* Enable all known interrupts by setting the interrupt mask. */
4168         RTL_W16(IntrMask, tp->intr_event);
4169 }
4170
4171 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4172 {
4173         int cap = pci_pcie_cap(pdev);
4174
4175         if (cap) {
4176                 u16 ctl;
4177
4178                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4179                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4180                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4181         }
4182 }
4183
4184 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4185 {
4186         u32 csi;
4187
4188         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4189         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4190 }
4191
4192 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4193 {
4194         rtl_csi_access_enable(ioaddr, 0x17000000);
4195 }
4196
4197 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4198 {
4199         rtl_csi_access_enable(ioaddr, 0x27000000);
4200 }
4201
4202 struct ephy_info {
4203         unsigned int offset;
4204         u16 mask;
4205         u16 bits;
4206 };
4207
4208 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4209 {
4210         u16 w;
4211
4212         while (len-- > 0) {
4213                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4214                 rtl_ephy_write(ioaddr, e->offset, w);
4215                 e++;
4216         }
4217 }
4218
4219 static void rtl_disable_clock_request(struct pci_dev *pdev)
4220 {
4221         int cap = pci_pcie_cap(pdev);
4222
4223         if (cap) {
4224                 u16 ctl;
4225
4226                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4227                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4228                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4229         }
4230 }
4231
4232 static void rtl_enable_clock_request(struct pci_dev *pdev)
4233 {
4234         int cap = pci_pcie_cap(pdev);
4235
4236         if (cap) {
4237                 u16 ctl;
4238
4239                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4240                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4241                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4242         }
4243 }
4244
4245 #define R8168_CPCMD_QUIRK_MASK (\
4246         EnableBist | \
4247         Mac_dbgo_oe | \
4248         Force_half_dup | \
4249         Force_rxflow_en | \
4250         Force_txflow_en | \
4251         Cxpl_dbg_sel | \
4252         ASF | \
4253         PktCntrDisable | \
4254         Mac_dbgo_sel)
4255
4256 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4257 {
4258         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4259
4260         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4261
4262         rtl_tx_performance_tweak(pdev,
4263                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4264 }
4265
4266 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4267 {
4268         rtl_hw_start_8168bb(ioaddr, pdev);
4269
4270         RTL_W8(MaxTxPacketSize, TxPacketMax);
4271
4272         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4273 }
4274
4275 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4276 {
4277         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4278
4279         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4280
4281         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4282
4283         rtl_disable_clock_request(pdev);
4284
4285         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4286 }
4287
4288 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4289 {
4290         static const struct ephy_info e_info_8168cp[] = {
4291                 { 0x01, 0,      0x0001 },
4292                 { 0x02, 0x0800, 0x1000 },
4293                 { 0x03, 0,      0x0042 },
4294                 { 0x06, 0x0080, 0x0000 },
4295                 { 0x07, 0,      0x2000 }
4296         };
4297
4298         rtl_csi_access_enable_2(ioaddr);
4299
4300         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4301
4302         __rtl_hw_start_8168cp(ioaddr, pdev);
4303 }
4304
4305 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4306 {
4307         rtl_csi_access_enable_2(ioaddr);
4308
4309         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4310
4311         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4312
4313         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4314 }
4315
4316 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4317 {
4318         rtl_csi_access_enable_2(ioaddr);
4319
4320         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4321
4322         /* Magic. */
4323         RTL_W8(DBG_REG, 0x20);
4324
4325         RTL_W8(MaxTxPacketSize, TxPacketMax);
4326
4327         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4328
4329         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4330 }
4331
4332 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4333 {
4334         static const struct ephy_info e_info_8168c_1[] = {
4335                 { 0x02, 0x0800, 0x1000 },
4336                 { 0x03, 0,      0x0002 },
4337                 { 0x06, 0x0080, 0x0000 }
4338         };
4339
4340         rtl_csi_access_enable_2(ioaddr);
4341
4342         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4343
4344         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4345
4346         __rtl_hw_start_8168cp(ioaddr, pdev);
4347 }
4348
4349 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4350 {
4351         static const struct ephy_info e_info_8168c_2[] = {
4352                 { 0x01, 0,      0x0001 },
4353                 { 0x03, 0x0400, 0x0220 }
4354         };
4355
4356         rtl_csi_access_enable_2(ioaddr);
4357
4358         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4359
4360         __rtl_hw_start_8168cp(ioaddr, pdev);
4361 }
4362
4363 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4364 {
4365         rtl_hw_start_8168c_2(ioaddr, pdev);
4366 }
4367
4368 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4369 {
4370         rtl_csi_access_enable_2(ioaddr);
4371
4372         __rtl_hw_start_8168cp(ioaddr, pdev);
4373 }
4374
4375 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4376 {
4377         rtl_csi_access_enable_2(ioaddr);
4378
4379         rtl_disable_clock_request(pdev);
4380
4381         RTL_W8(MaxTxPacketSize, TxPacketMax);
4382
4383         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4384
4385         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4386 }
4387
4388 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4389 {
4390         rtl_csi_access_enable_1(ioaddr);
4391
4392         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4393
4394         RTL_W8(MaxTxPacketSize, TxPacketMax);
4395
4396         rtl_disable_clock_request(pdev);
4397 }
4398
4399 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4400 {
4401         static const struct ephy_info e_info_8168d_4[] = {
4402                 { 0x0b, ~0,     0x48 },
4403                 { 0x19, 0x20,   0x50 },
4404                 { 0x0c, ~0,     0x20 }
4405         };
4406         int i;
4407
4408         rtl_csi_access_enable_1(ioaddr);
4409
4410         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4411
4412         RTL_W8(MaxTxPacketSize, TxPacketMax);
4413
4414         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4415                 const struct ephy_info *e = e_info_8168d_4 + i;
4416                 u16 w;
4417
4418                 w = rtl_ephy_read(ioaddr, e->offset);
4419                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4420         }
4421
4422         rtl_enable_clock_request(pdev);
4423 }
4424
4425 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4426 {
4427         static const struct ephy_info e_info_8168e_1[] = {
4428                 { 0x00, 0x0200, 0x0100 },
4429                 { 0x00, 0x0000, 0x0004 },
4430                 { 0x06, 0x0002, 0x0001 },
4431                 { 0x06, 0x0000, 0x0030 },
4432                 { 0x07, 0x0000, 0x2000 },
4433                 { 0x00, 0x0000, 0x0020 },
4434                 { 0x03, 0x5800, 0x2000 },
4435                 { 0x03, 0x0000, 0x0001 },
4436                 { 0x01, 0x0800, 0x1000 },
4437                 { 0x07, 0x0000, 0x4000 },
4438                 { 0x1e, 0x0000, 0x2000 },
4439                 { 0x19, 0xffff, 0xfe6c },
4440                 { 0x0a, 0x0000, 0x0040 }
4441         };
4442
4443         rtl_csi_access_enable_2(ioaddr);
4444
4445         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4446
4447         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4448
4449         RTL_W8(MaxTxPacketSize, TxPacketMax);
4450
4451         rtl_disable_clock_request(pdev);
4452
4453         /* Reset tx FIFO pointer */
4454         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4455         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4456
4457         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4458 }
4459
4460 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4461 {
4462         static const struct ephy_info e_info_8168e_2[] = {
4463                 { 0x09, 0x0000, 0x0080 },
4464                 { 0x19, 0x0000, 0x0224 }
4465         };
4466
4467         rtl_csi_access_enable_1(ioaddr);
4468
4469         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4470
4471         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4472
4473         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4474         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4475         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4476         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4477         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4478         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4479         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4480         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4481                      ERIAR_EXGMAC);
4482
4483         RTL_W8(MaxTxPacketSize, EarlySize);
4484
4485         rtl_disable_clock_request(pdev);
4486
4487         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4488         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4489
4490         /* Adjust EEE LED frequency */
4491         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4492
4493         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4494         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4495         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4496 }
4497
4498 static void rtl_hw_start_8168(struct net_device *dev)
4499 {
4500         struct rtl8169_private *tp = netdev_priv(dev);
4501         void __iomem *ioaddr = tp->mmio_addr;
4502         struct pci_dev *pdev = tp->pci_dev;
4503
4504         RTL_W8(Cfg9346, Cfg9346_Unlock);
4505
4506         RTL_W8(MaxTxPacketSize, TxPacketMax);
4507
4508         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4509
4510         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4511
4512         RTL_W16(CPlusCmd, tp->cp_cmd);
4513
4514         RTL_W16(IntrMitigate, 0x5151);
4515
4516         /* Work around for RxFIFO overflow. */
4517         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4518             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4519                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4520                 tp->intr_event &= ~RxOverflow;
4521         }
4522
4523         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4524
4525         rtl_set_rx_mode(dev);
4526
4527         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4528                 (InterFrameGap << TxInterFrameGapShift));
4529
4530         RTL_R8(IntrMask);
4531
4532         switch (tp->mac_version) {
4533         case RTL_GIGA_MAC_VER_11:
4534                 rtl_hw_start_8168bb(ioaddr, pdev);
4535                 break;
4536
4537         case RTL_GIGA_MAC_VER_12:
4538         case RTL_GIGA_MAC_VER_17:
4539                 rtl_hw_start_8168bef(ioaddr, pdev);
4540                 break;
4541
4542         case RTL_GIGA_MAC_VER_18:
4543                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4544                 break;
4545
4546         case RTL_GIGA_MAC_VER_19:
4547                 rtl_hw_start_8168c_1(ioaddr, pdev);
4548                 break;
4549
4550         case RTL_GIGA_MAC_VER_20:
4551                 rtl_hw_start_8168c_2(ioaddr, pdev);
4552                 break;
4553
4554         case RTL_GIGA_MAC_VER_21:
4555                 rtl_hw_start_8168c_3(ioaddr, pdev);
4556                 break;
4557
4558         case RTL_GIGA_MAC_VER_22:
4559                 rtl_hw_start_8168c_4(ioaddr, pdev);
4560                 break;
4561
4562         case RTL_GIGA_MAC_VER_23:
4563                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4564                 break;
4565
4566         case RTL_GIGA_MAC_VER_24:
4567                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4568                 break;
4569
4570         case RTL_GIGA_MAC_VER_25:
4571         case RTL_GIGA_MAC_VER_26:
4572         case RTL_GIGA_MAC_VER_27:
4573                 rtl_hw_start_8168d(ioaddr, pdev);
4574                 break;
4575
4576         case RTL_GIGA_MAC_VER_28:
4577                 rtl_hw_start_8168d_4(ioaddr, pdev);
4578                 break;
4579
4580         case RTL_GIGA_MAC_VER_31:
4581                 rtl_hw_start_8168dp(ioaddr, pdev);
4582                 break;
4583
4584         case RTL_GIGA_MAC_VER_32:
4585         case RTL_GIGA_MAC_VER_33:
4586                 rtl_hw_start_8168e_1(ioaddr, pdev);
4587                 break;
4588         case RTL_GIGA_MAC_VER_34:
4589                 rtl_hw_start_8168e_2(ioaddr, pdev);
4590                 break;
4591
4592         default:
4593                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4594                         dev->name, tp->mac_version);
4595                 break;
4596         }
4597
4598         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4599
4600         RTL_W8(Cfg9346, Cfg9346_Lock);
4601
4602         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4603
4604         RTL_W16(IntrMask, tp->intr_event);
4605 }
4606
4607 #define R810X_CPCMD_QUIRK_MASK (\
4608         EnableBist | \
4609         Mac_dbgo_oe | \
4610         Force_half_dup | \
4611         Force_rxflow_en | \
4612         Force_txflow_en | \
4613         Cxpl_dbg_sel | \
4614         ASF | \
4615         PktCntrDisable | \
4616         Mac_dbgo_sel)
4617
4618 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4619 {
4620         static const struct ephy_info e_info_8102e_1[] = {
4621                 { 0x01, 0, 0x6e65 },
4622                 { 0x02, 0, 0x091f },
4623                 { 0x03, 0, 0xc2f9 },
4624                 { 0x06, 0, 0xafb5 },
4625                 { 0x07, 0, 0x0e00 },
4626                 { 0x19, 0, 0xec80 },
4627                 { 0x01, 0, 0x2e65 },
4628                 { 0x01, 0, 0x6e65 }
4629         };
4630         u8 cfg1;
4631
4632         rtl_csi_access_enable_2(ioaddr);
4633
4634         RTL_W8(DBG_REG, FIX_NAK_1);
4635
4636         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4637
4638         RTL_W8(Config1,
4639                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4640         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4641
4642         cfg1 = RTL_R8(Config1);
4643         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4644                 RTL_W8(Config1, cfg1 & ~LEDS0);
4645
4646         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4647 }
4648
4649 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4650 {
4651         rtl_csi_access_enable_2(ioaddr);
4652
4653         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4654
4655         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4656         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4657 }
4658
4659 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4660 {
4661         rtl_hw_start_8102e_2(ioaddr, pdev);
4662
4663         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4664 }
4665
4666 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4667 {
4668         static const struct ephy_info e_info_8105e_1[] = {
4669                 { 0x07, 0, 0x4000 },
4670                 { 0x19, 0, 0x0200 },
4671                 { 0x19, 0, 0x0020 },
4672                 { 0x1e, 0, 0x2000 },
4673                 { 0x03, 0, 0x0001 },
4674                 { 0x19, 0, 0x0100 },
4675                 { 0x19, 0, 0x0004 },
4676                 { 0x0a, 0, 0x0020 }
4677         };
4678
4679         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4680         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4681
4682         /* Disable Early Tally Counter */
4683         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4684
4685         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4686         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4687
4688         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4689 }
4690
4691 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4692 {
4693         rtl_hw_start_8105e_1(ioaddr, pdev);
4694         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4695 }
4696
4697 static void rtl_hw_start_8101(struct net_device *dev)
4698 {
4699         struct rtl8169_private *tp = netdev_priv(dev);
4700         void __iomem *ioaddr = tp->mmio_addr;
4701         struct pci_dev *pdev = tp->pci_dev;
4702
4703         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4704             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4705                 int cap = pci_pcie_cap(pdev);
4706
4707                 if (cap) {
4708                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4709                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4710                 }
4711         }
4712
4713         RTL_W8(Cfg9346, Cfg9346_Unlock);
4714
4715         switch (tp->mac_version) {
4716         case RTL_GIGA_MAC_VER_07:
4717                 rtl_hw_start_8102e_1(ioaddr, pdev);
4718                 break;
4719
4720         case RTL_GIGA_MAC_VER_08:
4721                 rtl_hw_start_8102e_3(ioaddr, pdev);
4722                 break;
4723
4724         case RTL_GIGA_MAC_VER_09:
4725                 rtl_hw_start_8102e_2(ioaddr, pdev);
4726                 break;
4727
4728         case RTL_GIGA_MAC_VER_29:
4729                 rtl_hw_start_8105e_1(ioaddr, pdev);
4730                 break;
4731         case RTL_GIGA_MAC_VER_30:
4732                 rtl_hw_start_8105e_2(ioaddr, pdev);
4733                 break;
4734         }
4735
4736         RTL_W8(Cfg9346, Cfg9346_Lock);
4737
4738         RTL_W8(MaxTxPacketSize, TxPacketMax);
4739
4740         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4741
4742         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4743         RTL_W16(CPlusCmd, tp->cp_cmd);
4744
4745         RTL_W16(IntrMitigate, 0x0000);
4746
4747         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4748
4749         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4750         rtl_set_rx_tx_config_registers(tp);
4751
4752         RTL_R8(IntrMask);
4753
4754         rtl_set_rx_mode(dev);
4755
4756         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4757
4758         RTL_W16(IntrMask, tp->intr_event);
4759 }
4760
4761 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4762 {
4763         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4764                 return -EINVAL;
4765
4766         dev->mtu = new_mtu;
4767         netdev_update_features(dev);
4768
4769         return 0;
4770 }
4771
4772 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4773 {
4774         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4775         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4776 }
4777
4778 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4779                                      void **data_buff, struct RxDesc *desc)
4780 {
4781         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4782                          DMA_FROM_DEVICE);
4783
4784         kfree(*data_buff);
4785         *data_buff = NULL;
4786         rtl8169_make_unusable_by_asic(desc);
4787 }
4788
4789 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4790 {
4791         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4792
4793         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4794 }
4795
4796 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4797                                        u32 rx_buf_sz)
4798 {
4799         desc->addr = cpu_to_le64(mapping);
4800         wmb();
4801         rtl8169_mark_to_asic(desc, rx_buf_sz);
4802 }
4803
4804 static inline void *rtl8169_align(void *data)
4805 {
4806         return (void *)ALIGN((long)data, 16);
4807 }
4808
4809 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4810                                              struct RxDesc *desc)
4811 {
4812         void *data;
4813         dma_addr_t mapping;
4814         struct device *d = &tp->pci_dev->dev;
4815         struct net_device *dev = tp->dev;
4816         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4817
4818         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4819         if (!data)
4820                 return NULL;
4821
4822         if (rtl8169_align(data) != data) {
4823                 kfree(data);
4824                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4825                 if (!data)
4826                         return NULL;
4827         }
4828
4829         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4830                                  DMA_FROM_DEVICE);
4831         if (unlikely(dma_mapping_error(d, mapping))) {
4832                 if (net_ratelimit())
4833                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4834                 goto err_out;
4835         }
4836
4837         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4838         return data;
4839
4840 err_out:
4841         kfree(data);
4842         return NULL;
4843 }
4844
4845 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4846 {
4847         unsigned int i;
4848
4849         for (i = 0; i < NUM_RX_DESC; i++) {
4850                 if (tp->Rx_databuff[i]) {
4851                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4852                                             tp->RxDescArray + i);
4853                 }
4854         }
4855 }
4856
4857 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4858 {
4859         desc->opts1 |= cpu_to_le32(RingEnd);
4860 }
4861
4862 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4863 {
4864         unsigned int i;
4865
4866         for (i = 0; i < NUM_RX_DESC; i++) {
4867                 void *data;
4868
4869                 if (tp->Rx_databuff[i])
4870                         continue;
4871
4872                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4873                 if (!data) {
4874                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4875                         goto err_out;
4876                 }
4877                 tp->Rx_databuff[i] = data;
4878         }
4879
4880         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4881         return 0;
4882
4883 err_out:
4884         rtl8169_rx_clear(tp);
4885         return -ENOMEM;
4886 }
4887
4888 static int rtl8169_init_ring(struct net_device *dev)
4889 {
4890         struct rtl8169_private *tp = netdev_priv(dev);
4891
4892         rtl8169_init_ring_indexes(tp);
4893
4894         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4895         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4896
4897         return rtl8169_rx_fill(tp);
4898 }
4899
4900 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4901                                  struct TxDesc *desc)
4902 {
4903         unsigned int len = tx_skb->len;
4904
4905         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4906
4907         desc->opts1 = 0x00;
4908         desc->opts2 = 0x00;
4909         desc->addr = 0x00;
4910         tx_skb->len = 0;
4911 }
4912
4913 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4914                                    unsigned int n)
4915 {
4916         unsigned int i;
4917
4918         for (i = 0; i < n; i++) {
4919                 unsigned int entry = (start + i) % NUM_TX_DESC;
4920                 struct ring_info *tx_skb = tp->tx_skb + entry;
4921                 unsigned int len = tx_skb->len;
4922
4923                 if (len) {
4924                         struct sk_buff *skb = tx_skb->skb;
4925
4926                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4927                                              tp->TxDescArray + entry);
4928                         if (skb) {
4929                                 tp->dev->stats.tx_dropped++;
4930                                 dev_kfree_skb(skb);
4931                                 tx_skb->skb = NULL;
4932                         }
4933                 }
4934         }
4935 }
4936
4937 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4938 {
4939         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4940         tp->cur_tx = tp->dirty_tx = 0;
4941 }
4942
4943 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4944 {
4945         struct rtl8169_private *tp = netdev_priv(dev);
4946
4947         PREPARE_DELAYED_WORK(&tp->task, task);
4948         schedule_delayed_work(&tp->task, 4);
4949 }
4950
4951 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4952 {
4953         struct rtl8169_private *tp = netdev_priv(dev);
4954         void __iomem *ioaddr = tp->mmio_addr;
4955
4956         synchronize_irq(dev->irq);
4957
4958         /* Wait for any pending NAPI task to complete */
4959         napi_disable(&tp->napi);
4960
4961         rtl8169_irq_mask_and_ack(ioaddr);
4962
4963         tp->intr_mask = 0xffff;
4964         RTL_W16(IntrMask, tp->intr_event);
4965         napi_enable(&tp->napi);
4966 }
4967
4968 static void rtl8169_reinit_task(struct work_struct *work)
4969 {
4970         struct rtl8169_private *tp =
4971                 container_of(work, struct rtl8169_private, task.work);
4972         struct net_device *dev = tp->dev;
4973         int ret;
4974
4975         rtnl_lock();
4976
4977         if (!netif_running(dev))
4978                 goto out_unlock;
4979
4980         rtl8169_wait_for_quiescence(dev);
4981         rtl8169_close(dev);
4982
4983         ret = rtl8169_open(dev);
4984         if (unlikely(ret < 0)) {
4985                 if (net_ratelimit())
4986                         netif_err(tp, drv, dev,
4987                                   "reinit failure (status = %d). Rescheduling\n",
4988                                   ret);
4989                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4990         }
4991
4992 out_unlock:
4993         rtnl_unlock();
4994 }
4995
4996 static void rtl8169_reset_task(struct work_struct *work)
4997 {
4998         struct rtl8169_private *tp =
4999                 container_of(work, struct rtl8169_private, task.work);
5000         struct net_device *dev = tp->dev;
5001         int i;
5002
5003         rtnl_lock();
5004
5005         if (!netif_running(dev))
5006                 goto out_unlock;
5007
5008         rtl8169_wait_for_quiescence(dev);
5009
5010         for (i = 0; i < NUM_RX_DESC; i++)
5011                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5012
5013         rtl8169_tx_clear(tp);
5014
5015         rtl8169_hw_reset(tp);
5016         rtl_hw_start(dev);
5017         netif_wake_queue(dev);
5018         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5019
5020 out_unlock:
5021         rtnl_unlock();
5022 }
5023
5024 static void rtl8169_tx_timeout(struct net_device *dev)
5025 {
5026         struct rtl8169_private *tp = netdev_priv(dev);
5027
5028         rtl8169_hw_reset(tp);
5029
5030         /* Let's wait a bit while any (async) irq lands on */
5031         rtl8169_schedule_work(dev, rtl8169_reset_task);
5032 }
5033
5034 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5035                               u32 *opts)
5036 {
5037         struct skb_shared_info *info = skb_shinfo(skb);
5038         unsigned int cur_frag, entry;
5039         struct TxDesc * uninitialized_var(txd);
5040         struct device *d = &tp->pci_dev->dev;
5041
5042         entry = tp->cur_tx;
5043         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5044                 skb_frag_t *frag = info->frags + cur_frag;
5045                 dma_addr_t mapping;
5046                 u32 status, len;
5047                 void *addr;
5048
5049                 entry = (entry + 1) % NUM_TX_DESC;
5050
5051                 txd = tp->TxDescArray + entry;
5052                 len = frag->size;
5053                 addr = skb_frag_address(frag);
5054                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5055                 if (unlikely(dma_mapping_error(d, mapping))) {
5056                         if (net_ratelimit())
5057                                 netif_err(tp, drv, tp->dev,
5058                                           "Failed to map TX fragments DMA!\n");
5059                         goto err_out;
5060                 }
5061
5062                 /* Anti gcc 2.95.3 bugware (sic) */
5063                 status = opts[0] | len |
5064                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5065
5066                 txd->opts1 = cpu_to_le32(status);
5067                 txd->opts2 = cpu_to_le32(opts[1]);
5068                 txd->addr = cpu_to_le64(mapping);
5069
5070                 tp->tx_skb[entry].len = len;
5071         }
5072
5073         if (cur_frag) {
5074                 tp->tx_skb[entry].skb = skb;
5075                 txd->opts1 |= cpu_to_le32(LastFrag);
5076         }
5077
5078         return cur_frag;
5079
5080 err_out:
5081         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5082         return -EIO;
5083 }
5084
5085 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5086                                     struct sk_buff *skb, u32 *opts)
5087 {
5088         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5089         u32 mss = skb_shinfo(skb)->gso_size;
5090         int offset = info->opts_offset;
5091
5092         if (mss) {
5093                 opts[0] |= TD_LSO;
5094                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5095         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5096                 const struct iphdr *ip = ip_hdr(skb);
5097
5098                 if (ip->protocol == IPPROTO_TCP)
5099                         opts[offset] |= info->checksum.tcp;
5100                 else if (ip->protocol == IPPROTO_UDP)
5101                         opts[offset] |= info->checksum.udp;
5102                 else
5103                         WARN_ON_ONCE(1);
5104         }
5105 }
5106
5107 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5108                                       struct net_device *dev)
5109 {
5110         struct rtl8169_private *tp = netdev_priv(dev);
5111         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5112         struct TxDesc *txd = tp->TxDescArray + entry;
5113         void __iomem *ioaddr = tp->mmio_addr;
5114         struct device *d = &tp->pci_dev->dev;
5115         dma_addr_t mapping;
5116         u32 status, len;
5117         u32 opts[2];
5118         int frags;
5119
5120         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5121                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5122                 goto err_stop_0;
5123         }
5124
5125         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5126                 goto err_stop_0;
5127
5128         len = skb_headlen(skb);
5129         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5130         if (unlikely(dma_mapping_error(d, mapping))) {
5131                 if (net_ratelimit())
5132                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5133                 goto err_dma_0;
5134         }
5135
5136         tp->tx_skb[entry].len = len;
5137         txd->addr = cpu_to_le64(mapping);
5138
5139         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5140         opts[0] = DescOwn;
5141
5142         rtl8169_tso_csum(tp, skb, opts);
5143
5144         frags = rtl8169_xmit_frags(tp, skb, opts);
5145         if (frags < 0)
5146                 goto err_dma_1;
5147         else if (frags)
5148                 opts[0] |= FirstFrag;
5149         else {
5150                 opts[0] |= FirstFrag | LastFrag;
5151                 tp->tx_skb[entry].skb = skb;
5152         }
5153
5154         txd->opts2 = cpu_to_le32(opts[1]);
5155
5156         wmb();
5157
5158         /* Anti gcc 2.95.3 bugware (sic) */
5159         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5160         txd->opts1 = cpu_to_le32(status);
5161
5162         tp->cur_tx += frags + 1;
5163
5164         wmb();
5165
5166         RTL_W8(TxPoll, NPQ);
5167
5168         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5169                 netif_stop_queue(dev);
5170                 smp_rmb();
5171                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5172                         netif_wake_queue(dev);
5173         }
5174
5175         return NETDEV_TX_OK;
5176
5177 err_dma_1:
5178         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5179 err_dma_0:
5180         dev_kfree_skb(skb);
5181         dev->stats.tx_dropped++;
5182         return NETDEV_TX_OK;
5183
5184 err_stop_0:
5185         netif_stop_queue(dev);
5186         dev->stats.tx_dropped++;
5187         return NETDEV_TX_BUSY;
5188 }
5189
5190 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5191 {
5192         struct rtl8169_private *tp = netdev_priv(dev);
5193         struct pci_dev *pdev = tp->pci_dev;
5194         u16 pci_status, pci_cmd;
5195
5196         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5197         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5198
5199         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5200                   pci_cmd, pci_status);
5201
5202         /*
5203          * The recovery sequence below admits a very elaborated explanation:
5204          * - it seems to work;
5205          * - I did not see what else could be done;
5206          * - it makes iop3xx happy.
5207          *
5208          * Feel free to adjust to your needs.
5209          */
5210         if (pdev->broken_parity_status)
5211                 pci_cmd &= ~PCI_COMMAND_PARITY;
5212         else
5213                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5214
5215         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5216
5217         pci_write_config_word(pdev, PCI_STATUS,
5218                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5219                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5220                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5221
5222         /* The infamous DAC f*ckup only happens at boot time */
5223         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5224                 void __iomem *ioaddr = tp->mmio_addr;
5225
5226                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5227                 tp->cp_cmd &= ~PCIDAC;
5228                 RTL_W16(CPlusCmd, tp->cp_cmd);
5229                 dev->features &= ~NETIF_F_HIGHDMA;
5230         }
5231
5232         rtl8169_hw_reset(tp);
5233
5234         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5235 }
5236
5237 static void rtl8169_tx_interrupt(struct net_device *dev,
5238                                  struct rtl8169_private *tp,
5239                                  void __iomem *ioaddr)
5240 {
5241         unsigned int dirty_tx, tx_left;
5242
5243         dirty_tx = tp->dirty_tx;
5244         smp_rmb();
5245         tx_left = tp->cur_tx - dirty_tx;
5246
5247         while (tx_left > 0) {
5248                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5249                 struct ring_info *tx_skb = tp->tx_skb + entry;
5250                 u32 status;
5251
5252                 rmb();
5253                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5254                 if (status & DescOwn)
5255                         break;
5256
5257                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5258                                      tp->TxDescArray + entry);
5259                 if (status & LastFrag) {
5260                         dev->stats.tx_packets++;
5261                         dev->stats.tx_bytes += tx_skb->skb->len;
5262                         dev_kfree_skb(tx_skb->skb);
5263                         tx_skb->skb = NULL;
5264                 }
5265                 dirty_tx++;
5266                 tx_left--;
5267         }
5268
5269         if (tp->dirty_tx != dirty_tx) {
5270                 tp->dirty_tx = dirty_tx;
5271                 smp_wmb();
5272                 if (netif_queue_stopped(dev) &&
5273                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5274                         netif_wake_queue(dev);
5275                 }
5276                 /*
5277                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5278                  * too close. Let's kick an extra TxPoll request when a burst
5279                  * of start_xmit activity is detected (if it is not detected,
5280                  * it is slow enough). -- FR
5281                  */
5282                 smp_rmb();
5283                 if (tp->cur_tx != dirty_tx)
5284                         RTL_W8(TxPoll, NPQ);
5285         }
5286 }
5287
5288 static inline int rtl8169_fragmented_frame(u32 status)
5289 {
5290         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5291 }
5292
5293 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5294 {
5295         u32 status = opts1 & RxProtoMask;
5296
5297         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5298             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5299                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5300         else
5301                 skb_checksum_none_assert(skb);
5302 }
5303
5304 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5305                                            struct rtl8169_private *tp,
5306                                            int pkt_size,
5307                                            dma_addr_t addr)
5308 {
5309         struct sk_buff *skb;
5310         struct device *d = &tp->pci_dev->dev;
5311
5312         data = rtl8169_align(data);
5313         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5314         prefetch(data);
5315         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5316         if (skb)
5317                 memcpy(skb->data, data, pkt_size);
5318         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5319
5320         return skb;
5321 }
5322
5323 static int rtl8169_rx_interrupt(struct net_device *dev,
5324                                 struct rtl8169_private *tp,
5325                                 void __iomem *ioaddr, u32 budget)
5326 {
5327         unsigned int cur_rx, rx_left;
5328         unsigned int count;
5329
5330         cur_rx = tp->cur_rx;
5331         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5332         rx_left = min(rx_left, budget);
5333
5334         for (; rx_left > 0; rx_left--, cur_rx++) {
5335                 unsigned int entry = cur_rx % NUM_RX_DESC;
5336                 struct RxDesc *desc = tp->RxDescArray + entry;
5337                 u32 status;
5338
5339                 rmb();
5340                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5341
5342                 if (status & DescOwn)
5343                         break;
5344                 if (unlikely(status & RxRES)) {
5345                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5346                                    status);
5347                         dev->stats.rx_errors++;
5348                         if (status & (RxRWT | RxRUNT))
5349                                 dev->stats.rx_length_errors++;
5350                         if (status & RxCRC)
5351                                 dev->stats.rx_crc_errors++;
5352                         if (status & RxFOVF) {
5353                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5354                                 dev->stats.rx_fifo_errors++;
5355                         }
5356                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5357                 } else {
5358                         struct sk_buff *skb;
5359                         dma_addr_t addr = le64_to_cpu(desc->addr);
5360                         int pkt_size = (status & 0x00001FFF) - 4;
5361
5362                         /*
5363                          * The driver does not support incoming fragmented
5364                          * frames. They are seen as a symptom of over-mtu
5365                          * sized frames.
5366                          */
5367                         if (unlikely(rtl8169_fragmented_frame(status))) {
5368                                 dev->stats.rx_dropped++;
5369                                 dev->stats.rx_length_errors++;
5370                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5371                                 continue;
5372                         }
5373
5374                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5375                                                   tp, pkt_size, addr);
5376                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5377                         if (!skb) {
5378                                 dev->stats.rx_dropped++;
5379                                 continue;
5380                         }
5381
5382                         rtl8169_rx_csum(skb, status);
5383                         skb_put(skb, pkt_size);
5384                         skb->protocol = eth_type_trans(skb, dev);
5385
5386                         rtl8169_rx_vlan_tag(desc, skb);
5387
5388                         napi_gro_receive(&tp->napi, skb);
5389
5390                         dev->stats.rx_bytes += pkt_size;
5391                         dev->stats.rx_packets++;
5392                 }
5393
5394                 /* Work around for AMD plateform. */
5395                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5396                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5397                         desc->opts2 = 0;
5398                         cur_rx++;
5399                 }
5400         }
5401
5402         count = cur_rx - tp->cur_rx;
5403         tp->cur_rx = cur_rx;
5404
5405         tp->dirty_rx += count;
5406
5407         return count;
5408 }
5409
5410 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5411 {
5412         struct net_device *dev = dev_instance;
5413         struct rtl8169_private *tp = netdev_priv(dev);
5414         void __iomem *ioaddr = tp->mmio_addr;
5415         int handled = 0;
5416         int status;
5417
5418         /* loop handling interrupts until we have no new ones or
5419          * we hit a invalid/hotplug case.
5420          */
5421         status = RTL_R16(IntrStatus);
5422         while (status && status != 0xffff) {
5423                 handled = 1;
5424
5425                 /* Handle all of the error cases first. These will reset
5426                  * the chip, so just exit the loop.
5427                  */
5428                 if (unlikely(!netif_running(dev))) {
5429                         rtl8169_hw_reset(tp);
5430                         break;
5431                 }
5432
5433                 if (unlikely(status & RxFIFOOver)) {
5434                         switch (tp->mac_version) {
5435                         /* Work around for rx fifo overflow */
5436                         case RTL_GIGA_MAC_VER_11:
5437                         case RTL_GIGA_MAC_VER_22:
5438                         case RTL_GIGA_MAC_VER_26:
5439                                 netif_stop_queue(dev);
5440                                 rtl8169_tx_timeout(dev);
5441                                 goto done;
5442                         /* Testers needed. */
5443                         case RTL_GIGA_MAC_VER_17:
5444                         case RTL_GIGA_MAC_VER_19:
5445                         case RTL_GIGA_MAC_VER_20:
5446                         case RTL_GIGA_MAC_VER_21:
5447                         case RTL_GIGA_MAC_VER_23:
5448                         case RTL_GIGA_MAC_VER_24:
5449                         case RTL_GIGA_MAC_VER_27:
5450                         case RTL_GIGA_MAC_VER_28:
5451                         case RTL_GIGA_MAC_VER_31:
5452                         /* Experimental science. Pktgen proof. */
5453                         case RTL_GIGA_MAC_VER_12:
5454                         case RTL_GIGA_MAC_VER_25:
5455                                 if (status == RxFIFOOver)
5456                                         goto done;
5457                                 break;
5458                         default:
5459                                 break;
5460                         }
5461                 }
5462
5463                 if (unlikely(status & SYSErr)) {
5464                         rtl8169_pcierr_interrupt(dev);
5465                         break;
5466                 }
5467
5468                 if (status & LinkChg)
5469                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5470
5471                 /* We need to see the lastest version of tp->intr_mask to
5472                  * avoid ignoring an MSI interrupt and having to wait for
5473                  * another event which may never come.
5474                  */
5475                 smp_rmb();
5476                 if (status & tp->intr_mask & tp->napi_event) {
5477                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5478                         tp->intr_mask = ~tp->napi_event;
5479
5480                         if (likely(napi_schedule_prep(&tp->napi)))
5481                                 __napi_schedule(&tp->napi);
5482                         else
5483                                 netif_info(tp, intr, dev,
5484                                            "interrupt %04x in poll\n", status);
5485                 }
5486
5487                 /* We only get a new MSI interrupt when all active irq
5488                  * sources on the chip have been acknowledged. So, ack
5489                  * everything we've seen and check if new sources have become
5490                  * active to avoid blocking all interrupts from the chip.
5491                  */
5492                 RTL_W16(IntrStatus,
5493                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5494                 status = RTL_R16(IntrStatus);
5495         }
5496 done:
5497         return IRQ_RETVAL(handled);
5498 }
5499
5500 static int rtl8169_poll(struct napi_struct *napi, int budget)
5501 {
5502         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5503         struct net_device *dev = tp->dev;
5504         void __iomem *ioaddr = tp->mmio_addr;
5505         int work_done;
5506
5507         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5508         rtl8169_tx_interrupt(dev, tp, ioaddr);
5509
5510         if (work_done < budget) {
5511                 napi_complete(napi);
5512
5513                 /* We need for force the visibility of tp->intr_mask
5514                  * for other CPUs, as we can loose an MSI interrupt
5515                  * and potentially wait for a retransmit timeout if we don't.
5516                  * The posted write to IntrMask is safe, as it will
5517                  * eventually make it to the chip and we won't loose anything
5518                  * until it does.
5519                  */
5520                 tp->intr_mask = 0xffff;
5521                 wmb();
5522                 RTL_W16(IntrMask, tp->intr_event);
5523         }
5524
5525         return work_done;
5526 }
5527
5528 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5529 {
5530         struct rtl8169_private *tp = netdev_priv(dev);
5531
5532         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5533                 return;
5534
5535         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5536         RTL_W32(RxMissed, 0);
5537 }
5538
5539 static void rtl8169_down(struct net_device *dev)
5540 {
5541         struct rtl8169_private *tp = netdev_priv(dev);
5542         void __iomem *ioaddr = tp->mmio_addr;
5543
5544         del_timer_sync(&tp->timer);
5545
5546         netif_stop_queue(dev);
5547
5548         napi_disable(&tp->napi);
5549
5550         spin_lock_irq(&tp->lock);
5551
5552         rtl8169_hw_reset(tp);
5553         /*
5554          * At this point device interrupts can not be enabled in any function,
5555          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5556          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5557          */
5558         rtl8169_rx_missed(dev, ioaddr);
5559
5560         spin_unlock_irq(&tp->lock);
5561
5562         synchronize_irq(dev->irq);
5563
5564         /* Give a racing hard_start_xmit a few cycles to complete. */
5565         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5566
5567         rtl8169_tx_clear(tp);
5568
5569         rtl8169_rx_clear(tp);
5570
5571         rtl_pll_power_down(tp);
5572 }
5573
5574 static int rtl8169_close(struct net_device *dev)
5575 {
5576         struct rtl8169_private *tp = netdev_priv(dev);
5577         struct pci_dev *pdev = tp->pci_dev;
5578
5579         pm_runtime_get_sync(&pdev->dev);
5580
5581         /* Update counters before going down */
5582         rtl8169_update_counters(dev);
5583
5584         rtl8169_down(dev);
5585
5586         free_irq(dev->irq, dev);
5587
5588         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5589                           tp->RxPhyAddr);
5590         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5591                           tp->TxPhyAddr);
5592         tp->TxDescArray = NULL;
5593         tp->RxDescArray = NULL;
5594
5595         pm_runtime_put_sync(&pdev->dev);
5596
5597         return 0;
5598 }
5599
5600 static void rtl_set_rx_mode(struct net_device *dev)
5601 {
5602         struct rtl8169_private *tp = netdev_priv(dev);
5603         void __iomem *ioaddr = tp->mmio_addr;
5604         unsigned long flags;
5605         u32 mc_filter[2];       /* Multicast hash filter */
5606         int rx_mode;
5607         u32 tmp = 0;
5608
5609         if (dev->flags & IFF_PROMISC) {
5610                 /* Unconditionally log net taps. */
5611                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5612                 rx_mode =
5613                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5614                     AcceptAllPhys;
5615                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5616         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5617                    (dev->flags & IFF_ALLMULTI)) {
5618                 /* Too many to filter perfectly -- accept all multicasts. */
5619                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5620                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5621         } else {
5622                 struct netdev_hw_addr *ha;
5623
5624                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5625                 mc_filter[1] = mc_filter[0] = 0;
5626                 netdev_for_each_mc_addr(ha, dev) {
5627                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5628                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5629                         rx_mode |= AcceptMulticast;
5630                 }
5631         }
5632
5633         spin_lock_irqsave(&tp->lock, flags);
5634
5635         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5636
5637         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5638                 u32 data = mc_filter[0];
5639
5640                 mc_filter[0] = swab32(mc_filter[1]);
5641                 mc_filter[1] = swab32(data);
5642         }
5643
5644         RTL_W32(MAR0 + 4, mc_filter[1]);
5645         RTL_W32(MAR0 + 0, mc_filter[0]);
5646
5647         RTL_W32(RxConfig, tmp);
5648
5649         spin_unlock_irqrestore(&tp->lock, flags);
5650 }
5651
5652 /**
5653  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5654  *  @dev: The Ethernet Device to get statistics for
5655  *
5656  *  Get TX/RX statistics for rtl8169
5657  */
5658 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5659 {
5660         struct rtl8169_private *tp = netdev_priv(dev);
5661         void __iomem *ioaddr = tp->mmio_addr;
5662         unsigned long flags;
5663
5664         if (netif_running(dev)) {
5665                 spin_lock_irqsave(&tp->lock, flags);
5666                 rtl8169_rx_missed(dev, ioaddr);
5667                 spin_unlock_irqrestore(&tp->lock, flags);
5668         }
5669
5670         return &dev->stats;
5671 }
5672
5673 static void rtl8169_net_suspend(struct net_device *dev)
5674 {
5675         struct rtl8169_private *tp = netdev_priv(dev);
5676
5677         if (!netif_running(dev))
5678                 return;
5679
5680         rtl_pll_power_down(tp);
5681
5682         netif_device_detach(dev);
5683         netif_stop_queue(dev);
5684 }
5685
5686 #ifdef CONFIG_PM
5687
5688 static int rtl8169_suspend(struct device *device)
5689 {
5690         struct pci_dev *pdev = to_pci_dev(device);
5691         struct net_device *dev = pci_get_drvdata(pdev);
5692
5693         rtl8169_net_suspend(dev);
5694
5695         return 0;
5696 }
5697
5698 static void __rtl8169_resume(struct net_device *dev)
5699 {
5700         struct rtl8169_private *tp = netdev_priv(dev);
5701
5702         netif_device_attach(dev);
5703
5704         rtl_pll_power_up(tp);
5705
5706         rtl8169_schedule_work(dev, rtl8169_reset_task);
5707 }
5708
5709 static int rtl8169_resume(struct device *device)
5710 {
5711         struct pci_dev *pdev = to_pci_dev(device);
5712         struct net_device *dev = pci_get_drvdata(pdev);
5713         struct rtl8169_private *tp = netdev_priv(dev);
5714
5715         rtl8169_init_phy(dev, tp);
5716
5717         if (netif_running(dev))
5718                 __rtl8169_resume(dev);
5719
5720         return 0;
5721 }
5722
5723 static int rtl8169_runtime_suspend(struct device *device)
5724 {
5725         struct pci_dev *pdev = to_pci_dev(device);
5726         struct net_device *dev = pci_get_drvdata(pdev);
5727         struct rtl8169_private *tp = netdev_priv(dev);
5728
5729         if (!tp->TxDescArray)
5730                 return 0;
5731
5732         spin_lock_irq(&tp->lock);
5733         tp->saved_wolopts = __rtl8169_get_wol(tp);
5734         __rtl8169_set_wol(tp, WAKE_ANY);
5735         spin_unlock_irq(&tp->lock);
5736
5737         rtl8169_net_suspend(dev);
5738
5739         return 0;
5740 }
5741
5742 static int rtl8169_runtime_resume(struct device *device)
5743 {
5744         struct pci_dev *pdev = to_pci_dev(device);
5745         struct net_device *dev = pci_get_drvdata(pdev);
5746         struct rtl8169_private *tp = netdev_priv(dev);
5747
5748         if (!tp->TxDescArray)
5749                 return 0;
5750
5751         spin_lock_irq(&tp->lock);
5752         __rtl8169_set_wol(tp, tp->saved_wolopts);
5753         tp->saved_wolopts = 0;
5754         spin_unlock_irq(&tp->lock);
5755
5756         rtl8169_init_phy(dev, tp);
5757
5758         __rtl8169_resume(dev);
5759
5760         return 0;
5761 }
5762
5763 static int rtl8169_runtime_idle(struct device *device)
5764 {
5765         struct pci_dev *pdev = to_pci_dev(device);
5766         struct net_device *dev = pci_get_drvdata(pdev);
5767         struct rtl8169_private *tp = netdev_priv(dev);
5768
5769         return tp->TxDescArray ? -EBUSY : 0;
5770 }
5771
5772 static const struct dev_pm_ops rtl8169_pm_ops = {
5773         .suspend                = rtl8169_suspend,
5774         .resume                 = rtl8169_resume,
5775         .freeze                 = rtl8169_suspend,
5776         .thaw                   = rtl8169_resume,
5777         .poweroff               = rtl8169_suspend,
5778         .restore                = rtl8169_resume,
5779         .runtime_suspend        = rtl8169_runtime_suspend,
5780         .runtime_resume         = rtl8169_runtime_resume,
5781         .runtime_idle           = rtl8169_runtime_idle,
5782 };
5783
5784 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5785
5786 #else /* !CONFIG_PM */
5787
5788 #define RTL8169_PM_OPS  NULL
5789
5790 #endif /* !CONFIG_PM */
5791
5792 static void rtl_shutdown(struct pci_dev *pdev)
5793 {
5794         struct net_device *dev = pci_get_drvdata(pdev);
5795         struct rtl8169_private *tp = netdev_priv(dev);
5796         void __iomem *ioaddr = tp->mmio_addr;
5797
5798         rtl8169_net_suspend(dev);
5799
5800         /* Restore original MAC address */
5801         rtl_rar_set(tp, dev->perm_addr);
5802
5803         spin_lock_irq(&tp->lock);
5804
5805         rtl8169_hw_reset(tp);
5806
5807         spin_unlock_irq(&tp->lock);
5808
5809         if (system_state == SYSTEM_POWER_OFF) {
5810                 /* WoL fails with 8168b when the receiver is disabled. */
5811                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5812                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5813                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5814                     (tp->features & RTL_FEATURE_WOL)) {
5815                         pci_clear_master(pdev);
5816
5817                         RTL_W8(ChipCmd, CmdRxEnb);
5818                         /* PCI commit */
5819                         RTL_R8(ChipCmd);
5820                 }
5821
5822                 pci_wake_from_d3(pdev, true);
5823                 pci_set_power_state(pdev, PCI_D3hot);
5824         }
5825 }
5826
5827 static struct pci_driver rtl8169_pci_driver = {
5828         .name           = MODULENAME,
5829         .id_table       = rtl8169_pci_tbl,
5830         .probe          = rtl8169_init_one,
5831         .remove         = __devexit_p(rtl8169_remove_one),
5832         .shutdown       = rtl_shutdown,
5833         .driver.pm      = RTL8169_PM_OPS,
5834 };
5835
5836 static int __init rtl8169_init_module(void)
5837 {
5838         return pci_register_driver(&rtl8169_pci_driver);
5839 }
5840
5841 static void __exit rtl8169_cleanup_module(void)
5842 {
5843         pci_unregister_driver(&rtl8169_pci_driver);
5844 }
5845
5846 module_init(rtl8169_init_module);
5847 module_exit(rtl8169_cleanup_module);