drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_SLOTS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  66
  67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  69         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  70
  71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  72    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  73 static const int multicast_filter_limit = 32;
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define JUMBO_1K        ETH_DATA_LEN
 149 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 150 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 151 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 152 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 153
 154 #define _R(NAME,TD,FW,SZ,B) {   \
 155         .name = NAME,           \
 156         .txd_version = TD,      \
 157         .fw_name = FW,          \
 158         .jumbo_max = SZ,        \
 159         .jumbo_tx_csum = B      \
 160 }
 161
 162 static const struct {
 163         const char *name;
 164         enum rtl_tx_desc_version txd_version;
 165         const char *fw_name;
 166         u16 jumbo_max;
 167         bool jumbo_tx_csum;
 168 } rtl_chip_infos[] = {
 169         /* PCI devices. */
 170         [RTL_GIGA_MAC_VER_01] =
 171                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_02] =
 173                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_03] =
 175                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_04] =
 177                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_05] =
 179                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_06] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         /* PCI-E devices. */
 183         [RTL_GIGA_MAC_VER_07] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_08] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_09] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_10] =
 190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_11] =
 192                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 193         [RTL_GIGA_MAC_VER_12] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 195         [RTL_GIGA_MAC_VER_13] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_14] =
 198                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_15] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_16] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_17] =
 204                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_18] =
 206                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_19] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_20] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_21] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_22] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_23] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_24] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_25] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_26] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_31] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_32] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_33] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_34] =
 244                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_35] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_36] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 251                                                         JUMBO_9K, false),
 252 };
 253 #undef _R
 254
 255 enum cfg_version {
 256         RTL_CFG_0 = 0x00,
 257         RTL_CFG_1,
 258         RTL_CFG_2
 259 };
 260
 261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 271         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 272                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 273         { 0x0001,                               0x8168,
 274                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 275         {0,},
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 279
 280 static int rx_buf_sz = 16383;
 281 static int use_dac;
 282 static struct {
 283         u32 msg_enable;
 284 } debug = { -1 };
 285
 286 enum rtl_registers {
 287         MAC0            = 0,    /* Ethernet hardware address. */
 288         MAC4            = 4,
 289         MAR0            = 8,    /* Multicast filter. */
 290         CounterAddrLow          = 0x10,
 291         CounterAddrHigh         = 0x14,
 292         TxDescStartAddrLow      = 0x20,
 293         TxDescStartAddrHigh     = 0x24,
 294         TxHDescStartAddrLow     = 0x28,
 295         TxHDescStartAddrHigh    = 0x2c,
 296         FLASH           = 0x30,
 297         ERSR            = 0x36,
 298         ChipCmd         = 0x37,
 299         TxPoll          = 0x38,
 300         IntrMask        = 0x3c,
 301         IntrStatus      = 0x3e,
 302
 303         TxConfig        = 0x40,
 304 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 305 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 306
 307         RxConfig        = 0x44,
 308 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 309 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 310 #define RXCFG_FIFO_SHIFT                13
 311                                         /* No threshold before first PCI xfer */
 312 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 313 #define RXCFG_DMA_SHIFT                 8
 314                                         /* Unlimited maximum PCI burst. */
 315 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 316
 317         RxMissed        = 0x4c,
 318         Cfg9346         = 0x50,
 319         Config0         = 0x51,
 320         Config1         = 0x52,
 321         Config2         = 0x53,
 322         Config3         = 0x54,
 323         Config4         = 0x55,
 324         Config5         = 0x56,
 325         MultiIntr       = 0x5c,
 326         PHYAR           = 0x60,
 327         PHYstatus       = 0x6c,
 328         RxMaxSize       = 0xda,
 329         CPlusCmd        = 0xe0,
 330         IntrMitigate    = 0xe2,
 331         RxDescAddrLow   = 0xe4,
 332         RxDescAddrHigh  = 0xe8,
 333         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 334
 335 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 336
 337         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 338
 339 #define TxPacketMax     (8064 >> 7)
 340 #define EarlySize       0x27
 341
 342         FuncEvent       = 0xf0,
 343         FuncEventMask   = 0xf4,
 344         FuncPresetState = 0xf8,
 345         FuncForceEvent  = 0xfc,
 346 };
 347
 348 enum rtl8110_registers {
 349         TBICSR                  = 0x64,
 350         TBI_ANAR                = 0x68,
 351         TBI_LPAR                = 0x6a,
 352 };
 353
 354 enum rtl8168_8101_registers {
 355         CSIDR                   = 0x64,
 356         CSIAR                   = 0x68,
 357 #define CSIAR_FLAG                      0x80000000
 358 #define CSIAR_WRITE_CMD                 0x80000000
 359 #define CSIAR_BYTE_ENABLE               0x0f
 360 #define CSIAR_BYTE_ENABLE_SHIFT         12
 361 #define CSIAR_ADDR_MASK                 0x0fff
 362         PMCH                    = 0x6f,
 363         EPHYAR                  = 0x80,
 364 #define EPHYAR_FLAG                     0x80000000
 365 #define EPHYAR_WRITE_CMD                0x80000000
 366 #define EPHYAR_REG_MASK                 0x1f
 367 #define EPHYAR_REG_SHIFT                16
 368 #define EPHYAR_DATA_MASK                0xffff
 369         DLLPR                   = 0xd0,
 370 #define PFM_EN                          (1 << 6)
 371         DBG_REG                 = 0xd1,
 372 #define FIX_NAK_1                       (1 << 4)
 373 #define FIX_NAK_2                       (1 << 3)
 374         TWSI                    = 0xd2,
 375         MCU                     = 0xd3,
 376 #define NOW_IS_OOB                      (1 << 7)
 377 #define EN_NDP                          (1 << 3)
 378 #define EN_OOB_RESET                    (1 << 2)
 379         EFUSEAR                 = 0xdc,
 380 #define EFUSEAR_FLAG                    0x80000000
 381 #define EFUSEAR_WRITE_CMD               0x80000000
 382 #define EFUSEAR_READ_CMD                0x00000000
 383 #define EFUSEAR_REG_MASK                0x03ff
 384 #define EFUSEAR_REG_SHIFT               8
 385 #define EFUSEAR_DATA_MASK               0xff
 386 };
 387
 388 enum rtl8168_registers {
 389         LED_FREQ                = 0x1a,
 390         EEE_LED                 = 0x1b,
 391         ERIDR                   = 0x70,
 392         ERIAR                   = 0x74,
 393 #define ERIAR_FLAG                      0x80000000
 394 #define ERIAR_WRITE_CMD                 0x80000000
 395 #define ERIAR_READ_CMD                  0x00000000
 396 #define ERIAR_ADDR_BYTE_ALIGN           4
 397 #define ERIAR_TYPE_SHIFT                16
 398 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 399 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_MASK_SHIFT                12
 402 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 403 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 405         EPHY_RXER_NUM           = 0x7c,
 406         OCPDR                   = 0xb0, /* OCP GPHY access */
 407 #define OCPDR_WRITE_CMD                 0x80000000
 408 #define OCPDR_READ_CMD                  0x00000000
 409 #define OCPDR_REG_MASK                  0x7f
 410 #define OCPDR_GPHY_REG_SHIFT            16
 411 #define OCPDR_DATA_MASK                 0xffff
 412         OCPAR                   = 0xb4,
 413 #define OCPAR_FLAG                      0x80000000
 414 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 415 #define OCPAR_GPHY_READ_CMD             0x0000f060
 416         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 417         MISC                    = 0xf0, /* 8168e only. */
 418 #define TXPLA_RST                       (1 << 29)
 419 #define PWM_EN                          (1 << 22)
 420 };
 421
 422 enum rtl_register_content {
 423         /* InterruptStatusBits */
 424         SYSErr          = 0x8000,
 425         PCSTimeout      = 0x4000,
 426         SWInt           = 0x0100,
 427         TxDescUnavail   = 0x0080,
 428         RxFIFOOver      = 0x0040,
 429         LinkChg         = 0x0020,
 430         RxOverflow      = 0x0010,
 431         TxErr           = 0x0008,
 432         TxOK            = 0x0004,
 433         RxErr           = 0x0002,
 434         RxOK            = 0x0001,
 435
 436         /* RxStatusDesc */
 437         RxBOVF  = (1 << 24),
 438         RxFOVF  = (1 << 23),
 439         RxRWT   = (1 << 22),
 440         RxRES   = (1 << 21),
 441         RxRUNT  = (1 << 20),
 442         RxCRC   = (1 << 19),
 443
 444         /* ChipCmdBits */
 445         StopReq         = 0x80,
 446         CmdReset        = 0x10,
 447         CmdRxEnb        = 0x08,
 448         CmdTxEnb        = 0x04,
 449         RxBufEmpty      = 0x01,
 450
 451         /* TXPoll register p.5 */
 452         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 453         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 454         FSWInt          = 0x01,         /* Forced software interrupt */
 455
 456         /* Cfg9346Bits */
 457         Cfg9346_Lock    = 0x00,
 458         Cfg9346_Unlock  = 0xc0,
 459
 460         /* rx_mode_bits */
 461         AcceptErr       = 0x20,
 462         AcceptRunt      = 0x10,
 463         AcceptBroadcast = 0x08,
 464         AcceptMulticast = 0x04,
 465         AcceptMyPhys    = 0x02,
 466         AcceptAllPhys   = 0x01,
 467 #define RX_CONFIG_ACCEPT_MASK           0x3f
 468
 469         /* TxConfigBits */
 470         TxInterFrameGapShift = 24,
 471         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 472
 473         /* Config1 register p.24 */
 474         LEDS1           = (1 << 7),
 475         LEDS0           = (1 << 6),
 476         Speed_down      = (1 << 4),
 477         MEMMAP          = (1 << 3),
 478         IOMAP           = (1 << 2),
 479         VPD             = (1 << 1),
 480         PMEnable        = (1 << 0),     /* Power Management Enable */
 481
 482         /* Config2 register p. 25 */
 483         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 484         PCI_Clock_66MHz = 0x01,
 485         PCI_Clock_33MHz = 0x00,
 486
 487         /* Config3 register p.25 */
 488         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 489         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 490         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 491         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 492
 493         /* Config4 register */
 494         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 495
 496         /* Config5 register p.27 */
 497         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 498         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 499         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 500         Spi_en          = (1 << 3),
 501         LanWake         = (1 << 1),     /* LanWake enable/disable */
 502         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 503
 504         /* TBICSR p.28 */
 505         TBIReset        = 0x80000000,
 506         TBILoopback     = 0x40000000,
 507         TBINwEnable     = 0x20000000,
 508         TBINwRestart    = 0x10000000,
 509         TBILinkOk       = 0x02000000,
 510         TBINwComplete   = 0x01000000,
 511
 512         /* CPlusCmd p.31 */
 513         EnableBist      = (1 << 15),    // 8168 8101
 514         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 515         Normal_mode     = (1 << 13),    // unused
 516         Force_half_dup  = (1 << 12),    // 8168 8101
 517         Force_rxflow_en = (1 << 11),    // 8168 8101
 518         Force_txflow_en = (1 << 10),    // 8168 8101
 519         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 520         ASF             = (1 << 8),     // 8168 8101
 521         PktCntrDisable  = (1 << 7),     // 8168 8101
 522         Mac_dbgo_sel    = 0x001c,       // 8168
 523         RxVlan          = (1 << 6),
 524         RxChkSum        = (1 << 5),
 525         PCIDAC          = (1 << 4),
 526         PCIMulRW        = (1 << 3),
 527         INTT_0          = 0x0000,       // 8168
 528         INTT_1          = 0x0001,       // 8168
 529         INTT_2          = 0x0002,       // 8168
 530         INTT_3          = 0x0003,       // 8168
 531
 532         /* rtl8169_PHYstatus */
 533         TBI_Enable      = 0x80,
 534         TxFlowCtrl      = 0x40,
 535         RxFlowCtrl      = 0x20,
 536         _1000bpsF       = 0x10,
 537         _100bps         = 0x08,
 538         _10bps          = 0x04,
 539         LinkStatus      = 0x02,
 540         FullDup         = 0x01,
 541
 542         /* _TBICSRBit */
 543         TBILinkOK       = 0x02000000,
 544
 545         /* DumpCounterCommand */
 546         CounterDump     = 0x8,
 547 };
 548
 549 enum rtl_desc_bit {
 550         /* First doubleword. */
 551         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 552         RingEnd         = (1 << 30), /* End of descriptor ring */
 553         FirstFrag       = (1 << 29), /* First segment of a packet */
 554         LastFrag        = (1 << 28), /* Final segment of a packet */
 555 };
 556
 557 /* Generic case. */
 558 enum rtl_tx_desc_bit {
 559         /* First doubleword. */
 560         TD_LSO          = (1 << 27),            /* Large Send Offload */
 561 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 562
 563         /* Second doubleword. */
 564         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 565 };
 566
 567 /* 8169, 8168b and 810x except 8102e. */
 568 enum rtl_tx_desc_bit_0 {
 569         /* First doubleword. */
 570 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 571         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 572         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 573         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 574 };
 575
 576 /* 8102e, 8168c and beyond. */
 577 enum rtl_tx_desc_bit_1 {
 578         /* Second doubleword. */
 579 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 580         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 581         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 582         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 583 };
 584
 585 static const struct rtl_tx_desc_info {
 586         struct {
 587                 u32 udp;
 588                 u32 tcp;
 589         } checksum;
 590         u16 mss_shift;
 591         u16 opts_offset;
 592 } tx_desc_info [] = {
 593         [RTL_TD_0] = {
 594                 .checksum = {
 595                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 596                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 597                 },
 598                 .mss_shift      = TD0_MSS_SHIFT,
 599                 .opts_offset    = 0
 600         },
 601         [RTL_TD_1] = {
 602                 .checksum = {
 603                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 604                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 605                 },
 606                 .mss_shift      = TD1_MSS_SHIFT,
 607                 .opts_offset    = 1
 608         }
 609 };
 610
 611 enum rtl_rx_desc_bit {
 612         /* Rx private */
 613         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 614         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 615
 616 #define RxProtoUDP      (PID1)
 617 #define RxProtoTCP      (PID0)
 618 #define RxProtoIP       (PID1 | PID0)
 619 #define RxProtoMask     RxProtoIP
 620
 621         IPFail          = (1 << 16), /* IP checksum failed */
 622         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 623         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 624         RxVlanTag       = (1 << 16), /* VLAN tag available */
 625 };
 626
 627 #define RsvdMask        0x3fffc000
 628
 629 struct TxDesc {
 630         __le32 opts1;
 631         __le32 opts2;
 632         __le64 addr;
 633 };
 634
 635 struct RxDesc {
 636         __le32 opts1;
 637         __le32 opts2;
 638         __le64 addr;
 639 };
 640
 641 struct ring_info {
 642         struct sk_buff  *skb;
 643         u32             len;
 644         u8              __pad[sizeof(void *) - sizeof(u32)];
 645 };
 646
 647 enum features {
 648         RTL_FEATURE_WOL         = (1 << 0),
 649         RTL_FEATURE_MSI         = (1 << 1),
 650         RTL_FEATURE_GMII        = (1 << 2),
 651 };
 652
 653 struct rtl8169_counters {
 654         __le64  tx_packets;
 655         __le64  rx_packets;
 656         __le64  tx_errors;
 657         __le32  rx_errors;
 658         __le16  rx_missed;
 659         __le16  align_errors;
 660         __le32  tx_one_collision;
 661         __le32  tx_multi_collision;
 662         __le64  rx_unicast;
 663         __le64  rx_broadcast;
 664         __le32  rx_multicast;
 665         __le16  tx_aborted;
 666         __le16  tx_underun;
 667 };
 668
 669 enum rtl_flag {
 670         RTL_FLAG_TASK_ENABLED,
 671         RTL_FLAG_TASK_SLOW_PENDING,
 672         RTL_FLAG_TASK_RESET_PENDING,
 673         RTL_FLAG_TASK_PHY_PENDING,
 674         RTL_FLAG_MAX
 675 };
 676
 677 struct rtl8169_stats {
 678         u64                     packets;
 679         u64                     bytes;
 680         struct u64_stats_sync   syncp;
 681 };
 682
 683 struct rtl8169_private {
 684         void __iomem *mmio_addr;        /* memory map physical address */
 685         struct pci_dev *pci_dev;
 686         struct net_device *dev;
 687         struct napi_struct napi;
 688         u32 msg_enable;
 689         u16 txd_version;
 690         u16 mac_version;
 691         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 692         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 693         u32 dirty_rx;
 694         u32 dirty_tx;
 695         struct rtl8169_stats rx_stats;
 696         struct rtl8169_stats tx_stats;
 697         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 698         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 699         dma_addr_t TxPhyAddr;
 700         dma_addr_t RxPhyAddr;
 701         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 702         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 703         struct timer_list timer;
 704         u16 cp_cmd;
 705
 706         u16 event_slow;
 707         bool runtime_suspended;
 708
 709         struct mdio_ops {
 710                 void (*write)(void __iomem *, int, int);
 711                 int (*read)(void __iomem *, int);
 712         } mdio_ops;
 713
 714         struct pll_power_ops {
 715                 void (*down)(struct rtl8169_private *);
 716                 void (*up)(struct rtl8169_private *);
 717         } pll_power_ops;
 718
 719         struct jumbo_ops {
 720                 void (*enable)(struct rtl8169_private *);
 721                 void (*disable)(struct rtl8169_private *);
 722         } jumbo_ops;
 723
 724         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 725         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 726         void (*phy_reset_enable)(struct rtl8169_private *tp);
 727         void (*hw_start)(struct net_device *);
 728         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 729         unsigned int (*link_ok)(void __iomem *);
 730         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 731
 732         struct {
 733                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 734                 struct mutex mutex;
 735                 struct work_struct work;
 736         } wk;
 737
 738         unsigned features;
 739
 740         struct mii_if_info mii;
 741         struct rtl8169_counters counters;
 742         u32 saved_wolopts;
 743         u32 opts1_mask;
 744
 745         struct rtl_fw {
 746                 const struct firmware *fw;
 747
 748 #define RTL_VER_SIZE            32
 749
 750                 char version[RTL_VER_SIZE];
 751
 752                 struct rtl_fw_phy_action {
 753                         __le32 *code;
 754                         size_t size;
 755                 } phy_action;
 756         } *rtl_fw;
 757 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 758 };
 759
 760 static int aspm_disable = 0;
 761 module_param(aspm_disable, bool, 0444);
 762 MODULE_PARM_DESC(aspm_disable, "Disable ASPM completely.");
 763
 764 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 765 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 766 module_param(use_dac, int, 0);
 767 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 768 module_param_named(debug, debug.msg_enable, int, 0);
 769 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 770 MODULE_LICENSE("GPL");
 771 MODULE_VERSION(RTL8169_VERSION);
 772 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 773 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 774 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 775 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 776 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 777 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 778 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 779 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 780
 781 static void rtl_lock_work(struct rtl8169_private *tp)
 782 {
 783         mutex_lock(&tp->wk.mutex);
 784 }
 785
 786 static void rtl_unlock_work(struct rtl8169_private *tp)
 787 {
 788         mutex_unlock(&tp->wk.mutex);
 789 }
 790
 791 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 792 {
 793         int cap = pci_pcie_cap(pdev);
 794
 795         if (cap) {
 796                 u16 ctl;
 797
 798                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 799                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 800                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 801         }
 802 }
 803
 804 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 805 {
 806         void __iomem *ioaddr = tp->mmio_addr;
 807         int i;
 808
 809         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 810         for (i = 0; i < 20; i++) {
 811                 udelay(100);
 812                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 813                         break;
 814         }
 815         return RTL_R32(OCPDR);
 816 }
 817
 818 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 819 {
 820         void __iomem *ioaddr = tp->mmio_addr;
 821         int i;
 822
 823         RTL_W32(OCPDR, data);
 824         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 825         for (i = 0; i < 20; i++) {
 826                 udelay(100);
 827                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 828                         break;
 829         }
 830 }
 831
 832 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 833 {
 834         void __iomem *ioaddr = tp->mmio_addr;
 835         int i;
 836
 837         RTL_W8(ERIDR, cmd);
 838         RTL_W32(ERIAR, 0x800010e8);
 839         msleep(2);
 840         for (i = 0; i < 5; i++) {
 841                 udelay(100);
 842                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 843                         break;
 844         }
 845
 846         ocp_write(tp, 0x1, 0x30, 0x00000001);
 847 }
 848
 849 #define OOB_CMD_RESET           0x00
 850 #define OOB_CMD_DRIVER_START    0x05
 851 #define OOB_CMD_DRIVER_STOP     0x06
 852
 853 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 854 {
 855         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 856 }
 857
 858 static void rtl8168_driver_start(struct rtl8169_private *tp)
 859 {
 860         u16 reg;
 861         int i;
 862
 863         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 864
 865         reg = rtl8168_get_ocp_reg(tp);
 866
 867         for (i = 0; i < 10; i++) {
 868                 msleep(10);
 869                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 870                         break;
 871         }
 872 }
 873
 874 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 875 {
 876         u16 reg;
 877         int i;
 878
 879         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 880
 881         reg = rtl8168_get_ocp_reg(tp);
 882
 883         for (i = 0; i < 10; i++) {
 884                 msleep(10);
 885                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 886                         break;
 887         }
 888 }
 889
 890 static int r8168dp_check_dash(struct rtl8169_private *tp)
 891 {
 892         u16 reg = rtl8168_get_ocp_reg(tp);
 893
 894         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 895 }
 896
 897 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 898 {
 899         int i;
 900
 901         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 902
 903         for (i = 20; i > 0; i--) {
 904                 /*
 905                  * Check if the RTL8169 has completed writing to the specified
 906                  * MII register.
 907                  */
 908                 if (!(RTL_R32(PHYAR) & 0x80000000))
 909                         break;
 910                 udelay(25);
 911         }
 912         /*
 913          * According to hardware specs a 20us delay is required after write
 914          * complete indication, but before sending next command.
 915          */
 916         udelay(20);
 917 }
 918
 919 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 920 {
 921         int i, value = -1;
 922
 923         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 924
 925         for (i = 20; i > 0; i--) {
 926                 /*
 927                  * Check if the RTL8169 has completed retrieving data from
 928                  * the specified MII register.
 929                  */
 930                 if (RTL_R32(PHYAR) & 0x80000000) {
 931                         value = RTL_R32(PHYAR) & 0xffff;
 932                         break;
 933                 }
 934                 udelay(25);
 935         }
 936         /*
 937          * According to hardware specs a 20us delay is required after read
 938          * complete indication, but before sending next command.
 939          */
 940         udelay(20);
 941
 942         return value;
 943 }
 944
 945 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 946 {
 947         int i;
 948
 949         RTL_W32(OCPDR, data |
 950                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 951         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 952         RTL_W32(EPHY_RXER_NUM, 0);
 953
 954         for (i = 0; i < 100; i++) {
 955                 mdelay(1);
 956                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 957                         break;
 958         }
 959 }
 960
 961 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 962 {
 963         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 964                 (value & OCPDR_DATA_MASK));
 965 }
 966
 967 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 968 {
 969         int i;
 970
 971         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 972
 973         mdelay(1);
 974         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 975         RTL_W32(EPHY_RXER_NUM, 0);
 976
 977         for (i = 0; i < 100; i++) {
 978                 mdelay(1);
 979                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 980                         break;
 981         }
 982
 983         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 984 }
 985
 986 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 987
 988 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 989 {
 990         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 994 {
 995         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 996 }
 997
 998 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 999 {
1000         r8168dp_2_mdio_start(ioaddr);
1001
1002         r8169_mdio_write(ioaddr, reg_addr, value);
1003
1004         r8168dp_2_mdio_stop(ioaddr);
1005 }
1006
1007 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1008 {
1009         int value;
1010
1011         r8168dp_2_mdio_start(ioaddr);
1012
1013         value = r8169_mdio_read(ioaddr, reg_addr);
1014
1015         r8168dp_2_mdio_stop(ioaddr);
1016
1017         return value;
1018 }
1019
1020 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1021 {
1022         tp->mdio_ops.write(tp->mmio_addr, location, val);
1023 }
1024
1025 static int rtl_readphy(struct rtl8169_private *tp, int location)
1026 {
1027         return tp->mdio_ops.read(tp->mmio_addr, location);
1028 }
1029
1030 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1031 {
1032         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1033 }
1034
1035 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1036 {
1037         int val;
1038
1039         val = rtl_readphy(tp, reg_addr);
1040         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1041 }
1042
1043 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1044                            int val)
1045 {
1046         struct rtl8169_private *tp = netdev_priv(dev);
1047
1048         rtl_writephy(tp, location, val);
1049 }
1050
1051 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1052 {
1053         struct rtl8169_private *tp = netdev_priv(dev);
1054
1055         return rtl_readphy(tp, location);
1056 }
1057
1058 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1059 {
1060         unsigned int i;
1061
1062         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1063                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1064
1065         for (i = 0; i < 100; i++) {
1066                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1067                         break;
1068                 udelay(10);
1069         }
1070 }
1071
1072 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1073 {
1074         u16 value = 0xffff;
1075         unsigned int i;
1076
1077         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1078
1079         for (i = 0; i < 100; i++) {
1080                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1081                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1082                         break;
1083                 }
1084                 udelay(10);
1085         }
1086
1087         return value;
1088 }
1089
1090 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1091 {
1092         unsigned int i;
1093
1094         RTL_W32(CSIDR, value);
1095         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1096                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1097
1098         for (i = 0; i < 100; i++) {
1099                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1100                         break;
1101                 udelay(10);
1102         }
1103 }
1104
1105 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1106 {
1107         u32 value = ~0x00;
1108         unsigned int i;
1109
1110         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1111                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1112
1113         for (i = 0; i < 100; i++) {
1114                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1115                         value = RTL_R32(CSIDR);
1116                         break;
1117                 }
1118                 udelay(10);
1119         }
1120
1121         return value;
1122 }
1123
1124 static
1125 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1126 {
1127         unsigned int i;
1128
1129         BUG_ON((addr & 3) || (mask == 0));
1130         RTL_W32(ERIDR, val);
1131         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1132
1133         for (i = 0; i < 100; i++) {
1134                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1135                         break;
1136                 udelay(100);
1137         }
1138 }
1139
1140 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1141 {
1142         u32 value = ~0x00;
1143         unsigned int i;
1144
1145         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1146
1147         for (i = 0; i < 100; i++) {
1148                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1149                         value = RTL_R32(ERIDR);
1150                         break;
1151                 }
1152                 udelay(100);
1153         }
1154
1155         return value;
1156 }
1157
1158 static void
1159 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1160 {
1161         u32 val;
1162
1163         val = rtl_eri_read(ioaddr, addr, type);
1164         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1165 }
1166
1167 struct exgmac_reg {
1168         u16 addr;
1169         u16 mask;
1170         u32 val;
1171 };
1172
1173 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1174                                    const struct exgmac_reg *r, int len)
1175 {
1176         while (len-- > 0) {
1177                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1178                 r++;
1179         }
1180 }
1181
1182 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1183 {
1184         u8 value = 0xff;
1185         unsigned int i;
1186
1187         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1188
1189         for (i = 0; i < 300; i++) {
1190                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1191                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1192                         break;
1193                 }
1194                 udelay(100);
1195         }
1196
1197         return value;
1198 }
1199
1200 static u16 rtl_get_events(struct rtl8169_private *tp)
1201 {
1202         void __iomem *ioaddr = tp->mmio_addr;
1203
1204         return RTL_R16(IntrStatus);
1205 }
1206
1207 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1208 {
1209         void __iomem *ioaddr = tp->mmio_addr;
1210
1211         RTL_W16(IntrStatus, bits);
1212         mmiowb();
1213 }
1214
1215 static void rtl_irq_disable(struct rtl8169_private *tp)
1216 {
1217         void __iomem *ioaddr = tp->mmio_addr;
1218
1219         RTL_W16(IntrMask, 0);
1220         mmiowb();
1221 }
1222
1223 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1224 {
1225         void __iomem *ioaddr = tp->mmio_addr;
1226
1227         RTL_W16(IntrMask, bits);
1228 }
1229
1230 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1231 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1232 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1233
1234 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1235 {
1236         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1237 }
1238
1239 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242
1243         rtl_irq_disable(tp);
1244         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1245         RTL_R8(ChipCmd);
1246 }
1247
1248 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1249 {
1250         void __iomem *ioaddr = tp->mmio_addr;
1251
1252         return RTL_R32(TBICSR) & TBIReset;
1253 }
1254
1255 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1256 {
1257         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1258 }
1259
1260 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1261 {
1262         return RTL_R32(TBICSR) & TBILinkOk;
1263 }
1264
1265 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1266 {
1267         return RTL_R8(PHYstatus) & LinkStatus;
1268 }
1269
1270 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1271 {
1272         void __iomem *ioaddr = tp->mmio_addr;
1273
1274         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1275 }
1276
1277 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1278 {
1279         unsigned int val;
1280
1281         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1282         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1283 }
1284
1285 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1286 {
1287         void __iomem *ioaddr = tp->mmio_addr;
1288         struct net_device *dev = tp->dev;
1289
1290         if (!netif_running(dev))
1291                 return;
1292
1293         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1294                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1295                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1296                                       0x00000011, ERIAR_EXGMAC);
1297                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1298                                       0x00000005, ERIAR_EXGMAC);
1299                 } else if (RTL_R8(PHYstatus) & _100bps) {
1300                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1301                                       0x0000001f, ERIAR_EXGMAC);
1302                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1303                                       0x00000005, ERIAR_EXGMAC);
1304                 } else {
1305                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1306                                       0x0000001f, ERIAR_EXGMAC);
1307                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1308                                       0x0000003f, ERIAR_EXGMAC);
1309                 }
1310                 /* Reset packet filter */
1311                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1312                              ERIAR_EXGMAC);
1313                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1314                              ERIAR_EXGMAC);
1315         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1316                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1317                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1318                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1319                                       0x00000011, ERIAR_EXGMAC);
1320                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1321                                       0x00000005, ERIAR_EXGMAC);
1322                 } else {
1323                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1324                                       0x0000001f, ERIAR_EXGMAC);
1325                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1326                                       0x0000003f, ERIAR_EXGMAC);
1327                 }
1328         }
1329 }
1330
1331 static void __rtl8169_check_link_status(struct net_device *dev,
1332                                         struct rtl8169_private *tp,
1333                                         void __iomem *ioaddr, bool pm)
1334 {
1335         if (tp->link_ok(ioaddr)) {
1336                 rtl_link_chg_patch(tp);
1337                 /* This is to cancel a scheduled suspend if there's one. */
1338                 if (pm)
1339                         pm_request_resume(&tp->pci_dev->dev);
1340                 netif_carrier_on(dev);
1341                 if (net_ratelimit())
1342                         netif_info(tp, ifup, dev, "link up\n");
1343         } else {
1344                 netif_carrier_off(dev);
1345                 netif_info(tp, ifdown, dev, "link down\n");
1346                 if (pm)
1347                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1348         }
1349 }
1350
1351 static void rtl8169_check_link_status(struct net_device *dev,
1352                                       struct rtl8169_private *tp,
1353                                       void __iomem *ioaddr)
1354 {
1355         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1356 }
1357
1358 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1359
1360 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1361 {
1362         void __iomem *ioaddr = tp->mmio_addr;
1363         u8 options;
1364         u32 wolopts = 0;
1365
1366         options = RTL_R8(Config1);
1367         if (!(options & PMEnable))
1368                 return 0;
1369
1370         options = RTL_R8(Config3);
1371         if (options & LinkUp)
1372                 wolopts |= WAKE_PHY;
1373         if (options & MagicPacket)
1374                 wolopts |= WAKE_MAGIC;
1375
1376         options = RTL_R8(Config5);
1377         if (options & UWF)
1378                 wolopts |= WAKE_UCAST;
1379         if (options & BWF)
1380                 wolopts |= WAKE_BCAST;
1381         if (options & MWF)
1382                 wolopts |= WAKE_MCAST;
1383
1384         return wolopts;
1385 }
1386
1387 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1388 {
1389         struct rtl8169_private *tp = netdev_priv(dev);
1390
1391         rtl_lock_work(tp);
1392
1393         wol->supported = WAKE_ANY;
1394         wol->wolopts = __rtl8169_get_wol(tp);
1395
1396         rtl_unlock_work(tp);
1397 }
1398
1399 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1400 {
1401         void __iomem *ioaddr = tp->mmio_addr;
1402         unsigned int i;
1403         static const struct {
1404                 u32 opt;
1405                 u16 reg;
1406                 u8  mask;
1407         } cfg[] = {
1408                 { WAKE_ANY,   Config1, PMEnable },
1409                 { WAKE_PHY,   Config3, LinkUp },
1410                 { WAKE_MAGIC, Config3, MagicPacket },
1411                 { WAKE_UCAST, Config5, UWF },
1412                 { WAKE_BCAST, Config5, BWF },
1413                 { WAKE_MCAST, Config5, MWF },
1414                 { WAKE_ANY,   Config5, LanWake }
1415         };
1416
1417         RTL_W8(Cfg9346, Cfg9346_Unlock);
1418
1419         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1420                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1421                 if (wolopts & cfg[i].opt)
1422                         options |= cfg[i].mask;
1423                 RTL_W8(cfg[i].reg, options);
1424         }
1425
1426         RTL_W8(Cfg9346, Cfg9346_Lock);
1427 }
1428
1429 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1430 {
1431         struct rtl8169_private *tp = netdev_priv(dev);
1432
1433         rtl_lock_work(tp);
1434
1435         if (wol->wolopts)
1436                 tp->features |= RTL_FEATURE_WOL;
1437         else
1438                 tp->features &= ~RTL_FEATURE_WOL;
1439         __rtl8169_set_wol(tp, wol->wolopts);
1440
1441         rtl_unlock_work(tp);
1442
1443         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1444
1445         return 0;
1446 }
1447
1448 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1449 {
1450         return rtl_chip_infos[tp->mac_version].fw_name;
1451 }
1452
1453 static void rtl8169_get_drvinfo(struct net_device *dev,
1454                                 struct ethtool_drvinfo *info)
1455 {
1456         struct rtl8169_private *tp = netdev_priv(dev);
1457         struct rtl_fw *rtl_fw = tp->rtl_fw;
1458
1459         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1460         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1461         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1462         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1463         if (!IS_ERR_OR_NULL(rtl_fw))
1464                 strlcpy(info->fw_version, rtl_fw->version,
1465                         sizeof(info->fw_version));
1466 }
1467
1468 static int rtl8169_get_regs_len(struct net_device *dev)
1469 {
1470         return R8169_REGS_SIZE;
1471 }
1472
1473 static int rtl8169_set_speed_tbi(struct net_device *dev,
1474                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1475 {
1476         struct rtl8169_private *tp = netdev_priv(dev);
1477         void __iomem *ioaddr = tp->mmio_addr;
1478         int ret = 0;
1479         u32 reg;
1480
1481         reg = RTL_R32(TBICSR);
1482         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1483             (duplex == DUPLEX_FULL)) {
1484                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1485         } else if (autoneg == AUTONEG_ENABLE)
1486                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1487         else {
1488                 netif_warn(tp, link, dev,
1489                            "incorrect speed setting refused in TBI mode\n");
1490                 ret = -EOPNOTSUPP;
1491         }
1492
1493         return ret;
1494 }
1495
1496 static int rtl8169_set_speed_xmii(struct net_device *dev,
1497                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1498 {
1499         struct rtl8169_private *tp = netdev_priv(dev);
1500         int giga_ctrl, bmcr;
1501         int rc = -EINVAL;
1502
1503         rtl_writephy(tp, 0x1f, 0x0000);
1504
1505         if (autoneg == AUTONEG_ENABLE) {
1506                 int auto_nego;
1507
1508                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1509                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1510                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1511
1512                 if (adv & ADVERTISED_10baseT_Half)
1513                         auto_nego |= ADVERTISE_10HALF;
1514                 if (adv & ADVERTISED_10baseT_Full)
1515                         auto_nego |= ADVERTISE_10FULL;
1516                 if (adv & ADVERTISED_100baseT_Half)
1517                         auto_nego |= ADVERTISE_100HALF;
1518                 if (adv & ADVERTISED_100baseT_Full)
1519                         auto_nego |= ADVERTISE_100FULL;
1520
1521                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1522
1523                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1524                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1525
1526                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1527                 if (tp->mii.supports_gmii) {
1528                         if (adv & ADVERTISED_1000baseT_Half)
1529                                 giga_ctrl |= ADVERTISE_1000HALF;
1530                         if (adv & ADVERTISED_1000baseT_Full)
1531                                 giga_ctrl |= ADVERTISE_1000FULL;
1532                 } else if (adv & (ADVERTISED_1000baseT_Half |
1533                                   ADVERTISED_1000baseT_Full)) {
1534                         netif_info(tp, link, dev,
1535                                    "PHY does not support 1000Mbps\n");
1536                         goto out;
1537                 }
1538
1539                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1540
1541                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1542                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1543         } else {
1544                 giga_ctrl = 0;
1545
1546                 if (speed == SPEED_10)
1547                         bmcr = 0;
1548                 else if (speed == SPEED_100)
1549                         bmcr = BMCR_SPEED100;
1550                 else
1551                         goto out;
1552
1553                 if (duplex == DUPLEX_FULL)
1554                         bmcr |= BMCR_FULLDPLX;
1555         }
1556
1557         rtl_writephy(tp, MII_BMCR, bmcr);
1558
1559         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1560             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1561                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1562                         rtl_writephy(tp, 0x17, 0x2138);
1563                         rtl_writephy(tp, 0x0e, 0x0260);
1564                 } else {
1565                         rtl_writephy(tp, 0x17, 0x2108);
1566                         rtl_writephy(tp, 0x0e, 0x0000);
1567                 }
1568         }
1569
1570         rc = 0;
1571 out:
1572         return rc;
1573 }
1574
1575 static int rtl8169_set_speed(struct net_device *dev,
1576                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1577 {
1578         struct rtl8169_private *tp = netdev_priv(dev);
1579         int ret;
1580
1581         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1582         if (ret < 0)
1583                 goto out;
1584
1585         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1586             (advertising & ADVERTISED_1000baseT_Full)) {
1587                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1588         }
1589 out:
1590         return ret;
1591 }
1592
1593 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         int ret;
1597
1598         del_timer_sync(&tp->timer);
1599
1600         rtl_lock_work(tp);
1601         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1602                                 cmd->duplex, cmd->advertising);
1603         rtl_unlock_work(tp);
1604
1605         return ret;
1606 }
1607
1608 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1609         netdev_features_t features)
1610 {
1611         struct rtl8169_private *tp = netdev_priv(dev);
1612
1613         if (dev->mtu > TD_MSS_MAX)
1614                 features &= ~NETIF_F_ALL_TSO;
1615
1616         if (dev->mtu > JUMBO_1K &&
1617             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1618                 features &= ~NETIF_F_IP_CSUM;
1619
1620         return features;
1621 }
1622
1623 static void __rtl8169_set_features(struct net_device *dev,
1624                                    netdev_features_t features)
1625 {
1626         struct rtl8169_private *tp = netdev_priv(dev);
1627         netdev_features_t changed = features ^ dev->features;
1628         void __iomem *ioaddr = tp->mmio_addr;
1629
1630         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1631                 return;
1632
1633         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1634                 if (features & NETIF_F_RXCSUM)
1635                         tp->cp_cmd |= RxChkSum;
1636                 else
1637                         tp->cp_cmd &= ~RxChkSum;
1638
1639                 if (dev->features & NETIF_F_HW_VLAN_RX)
1640                         tp->cp_cmd |= RxVlan;
1641                 else
1642                         tp->cp_cmd &= ~RxVlan;
1643
1644                 RTL_W16(CPlusCmd, tp->cp_cmd);
1645                 RTL_R16(CPlusCmd);
1646         }
1647         if (changed & NETIF_F_RXALL) {
1648                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1649                 if (features & NETIF_F_RXALL)
1650                         tmp |= (AcceptErr | AcceptRunt);
1651                 RTL_W32(RxConfig, tmp);
1652         }
1653 }
1654
1655 static int rtl8169_set_features(struct net_device *dev,
1656                                 netdev_features_t features)
1657 {
1658         struct rtl8169_private *tp = netdev_priv(dev);
1659
1660         rtl_lock_work(tp);
1661         __rtl8169_set_features(dev, features);
1662         rtl_unlock_work(tp);
1663
1664         return 0;
1665 }
1666
1667
1668 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1669                                       struct sk_buff *skb)
1670 {
1671         return (vlan_tx_tag_present(skb)) ?
1672                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1673 }
1674
1675 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1676 {
1677         u32 opts2 = le32_to_cpu(desc->opts2);
1678
1679         if (opts2 & RxVlanTag)
1680                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1681
1682         desc->opts2 = 0;
1683 }
1684
1685 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1686 {
1687         struct rtl8169_private *tp = netdev_priv(dev);
1688         void __iomem *ioaddr = tp->mmio_addr;
1689         u32 status;
1690
1691         cmd->supported =
1692                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1693         cmd->port = PORT_FIBRE;
1694         cmd->transceiver = XCVR_INTERNAL;
1695
1696         status = RTL_R32(TBICSR);
1697         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1698         cmd->autoneg = !!(status & TBINwEnable);
1699
1700         ethtool_cmd_speed_set(cmd, SPEED_1000);
1701         cmd->duplex = DUPLEX_FULL; /* Always set */
1702
1703         return 0;
1704 }
1705
1706 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1707 {
1708         struct rtl8169_private *tp = netdev_priv(dev);
1709
1710         return mii_ethtool_gset(&tp->mii, cmd);
1711 }
1712
1713 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1714 {
1715         struct rtl8169_private *tp = netdev_priv(dev);
1716         int rc;
1717
1718         rtl_lock_work(tp);
1719         rc = tp->get_settings(dev, cmd);
1720         rtl_unlock_work(tp);
1721
1722         return rc;
1723 }
1724
1725 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1726                              void *p)
1727 {
1728         struct rtl8169_private *tp = netdev_priv(dev);
1729
1730         if (regs->len > R8169_REGS_SIZE)
1731                 regs->len = R8169_REGS_SIZE;
1732
1733         rtl_lock_work(tp);
1734         memcpy_fromio(p, tp->mmio_addr, regs->len);
1735         rtl_unlock_work(tp);
1736 }
1737
1738 static u32 rtl8169_get_msglevel(struct net_device *dev)
1739 {
1740         struct rtl8169_private *tp = netdev_priv(dev);
1741
1742         return tp->msg_enable;
1743 }
1744
1745 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1746 {
1747         struct rtl8169_private *tp = netdev_priv(dev);
1748
1749         tp->msg_enable = value;
1750 }
1751
1752 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1753         "tx_packets",
1754         "rx_packets",
1755         "tx_errors",
1756         "rx_errors",
1757         "rx_missed",
1758         "align_errors",
1759         "tx_single_collisions",
1760         "tx_multi_collisions",
1761         "unicast",
1762         "broadcast",
1763         "multicast",
1764         "tx_aborted",
1765         "tx_underrun",
1766 };
1767
1768 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1769 {
1770         switch (sset) {
1771         case ETH_SS_STATS:
1772                 return ARRAY_SIZE(rtl8169_gstrings);
1773         default:
1774                 return -EOPNOTSUPP;
1775         }
1776 }
1777
1778 static void rtl8169_update_counters(struct net_device *dev)
1779 {
1780         struct rtl8169_private *tp = netdev_priv(dev);
1781         void __iomem *ioaddr = tp->mmio_addr;
1782         struct device *d = &tp->pci_dev->dev;
1783         struct rtl8169_counters *counters;
1784         dma_addr_t paddr;
1785         u32 cmd;
1786         int wait = 1000;
1787
1788         /*
1789          * Some chips are unable to dump tally counters when the receiver
1790          * is disabled.
1791          */
1792         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1793                 return;
1794
1795         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1796         if (!counters)
1797                 return;
1798
1799         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1800         cmd = (u64)paddr & DMA_BIT_MASK(32);
1801         RTL_W32(CounterAddrLow, cmd);
1802         RTL_W32(CounterAddrLow, cmd | CounterDump);
1803
1804         while (wait--) {
1805                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1806                         memcpy(&tp->counters, counters, sizeof(*counters));
1807                         break;
1808                 }
1809                 udelay(10);
1810         }
1811
1812         RTL_W32(CounterAddrLow, 0);
1813         RTL_W32(CounterAddrHigh, 0);
1814
1815         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1816 }
1817
1818 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1819                                       struct ethtool_stats *stats, u64 *data)
1820 {
1821         struct rtl8169_private *tp = netdev_priv(dev);
1822
1823         ASSERT_RTNL();
1824
1825         rtl8169_update_counters(dev);
1826
1827         data[0] = le64_to_cpu(tp->counters.tx_packets);
1828         data[1] = le64_to_cpu(tp->counters.rx_packets);
1829         data[2] = le64_to_cpu(tp->counters.tx_errors);
1830         data[3] = le32_to_cpu(tp->counters.rx_errors);
1831         data[4] = le16_to_cpu(tp->counters.rx_missed);
1832         data[5] = le16_to_cpu(tp->counters.align_errors);
1833         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1834         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1835         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1836         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1837         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1838         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1839         data[12] = le16_to_cpu(tp->counters.tx_underun);
1840 }
1841
1842 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1843 {
1844         switch(stringset) {
1845         case ETH_SS_STATS:
1846                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1847                 break;
1848         }
1849 }
1850
1851 static const struct ethtool_ops rtl8169_ethtool_ops = {
1852         .get_drvinfo            = rtl8169_get_drvinfo,
1853         .get_regs_len           = rtl8169_get_regs_len,
1854         .get_link               = ethtool_op_get_link,
1855         .get_settings           = rtl8169_get_settings,
1856         .set_settings           = rtl8169_set_settings,
1857         .get_msglevel           = rtl8169_get_msglevel,
1858         .set_msglevel           = rtl8169_set_msglevel,
1859         .get_regs               = rtl8169_get_regs,
1860         .get_wol                = rtl8169_get_wol,
1861         .set_wol                = rtl8169_set_wol,
1862         .get_strings            = rtl8169_get_strings,
1863         .get_sset_count         = rtl8169_get_sset_count,
1864         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1865 };
1866
1867 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1868                                     struct net_device *dev, u8 default_version)
1869 {
1870         void __iomem *ioaddr = tp->mmio_addr;
1871         /*
1872          * The driver currently handles the 8168Bf and the 8168Be identically
1873          * but they can be identified more specifically through the test below
1874          * if needed:
1875          *
1876          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1877          *
1878          * Same thing for the 8101Eb and the 8101Ec:
1879          *
1880          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1881          */
1882         static const struct rtl_mac_info {
1883                 u32 mask;
1884                 u32 val;
1885                 int mac_version;
1886         } mac_info[] = {
1887                 /* 8168F family. */
1888                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1889                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1890
1891                 /* 8168E family. */
1892                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1893                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1894                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1895                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1896
1897                 /* 8168D family. */
1898                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1899                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1900                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1901
1902                 /* 8168DP family. */
1903                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1904                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1905                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1906
1907                 /* 8168C family. */
1908                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1909                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1910                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1911                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1912                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1913                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1914                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1915                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1916                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1917
1918                 /* 8168B family. */
1919                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1920                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1921                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1922                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1923
1924                 /* 8101 family. */
1925                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1926                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1927                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1928                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1929                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1930                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1931                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1932                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1933                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1934                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1935                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1936                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1937                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1938                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1939                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1940                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1941                 /* FIXME: where did these entries come from ? -- FR */
1942                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1943                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1944
1945                 /* 8110 family. */
1946                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1947                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1948                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1949                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1950                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1951                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1952
1953                 /* Catch-all */
1954                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1955         };
1956         const struct rtl_mac_info *p = mac_info;
1957         u32 reg;
1958
1959         reg = RTL_R32(TxConfig);
1960         while ((reg & p->mask) != p->val)
1961                 p++;
1962         tp->mac_version = p->mac_version;
1963
1964         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1965                 netif_notice(tp, probe, dev,
1966                              "unknown MAC, using family default\n");
1967                 tp->mac_version = default_version;
1968         }
1969 }
1970
1971 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1972 {
1973         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1974 }
1975
1976 struct phy_reg {
1977         u16 reg;
1978         u16 val;
1979 };
1980
1981 static void rtl_writephy_batch(struct rtl8169_private *tp,
1982                                const struct phy_reg *regs, int len)
1983 {
1984         while (len-- > 0) {
1985                 rtl_writephy(tp, regs->reg, regs->val);
1986                 regs++;
1987         }
1988 }
1989
1990 #define PHY_READ                0x00000000
1991 #define PHY_DATA_OR             0x10000000
1992 #define PHY_DATA_AND            0x20000000
1993 #define PHY_BJMPN               0x30000000
1994 #define PHY_READ_EFUSE          0x40000000
1995 #define PHY_READ_MAC_BYTE       0x50000000
1996 #define PHY_WRITE_MAC_BYTE      0x60000000
1997 #define PHY_CLEAR_READCOUNT     0x70000000
1998 #define PHY_WRITE               0x80000000
1999 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2000 #define PHY_COMP_EQ_SKIPN       0xa0000000
2001 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2002 #define PHY_WRITE_PREVIOUS      0xc0000000
2003 #define PHY_SKIPN               0xd0000000
2004 #define PHY_DELAY_MS            0xe0000000
2005 #define PHY_WRITE_ERI_WORD      0xf0000000
2006
2007 struct fw_info {
2008         u32     magic;
2009         char    version[RTL_VER_SIZE];
2010         __le32  fw_start;
2011         __le32  fw_len;
2012         u8      chksum;
2013 } __packed;
2014
2015 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2016
2017 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2018 {
2019         const struct firmware *fw = rtl_fw->fw;
2020         struct fw_info *fw_info = (struct fw_info *)fw->data;
2021         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2022         char *version = rtl_fw->version;
2023         bool rc = false;
2024
2025         if (fw->size < FW_OPCODE_SIZE)
2026                 goto out;
2027
2028         if (!fw_info->magic) {
2029                 size_t i, size, start;
2030                 u8 checksum = 0;
2031
2032                 if (fw->size < sizeof(*fw_info))
2033                         goto out;
2034
2035                 for (i = 0; i < fw->size; i++)
2036                         checksum += fw->data[i];
2037                 if (checksum != 0)
2038                         goto out;
2039
2040                 start = le32_to_cpu(fw_info->fw_start);
2041                 if (start > fw->size)
2042                         goto out;
2043
2044                 size = le32_to_cpu(fw_info->fw_len);
2045                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2046                         goto out;
2047
2048                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2049
2050                 pa->code = (__le32 *)(fw->data + start);
2051                 pa->size = size;
2052         } else {
2053                 if (fw->size % FW_OPCODE_SIZE)
2054                         goto out;
2055
2056                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2057
2058                 pa->code = (__le32 *)fw->data;
2059                 pa->size = fw->size / FW_OPCODE_SIZE;
2060         }
2061         version[RTL_VER_SIZE - 1] = 0;
2062
2063         rc = true;
2064 out:
2065         return rc;
2066 }
2067
2068 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2069                            struct rtl_fw_phy_action *pa)
2070 {
2071         bool rc = false;
2072         size_t index;
2073
2074         for (index = 0; index < pa->size; index++) {
2075                 u32 action = le32_to_cpu(pa->code[index]);
2076                 u32 regno = (action & 0x0fff0000) >> 16;
2077
2078                 switch(action & 0xf0000000) {
2079                 case PHY_READ:
2080                 case PHY_DATA_OR:
2081                 case PHY_DATA_AND:
2082                 case PHY_READ_EFUSE:
2083                 case PHY_CLEAR_READCOUNT:
2084                 case PHY_WRITE:
2085                 case PHY_WRITE_PREVIOUS:
2086                 case PHY_DELAY_MS:
2087                         break;
2088
2089                 case PHY_BJMPN:
2090                         if (regno > index) {
2091                                 netif_err(tp, ifup, tp->dev,
2092                                           "Out of range of firmware\n");
2093                                 goto out;
2094                         }
2095                         break;
2096                 case PHY_READCOUNT_EQ_SKIP:
2097                         if (index + 2 >= pa->size) {
2098                                 netif_err(tp, ifup, tp->dev,
2099                                           "Out of range of firmware\n");
2100                                 goto out;
2101                         }
2102                         break;
2103                 case PHY_COMP_EQ_SKIPN:
2104                 case PHY_COMP_NEQ_SKIPN:
2105                 case PHY_SKIPN:
2106                         if (index + 1 + regno >= pa->size) {
2107                                 netif_err(tp, ifup, tp->dev,
2108                                           "Out of range of firmware\n");
2109                                 goto out;
2110                         }
2111                         break;
2112
2113                 case PHY_READ_MAC_BYTE:
2114                 case PHY_WRITE_MAC_BYTE:
2115                 case PHY_WRITE_ERI_WORD:
2116                 default:
2117                         netif_err(tp, ifup, tp->dev,
2118                                   "Invalid action 0x%08x\n", action);
2119                         goto out;
2120                 }
2121         }
2122         rc = true;
2123 out:
2124         return rc;
2125 }
2126
2127 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2128 {
2129         struct net_device *dev = tp->dev;
2130         int rc = -EINVAL;
2131
2132         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2133                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2134                 goto out;
2135         }
2136
2137         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2138                 rc = 0;
2139 out:
2140         return rc;
2141 }
2142
2143 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2144 {
2145         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2146         u32 predata, count;
2147         size_t index;
2148
2149         predata = count = 0;
2150
2151         for (index = 0; index < pa->size; ) {
2152                 u32 action = le32_to_cpu(pa->code[index]);
2153                 u32 data = action & 0x0000ffff;
2154                 u32 regno = (action & 0x0fff0000) >> 16;
2155
2156                 if (!action)
2157                         break;
2158
2159                 switch(action & 0xf0000000) {
2160                 case PHY_READ:
2161                         predata = rtl_readphy(tp, regno);
2162                         count++;
2163                         index++;
2164                         break;
2165                 case PHY_DATA_OR:
2166                         predata |= data;
2167                         index++;
2168                         break;
2169                 case PHY_DATA_AND:
2170                         predata &= data;
2171                         index++;
2172                         break;
2173                 case PHY_BJMPN:
2174                         index -= regno;
2175                         break;
2176                 case PHY_READ_EFUSE:
2177                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2178                         index++;
2179                         break;
2180                 case PHY_CLEAR_READCOUNT:
2181                         count = 0;
2182                         index++;
2183                         break;
2184                 case PHY_WRITE:
2185                         rtl_writephy(tp, regno, data);
2186                         index++;
2187                         break;
2188                 case PHY_READCOUNT_EQ_SKIP:
2189                         index += (count == data) ? 2 : 1;
2190                         break;
2191                 case PHY_COMP_EQ_SKIPN:
2192                         if (predata == data)
2193                                 index += regno;
2194                         index++;
2195                         break;
2196                 case PHY_COMP_NEQ_SKIPN:
2197                         if (predata != data)
2198                                 index += regno;
2199                         index++;
2200                         break;
2201                 case PHY_WRITE_PREVIOUS:
2202                         rtl_writephy(tp, regno, predata);
2203                         index++;
2204                         break;
2205                 case PHY_SKIPN:
2206                         index += regno + 1;
2207                         break;
2208                 case PHY_DELAY_MS:
2209                         mdelay(data);
2210                         index++;
2211                         break;
2212
2213                 case PHY_READ_MAC_BYTE:
2214                 case PHY_WRITE_MAC_BYTE:
2215                 case PHY_WRITE_ERI_WORD:
2216                 default:
2217                         BUG();
2218                 }
2219         }
2220 }
2221
2222 static void rtl_release_firmware(struct rtl8169_private *tp)
2223 {
2224         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2225                 release_firmware(tp->rtl_fw->fw);
2226                 kfree(tp->rtl_fw);
2227         }
2228         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2229 }
2230
2231 static void rtl_apply_firmware(struct rtl8169_private *tp)
2232 {
2233         struct rtl_fw *rtl_fw = tp->rtl_fw;
2234
2235         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2236         if (!IS_ERR_OR_NULL(rtl_fw))
2237                 rtl_phy_write_fw(tp, rtl_fw);
2238 }
2239
2240 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2241 {
2242         if (rtl_readphy(tp, reg) != val)
2243                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2244         else
2245                 rtl_apply_firmware(tp);
2246 }
2247
2248 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2249 {
2250         static const struct phy_reg phy_reg_init[] = {
2251                 { 0x1f, 0x0001 },
2252                 { 0x06, 0x006e },
2253                 { 0x08, 0x0708 },
2254                 { 0x15, 0x4000 },
2255                 { 0x18, 0x65c7 },
2256
2257                 { 0x1f, 0x0001 },
2258                 { 0x03, 0x00a1 },
2259                 { 0x02, 0x0008 },
2260                 { 0x01, 0x0120 },
2261                 { 0x00, 0x1000 },
2262                 { 0x04, 0x0800 },
2263                 { 0x04, 0x0000 },
2264
2265                 { 0x03, 0xff41 },
2266                 { 0x02, 0xdf60 },
2267                 { 0x01, 0x0140 },
2268                 { 0x00, 0x0077 },
2269                 { 0x04, 0x7800 },
2270                 { 0x04, 0x7000 },
2271
2272                 { 0x03, 0x802f },
2273                 { 0x02, 0x4f02 },
2274                 { 0x01, 0x0409 },
2275                 { 0x00, 0xf0f9 },
2276                 { 0x04, 0x9800 },
2277                 { 0x04, 0x9000 },
2278
2279                 { 0x03, 0xdf01 },
2280                 { 0x02, 0xdf20 },
2281                 { 0x01, 0xff95 },
2282                 { 0x00, 0xba00 },
2283                 { 0x04, 0xa800 },
2284                 { 0x04, 0xa000 },
2285
2286                 { 0x03, 0xff41 },
2287                 { 0x02, 0xdf20 },
2288                 { 0x01, 0x0140 },
2289                 { 0x00, 0x00bb },
2290                 { 0x04, 0xb800 },
2291                 { 0x04, 0xb000 },
2292
2293                 { 0x03, 0xdf41 },
2294                 { 0x02, 0xdc60 },
2295                 { 0x01, 0x6340 },
2296                 { 0x00, 0x007d },
2297                 { 0x04, 0xd800 },
2298                 { 0x04, 0xd000 },
2299
2300                 { 0x03, 0xdf01 },
2301                 { 0x02, 0xdf20 },
2302                 { 0x01, 0x100a },
2303                 { 0x00, 0xa0ff },
2304                 { 0x04, 0xf800 },
2305                 { 0x04, 0xf000 },
2306
2307                 { 0x1f, 0x0000 },
2308                 { 0x0b, 0x0000 },
2309                 { 0x00, 0x9200 }
2310         };
2311
2312         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2313 }
2314
2315 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2316 {
2317         static const struct phy_reg phy_reg_init[] = {
2318                 { 0x1f, 0x0002 },
2319                 { 0x01, 0x90d0 },
2320                 { 0x1f, 0x0000 }
2321         };
2322
2323         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2324 }
2325
2326 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2327 {
2328         struct pci_dev *pdev = tp->pci_dev;
2329
2330         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2331             (pdev->subsystem_device != 0xe000))
2332                 return;
2333
2334         rtl_writephy(tp, 0x1f, 0x0001);
2335         rtl_writephy(tp, 0x10, 0xf01b);
2336         rtl_writephy(tp, 0x1f, 0x0000);
2337 }
2338
2339 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2340 {
2341         static const struct phy_reg phy_reg_init[] = {
2342                 { 0x1f, 0x0001 },
2343                 { 0x04, 0x0000 },
2344                 { 0x03, 0x00a1 },
2345                 { 0x02, 0x0008 },
2346                 { 0x01, 0x0120 },
2347                 { 0x00, 0x1000 },
2348                 { 0x04, 0x0800 },
2349                 { 0x04, 0x9000 },
2350                 { 0x03, 0x802f },
2351                 { 0x02, 0x4f02 },
2352                 { 0x01, 0x0409 },
2353                 { 0x00, 0xf099 },
2354                 { 0x04, 0x9800 },
2355                 { 0x04, 0xa000 },
2356                 { 0x03, 0xdf01 },
2357                 { 0x02, 0xdf20 },
2358                 { 0x01, 0xff95 },
2359                 { 0x00, 0xba00 },
2360                 { 0x04, 0xa800 },
2361                 { 0x04, 0xf000 },
2362                 { 0x03, 0xdf01 },
2363                 { 0x02, 0xdf20 },
2364                 { 0x01, 0x101a },
2365                 { 0x00, 0xa0ff },
2366                 { 0x04, 0xf800 },
2367                 { 0x04, 0x0000 },
2368                 { 0x1f, 0x0000 },
2369
2370                 { 0x1f, 0x0001 },
2371                 { 0x10, 0xf41b },
2372                 { 0x14, 0xfb54 },
2373                 { 0x18, 0xf5c7 },
2374                 { 0x1f, 0x0000 },
2375
2376                 { 0x1f, 0x0001 },
2377                 { 0x17, 0x0cc0 },
2378                 { 0x1f, 0x0000 }
2379         };
2380
2381         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2382
2383         rtl8169scd_hw_phy_config_quirk(tp);
2384 }
2385
2386 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2387 {
2388         static const struct phy_reg phy_reg_init[] = {
2389                 { 0x1f, 0x0001 },
2390                 { 0x04, 0x0000 },
2391                 { 0x03, 0x00a1 },
2392                 { 0x02, 0x0008 },
2393                 { 0x01, 0x0120 },
2394                 { 0x00, 0x1000 },
2395                 { 0x04, 0x0800 },
2396                 { 0x04, 0x9000 },
2397                 { 0x03, 0x802f },
2398                 { 0x02, 0x4f02 },
2399                 { 0x01, 0x0409 },
2400                 { 0x00, 0xf099 },
2401                 { 0x04, 0x9800 },
2402                 { 0x04, 0xa000 },
2403                 { 0x03, 0xdf01 },
2404                 { 0x02, 0xdf20 },
2405                 { 0x01, 0xff95 },
2406                 { 0x00, 0xba00 },
2407                 { 0x04, 0xa800 },
2408                 { 0x04, 0xf000 },
2409                 { 0x03, 0xdf01 },
2410                 { 0x02, 0xdf20 },
2411                 { 0x01, 0x101a },
2412                 { 0x00, 0xa0ff },
2413                 { 0x04, 0xf800 },
2414                 { 0x04, 0x0000 },
2415                 { 0x1f, 0x0000 },
2416
2417                 { 0x1f, 0x0001 },
2418                 { 0x0b, 0x8480 },
2419                 { 0x1f, 0x0000 },
2420
2421                 { 0x1f, 0x0001 },
2422                 { 0x18, 0x67c7 },
2423                 { 0x04, 0x2000 },
2424                 { 0x03, 0x002f },
2425                 { 0x02, 0x4360 },
2426                 { 0x01, 0x0109 },
2427                 { 0x00, 0x3022 },
2428                 { 0x04, 0x2800 },
2429                 { 0x1f, 0x0000 },
2430
2431                 { 0x1f, 0x0001 },
2432                 { 0x17, 0x0cc0 },
2433                 { 0x1f, 0x0000 }
2434         };
2435
2436         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2437 }
2438
2439 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2440 {
2441         static const struct phy_reg phy_reg_init[] = {
2442                 { 0x10, 0xf41b },
2443                 { 0x1f, 0x0000 }
2444         };
2445
2446         rtl_writephy(tp, 0x1f, 0x0001);
2447         rtl_patchphy(tp, 0x16, 1 << 0);
2448
2449         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2450 }
2451
2452 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2453 {
2454         static const struct phy_reg phy_reg_init[] = {
2455                 { 0x1f, 0x0001 },
2456                 { 0x10, 0xf41b },
2457                 { 0x1f, 0x0000 }
2458         };
2459
2460         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2461 }
2462
2463 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2464 {
2465         static const struct phy_reg phy_reg_init[] = {
2466                 { 0x1f, 0x0000 },
2467                 { 0x1d, 0x0f00 },
2468                 { 0x1f, 0x0002 },
2469                 { 0x0c, 0x1ec8 },
2470                 { 0x1f, 0x0000 }
2471         };
2472
2473         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2474 }
2475
2476 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2477 {
2478         static const struct phy_reg phy_reg_init[] = {
2479                 { 0x1f, 0x0001 },
2480                 { 0x1d, 0x3d98 },
2481                 { 0x1f, 0x0000 }
2482         };
2483
2484         rtl_writephy(tp, 0x1f, 0x0000);
2485         rtl_patchphy(tp, 0x14, 1 << 5);
2486         rtl_patchphy(tp, 0x0d, 1 << 5);
2487
2488         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2489 }
2490
2491 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2492 {
2493         static const struct phy_reg phy_reg_init[] = {
2494                 { 0x1f, 0x0001 },
2495                 { 0x12, 0x2300 },
2496                 { 0x1f, 0x0002 },
2497                 { 0x00, 0x88d4 },
2498                 { 0x01, 0x82b1 },
2499                 { 0x03, 0x7002 },
2500                 { 0x08, 0x9e30 },
2501                 { 0x09, 0x01f0 },
2502                 { 0x0a, 0x5500 },
2503                 { 0x0c, 0x00c8 },
2504                 { 0x1f, 0x0003 },
2505                 { 0x12, 0xc096 },
2506                 { 0x16, 0x000a },
2507                 { 0x1f, 0x0000 },
2508                 { 0x1f, 0x0000 },
2509                 { 0x09, 0x2000 },
2510                 { 0x09, 0x0000 }
2511         };
2512
2513         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514
2515         rtl_patchphy(tp, 0x14, 1 << 5);
2516         rtl_patchphy(tp, 0x0d, 1 << 5);
2517         rtl_writephy(tp, 0x1f, 0x0000);
2518 }
2519
2520 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2521 {
2522         static const struct phy_reg phy_reg_init[] = {
2523                 { 0x1f, 0x0001 },
2524                 { 0x12, 0x2300 },
2525                 { 0x03, 0x802f },
2526                 { 0x02, 0x4f02 },
2527                 { 0x01, 0x0409 },
2528                 { 0x00, 0xf099 },
2529                 { 0x04, 0x9800 },
2530                 { 0x04, 0x9000 },
2531                 { 0x1d, 0x3d98 },
2532                 { 0x1f, 0x0002 },
2533                 { 0x0c, 0x7eb8 },
2534                 { 0x06, 0x0761 },
2535                 { 0x1f, 0x0003 },
2536                 { 0x16, 0x0f0a },
2537                 { 0x1f, 0x0000 }
2538         };
2539
2540         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2541
2542         rtl_patchphy(tp, 0x16, 1 << 0);
2543         rtl_patchphy(tp, 0x14, 1 << 5);
2544         rtl_patchphy(tp, 0x0d, 1 << 5);
2545         rtl_writephy(tp, 0x1f, 0x0000);
2546 }
2547
2548 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2549 {
2550         static const struct phy_reg phy_reg_init[] = {
2551                 { 0x1f, 0x0001 },
2552                 { 0x12, 0x2300 },
2553                 { 0x1d, 0x3d98 },
2554                 { 0x1f, 0x0002 },
2555                 { 0x0c, 0x7eb8 },
2556                 { 0x06, 0x5461 },
2557                 { 0x1f, 0x0003 },
2558                 { 0x16, 0x0f0a },
2559                 { 0x1f, 0x0000 }
2560         };
2561
2562         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2563
2564         rtl_patchphy(tp, 0x16, 1 << 0);
2565         rtl_patchphy(tp, 0x14, 1 << 5);
2566         rtl_patchphy(tp, 0x0d, 1 << 5);
2567         rtl_writephy(tp, 0x1f, 0x0000);
2568 }
2569
2570 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572         rtl8168c_3_hw_phy_config(tp);
2573 }
2574
2575 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2576 {
2577         static const struct phy_reg phy_reg_init_0[] = {
2578                 /* Channel Estimation */
2579                 { 0x1f, 0x0001 },
2580                 { 0x06, 0x4064 },
2581                 { 0x07, 0x2863 },
2582                 { 0x08, 0x059c },
2583                 { 0x09, 0x26b4 },
2584                 { 0x0a, 0x6a19 },
2585                 { 0x0b, 0xdcc8 },
2586                 { 0x10, 0xf06d },
2587                 { 0x14, 0x7f68 },
2588                 { 0x18, 0x7fd9 },
2589                 { 0x1c, 0xf0ff },
2590                 { 0x1d, 0x3d9c },
2591                 { 0x1f, 0x0003 },
2592                 { 0x12, 0xf49f },
2593                 { 0x13, 0x070b },
2594                 { 0x1a, 0x05ad },
2595                 { 0x14, 0x94c0 },
2596
2597                 /*
2598                  * Tx Error Issue
2599                  * Enhance line driver power
2600                  */
2601                 { 0x1f, 0x0002 },
2602                 { 0x06, 0x5561 },
2603                 { 0x1f, 0x0005 },
2604                 { 0x05, 0x8332 },
2605                 { 0x06, 0x5561 },
2606
2607                 /*
2608                  * Can not link to 1Gbps with bad cable
2609                  * Decrease SNR threshold form 21.07dB to 19.04dB
2610                  */
2611                 { 0x1f, 0x0001 },
2612                 { 0x17, 0x0cc0 },
2613
2614                 { 0x1f, 0x0000 },
2615                 { 0x0d, 0xf880 }
2616         };
2617         void __iomem *ioaddr = tp->mmio_addr;
2618
2619         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2620
2621         /*
2622          * Rx Error Issue
2623          * Fine Tune Switching regulator parameter
2624          */
2625         rtl_writephy(tp, 0x1f, 0x0002);
2626         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2627         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2628
2629         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2630                 static const struct phy_reg phy_reg_init[] = {
2631                         { 0x1f, 0x0002 },
2632                         { 0x05, 0x669a },
2633                         { 0x1f, 0x0005 },
2634                         { 0x05, 0x8330 },
2635                         { 0x06, 0x669a },
2636                         { 0x1f, 0x0002 }
2637                 };
2638                 int val;
2639
2640                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2641
2642                 val = rtl_readphy(tp, 0x0d);
2643
2644                 if ((val & 0x00ff) != 0x006c) {
2645                         static const u32 set[] = {
2646                                 0x0065, 0x0066, 0x0067, 0x0068,
2647                                 0x0069, 0x006a, 0x006b, 0x006c
2648                         };
2649                         int i;
2650
2651                         rtl_writephy(tp, 0x1f, 0x0002);
2652
2653                         val &= 0xff00;
2654                         for (i = 0; i < ARRAY_SIZE(set); i++)
2655                                 rtl_writephy(tp, 0x0d, val | set[i]);
2656                 }
2657         } else {
2658                 static const struct phy_reg phy_reg_init[] = {
2659                         { 0x1f, 0x0002 },
2660                         { 0x05, 0x6662 },
2661                         { 0x1f, 0x0005 },
2662                         { 0x05, 0x8330 },
2663                         { 0x06, 0x6662 }
2664                 };
2665
2666                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2667         }
2668
2669         /* RSET couple improve */
2670         rtl_writephy(tp, 0x1f, 0x0002);
2671         rtl_patchphy(tp, 0x0d, 0x0300);
2672         rtl_patchphy(tp, 0x0f, 0x0010);
2673
2674         /* Fine tune PLL performance */
2675         rtl_writephy(tp, 0x1f, 0x0002);
2676         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2677         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2678
2679         rtl_writephy(tp, 0x1f, 0x0005);
2680         rtl_writephy(tp, 0x05, 0x001b);
2681
2682         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2683
2684         rtl_writephy(tp, 0x1f, 0x0000);
2685 }
2686
2687 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689         static const struct phy_reg phy_reg_init_0[] = {
2690                 /* Channel Estimation */
2691                 { 0x1f, 0x0001 },
2692                 { 0x06, 0x4064 },
2693                 { 0x07, 0x2863 },
2694                 { 0x08, 0x059c },
2695                 { 0x09, 0x26b4 },
2696                 { 0x0a, 0x6a19 },
2697                 { 0x0b, 0xdcc8 },
2698                 { 0x10, 0xf06d },
2699                 { 0x14, 0x7f68 },
2700                 { 0x18, 0x7fd9 },
2701                 { 0x1c, 0xf0ff },
2702                 { 0x1d, 0x3d9c },
2703                 { 0x1f, 0x0003 },
2704                 { 0x12, 0xf49f },
2705                 { 0x13, 0x070b },
2706                 { 0x1a, 0x05ad },
2707                 { 0x14, 0x94c0 },
2708
2709                 /*
2710                  * Tx Error Issue
2711                  * Enhance line driver power
2712                  */
2713                 { 0x1f, 0x0002 },
2714                 { 0x06, 0x5561 },
2715                 { 0x1f, 0x0005 },
2716                 { 0x05, 0x8332 },
2717                 { 0x06, 0x5561 },
2718
2719                 /*
2720                  * Can not link to 1Gbps with bad cable
2721                  * Decrease SNR threshold form 21.07dB to 19.04dB
2722                  */
2723                 { 0x1f, 0x0001 },
2724                 { 0x17, 0x0cc0 },
2725
2726                 { 0x1f, 0x0000 },
2727                 { 0x0d, 0xf880 }
2728         };
2729         void __iomem *ioaddr = tp->mmio_addr;
2730
2731         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2732
2733         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2734                 static const struct phy_reg phy_reg_init[] = {
2735                         { 0x1f, 0x0002 },
2736                         { 0x05, 0x669a },
2737                         { 0x1f, 0x0005 },
2738                         { 0x05, 0x8330 },
2739                         { 0x06, 0x669a },
2740
2741                         { 0x1f, 0x0002 }
2742                 };
2743                 int val;
2744
2745                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747                 val = rtl_readphy(tp, 0x0d);
2748                 if ((val & 0x00ff) != 0x006c) {
2749                         static const u32 set[] = {
2750                                 0x0065, 0x0066, 0x0067, 0x0068,
2751                                 0x0069, 0x006a, 0x006b, 0x006c
2752                         };
2753                         int i;
2754
2755                         rtl_writephy(tp, 0x1f, 0x0002);
2756
2757                         val &= 0xff00;
2758                         for (i = 0; i < ARRAY_SIZE(set); i++)
2759                                 rtl_writephy(tp, 0x0d, val | set[i]);
2760                 }
2761         } else {
2762                 static const struct phy_reg phy_reg_init[] = {
2763                         { 0x1f, 0x0002 },
2764                         { 0x05, 0x2642 },
2765                         { 0x1f, 0x0005 },
2766                         { 0x05, 0x8330 },
2767                         { 0x06, 0x2642 }
2768                 };
2769
2770                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2771         }
2772
2773         /* Fine tune PLL performance */
2774         rtl_writephy(tp, 0x1f, 0x0002);
2775         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2776         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2777
2778         /* Switching regulator Slew rate */
2779         rtl_writephy(tp, 0x1f, 0x0002);
2780         rtl_patchphy(tp, 0x0f, 0x0017);
2781
2782         rtl_writephy(tp, 0x1f, 0x0005);
2783         rtl_writephy(tp, 0x05, 0x001b);
2784
2785         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2786
2787         rtl_writephy(tp, 0x1f, 0x0000);
2788 }
2789
2790 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2791 {
2792         static const struct phy_reg phy_reg_init[] = {
2793                 { 0x1f, 0x0002 },
2794                 { 0x10, 0x0008 },
2795                 { 0x0d, 0x006c },
2796
2797                 { 0x1f, 0x0000 },
2798                 { 0x0d, 0xf880 },
2799
2800                 { 0x1f, 0x0001 },
2801                 { 0x17, 0x0cc0 },
2802
2803                 { 0x1f, 0x0001 },
2804                 { 0x0b, 0xa4d8 },
2805                 { 0x09, 0x281c },
2806                 { 0x07, 0x2883 },
2807                 { 0x0a, 0x6b35 },
2808                 { 0x1d, 0x3da4 },
2809                 { 0x1c, 0xeffd },
2810                 { 0x14, 0x7f52 },
2811                 { 0x18, 0x7fc6 },
2812                 { 0x08, 0x0601 },
2813                 { 0x06, 0x4063 },
2814                 { 0x10, 0xf074 },
2815                 { 0x1f, 0x0003 },
2816                 { 0x13, 0x0789 },
2817                 { 0x12, 0xf4bd },
2818                 { 0x1a, 0x04fd },
2819                 { 0x14, 0x84b0 },
2820                 { 0x1f, 0x0000 },
2821                 { 0x00, 0x9200 },
2822
2823                 { 0x1f, 0x0005 },
2824                 { 0x01, 0x0340 },
2825                 { 0x1f, 0x0001 },
2826                 { 0x04, 0x4000 },
2827                 { 0x03, 0x1d21 },
2828                 { 0x02, 0x0c32 },
2829                 { 0x01, 0x0200 },
2830                 { 0x00, 0x5554 },
2831                 { 0x04, 0x4800 },
2832                 { 0x04, 0x4000 },
2833                 { 0x04, 0xf000 },
2834                 { 0x03, 0xdf01 },
2835                 { 0x02, 0xdf20 },
2836                 { 0x01, 0x101a },
2837                 { 0x00, 0xa0ff },
2838                 { 0x04, 0xf800 },
2839                 { 0x04, 0xf000 },
2840                 { 0x1f, 0x0000 },
2841
2842                 { 0x1f, 0x0007 },
2843                 { 0x1e, 0x0023 },
2844                 { 0x16, 0x0000 },
2845                 { 0x1f, 0x0000 }
2846         };
2847
2848         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2849 }
2850
2851 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2852 {
2853         static const struct phy_reg phy_reg_init[] = {
2854                 { 0x1f, 0x0001 },
2855                 { 0x17, 0x0cc0 },
2856
2857                 { 0x1f, 0x0007 },
2858                 { 0x1e, 0x002d },
2859                 { 0x18, 0x0040 },
2860                 { 0x1f, 0x0000 }
2861         };
2862
2863         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2864         rtl_patchphy(tp, 0x0d, 1 << 5);
2865 }
2866
2867 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2868 {
2869         static const struct phy_reg phy_reg_init[] = {
2870                 /* Enable Delay cap */
2871                 { 0x1f, 0x0005 },
2872                 { 0x05, 0x8b80 },
2873                 { 0x06, 0xc896 },
2874                 { 0x1f, 0x0000 },
2875
2876                 /* Channel estimation fine tune */
2877                 { 0x1f, 0x0001 },
2878                 { 0x0b, 0x6c20 },
2879                 { 0x07, 0x2872 },
2880                 { 0x1c, 0xefff },
2881                 { 0x1f, 0x0003 },
2882                 { 0x14, 0x6420 },
2883                 { 0x1f, 0x0000 },
2884
2885                 /* Update PFM & 10M TX idle timer */
2886                 { 0x1f, 0x0007 },
2887                 { 0x1e, 0x002f },
2888                 { 0x15, 0x1919 },
2889                 { 0x1f, 0x0000 },
2890
2891                 { 0x1f, 0x0007 },
2892                 { 0x1e, 0x00ac },
2893                 { 0x18, 0x0006 },
2894                 { 0x1f, 0x0000 }
2895         };
2896
2897         rtl_apply_firmware(tp);
2898
2899         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2900
2901         /* DCO enable for 10M IDLE Power */
2902         rtl_writephy(tp, 0x1f, 0x0007);
2903         rtl_writephy(tp, 0x1e, 0x0023);
2904         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2905         rtl_writephy(tp, 0x1f, 0x0000);
2906
2907         /* For impedance matching */
2908         rtl_writephy(tp, 0x1f, 0x0002);
2909         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2910         rtl_writephy(tp, 0x1f, 0x0000);
2911
2912         /* PHY auto speed down */
2913         rtl_writephy(tp, 0x1f, 0x0007);
2914         rtl_writephy(tp, 0x1e, 0x002d);
2915         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2916         rtl_writephy(tp, 0x1f, 0x0000);
2917         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2918
2919         rtl_writephy(tp, 0x1f, 0x0005);
2920         rtl_writephy(tp, 0x05, 0x8b86);
2921         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2922         rtl_writephy(tp, 0x1f, 0x0000);
2923
2924         rtl_writephy(tp, 0x1f, 0x0005);
2925         rtl_writephy(tp, 0x05, 0x8b85);
2926         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2927         rtl_writephy(tp, 0x1f, 0x0007);
2928         rtl_writephy(tp, 0x1e, 0x0020);
2929         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2930         rtl_writephy(tp, 0x1f, 0x0006);
2931         rtl_writephy(tp, 0x00, 0x5a00);
2932         rtl_writephy(tp, 0x1f, 0x0000);
2933         rtl_writephy(tp, 0x0d, 0x0007);
2934         rtl_writephy(tp, 0x0e, 0x003c);
2935         rtl_writephy(tp, 0x0d, 0x4007);
2936         rtl_writephy(tp, 0x0e, 0x0000);
2937         rtl_writephy(tp, 0x0d, 0x0000);
2938 }
2939
2940 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2941 {
2942         static const struct phy_reg phy_reg_init[] = {
2943                 /* Enable Delay cap */
2944                 { 0x1f, 0x0004 },
2945                 { 0x1f, 0x0007 },
2946                 { 0x1e, 0x00ac },
2947                 { 0x18, 0x0006 },
2948                 { 0x1f, 0x0002 },
2949                 { 0x1f, 0x0000 },
2950                 { 0x1f, 0x0000 },
2951
2952                 /* Channel estimation fine tune */
2953                 { 0x1f, 0x0003 },
2954                 { 0x09, 0xa20f },
2955                 { 0x1f, 0x0000 },
2956                 { 0x1f, 0x0000 },
2957
2958                 /* Green Setting */
2959                 { 0x1f, 0x0005 },
2960                 { 0x05, 0x8b5b },
2961                 { 0x06, 0x9222 },
2962                 { 0x05, 0x8b6d },
2963                 { 0x06, 0x8000 },
2964                 { 0x05, 0x8b76 },
2965                 { 0x06, 0x8000 },
2966                 { 0x1f, 0x0000 }
2967         };
2968
2969         rtl_apply_firmware(tp);
2970
2971         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2972
2973         /* For 4-corner performance improve */
2974         rtl_writephy(tp, 0x1f, 0x0005);
2975         rtl_writephy(tp, 0x05, 0x8b80);
2976         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2977         rtl_writephy(tp, 0x1f, 0x0000);
2978
2979         /* PHY auto speed down */
2980         rtl_writephy(tp, 0x1f, 0x0004);
2981         rtl_writephy(tp, 0x1f, 0x0007);
2982         rtl_writephy(tp, 0x1e, 0x002d);
2983         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2984         rtl_writephy(tp, 0x1f, 0x0002);
2985         rtl_writephy(tp, 0x1f, 0x0000);
2986         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2987
2988         /* improve 10M EEE waveform */
2989         rtl_writephy(tp, 0x1f, 0x0005);
2990         rtl_writephy(tp, 0x05, 0x8b86);
2991         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2992         rtl_writephy(tp, 0x1f, 0x0000);
2993
2994         /* Improve 2-pair detection performance */
2995         rtl_writephy(tp, 0x1f, 0x0005);
2996         rtl_writephy(tp, 0x05, 0x8b85);
2997         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2998         rtl_writephy(tp, 0x1f, 0x0000);
2999
3000         /* EEE setting */
3001         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3002                      ERIAR_EXGMAC);
3003         rtl_writephy(tp, 0x1f, 0x0005);
3004         rtl_writephy(tp, 0x05, 0x8b85);
3005         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3006         rtl_writephy(tp, 0x1f, 0x0004);
3007         rtl_writephy(tp, 0x1f, 0x0007);
3008         rtl_writephy(tp, 0x1e, 0x0020);
3009         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3010         rtl_writephy(tp, 0x1f, 0x0002);
3011         rtl_writephy(tp, 0x1f, 0x0000);
3012         rtl_writephy(tp, 0x0d, 0x0007);
3013         rtl_writephy(tp, 0x0e, 0x003c);
3014         rtl_writephy(tp, 0x0d, 0x4007);
3015         rtl_writephy(tp, 0x0e, 0x0000);
3016         rtl_writephy(tp, 0x0d, 0x0000);
3017
3018         /* Green feature */
3019         rtl_writephy(tp, 0x1f, 0x0003);
3020         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3021         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3022         rtl_writephy(tp, 0x1f, 0x0000);
3023 }
3024
3025 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3026 {
3027         static const struct phy_reg phy_reg_init[] = {
3028                 /* Channel estimation fine tune */
3029                 { 0x1f, 0x0003 },
3030                 { 0x09, 0xa20f },
3031                 { 0x1f, 0x0000 },
3032
3033                 /* Modify green table for giga & fnet */
3034                 { 0x1f, 0x0005 },
3035                 { 0x05, 0x8b55 },
3036                 { 0x06, 0x0000 },
3037                 { 0x05, 0x8b5e },
3038                 { 0x06, 0x0000 },
3039                 { 0x05, 0x8b67 },
3040                 { 0x06, 0x0000 },
3041                 { 0x05, 0x8b70 },
3042                 { 0x06, 0x0000 },
3043                 { 0x1f, 0x0000 },
3044                 { 0x1f, 0x0007 },
3045                 { 0x1e, 0x0078 },
3046                 { 0x17, 0x0000 },
3047                 { 0x19, 0x00fb },
3048                 { 0x1f, 0x0000 },
3049
3050                 /* Modify green table for 10M */
3051                 { 0x1f, 0x0005 },
3052                 { 0x05, 0x8b79 },
3053                 { 0x06, 0xaa00 },
3054                 { 0x1f, 0x0000 },
3055
3056                 /* Disable hiimpedance detection (RTCT) */
3057                 { 0x1f, 0x0003 },
3058                 { 0x01, 0x328a },
3059                 { 0x1f, 0x0000 }
3060         };
3061
3062         rtl_apply_firmware(tp);
3063
3064         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3065
3066         /* For 4-corner performance improve */
3067         rtl_writephy(tp, 0x1f, 0x0005);
3068         rtl_writephy(tp, 0x05, 0x8b80);
3069         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3070         rtl_writephy(tp, 0x1f, 0x0000);
3071
3072         /* PHY auto speed down */
3073         rtl_writephy(tp, 0x1f, 0x0007);
3074         rtl_writephy(tp, 0x1e, 0x002d);
3075         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3076         rtl_writephy(tp, 0x1f, 0x0000);
3077         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3078
3079         /* Improve 10M EEE waveform */
3080         rtl_writephy(tp, 0x1f, 0x0005);
3081         rtl_writephy(tp, 0x05, 0x8b86);
3082         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3083         rtl_writephy(tp, 0x1f, 0x0000);
3084
3085         /* Improve 2-pair detection performance */
3086         rtl_writephy(tp, 0x1f, 0x0005);
3087         rtl_writephy(tp, 0x05, 0x8b85);
3088         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3089         rtl_writephy(tp, 0x1f, 0x0000);
3090 }
3091
3092 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3093 {
3094         rtl_apply_firmware(tp);
3095
3096         /* For 4-corner performance improve */
3097         rtl_writephy(tp, 0x1f, 0x0005);
3098         rtl_writephy(tp, 0x05, 0x8b80);
3099         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3100         rtl_writephy(tp, 0x1f, 0x0000);
3101
3102         /* PHY auto speed down */
3103         rtl_writephy(tp, 0x1f, 0x0007);
3104         rtl_writephy(tp, 0x1e, 0x002d);
3105         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3106         rtl_writephy(tp, 0x1f, 0x0000);
3107         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3108
3109         /* Improve 10M EEE waveform */
3110         rtl_writephy(tp, 0x1f, 0x0005);
3111         rtl_writephy(tp, 0x05, 0x8b86);
3112         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114 }
3115
3116 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3117 {
3118         static const struct phy_reg phy_reg_init[] = {
3119                 { 0x1f, 0x0003 },
3120                 { 0x08, 0x441d },
3121                 { 0x01, 0x9100 },
3122                 { 0x1f, 0x0000 }
3123         };
3124
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126         rtl_patchphy(tp, 0x11, 1 << 12);
3127         rtl_patchphy(tp, 0x19, 1 << 13);
3128         rtl_patchphy(tp, 0x10, 1 << 15);
3129
3130         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3131 }
3132
3133 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3134 {
3135         static const struct phy_reg phy_reg_init[] = {
3136                 { 0x1f, 0x0005 },
3137                 { 0x1a, 0x0000 },
3138                 { 0x1f, 0x0000 },
3139
3140                 { 0x1f, 0x0004 },
3141                 { 0x1c, 0x0000 },
3142                 { 0x1f, 0x0000 },
3143
3144                 { 0x1f, 0x0001 },
3145                 { 0x15, 0x7701 },
3146                 { 0x1f, 0x0000 }
3147         };
3148
3149         /* Disable ALDPS before ram code */
3150         rtl_writephy(tp, 0x1f, 0x0000);
3151         rtl_writephy(tp, 0x18, 0x0310);
3152         msleep(100);
3153
3154         rtl_apply_firmware(tp);
3155
3156         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3157 }
3158
3159 static void rtl_hw_phy_config(struct net_device *dev)
3160 {
3161         struct rtl8169_private *tp = netdev_priv(dev);
3162
3163         rtl8169_print_mac_version(tp);
3164
3165         switch (tp->mac_version) {
3166         case RTL_GIGA_MAC_VER_01:
3167                 break;
3168         case RTL_GIGA_MAC_VER_02:
3169         case RTL_GIGA_MAC_VER_03:
3170                 rtl8169s_hw_phy_config(tp);
3171                 break;
3172         case RTL_GIGA_MAC_VER_04:
3173                 rtl8169sb_hw_phy_config(tp);
3174                 break;
3175         case RTL_GIGA_MAC_VER_05:
3176                 rtl8169scd_hw_phy_config(tp);
3177                 break;
3178         case RTL_GIGA_MAC_VER_06:
3179                 rtl8169sce_hw_phy_config(tp);
3180                 break;
3181         case RTL_GIGA_MAC_VER_07:
3182         case RTL_GIGA_MAC_VER_08:
3183         case RTL_GIGA_MAC_VER_09:
3184                 rtl8102e_hw_phy_config(tp);
3185                 break;
3186         case RTL_GIGA_MAC_VER_11:
3187                 rtl8168bb_hw_phy_config(tp);
3188                 break;
3189         case RTL_GIGA_MAC_VER_12:
3190                 rtl8168bef_hw_phy_config(tp);
3191                 break;
3192         case RTL_GIGA_MAC_VER_17:
3193                 rtl8168bef_hw_phy_config(tp);
3194                 break;
3195         case RTL_GIGA_MAC_VER_18:
3196                 rtl8168cp_1_hw_phy_config(tp);
3197                 break;
3198         case RTL_GIGA_MAC_VER_19:
3199                 rtl8168c_1_hw_phy_config(tp);
3200                 break;
3201         case RTL_GIGA_MAC_VER_20:
3202                 rtl8168c_2_hw_phy_config(tp);
3203                 break;
3204         case RTL_GIGA_MAC_VER_21:
3205                 rtl8168c_3_hw_phy_config(tp);
3206                 break;
3207         case RTL_GIGA_MAC_VER_22:
3208                 rtl8168c_4_hw_phy_config(tp);
3209                 break;
3210         case RTL_GIGA_MAC_VER_23:
3211         case RTL_GIGA_MAC_VER_24:
3212                 rtl8168cp_2_hw_phy_config(tp);
3213                 break;
3214         case RTL_GIGA_MAC_VER_25:
3215                 rtl8168d_1_hw_phy_config(tp);
3216                 break;
3217         case RTL_GIGA_MAC_VER_26:
3218                 rtl8168d_2_hw_phy_config(tp);
3219                 break;
3220         case RTL_GIGA_MAC_VER_27:
3221                 rtl8168d_3_hw_phy_config(tp);
3222                 break;
3223         case RTL_GIGA_MAC_VER_28:
3224                 rtl8168d_4_hw_phy_config(tp);
3225                 break;
3226         case RTL_GIGA_MAC_VER_29:
3227         case RTL_GIGA_MAC_VER_30:
3228                 rtl8105e_hw_phy_config(tp);
3229                 break;
3230         case RTL_GIGA_MAC_VER_31:
3231                 /* None. */
3232                 break;
3233         case RTL_GIGA_MAC_VER_32:
3234         case RTL_GIGA_MAC_VER_33:
3235                 rtl8168e_1_hw_phy_config(tp);
3236                 break;
3237         case RTL_GIGA_MAC_VER_34:
3238                 rtl8168e_2_hw_phy_config(tp);
3239                 break;
3240         case RTL_GIGA_MAC_VER_35:
3241                 rtl8168f_1_hw_phy_config(tp);
3242                 break;
3243         case RTL_GIGA_MAC_VER_36:
3244                 rtl8168f_2_hw_phy_config(tp);
3245                 break;
3246
3247         default:
3248                 break;
3249         }
3250 }
3251
3252 static void rtl_phy_work(struct rtl8169_private *tp)
3253 {
3254         struct timer_list *timer = &tp->timer;
3255         void __iomem *ioaddr = tp->mmio_addr;
3256         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3257
3258         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3259
3260         if (tp->phy_reset_pending(tp)) {
3261                 /*
3262                  * A busy loop could burn quite a few cycles on nowadays CPU.
3263                  * Let's delay the execution of the timer for a few ticks.
3264                  */
3265                 timeout = HZ/10;
3266                 goto out_mod_timer;
3267         }
3268
3269         if (tp->link_ok(ioaddr))
3270                 return;
3271
3272         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3273
3274         tp->phy_reset_enable(tp);
3275
3276 out_mod_timer:
3277         mod_timer(timer, jiffies + timeout);
3278 }
3279
3280 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3281 {
3282         if (!test_and_set_bit(flag, tp->wk.flags))
3283                 schedule_work(&tp->wk.work);
3284 }
3285
3286 static void rtl8169_phy_timer(unsigned long __opaque)
3287 {
3288         struct net_device *dev = (struct net_device *)__opaque;
3289         struct rtl8169_private *tp = netdev_priv(dev);
3290
3291         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3292 }
3293
3294 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3295                                   void __iomem *ioaddr)
3296 {
3297         iounmap(ioaddr);
3298         pci_release_regions(pdev);
3299         pci_clear_mwi(pdev);
3300         pci_disable_device(pdev);
3301         free_netdev(dev);
3302 }
3303
3304 static void rtl8169_phy_reset(struct net_device *dev,
3305                               struct rtl8169_private *tp)
3306 {
3307         unsigned int i;
3308
3309         tp->phy_reset_enable(tp);
3310         for (i = 0; i < 100; i++) {
3311                 if (!tp->phy_reset_pending(tp))
3312                         return;
3313                 msleep(1);
3314         }
3315         netif_err(tp, link, dev, "PHY reset failed\n");
3316 }
3317
3318 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3319 {
3320         void __iomem *ioaddr = tp->mmio_addr;
3321
3322         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3323             (RTL_R8(PHYstatus) & TBI_Enable);
3324 }
3325
3326 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3327 {
3328         void __iomem *ioaddr = tp->mmio_addr;
3329
3330         rtl_hw_phy_config(dev);
3331
3332         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3333                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3334                 RTL_W8(0x82, 0x01);
3335         }
3336
3337         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3338
3339         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3340                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3341
3342         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3343                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3344                 RTL_W8(0x82, 0x01);
3345                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3346                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3347         }
3348
3349         rtl8169_phy_reset(dev, tp);
3350
3351         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3352                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3353                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3354                           (tp->mii.supports_gmii ?
3355                            ADVERTISED_1000baseT_Half |
3356                            ADVERTISED_1000baseT_Full : 0));
3357
3358         if (rtl_tbi_enabled(tp))
3359                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3360 }
3361
3362 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3363 {
3364         void __iomem *ioaddr = tp->mmio_addr;
3365         u32 high;
3366         u32 low;
3367
3368         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3369         high = addr[4] | (addr[5] << 8);
3370
3371         rtl_lock_work(tp);
3372
3373         RTL_W8(Cfg9346, Cfg9346_Unlock);
3374
3375         RTL_W32(MAC4, high);
3376         RTL_R32(MAC4);
3377
3378         RTL_W32(MAC0, low);
3379         RTL_R32(MAC0);
3380
3381         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3382                 const struct exgmac_reg e[] = {
3383                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3384                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3385                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3386                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3387                                                                 low  >> 16 },
3388                 };
3389
3390                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3391         }
3392
3393         RTL_W8(Cfg9346, Cfg9346_Lock);
3394
3395         rtl_unlock_work(tp);
3396 }
3397
3398 static int rtl_set_mac_address(struct net_device *dev, void *p)
3399 {
3400         struct rtl8169_private *tp = netdev_priv(dev);
3401         struct sockaddr *addr = p;
3402
3403         if (!is_valid_ether_addr(addr->sa_data))
3404                 return -EADDRNOTAVAIL;
3405
3406         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3407
3408         rtl_rar_set(tp, dev->dev_addr);
3409
3410         return 0;
3411 }
3412
3413 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3414 {
3415         struct rtl8169_private *tp = netdev_priv(dev);
3416         struct mii_ioctl_data *data = if_mii(ifr);
3417
3418         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3419 }
3420
3421 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3422                           struct mii_ioctl_data *data, int cmd)
3423 {
3424         switch (cmd) {
3425         case SIOCGMIIPHY:
3426                 data->phy_id = 32; /* Internal PHY */
3427                 return 0;
3428
3429         case SIOCGMIIREG:
3430                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3431                 return 0;
3432
3433         case SIOCSMIIREG:
3434                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3435                 return 0;
3436         }
3437         return -EOPNOTSUPP;
3438 }
3439
3440 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3441 {
3442         return -EOPNOTSUPP;
3443 }
3444
3445 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3446 {
3447         if (tp->features & RTL_FEATURE_MSI) {
3448                 pci_disable_msi(pdev);
3449                 tp->features &= ~RTL_FEATURE_MSI;
3450         }
3451 }
3452
3453 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3454 {
3455         struct mdio_ops *ops = &tp->mdio_ops;
3456
3457         switch (tp->mac_version) {
3458         case RTL_GIGA_MAC_VER_27:
3459                 ops->write      = r8168dp_1_mdio_write;
3460                 ops->read       = r8168dp_1_mdio_read;
3461                 break;
3462         case RTL_GIGA_MAC_VER_28:
3463         case RTL_GIGA_MAC_VER_31:
3464                 ops->write      = r8168dp_2_mdio_write;
3465                 ops->read       = r8168dp_2_mdio_read;
3466                 break;
3467         default:
3468                 ops->write      = r8169_mdio_write;
3469                 ops->read       = r8169_mdio_read;
3470                 break;
3471         }
3472 }
3473
3474 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3475 {
3476         void __iomem *ioaddr = tp->mmio_addr;
3477
3478         switch (tp->mac_version) {
3479         case RTL_GIGA_MAC_VER_29:
3480         case RTL_GIGA_MAC_VER_30:
3481         case RTL_GIGA_MAC_VER_32:
3482         case RTL_GIGA_MAC_VER_33:
3483         case RTL_GIGA_MAC_VER_34:
3484                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3485                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3486                 break;
3487         default:
3488                 break;
3489         }
3490 }
3491
3492 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3493 {
3494         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3495                 return false;
3496
3497         rtl_writephy(tp, 0x1f, 0x0000);
3498         rtl_writephy(tp, MII_BMCR, 0x0000);
3499
3500         rtl_wol_suspend_quirk(tp);
3501
3502         return true;
3503 }
3504
3505 static void r810x_phy_power_down(struct rtl8169_private *tp)
3506 {
3507         rtl_writephy(tp, 0x1f, 0x0000);
3508         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3509 }
3510
3511 static void r810x_phy_power_up(struct rtl8169_private *tp)
3512 {
3513         rtl_writephy(tp, 0x1f, 0x0000);
3514         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3515 }
3516
3517 static void r810x_pll_power_down(struct rtl8169_private *tp)
3518 {
3519         if (rtl_wol_pll_power_down(tp))
3520                 return;
3521
3522         r810x_phy_power_down(tp);
3523 }
3524
3525 static void r810x_pll_power_up(struct rtl8169_private *tp)
3526 {
3527         r810x_phy_power_up(tp);
3528 }
3529
3530 static void r8168_phy_power_up(struct rtl8169_private *tp)
3531 {
3532         rtl_writephy(tp, 0x1f, 0x0000);
3533         switch (tp->mac_version) {
3534         case RTL_GIGA_MAC_VER_11:
3535         case RTL_GIGA_MAC_VER_12:
3536         case RTL_GIGA_MAC_VER_17:
3537         case RTL_GIGA_MAC_VER_18:
3538         case RTL_GIGA_MAC_VER_19:
3539         case RTL_GIGA_MAC_VER_20:
3540         case RTL_GIGA_MAC_VER_21:
3541         case RTL_GIGA_MAC_VER_22:
3542         case RTL_GIGA_MAC_VER_23:
3543         case RTL_GIGA_MAC_VER_24:
3544         case RTL_GIGA_MAC_VER_25:
3545         case RTL_GIGA_MAC_VER_26:
3546         case RTL_GIGA_MAC_VER_27:
3547         case RTL_GIGA_MAC_VER_28:
3548         case RTL_GIGA_MAC_VER_31:
3549                 rtl_writephy(tp, 0x0e, 0x0000);
3550                 break;
3551         default:
3552                 break;
3553         }
3554         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3555 }
3556
3557 static void r8168_phy_power_down(struct rtl8169_private *tp)
3558 {
3559         rtl_writephy(tp, 0x1f, 0x0000);
3560         switch (tp->mac_version) {
3561         case RTL_GIGA_MAC_VER_32:
3562         case RTL_GIGA_MAC_VER_33:
3563                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3564                 break;
3565
3566         case RTL_GIGA_MAC_VER_11:
3567         case RTL_GIGA_MAC_VER_12:
3568         case RTL_GIGA_MAC_VER_17:
3569         case RTL_GIGA_MAC_VER_18:
3570         case RTL_GIGA_MAC_VER_19:
3571         case RTL_GIGA_MAC_VER_20:
3572         case RTL_GIGA_MAC_VER_21:
3573         case RTL_GIGA_MAC_VER_22:
3574         case RTL_GIGA_MAC_VER_23:
3575         case RTL_GIGA_MAC_VER_24:
3576         case RTL_GIGA_MAC_VER_25:
3577         case RTL_GIGA_MAC_VER_26:
3578         case RTL_GIGA_MAC_VER_27:
3579         case RTL_GIGA_MAC_VER_28:
3580         case RTL_GIGA_MAC_VER_31:
3581                 rtl_writephy(tp, 0x0e, 0x0200);
3582         default:
3583                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3584                 break;
3585         }
3586 }
3587
3588 static void r8168_pll_power_down(struct rtl8169_private *tp)
3589 {
3590         void __iomem *ioaddr = tp->mmio_addr;
3591
3592         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3593              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3594              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3595             r8168dp_check_dash(tp)) {
3596                 return;
3597         }
3598
3599         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3600              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3601             (RTL_R16(CPlusCmd) & ASF)) {
3602                 return;
3603         }
3604
3605         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3606             tp->mac_version == RTL_GIGA_MAC_VER_33)
3607                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3608
3609         if (rtl_wol_pll_power_down(tp))
3610                 return;
3611
3612         r8168_phy_power_down(tp);
3613
3614         switch (tp->mac_version) {
3615         case RTL_GIGA_MAC_VER_25:
3616         case RTL_GIGA_MAC_VER_26:
3617         case RTL_GIGA_MAC_VER_27:
3618         case RTL_GIGA_MAC_VER_28:
3619         case RTL_GIGA_MAC_VER_31:
3620         case RTL_GIGA_MAC_VER_32:
3621         case RTL_GIGA_MAC_VER_33:
3622                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3623                 break;
3624         }
3625 }
3626
3627 static void r8168_pll_power_up(struct rtl8169_private *tp)
3628 {
3629         void __iomem *ioaddr = tp->mmio_addr;
3630
3631         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3632              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3633              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3634             r8168dp_check_dash(tp)) {
3635                 return;
3636         }
3637
3638         switch (tp->mac_version) {
3639         case RTL_GIGA_MAC_VER_25:
3640         case RTL_GIGA_MAC_VER_26:
3641         case RTL_GIGA_MAC_VER_27:
3642         case RTL_GIGA_MAC_VER_28:
3643         case RTL_GIGA_MAC_VER_31:
3644         case RTL_GIGA_MAC_VER_32:
3645         case RTL_GIGA_MAC_VER_33:
3646                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3647                 break;
3648         }
3649
3650         r8168_phy_power_up(tp);
3651 }
3652
3653 static void rtl_generic_op(struct rtl8169_private *tp,
3654                            void (*op)(struct rtl8169_private *))
3655 {
3656         if (op)
3657                 op(tp);
3658 }
3659
3660 static void rtl_pll_power_down(struct rtl8169_private *tp)
3661 {
3662         rtl_generic_op(tp, tp->pll_power_ops.down);
3663 }
3664
3665 static void rtl_pll_power_up(struct rtl8169_private *tp)
3666 {
3667         rtl_generic_op(tp, tp->pll_power_ops.up);
3668 }
3669
3670 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3671 {
3672         struct pll_power_ops *ops = &tp->pll_power_ops;
3673
3674         switch (tp->mac_version) {
3675         case RTL_GIGA_MAC_VER_07:
3676         case RTL_GIGA_MAC_VER_08:
3677         case RTL_GIGA_MAC_VER_09:
3678         case RTL_GIGA_MAC_VER_10:
3679         case RTL_GIGA_MAC_VER_16:
3680         case RTL_GIGA_MAC_VER_29:
3681         case RTL_GIGA_MAC_VER_30:
3682                 ops->down       = r810x_pll_power_down;
3683                 ops->up         = r810x_pll_power_up;
3684                 break;
3685
3686         case RTL_GIGA_MAC_VER_11:
3687         case RTL_GIGA_MAC_VER_12:
3688         case RTL_GIGA_MAC_VER_17:
3689         case RTL_GIGA_MAC_VER_18:
3690         case RTL_GIGA_MAC_VER_19:
3691         case RTL_GIGA_MAC_VER_20:
3692         case RTL_GIGA_MAC_VER_21:
3693         case RTL_GIGA_MAC_VER_22:
3694         case RTL_GIGA_MAC_VER_23:
3695         case RTL_GIGA_MAC_VER_24:
3696         case RTL_GIGA_MAC_VER_25:
3697         case RTL_GIGA_MAC_VER_26:
3698         case RTL_GIGA_MAC_VER_27:
3699         case RTL_GIGA_MAC_VER_28:
3700         case RTL_GIGA_MAC_VER_31:
3701         case RTL_GIGA_MAC_VER_32:
3702         case RTL_GIGA_MAC_VER_33:
3703         case RTL_GIGA_MAC_VER_34:
3704         case RTL_GIGA_MAC_VER_35:
3705         case RTL_GIGA_MAC_VER_36:
3706                 ops->down       = r8168_pll_power_down;
3707                 ops->up         = r8168_pll_power_up;
3708                 break;
3709
3710         default:
3711                 ops->down       = NULL;
3712                 ops->up         = NULL;
3713                 break;
3714         }
3715 }
3716
3717 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3718 {
3719         void __iomem *ioaddr = tp->mmio_addr;
3720
3721         switch (tp->mac_version) {
3722         case RTL_GIGA_MAC_VER_01:
3723         case RTL_GIGA_MAC_VER_02:
3724         case RTL_GIGA_MAC_VER_03:
3725         case RTL_GIGA_MAC_VER_04:
3726         case RTL_GIGA_MAC_VER_05:
3727         case RTL_GIGA_MAC_VER_06:
3728         case RTL_GIGA_MAC_VER_10:
3729         case RTL_GIGA_MAC_VER_11:
3730         case RTL_GIGA_MAC_VER_12:
3731         case RTL_GIGA_MAC_VER_13:
3732         case RTL_GIGA_MAC_VER_14:
3733         case RTL_GIGA_MAC_VER_15:
3734         case RTL_GIGA_MAC_VER_16:
3735         case RTL_GIGA_MAC_VER_17:
3736                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3737                 break;
3738         case RTL_GIGA_MAC_VER_18:
3739         case RTL_GIGA_MAC_VER_19:
3740         case RTL_GIGA_MAC_VER_20:
3741         case RTL_GIGA_MAC_VER_21:
3742         case RTL_GIGA_MAC_VER_22:
3743         case RTL_GIGA_MAC_VER_23:
3744         case RTL_GIGA_MAC_VER_24:
3745                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3746                 break;
3747         default:
3748                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3749                 break;
3750         }
3751 }
3752
3753 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3754 {
3755         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3756 }
3757
3758 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3759 {
3760         void __iomem *ioaddr = tp->mmio_addr;
3761
3762         RTL_W8(Cfg9346, Cfg9346_Unlock);
3763         rtl_generic_op(tp, tp->jumbo_ops.enable);
3764         RTL_W8(Cfg9346, Cfg9346_Lock);
3765 }
3766
3767 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3768 {
3769         void __iomem *ioaddr = tp->mmio_addr;
3770
3771         RTL_W8(Cfg9346, Cfg9346_Unlock);
3772         rtl_generic_op(tp, tp->jumbo_ops.disable);
3773         RTL_W8(Cfg9346, Cfg9346_Lock);
3774 }
3775
3776 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3777 {
3778         void __iomem *ioaddr = tp->mmio_addr;
3779
3780         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3781         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3782         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3783 }
3784
3785 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3786 {
3787         void __iomem *ioaddr = tp->mmio_addr;
3788
3789         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3790         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3791         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3792 }
3793
3794 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3795 {
3796         void __iomem *ioaddr = tp->mmio_addr;
3797
3798         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3799 }
3800
3801 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3802 {
3803         void __iomem *ioaddr = tp->mmio_addr;
3804
3805         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3806 }
3807
3808 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3809 {
3810         void __iomem *ioaddr = tp->mmio_addr;
3811
3812         RTL_W8(MaxTxPacketSize, 0x3f);
3813         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3814         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3815         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3816 }
3817
3818 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3819 {
3820         void __iomem *ioaddr = tp->mmio_addr;
3821
3822         RTL_W8(MaxTxPacketSize, 0x0c);
3823         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3824         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3825         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3826 }
3827
3828 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3829 {
3830         rtl_tx_performance_tweak(tp->pci_dev,
3831                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3832 }
3833
3834 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3835 {
3836         rtl_tx_performance_tweak(tp->pci_dev,
3837                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3838 }
3839
3840 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3841 {
3842         void __iomem *ioaddr = tp->mmio_addr;
3843
3844         r8168b_0_hw_jumbo_enable(tp);
3845
3846         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3847 }
3848
3849 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3850 {
3851         void __iomem *ioaddr = tp->mmio_addr;
3852
3853         r8168b_0_hw_jumbo_disable(tp);
3854
3855         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3856 }
3857
3858 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3859 {
3860         struct jumbo_ops *ops = &tp->jumbo_ops;
3861
3862         switch (tp->mac_version) {
3863         case RTL_GIGA_MAC_VER_11:
3864                 ops->disable    = r8168b_0_hw_jumbo_disable;
3865                 ops->enable     = r8168b_0_hw_jumbo_enable;
3866                 break;
3867         case RTL_GIGA_MAC_VER_12:
3868         case RTL_GIGA_MAC_VER_17:
3869                 ops->disable    = r8168b_1_hw_jumbo_disable;
3870                 ops->enable     = r8168b_1_hw_jumbo_enable;
3871                 break;
3872         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3873         case RTL_GIGA_MAC_VER_19:
3874         case RTL_GIGA_MAC_VER_20:
3875         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3876         case RTL_GIGA_MAC_VER_22:
3877         case RTL_GIGA_MAC_VER_23:
3878         case RTL_GIGA_MAC_VER_24:
3879         case RTL_GIGA_MAC_VER_25:
3880         case RTL_GIGA_MAC_VER_26:
3881                 ops->disable    = r8168c_hw_jumbo_disable;
3882                 ops->enable     = r8168c_hw_jumbo_enable;
3883                 break;
3884         case RTL_GIGA_MAC_VER_27:
3885         case RTL_GIGA_MAC_VER_28:
3886                 ops->disable    = r8168dp_hw_jumbo_disable;
3887                 ops->enable     = r8168dp_hw_jumbo_enable;
3888                 break;
3889         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3890         case RTL_GIGA_MAC_VER_32:
3891         case RTL_GIGA_MAC_VER_33:
3892         case RTL_GIGA_MAC_VER_34:
3893                 ops->disable    = r8168e_hw_jumbo_disable;
3894                 ops->enable     = r8168e_hw_jumbo_enable;
3895                 break;
3896
3897         /*
3898          * No action needed for jumbo frames with 8169.
3899          * No jumbo for 810x at all.
3900          */
3901         default:
3902                 ops->disable    = NULL;
3903                 ops->enable     = NULL;
3904                 break;
3905         }
3906 }
3907
3908 static void rtl_hw_reset(struct rtl8169_private *tp)
3909 {
3910         void __iomem *ioaddr = tp->mmio_addr;
3911         int i;
3912
3913         /* Soft reset the chip. */
3914         RTL_W8(ChipCmd, CmdReset);
3915
3916         /* Check that the chip has finished the reset. */
3917         for (i = 0; i < 100; i++) {
3918                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3919                         break;
3920                 udelay(100);
3921         }
3922 }
3923
3924 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3925 {
3926         struct rtl_fw *rtl_fw;
3927         const char *name;
3928         int rc = -ENOMEM;
3929
3930         name = rtl_lookup_firmware_name(tp);
3931         if (!name)
3932                 goto out_no_firmware;
3933
3934         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3935         if (!rtl_fw)
3936                 goto err_warn;
3937
3938         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3939         if (rc < 0)
3940                 goto err_free;
3941
3942         rc = rtl_check_firmware(tp, rtl_fw);
3943         if (rc < 0)
3944                 goto err_release_firmware;
3945
3946         tp->rtl_fw = rtl_fw;
3947 out:
3948         return;
3949
3950 err_release_firmware:
3951         release_firmware(rtl_fw->fw);
3952 err_free:
3953         kfree(rtl_fw);
3954 err_warn:
3955         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3956                    name, rc);
3957 out_no_firmware:
3958         tp->rtl_fw = NULL;
3959         goto out;
3960 }
3961
3962 static void rtl_request_firmware(struct rtl8169_private *tp)
3963 {
3964         if (IS_ERR(tp->rtl_fw))
3965                 rtl_request_uncached_firmware(tp);
3966 }
3967
3968 static void rtl_rx_close(struct rtl8169_private *tp)
3969 {
3970         void __iomem *ioaddr = tp->mmio_addr;
3971
3972         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3973 }
3974
3975 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3976 {
3977         void __iomem *ioaddr = tp->mmio_addr;
3978
3979         /* Disable interrupts */
3980         rtl8169_irq_mask_and_ack(tp);
3981
3982         rtl_rx_close(tp);
3983
3984         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3985             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3986             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3987                 while (RTL_R8(TxPoll) & NPQ)
3988                         udelay(20);
3989         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3990                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3991                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
3992                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3993                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3994                         udelay(100);
3995         } else {
3996                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3997                 udelay(100);
3998         }
3999
4000         rtl_hw_reset(tp);
4001 }
4002
4003 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4004 {
4005         void __iomem *ioaddr = tp->mmio_addr;
4006
4007         /* Set DMA burst size and Interframe Gap Time */
4008         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4009                 (InterFrameGap << TxInterFrameGapShift));
4010 }
4011
4012 static void rtl_hw_start(struct net_device *dev)
4013 {
4014         struct rtl8169_private *tp = netdev_priv(dev);
4015
4016         tp->hw_start(dev);
4017
4018         rtl_irq_enable_all(tp);
4019 }
4020
4021 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4022                                          void __iomem *ioaddr)
4023 {
4024         /*
4025          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4026          * register to be written before TxDescAddrLow to work.
4027          * Switching from MMIO to I/O access fixes the issue as well.
4028          */
4029         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4030         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4031         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4032         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4033 }
4034
4035 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4036 {
4037         u16 cmd;
4038
4039         cmd = RTL_R16(CPlusCmd);
4040         RTL_W16(CPlusCmd, cmd);
4041         return cmd;
4042 }
4043
4044 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4045 {
4046         /* Low hurts. Let's disable the filtering. */
4047         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4048 }
4049
4050 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4051 {
4052         static const struct rtl_cfg2_info {
4053                 u32 mac_version;
4054                 u32 clk;
4055                 u32 val;
4056         } cfg2_info [] = {
4057                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4058                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4059                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4060                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4061         };
4062         const struct rtl_cfg2_info *p = cfg2_info;
4063         unsigned int i;
4064         u32 clk;
4065
4066         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4067         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4068                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4069                         RTL_W32(0x7c, p->val);
4070                         break;
4071                 }
4072         }
4073 }
4074
4075 static void rtl_set_rx_mode(struct net_device *dev)
4076 {
4077         struct rtl8169_private *tp = netdev_priv(dev);
4078         void __iomem *ioaddr = tp->mmio_addr;
4079         u32 mc_filter[2];       /* Multicast hash filter */
4080         int rx_mode;
4081         u32 tmp = 0;
4082
4083         if (dev->flags & IFF_PROMISC) {
4084                 /* Unconditionally log net taps. */
4085                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4086                 rx_mode =
4087                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4088                     AcceptAllPhys;
4089                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4090         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4091                    (dev->flags & IFF_ALLMULTI)) {
4092                 /* Too many to filter perfectly -- accept all multicasts. */
4093                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4094                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4095         } else {
4096                 struct netdev_hw_addr *ha;
4097
4098                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4099                 mc_filter[1] = mc_filter[0] = 0;
4100                 netdev_for_each_mc_addr(ha, dev) {
4101                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4102                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4103                         rx_mode |= AcceptMulticast;
4104                 }
4105         }
4106
4107         if (dev->features & NETIF_F_RXALL)
4108                 rx_mode |= (AcceptErr | AcceptRunt);
4109
4110         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4111
4112         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4113                 u32 data = mc_filter[0];
4114
4115                 mc_filter[0] = swab32(mc_filter[1]);
4116                 mc_filter[1] = swab32(data);
4117         }
4118
4119         RTL_W32(MAR0 + 4, mc_filter[1]);
4120         RTL_W32(MAR0 + 0, mc_filter[0]);
4121
4122         RTL_W32(RxConfig, tmp);
4123 }
4124
4125 static void rtl_hw_start_8169(struct net_device *dev)
4126 {
4127         struct rtl8169_private *tp = netdev_priv(dev);
4128         void __iomem *ioaddr = tp->mmio_addr;
4129         struct pci_dev *pdev = tp->pci_dev;
4130
4131         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4132                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4133                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4134         }
4135
4136         RTL_W8(Cfg9346, Cfg9346_Unlock);
4137         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4138             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4139             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4140             tp->mac_version == RTL_GIGA_MAC_VER_04)
4141                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4142
4143         rtl_init_rxcfg(tp);
4144
4145         RTL_W8(EarlyTxThres, NoEarlyTx);
4146
4147         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4148
4149         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4150             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4151             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4152             tp->mac_version == RTL_GIGA_MAC_VER_04)
4153                 rtl_set_rx_tx_config_registers(tp);
4154
4155         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4156
4157         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4158             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4159                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4160                         "Bit-3 and bit-14 MUST be 1\n");
4161                 tp->cp_cmd |= (1 << 14);
4162         }
4163
4164         RTL_W16(CPlusCmd, tp->cp_cmd);
4165
4166         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4167
4168         /*
4169          * Undocumented corner. Supposedly:
4170          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4171          */
4172         RTL_W16(IntrMitigate, 0x0000);
4173
4174         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4175
4176         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4177             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4178             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4179             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4180                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4181                 rtl_set_rx_tx_config_registers(tp);
4182         }
4183
4184         RTL_W8(Cfg9346, Cfg9346_Lock);
4185
4186         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4187         RTL_R8(IntrMask);
4188
4189         RTL_W32(RxMissed, 0);
4190
4191         rtl_set_rx_mode(dev);
4192
4193         /* no early-rx interrupts */
4194         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4195 }
4196
4197 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4198 {
4199         u32 csi;
4200
4201         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4202         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4203 }
4204
4205 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4206 {
4207         rtl_csi_access_enable(ioaddr, 0x17000000);
4208 }
4209
4210 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4211 {
4212         rtl_csi_access_enable(ioaddr, 0x27000000);
4213 }
4214
4215 struct ephy_info {
4216         unsigned int offset;
4217         u16 mask;
4218         u16 bits;
4219 };
4220
4221 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4222 {
4223         u16 w;
4224
4225         while (len-- > 0) {
4226                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4227                 rtl_ephy_write(ioaddr, e->offset, w);
4228                 e++;
4229         }
4230 }
4231
4232 static void rtl_disable_clock_request(struct pci_dev *pdev)
4233 {
4234         int cap = pci_pcie_cap(pdev);
4235
4236         if (cap) {
4237                 u16 ctl;
4238
4239                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4240                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4241                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4242         }
4243 }
4244
4245 static void rtl_enable_clock_request(struct pci_dev *pdev)
4246 {
4247         int cap = pci_pcie_cap(pdev);
4248
4249         if (cap) {
4250                 u16 ctl;
4251
4252                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4253                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4254                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4255         }
4256 }
4257
4258 #define R8168_CPCMD_QUIRK_MASK (\
4259         EnableBist | \
4260         Mac_dbgo_oe | \
4261         Force_half_dup | \
4262         Force_rxflow_en | \
4263         Force_txflow_en | \
4264         Cxpl_dbg_sel | \
4265         ASF | \
4266         PktCntrDisable | \
4267         Mac_dbgo_sel)
4268
4269 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4270 {
4271         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4272
4273         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4274
4275         rtl_tx_performance_tweak(pdev,
4276                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4277 }
4278
4279 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4280 {
4281         rtl_hw_start_8168bb(ioaddr, pdev);
4282
4283         RTL_W8(MaxTxPacketSize, TxPacketMax);
4284
4285         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4286 }
4287
4288 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4289 {
4290         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4291
4292         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4293
4294         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4295
4296         rtl_disable_clock_request(pdev);
4297
4298         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4299 }
4300
4301 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4302 {
4303         static const struct ephy_info e_info_8168cp[] = {
4304                 { 0x01, 0,      0x0001 },
4305                 { 0x02, 0x0800, 0x1000 },
4306                 { 0x03, 0,      0x0042 },
4307                 { 0x06, 0x0080, 0x0000 },
4308                 { 0x07, 0,      0x2000 }
4309         };
4310
4311         rtl_csi_access_enable_2(ioaddr);
4312
4313         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4314
4315         __rtl_hw_start_8168cp(ioaddr, pdev);
4316 }
4317
4318 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4319 {
4320         rtl_csi_access_enable_2(ioaddr);
4321
4322         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4323
4324         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4325
4326         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4327 }
4328
4329 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4330 {
4331         rtl_csi_access_enable_2(ioaddr);
4332
4333         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4334
4335         /* Magic. */
4336         RTL_W8(DBG_REG, 0x20);
4337
4338         RTL_W8(MaxTxPacketSize, TxPacketMax);
4339
4340         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4341
4342         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4343 }
4344
4345 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4346 {
4347         static const struct ephy_info e_info_8168c_1[] = {
4348                 { 0x02, 0x0800, 0x1000 },
4349                 { 0x03, 0,      0x0002 },
4350                 { 0x06, 0x0080, 0x0000 }
4351         };
4352
4353         rtl_csi_access_enable_2(ioaddr);
4354
4355         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4356
4357         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4358
4359         __rtl_hw_start_8168cp(ioaddr, pdev);
4360 }
4361
4362 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4363 {
4364         static const struct ephy_info e_info_8168c_2[] = {
4365                 { 0x01, 0,      0x0001 },
4366                 { 0x03, 0x0400, 0x0220 }
4367         };
4368
4369         rtl_csi_access_enable_2(ioaddr);
4370
4371         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4372
4373         __rtl_hw_start_8168cp(ioaddr, pdev);
4374 }
4375
4376 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4377 {
4378         rtl_hw_start_8168c_2(ioaddr, pdev);
4379 }
4380
4381 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4382 {
4383         rtl_csi_access_enable_2(ioaddr);
4384
4385         __rtl_hw_start_8168cp(ioaddr, pdev);
4386 }
4387
4388 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4389 {
4390         rtl_csi_access_enable_2(ioaddr);
4391
4392         rtl_disable_clock_request(pdev);
4393
4394         RTL_W8(MaxTxPacketSize, TxPacketMax);
4395
4396         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4397
4398         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4399 }
4400
4401 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4402 {
4403         rtl_csi_access_enable_1(ioaddr);
4404
4405         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4406
4407         RTL_W8(MaxTxPacketSize, TxPacketMax);
4408
4409         rtl_disable_clock_request(pdev);
4410 }
4411
4412 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4413 {
4414         static const struct ephy_info e_info_8168d_4[] = {
4415                 { 0x0b, ~0,     0x48 },
4416                 { 0x19, 0x20,   0x50 },
4417                 { 0x0c, ~0,     0x20 }
4418         };
4419         int i;
4420
4421         rtl_csi_access_enable_1(ioaddr);
4422
4423         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4424
4425         RTL_W8(MaxTxPacketSize, TxPacketMax);
4426
4427         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4428                 const struct ephy_info *e = e_info_8168d_4 + i;
4429                 u16 w;
4430
4431                 w = rtl_ephy_read(ioaddr, e->offset);
4432                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4433         }
4434
4435         rtl_enable_clock_request(pdev);
4436 }
4437
4438 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4439 {
4440         static const struct ephy_info e_info_8168e_1[] = {
4441                 { 0x00, 0x0200, 0x0100 },
4442                 { 0x00, 0x0000, 0x0004 },
4443                 { 0x06, 0x0002, 0x0001 },
4444                 { 0x06, 0x0000, 0x0030 },
4445                 { 0x07, 0x0000, 0x2000 },
4446                 { 0x00, 0x0000, 0x0020 },
4447                 { 0x03, 0x5800, 0x2000 },
4448                 { 0x03, 0x0000, 0x0001 },
4449                 { 0x01, 0x0800, 0x1000 },
4450                 { 0x07, 0x0000, 0x4000 },
4451                 { 0x1e, 0x0000, 0x2000 },
4452                 { 0x19, 0xffff, 0xfe6c },
4453                 { 0x0a, 0x0000, 0x0040 }
4454         };
4455
4456         rtl_csi_access_enable_2(ioaddr);
4457
4458         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4459
4460         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4461
4462         RTL_W8(MaxTxPacketSize, TxPacketMax);
4463
4464         rtl_disable_clock_request(pdev);
4465
4466         /* Reset tx FIFO pointer */
4467         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4468         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4469
4470         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4471 }
4472
4473 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4474 {
4475         static const struct ephy_info e_info_8168e_2[] = {
4476                 { 0x09, 0x0000, 0x0080 },
4477                 { 0x19, 0x0000, 0x0224 }
4478         };
4479
4480         rtl_csi_access_enable_1(ioaddr);
4481
4482         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4483
4484         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4485
4486         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4487         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4488         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4489         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4490         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4491         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4492         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4493         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4494                      ERIAR_EXGMAC);
4495
4496         RTL_W8(MaxTxPacketSize, EarlySize);
4497
4498         rtl_disable_clock_request(pdev);
4499
4500         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4501         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4502
4503         /* Adjust EEE LED frequency */
4504         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4505
4506         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4507         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4508         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4509 }
4510
4511 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4512 {
4513         static const struct ephy_info e_info_8168f_1[] = {
4514                 { 0x06, 0x00c0, 0x0020 },
4515                 { 0x08, 0x0001, 0x0002 },
4516                 { 0x09, 0x0000, 0x0080 },
4517                 { 0x19, 0x0000, 0x0224 }
4518         };
4519
4520         rtl_csi_access_enable_1(ioaddr);
4521
4522         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4523
4524         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4525
4526         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4527         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4528         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4529         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4530         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4531         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4532         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4533         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4534         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4535         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4536         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4537                      ERIAR_EXGMAC);
4538
4539         RTL_W8(MaxTxPacketSize, EarlySize);
4540
4541         rtl_disable_clock_request(pdev);
4542
4543         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4544         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4545
4546         /* Adjust EEE LED frequency */
4547         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4548
4549         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4550         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4551         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4552 }
4553
4554 static void rtl_hw_start_8168(struct net_device *dev)
4555 {
4556         struct rtl8169_private *tp = netdev_priv(dev);
4557         void __iomem *ioaddr = tp->mmio_addr;
4558         struct pci_dev *pdev = tp->pci_dev;
4559
4560         RTL_W8(Cfg9346, Cfg9346_Unlock);
4561
4562         RTL_W8(MaxTxPacketSize, TxPacketMax);
4563
4564         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4565
4566         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4567
4568         RTL_W16(CPlusCmd, tp->cp_cmd);
4569
4570         RTL_W16(IntrMitigate, 0x5151);
4571
4572         /* Work around for RxFIFO overflow. */
4573         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4574                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4575                 tp->event_slow &= ~RxOverflow;
4576         }
4577
4578         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4579
4580         rtl_set_rx_mode(dev);
4581
4582         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4583                 (InterFrameGap << TxInterFrameGapShift));
4584
4585         RTL_R8(IntrMask);
4586
4587         switch (tp->mac_version) {
4588         case RTL_GIGA_MAC_VER_11:
4589                 rtl_hw_start_8168bb(ioaddr, pdev);
4590                 break;
4591
4592         case RTL_GIGA_MAC_VER_12:
4593         case RTL_GIGA_MAC_VER_17:
4594                 rtl_hw_start_8168bef(ioaddr, pdev);
4595                 break;
4596
4597         case RTL_GIGA_MAC_VER_18:
4598                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4599                 break;
4600
4601         case RTL_GIGA_MAC_VER_19:
4602                 rtl_hw_start_8168c_1(ioaddr, pdev);
4603                 break;
4604
4605         case RTL_GIGA_MAC_VER_20:
4606                 rtl_hw_start_8168c_2(ioaddr, pdev);
4607                 break;
4608
4609         case RTL_GIGA_MAC_VER_21:
4610                 rtl_hw_start_8168c_3(ioaddr, pdev);
4611                 break;
4612
4613         case RTL_GIGA_MAC_VER_22:
4614                 rtl_hw_start_8168c_4(ioaddr, pdev);
4615                 break;
4616
4617         case RTL_GIGA_MAC_VER_23:
4618                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4619                 break;
4620
4621         case RTL_GIGA_MAC_VER_24:
4622                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4623                 break;
4624
4625         case RTL_GIGA_MAC_VER_25:
4626         case RTL_GIGA_MAC_VER_26:
4627         case RTL_GIGA_MAC_VER_27:
4628                 rtl_hw_start_8168d(ioaddr, pdev);
4629                 break;
4630
4631         case RTL_GIGA_MAC_VER_28:
4632                 rtl_hw_start_8168d_4(ioaddr, pdev);
4633                 break;
4634
4635         case RTL_GIGA_MAC_VER_31:
4636                 rtl_hw_start_8168dp(ioaddr, pdev);
4637                 break;
4638
4639         case RTL_GIGA_MAC_VER_32:
4640         case RTL_GIGA_MAC_VER_33:
4641                 rtl_hw_start_8168e_1(ioaddr, pdev);
4642                 break;
4643         case RTL_GIGA_MAC_VER_34:
4644                 rtl_hw_start_8168e_2(ioaddr, pdev);
4645                 break;
4646
4647         case RTL_GIGA_MAC_VER_35:
4648         case RTL_GIGA_MAC_VER_36:
4649                 rtl_hw_start_8168f_1(ioaddr, pdev);
4650                 break;
4651
4652         default:
4653                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4654                         dev->name, tp->mac_version);
4655                 break;
4656         }
4657
4658         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4659
4660         RTL_W8(Cfg9346, Cfg9346_Lock);
4661
4662         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4663 }
4664
4665 #define R810X_CPCMD_QUIRK_MASK (\
4666         EnableBist | \
4667         Mac_dbgo_oe | \
4668         Force_half_dup | \
4669         Force_rxflow_en | \
4670         Force_txflow_en | \
4671         Cxpl_dbg_sel | \
4672         ASF | \
4673         PktCntrDisable | \
4674         Mac_dbgo_sel)
4675
4676 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4677 {
4678         static const struct ephy_info e_info_8102e_1[] = {
4679                 { 0x01, 0, 0x6e65 },
4680                 { 0x02, 0, 0x091f },
4681                 { 0x03, 0, 0xc2f9 },
4682                 { 0x06, 0, 0xafb5 },
4683                 { 0x07, 0, 0x0e00 },
4684                 { 0x19, 0, 0xec80 },
4685                 { 0x01, 0, 0x2e65 },
4686                 { 0x01, 0, 0x6e65 }
4687         };
4688         u8 cfg1;
4689
4690         rtl_csi_access_enable_2(ioaddr);
4691
4692         RTL_W8(DBG_REG, FIX_NAK_1);
4693
4694         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4695
4696         RTL_W8(Config1,
4697                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4698         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4699
4700         cfg1 = RTL_R8(Config1);
4701         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4702                 RTL_W8(Config1, cfg1 & ~LEDS0);
4703
4704         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4705 }
4706
4707 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4708 {
4709         rtl_csi_access_enable_2(ioaddr);
4710
4711         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4712
4713         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4714         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4715 }
4716
4717 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4718 {
4719         rtl_hw_start_8102e_2(ioaddr, pdev);
4720
4721         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4722 }
4723
4724 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4725 {
4726         static const struct ephy_info e_info_8105e_1[] = {
4727                 { 0x07, 0, 0x4000 },
4728                 { 0x19, 0, 0x0200 },
4729                 { 0x19, 0, 0x0020 },
4730                 { 0x1e, 0, 0x2000 },
4731                 { 0x03, 0, 0x0001 },
4732                 { 0x19, 0, 0x0100 },
4733                 { 0x19, 0, 0x0004 },
4734                 { 0x0a, 0, 0x0020 }
4735         };
4736
4737         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4738         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4739
4740         /* Disable Early Tally Counter */
4741         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4742
4743         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4744         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4745
4746         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4747 }
4748
4749 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4750 {
4751         rtl_hw_start_8105e_1(ioaddr, pdev);
4752         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4753 }
4754
4755 static void rtl_hw_start_8101(struct net_device *dev)
4756 {
4757         struct rtl8169_private *tp = netdev_priv(dev);
4758         void __iomem *ioaddr = tp->mmio_addr;
4759         struct pci_dev *pdev = tp->pci_dev;
4760
4761         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4762                 tp->event_slow &= ~RxFIFOOver;
4763
4764         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4765             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4766                 int cap = pci_pcie_cap(pdev);
4767
4768                 if (cap) {
4769                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4770                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4771                 }
4772         }
4773
4774         RTL_W8(Cfg9346, Cfg9346_Unlock);
4775
4776         switch (tp->mac_version) {
4777         case RTL_GIGA_MAC_VER_07:
4778                 rtl_hw_start_8102e_1(ioaddr, pdev);
4779                 break;
4780
4781         case RTL_GIGA_MAC_VER_08:
4782                 rtl_hw_start_8102e_3(ioaddr, pdev);
4783                 break;
4784
4785         case RTL_GIGA_MAC_VER_09:
4786                 rtl_hw_start_8102e_2(ioaddr, pdev);
4787                 break;
4788
4789         case RTL_GIGA_MAC_VER_29:
4790                 rtl_hw_start_8105e_1(ioaddr, pdev);
4791                 break;
4792         case RTL_GIGA_MAC_VER_30:
4793                 rtl_hw_start_8105e_2(ioaddr, pdev);
4794                 break;
4795         }
4796
4797         RTL_W8(Cfg9346, Cfg9346_Lock);
4798
4799         RTL_W8(MaxTxPacketSize, TxPacketMax);
4800
4801         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4802
4803         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4804         RTL_W16(CPlusCmd, tp->cp_cmd);
4805
4806         RTL_W16(IntrMitigate, 0x0000);
4807
4808         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4809
4810         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4811         rtl_set_rx_tx_config_registers(tp);
4812
4813         RTL_R8(IntrMask);
4814
4815         rtl_set_rx_mode(dev);
4816
4817         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4818 }
4819
4820 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4821 {
4822         struct rtl8169_private *tp = netdev_priv(dev);
4823
4824         if (new_mtu < ETH_ZLEN ||
4825             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4826                 return -EINVAL;
4827
4828         if (new_mtu > ETH_DATA_LEN)
4829                 rtl_hw_jumbo_enable(tp);
4830         else
4831                 rtl_hw_jumbo_disable(tp);
4832
4833         dev->mtu = new_mtu;
4834         netdev_update_features(dev);
4835
4836         return 0;
4837 }
4838
4839 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4840 {
4841         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4842         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4843 }
4844
4845 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4846                                      void **data_buff, struct RxDesc *desc)
4847 {
4848         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4849                          DMA_FROM_DEVICE);
4850
4851         kfree(*data_buff);
4852         *data_buff = NULL;
4853         rtl8169_make_unusable_by_asic(desc);
4854 }
4855
4856 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4857 {
4858         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4859
4860         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4861 }
4862
4863 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4864                                        u32 rx_buf_sz)
4865 {
4866         desc->addr = cpu_to_le64(mapping);
4867         wmb();
4868         rtl8169_mark_to_asic(desc, rx_buf_sz);
4869 }
4870
4871 static inline void *rtl8169_align(void *data)
4872 {
4873         return (void *)ALIGN((long)data, 16);
4874 }
4875
4876 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4877                                              struct RxDesc *desc)
4878 {
4879         void *data;
4880         dma_addr_t mapping;
4881         struct device *d = &tp->pci_dev->dev;
4882         struct net_device *dev = tp->dev;
4883         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4884
4885         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4886         if (!data)
4887                 return NULL;
4888
4889         if (rtl8169_align(data) != data) {
4890                 kfree(data);
4891                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4892                 if (!data)
4893                         return NULL;
4894         }
4895
4896         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4897                                  DMA_FROM_DEVICE);
4898         if (unlikely(dma_mapping_error(d, mapping))) {
4899                 if (net_ratelimit())
4900                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4901                 goto err_out;
4902         }
4903
4904         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4905         return data;
4906
4907 err_out:
4908         kfree(data);
4909         return NULL;
4910 }
4911
4912 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4913 {
4914         unsigned int i;
4915
4916         for (i = 0; i < NUM_RX_DESC; i++) {
4917                 if (tp->Rx_databuff[i]) {
4918                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4919                                             tp->RxDescArray + i);
4920                 }
4921         }
4922 }
4923
4924 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4925 {
4926         desc->opts1 |= cpu_to_le32(RingEnd);
4927 }
4928
4929 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4930 {
4931         unsigned int i;
4932
4933         for (i = 0; i < NUM_RX_DESC; i++) {
4934                 void *data;
4935
4936                 if (tp->Rx_databuff[i])
4937                         continue;
4938
4939                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4940                 if (!data) {
4941                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4942                         goto err_out;
4943                 }
4944                 tp->Rx_databuff[i] = data;
4945         }
4946
4947         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4948         return 0;
4949
4950 err_out:
4951         rtl8169_rx_clear(tp);
4952         return -ENOMEM;
4953 }
4954
4955 static int rtl8169_init_ring(struct net_device *dev)
4956 {
4957         struct rtl8169_private *tp = netdev_priv(dev);
4958
4959         rtl8169_init_ring_indexes(tp);
4960
4961         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4962         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4963
4964         return rtl8169_rx_fill(tp);
4965 }
4966
4967 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4968                                  struct TxDesc *desc)
4969 {
4970         unsigned int len = tx_skb->len;
4971
4972         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4973
4974         desc->opts1 = 0x00;
4975         desc->opts2 = 0x00;
4976         desc->addr = 0x00;
4977         tx_skb->len = 0;
4978 }
4979
4980 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4981                                    unsigned int n)
4982 {
4983         unsigned int i;
4984
4985         for (i = 0; i < n; i++) {
4986                 unsigned int entry = (start + i) % NUM_TX_DESC;
4987                 struct ring_info *tx_skb = tp->tx_skb + entry;
4988                 unsigned int len = tx_skb->len;
4989
4990                 if (len) {
4991                         struct sk_buff *skb = tx_skb->skb;
4992
4993                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4994                                              tp->TxDescArray + entry);
4995                         if (skb) {
4996                                 tp->dev->stats.tx_dropped++;
4997                                 dev_kfree_skb(skb);
4998                                 tx_skb->skb = NULL;
4999                         }
5000                 }
5001         }
5002 }
5003
5004 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5005 {
5006         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5007         tp->cur_tx = tp->dirty_tx = 0;
5008         netdev_reset_queue(tp->dev);
5009 }
5010
5011 static void rtl_reset_work(struct rtl8169_private *tp)
5012 {
5013         struct net_device *dev = tp->dev;
5014         int i;
5015
5016         napi_disable(&tp->napi);
5017         netif_stop_queue(dev);
5018         synchronize_sched();
5019
5020         rtl8169_hw_reset(tp);
5021
5022         for (i = 0; i < NUM_RX_DESC; i++)
5023                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5024
5025         rtl8169_tx_clear(tp);
5026         rtl8169_init_ring_indexes(tp);
5027
5028         napi_enable(&tp->napi);
5029         rtl_hw_start(dev);
5030         netif_wake_queue(dev);
5031         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5032 }
5033
5034 static void rtl8169_tx_timeout(struct net_device *dev)
5035 {
5036         struct rtl8169_private *tp = netdev_priv(dev);
5037
5038         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5039 }
5040
5041 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5042                               u32 *opts)
5043 {
5044         struct skb_shared_info *info = skb_shinfo(skb);
5045         unsigned int cur_frag, entry;
5046         struct TxDesc * uninitialized_var(txd);
5047         struct device *d = &tp->pci_dev->dev;
5048
5049         entry = tp->cur_tx;
5050         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5051                 const skb_frag_t *frag = info->frags + cur_frag;
5052                 dma_addr_t mapping;
5053                 u32 status, len;
5054                 void *addr;
5055
5056                 entry = (entry + 1) % NUM_TX_DESC;
5057
5058                 txd = tp->TxDescArray + entry;
5059                 len = skb_frag_size(frag);
5060                 addr = skb_frag_address(frag);
5061                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5062                 if (unlikely(dma_mapping_error(d, mapping))) {
5063                         if (net_ratelimit())
5064                                 netif_err(tp, drv, tp->dev,
5065                                           "Failed to map TX fragments DMA!\n");
5066                         goto err_out;
5067                 }
5068
5069                 /* Anti gcc 2.95.3 bugware (sic) */
5070                 status = opts[0] | len |
5071                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5072
5073                 txd->opts1 = cpu_to_le32(status);
5074                 txd->opts2 = cpu_to_le32(opts[1]);
5075                 txd->addr = cpu_to_le64(mapping);
5076
5077                 tp->tx_skb[entry].len = len;
5078         }
5079
5080         if (cur_frag) {
5081                 tp->tx_skb[entry].skb = skb;
5082                 txd->opts1 |= cpu_to_le32(LastFrag);
5083         }
5084
5085         return cur_frag;
5086
5087 err_out:
5088         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5089         return -EIO;
5090 }
5091
5092 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5093                                     struct sk_buff *skb, u32 *opts)
5094 {
5095         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5096         u32 mss = skb_shinfo(skb)->gso_size;
5097         int offset = info->opts_offset;
5098
5099         if (mss) {
5100                 opts[0] |= TD_LSO;
5101                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5102         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5103                 const struct iphdr *ip = ip_hdr(skb);
5104
5105                 if (ip->protocol == IPPROTO_TCP)
5106                         opts[offset] |= info->checksum.tcp;
5107                 else if (ip->protocol == IPPROTO_UDP)
5108                         opts[offset] |= info->checksum.udp;
5109                 else
5110                         WARN_ON_ONCE(1);
5111         }
5112 }
5113
5114 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5115                                       struct net_device *dev)
5116 {
5117         struct rtl8169_private *tp = netdev_priv(dev);
5118         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5119         struct TxDesc *txd = tp->TxDescArray + entry;
5120         void __iomem *ioaddr = tp->mmio_addr;
5121         struct device *d = &tp->pci_dev->dev;
5122         dma_addr_t mapping;
5123         u32 status, len;
5124         u32 opts[2];
5125         int frags;
5126
5127         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5128                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5129                 goto err_stop_0;
5130         }
5131
5132         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5133                 goto err_stop_0;
5134
5135         len = skb_headlen(skb);
5136         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5137         if (unlikely(dma_mapping_error(d, mapping))) {
5138                 if (net_ratelimit())
5139                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5140                 goto err_dma_0;
5141         }
5142
5143         tp->tx_skb[entry].len = len;
5144         txd->addr = cpu_to_le64(mapping);
5145
5146         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5147         opts[0] = DescOwn;
5148
5149         rtl8169_tso_csum(tp, skb, opts);
5150
5151         frags = rtl8169_xmit_frags(tp, skb, opts);
5152         if (frags < 0)
5153                 goto err_dma_1;
5154         else if (frags)
5155                 opts[0] |= FirstFrag;
5156         else {
5157                 opts[0] |= FirstFrag | LastFrag;
5158                 tp->tx_skb[entry].skb = skb;
5159         }
5160
5161         txd->opts2 = cpu_to_le32(opts[1]);
5162
5163         netdev_sent_queue(dev, skb->len);
5164
5165         skb_tx_timestamp(skb);
5166
5167         wmb();
5168
5169         /* Anti gcc 2.95.3 bugware (sic) */
5170         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5171         txd->opts1 = cpu_to_le32(status);
5172
5173         tp->cur_tx += frags + 1;
5174
5175         wmb();
5176
5177         RTL_W8(TxPoll, NPQ);
5178
5179         mmiowb();
5180
5181         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5182                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5183                  * not miss a ring update when it notices a stopped queue.
5184                  */
5185                 smp_wmb();
5186                 netif_stop_queue(dev);
5187                 /* Sync with rtl_tx:
5188                  * - publish queue status and cur_tx ring index (write barrier)
5189                  * - refresh dirty_tx ring index (read barrier).
5190                  * May the current thread have a pessimistic view of the ring
5191                  * status and forget to wake up queue, a racing rtl_tx thread
5192                  * can't.
5193                  */
5194                 smp_mb();
5195                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5196                         netif_wake_queue(dev);
5197         }
5198
5199         return NETDEV_TX_OK;
5200
5201 err_dma_1:
5202         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5203 err_dma_0:
5204         dev_kfree_skb(skb);
5205         dev->stats.tx_dropped++;
5206         return NETDEV_TX_OK;
5207
5208 err_stop_0:
5209         netif_stop_queue(dev);
5210         dev->stats.tx_dropped++;
5211         return NETDEV_TX_BUSY;
5212 }
5213
5214 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5215 {
5216         struct rtl8169_private *tp = netdev_priv(dev);
5217         struct pci_dev *pdev = tp->pci_dev;
5218         u16 pci_status, pci_cmd;
5219
5220         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5221         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5222
5223         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5224                   pci_cmd, pci_status);
5225
5226         /*
5227          * The recovery sequence below admits a very elaborated explanation:
5228          * - it seems to work;
5229          * - I did not see what else could be done;
5230          * - it makes iop3xx happy.
5231          *
5232          * Feel free to adjust to your needs.
5233          */
5234         if (pdev->broken_parity_status)
5235                 pci_cmd &= ~PCI_COMMAND_PARITY;
5236         else
5237                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5238
5239         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5240
5241         pci_write_config_word(pdev, PCI_STATUS,
5242                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5243                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5244                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5245
5246         /* The infamous DAC f*ckup only happens at boot time */
5247         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5248                 void __iomem *ioaddr = tp->mmio_addr;
5249
5250                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5251                 tp->cp_cmd &= ~PCIDAC;
5252                 RTL_W16(CPlusCmd, tp->cp_cmd);
5253                 dev->features &= ~NETIF_F_HIGHDMA;
5254         }
5255
5256         rtl8169_hw_reset(tp);
5257
5258         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5259 }
5260
5261 struct rtl_txc {
5262         int packets;
5263         int bytes;
5264 };
5265
5266 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5267 {
5268         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5269         unsigned int dirty_tx, tx_left;
5270         struct rtl_txc txc = { 0, 0 };
5271
5272         dirty_tx = tp->dirty_tx;
5273         smp_rmb();
5274         tx_left = tp->cur_tx - dirty_tx;
5275
5276         while (tx_left > 0) {
5277                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5278                 struct ring_info *tx_skb = tp->tx_skb + entry;
5279                 u32 status;
5280
5281                 rmb();
5282                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5283                 if (status & DescOwn)
5284                         break;
5285
5286                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5287                                      tp->TxDescArray + entry);
5288                 if (status & LastFrag) {
5289                         struct sk_buff *skb = tx_skb->skb;
5290
5291                         txc.packets++;
5292                         txc.bytes += skb->len;
5293                         dev_kfree_skb(skb);
5294                         tx_skb->skb = NULL;
5295                 }
5296                 dirty_tx++;
5297                 tx_left--;
5298         }
5299
5300         u64_stats_update_begin(&tx_stats->syncp);
5301         tx_stats->packets += txc.packets;
5302         tx_stats->bytes += txc.bytes;
5303         u64_stats_update_end(&tx_stats->syncp);
5304
5305         netdev_completed_queue(dev, txc.packets, txc.bytes);
5306
5307         if (tp->dirty_tx != dirty_tx) {
5308                 tp->dirty_tx = dirty_tx;
5309                 /* Sync with rtl8169_start_xmit:
5310                  * - publish dirty_tx ring index (write barrier)
5311                  * - refresh cur_tx ring index and queue status (read barrier)
5312                  * May the current thread miss the stopped queue condition,
5313                  * a racing xmit thread can only have a right view of the
5314                  * ring status.
5315                  */
5316                 smp_mb();
5317                 if (netif_queue_stopped(dev) &&
5318                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5319                         netif_wake_queue(dev);
5320                 }
5321                 /*
5322                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5323                  * too close. Let's kick an extra TxPoll request when a burst
5324                  * of start_xmit activity is detected (if it is not detected,
5325                  * it is slow enough). -- FR
5326                  */
5327                 if (tp->cur_tx != dirty_tx) {
5328                         void __iomem *ioaddr = tp->mmio_addr;
5329
5330                         RTL_W8(TxPoll, NPQ);
5331                 }
5332         }
5333 }
5334
5335 static inline int rtl8169_fragmented_frame(u32 status)
5336 {
5337         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5338 }
5339
5340 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5341 {
5342         u32 status = opts1 & RxProtoMask;
5343
5344         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5345             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5346                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5347         else
5348                 skb_checksum_none_assert(skb);
5349 }
5350
5351 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5352                                            struct rtl8169_private *tp,
5353                                            int pkt_size,
5354                                            dma_addr_t addr)
5355 {
5356         struct sk_buff *skb;
5357         struct device *d = &tp->pci_dev->dev;
5358
5359         data = rtl8169_align(data);
5360         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5361         prefetch(data);
5362         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5363         if (skb)
5364                 memcpy(skb->data, data, pkt_size);
5365         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5366
5367         return skb;
5368 }
5369
5370 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5371 {
5372         unsigned int cur_rx, rx_left;
5373         unsigned int count;
5374
5375         cur_rx = tp->cur_rx;
5376         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5377         rx_left = min(rx_left, budget);
5378
5379         for (; rx_left > 0; rx_left--, cur_rx++) {
5380                 unsigned int entry = cur_rx % NUM_RX_DESC;
5381                 struct RxDesc *desc = tp->RxDescArray + entry;
5382                 u32 status;
5383
5384                 rmb();
5385                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5386
5387                 if (status & DescOwn)
5388                         break;
5389                 if (unlikely(status & RxRES)) {
5390                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5391                                    status);
5392                         dev->stats.rx_errors++;
5393                         if (status & (RxRWT | RxRUNT))
5394                                 dev->stats.rx_length_errors++;
5395                         if (status & RxCRC)
5396                                 dev->stats.rx_crc_errors++;
5397                         if (status & RxFOVF) {
5398                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5399                                 dev->stats.rx_fifo_errors++;
5400                         }
5401                         if ((status & (RxRUNT | RxCRC)) &&
5402                             !(status & (RxRWT | RxFOVF)) &&
5403                             (dev->features & NETIF_F_RXALL))
5404                                 goto process_pkt;
5405
5406                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5407                 } else {
5408                         struct sk_buff *skb;
5409                         dma_addr_t addr;
5410                         int pkt_size;
5411
5412 process_pkt:
5413                         addr = le64_to_cpu(desc->addr);
5414                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5415                                 pkt_size = (status & 0x00003fff) - 4;
5416                         else
5417                                 pkt_size = status & 0x00003fff;
5418
5419                         /*
5420                          * The driver does not support incoming fragmented
5421                          * frames. They are seen as a symptom of over-mtu
5422                          * sized frames.
5423                          */
5424                         if (unlikely(rtl8169_fragmented_frame(status))) {
5425                                 dev->stats.rx_dropped++;
5426                                 dev->stats.rx_length_errors++;
5427                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5428                                 continue;
5429                         }
5430
5431                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5432                                                   tp, pkt_size, addr);
5433                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5434                         if (!skb) {
5435                                 dev->stats.rx_dropped++;
5436                                 continue;
5437                         }
5438
5439                         rtl8169_rx_csum(skb, status);
5440                         skb_put(skb, pkt_size);
5441                         skb->protocol = eth_type_trans(skb, dev);
5442
5443                         rtl8169_rx_vlan_tag(desc, skb);
5444
5445                         napi_gro_receive(&tp->napi, skb);
5446
5447                         u64_stats_update_begin(&tp->rx_stats.syncp);
5448                         tp->rx_stats.packets++;
5449                         tp->rx_stats.bytes += pkt_size;
5450                         u64_stats_update_end(&tp->rx_stats.syncp);
5451                 }
5452
5453                 /* Work around for AMD plateform. */
5454                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5455                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5456                         desc->opts2 = 0;
5457                         cur_rx++;
5458                 }
5459         }
5460
5461         count = cur_rx - tp->cur_rx;
5462         tp->cur_rx = cur_rx;
5463
5464         tp->dirty_rx += count;
5465
5466         return count;
5467 }
5468
5469 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5470 {
5471         struct net_device *dev = dev_instance;
5472         struct rtl8169_private *tp = netdev_priv(dev);
5473         int handled = 0;
5474         u16 status;
5475
5476         status = rtl_get_events(tp);
5477         if (status && status != 0xffff) {
5478                 status &= RTL_EVENT_NAPI | tp->event_slow;
5479                 if (status) {
5480                         handled = 1;
5481
5482                         rtl_irq_disable(tp);
5483                         napi_schedule(&tp->napi);
5484                 }
5485         }
5486         return IRQ_RETVAL(handled);
5487 }
5488
5489 /*
5490  * Workqueue context.
5491  */
5492 static void rtl_slow_event_work(struct rtl8169_private *tp)
5493 {
5494         struct net_device *dev = tp->dev;
5495         u16 status;
5496
5497         status = rtl_get_events(tp) & tp->event_slow;
5498         rtl_ack_events(tp, status);
5499
5500         if (unlikely(status & RxFIFOOver)) {
5501                 switch (tp->mac_version) {
5502                 /* Work around for rx fifo overflow */
5503                 case RTL_GIGA_MAC_VER_11:
5504                         netif_stop_queue(dev);
5505                         /* XXX - Hack alert. See rtl_task(). */
5506                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5507                 default:
5508                         break;
5509                 }
5510         }
5511
5512         if (unlikely(status & SYSErr))
5513                 rtl8169_pcierr_interrupt(dev);
5514
5515         if (status & LinkChg)
5516                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5517
5518         napi_disable(&tp->napi);
5519         rtl_irq_disable(tp);
5520
5521         napi_enable(&tp->napi);
5522         napi_schedule(&tp->napi);
5523 }
5524
5525 static void rtl_task(struct work_struct *work)
5526 {
5527         static const struct {
5528                 int bitnr;
5529                 void (*action)(struct rtl8169_private *);
5530         } rtl_work[] = {
5531                 /* XXX - keep rtl_slow_event_work() as first element. */
5532                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5533                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5534                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5535         };
5536         struct rtl8169_private *tp =
5537                 container_of(work, struct rtl8169_private, wk.work);
5538         struct net_device *dev = tp->dev;
5539         int i;
5540
5541         rtl_lock_work(tp);
5542
5543         if (!netif_running(dev) ||
5544             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5545                 goto out_unlock;
5546
5547         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5548                 bool pending;
5549
5550                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5551                 if (pending)
5552                         rtl_work[i].action(tp);
5553         }
5554
5555 out_unlock:
5556         rtl_unlock_work(tp);
5557 }
5558
5559 static int rtl8169_poll(struct napi_struct *napi, int budget)
5560 {
5561         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5562         struct net_device *dev = tp->dev;
5563         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5564         int work_done= 0;
5565         u16 status;
5566
5567         status = rtl_get_events(tp);
5568         rtl_ack_events(tp, status & ~tp->event_slow);
5569
5570         if (status & RTL_EVENT_NAPI_RX)
5571                 work_done = rtl_rx(dev, tp, (u32) budget);
5572
5573         if (status & RTL_EVENT_NAPI_TX)
5574                 rtl_tx(dev, tp);
5575
5576         if (status & tp->event_slow) {
5577                 enable_mask &= ~tp->event_slow;
5578
5579                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5580         }
5581
5582         if (work_done < budget) {
5583                 napi_complete(napi);
5584
5585                 rtl_irq_enable(tp, enable_mask);
5586                 mmiowb();
5587         }
5588
5589         return work_done;
5590 }
5591
5592 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5593 {
5594         struct rtl8169_private *tp = netdev_priv(dev);
5595
5596         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5597                 return;
5598
5599         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5600         RTL_W32(RxMissed, 0);
5601 }
5602
5603 static void rtl8169_down(struct net_device *dev)
5604 {
5605         struct rtl8169_private *tp = netdev_priv(dev);
5606         void __iomem *ioaddr = tp->mmio_addr;
5607
5608         del_timer_sync(&tp->timer);
5609
5610         napi_disable(&tp->napi);
5611         netif_stop_queue(dev);
5612
5613         rtl8169_hw_reset(tp);
5614         /*
5615          * At this point device interrupts can not be enabled in any function,
5616          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5617          * and napi is disabled (rtl8169_poll).
5618          */
5619         rtl8169_rx_missed(dev, ioaddr);
5620
5621         /* Give a racing hard_start_xmit a few cycles to complete. */
5622         synchronize_sched();
5623
5624         rtl8169_tx_clear(tp);
5625
5626         rtl8169_rx_clear(tp);
5627
5628         rtl_pll_power_down(tp);
5629 }
5630
5631 static int rtl8169_close(struct net_device *dev)
5632 {
5633         struct rtl8169_private *tp = netdev_priv(dev);
5634         struct pci_dev *pdev = tp->pci_dev;
5635
5636         pm_runtime_get_sync(&pdev->dev);
5637
5638         /* Update counters before going down */
5639         rtl8169_update_counters(dev);
5640
5641         rtl_lock_work(tp);
5642         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5643
5644         rtl8169_down(dev);
5645         rtl_unlock_work(tp);
5646
5647         free_irq(pdev->irq, dev);
5648
5649         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5650                           tp->RxPhyAddr);
5651         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5652                           tp->TxPhyAddr);
5653         tp->TxDescArray = NULL;
5654         tp->RxDescArray = NULL;
5655
5656         pm_runtime_put_sync(&pdev->dev);
5657
5658         return 0;
5659 }
5660
5661 #ifdef CONFIG_NET_POLL_CONTROLLER
5662 static void rtl8169_netpoll(struct net_device *dev)
5663 {
5664         struct rtl8169_private *tp = netdev_priv(dev);
5665
5666         rtl8169_interrupt(tp->pci_dev->irq, dev);
5667 }
5668 #endif
5669
5670 static int rtl_open(struct net_device *dev)
5671 {
5672         struct rtl8169_private *tp = netdev_priv(dev);
5673         void __iomem *ioaddr = tp->mmio_addr;
5674         struct pci_dev *pdev = tp->pci_dev;
5675         int retval = -ENOMEM;
5676
5677         pm_runtime_get_sync(&pdev->dev);
5678
5679         /*
5680          * Rx and Tx desscriptors needs 256 bytes alignment.
5681          * dma_alloc_coherent provides more.
5682          */
5683         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5684                                              &tp->TxPhyAddr, GFP_KERNEL);
5685         if (!tp->TxDescArray)
5686                 goto err_pm_runtime_put;
5687
5688         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5689                                              &tp->RxPhyAddr, GFP_KERNEL);
5690         if (!tp->RxDescArray)
5691                 goto err_free_tx_0;
5692
5693         retval = rtl8169_init_ring(dev);
5694         if (retval < 0)
5695                 goto err_free_rx_1;
5696
5697         INIT_WORK(&tp->wk.work, rtl_task);
5698
5699         smp_mb();
5700
5701         rtl_request_firmware(tp);
5702
5703         retval = request_irq(pdev->irq, rtl8169_interrupt,
5704                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5705                              dev->name, dev);
5706         if (retval < 0)
5707                 goto err_release_fw_2;
5708
5709         rtl_lock_work(tp);
5710
5711         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5712
5713         napi_enable(&tp->napi);
5714
5715         rtl8169_init_phy(dev, tp);
5716
5717         __rtl8169_set_features(dev, dev->features);
5718
5719         rtl_pll_power_up(tp);
5720
5721         rtl_hw_start(dev);
5722
5723         netif_start_queue(dev);
5724
5725         rtl_unlock_work(tp);
5726
5727         tp->saved_wolopts = 0;
5728         tp->runtime_suspended = false;
5729         pm_runtime_put_noidle(&pdev->dev);
5730
5731         rtl8169_check_link_status(dev, tp, ioaddr);
5732 out:
5733         return retval;
5734
5735 err_release_fw_2:
5736         rtl_release_firmware(tp);
5737         rtl8169_rx_clear(tp);
5738 err_free_rx_1:
5739         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5740                           tp->RxPhyAddr);
5741         tp->RxDescArray = NULL;
5742 err_free_tx_0:
5743         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5744                           tp->TxPhyAddr);
5745         tp->TxDescArray = NULL;
5746 err_pm_runtime_put:
5747         pm_runtime_put_noidle(&pdev->dev);
5748         goto out;
5749 }
5750
5751 static struct rtnl_link_stats64 *
5752 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5753 {
5754         struct rtl8169_private *tp = netdev_priv(dev);
5755         void __iomem *ioaddr = tp->mmio_addr;
5756         unsigned int start;
5757
5758         if (netif_running(dev))
5759                 rtl8169_rx_missed(dev, ioaddr);
5760
5761         do {
5762                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5763                 stats->rx_packets = tp->rx_stats.packets;
5764                 stats->rx_bytes = tp->rx_stats.bytes;
5765         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5766
5767
5768         do {
5769                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5770                 stats->tx_packets = tp->tx_stats.packets;
5771                 stats->tx_bytes = tp->tx_stats.bytes;
5772         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5773
5774         stats->rx_dropped       = dev->stats.rx_dropped;
5775         stats->tx_dropped       = dev->stats.tx_dropped;
5776         stats->rx_length_errors = dev->stats.rx_length_errors;
5777         stats->rx_errors        = dev->stats.rx_errors;
5778         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5779         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5780         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5781
5782         return stats;
5783 }
5784
5785 static void rtl8169_net_suspend(struct net_device *dev)
5786 {
5787         struct rtl8169_private *tp = netdev_priv(dev);
5788
5789         if (!netif_running(dev))
5790                 return;
5791
5792         netif_device_detach(dev);
5793         netif_stop_queue(dev);
5794
5795         rtl_lock_work(tp);
5796         napi_disable(&tp->napi);
5797         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5798         rtl_unlock_work(tp);
5799
5800         rtl_pll_power_down(tp);
5801 }
5802
5803 #ifdef CONFIG_PM
5804
5805 static int rtl8169_suspend(struct device *device)
5806 {
5807         struct pci_dev *pdev = to_pci_dev(device);
5808         struct net_device *dev = pci_get_drvdata(pdev);
5809
5810         rtl8169_net_suspend(dev);
5811
5812         return 0;
5813 }
5814
5815 static void __rtl8169_resume(struct net_device *dev)
5816 {
5817         struct rtl8169_private *tp = netdev_priv(dev);
5818
5819         netif_device_attach(dev);
5820
5821         rtl_pll_power_up(tp);
5822
5823         rtl_lock_work(tp);
5824         napi_enable(&tp->napi);
5825         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5826         rtl_unlock_work(tp);
5827
5828         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5829 }
5830
5831 static int rtl8169_resume(struct device *device)
5832 {
5833         struct pci_dev *pdev = to_pci_dev(device);
5834         struct net_device *dev = pci_get_drvdata(pdev);
5835         struct rtl8169_private *tp = netdev_priv(dev);
5836
5837         rtl8169_init_phy(dev, tp);
5838
5839         if (netif_running(dev))
5840                 __rtl8169_resume(dev);
5841
5842         return 0;
5843 }
5844
5845 static int rtl8169_runtime_suspend(struct device *device)
5846 {
5847         struct pci_dev *pdev = to_pci_dev(device);
5848         struct net_device *dev = pci_get_drvdata(pdev);
5849         struct rtl8169_private *tp = netdev_priv(dev);
5850
5851         if (!tp->TxDescArray)
5852                 return 0;
5853
5854         rtl_lock_work(tp);
5855         tp->saved_wolopts = __rtl8169_get_wol(tp);
5856         __rtl8169_set_wol(tp, WAKE_ANY);
5857         tp->runtime_suspended = true;
5858         rtl_unlock_work(tp);
5859
5860         rtl8169_net_suspend(dev);
5861
5862         return 0;
5863 }
5864
5865 static int rtl8169_runtime_resume(struct device *device)
5866 {
5867         struct pci_dev *pdev = to_pci_dev(device);
5868         struct net_device *dev = pci_get_drvdata(pdev);
5869         struct rtl8169_private *tp = netdev_priv(dev);
5870
5871         if (!tp->TxDescArray)
5872                 return 0;
5873
5874         rtl_lock_work(tp);
5875         __rtl8169_set_wol(tp, tp->saved_wolopts);
5876         tp->saved_wolopts = 0;
5877         tp->runtime_suspended = false;
5878         rtl_unlock_work(tp);
5879
5880         rtl8169_init_phy(dev, tp);
5881
5882         __rtl8169_resume(dev);
5883
5884         return 0;
5885 }
5886
5887 static int rtl8169_runtime_idle(struct device *device)
5888 {
5889         struct pci_dev *pdev = to_pci_dev(device);
5890         struct net_device *dev = pci_get_drvdata(pdev);
5891         struct rtl8169_private *tp = netdev_priv(dev);
5892
5893         __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5894         return tp->TxDescArray ? -EBUSY : 0;
5895 }
5896
5897 static const struct dev_pm_ops rtl8169_pm_ops = {
5898         .suspend                = rtl8169_suspend,
5899         .resume                 = rtl8169_resume,
5900         .freeze                 = rtl8169_suspend,
5901         .thaw                   = rtl8169_resume,
5902         .poweroff               = rtl8169_suspend,
5903         .restore                = rtl8169_resume,
5904         .runtime_suspend        = rtl8169_runtime_suspend,
5905         .runtime_resume         = rtl8169_runtime_resume,
5906         .runtime_idle           = rtl8169_runtime_idle,
5907 };
5908
5909 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5910
5911 #else /* !CONFIG_PM */
5912
5913 #define RTL8169_PM_OPS  NULL
5914
5915 #endif /* !CONFIG_PM */
5916
5917 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5918 {
5919         void __iomem *ioaddr = tp->mmio_addr;
5920
5921         /* WoL fails with 8168b when the receiver is disabled. */
5922         switch (tp->mac_version) {
5923         case RTL_GIGA_MAC_VER_11:
5924         case RTL_GIGA_MAC_VER_12:
5925         case RTL_GIGA_MAC_VER_17:
5926                 pci_clear_master(tp->pci_dev);
5927
5928                 RTL_W8(ChipCmd, CmdRxEnb);
5929                 /* PCI commit */
5930                 RTL_R8(ChipCmd);
5931                 break;
5932         default:
5933                 break;
5934         }
5935 }
5936
5937 static void rtl_shutdown(struct pci_dev *pdev)
5938 {
5939         struct net_device *dev = pci_get_drvdata(pdev);
5940         struct rtl8169_private *tp = netdev_priv(dev);
5941         struct device *d = &pdev->dev;
5942
5943         pm_runtime_get_sync(d);
5944
5945         /* Get the device back to D0 state if it was runtime suspended. */
5946         if (tp->runtime_suspended)
5947                 pci_set_power_state(pdev, PCI_D0);
5948
5949         rtl8169_net_suspend(dev);
5950
5951         /* Restore original MAC address */
5952         rtl_rar_set(tp, dev->perm_addr);
5953
5954         rtl8169_hw_reset(tp);
5955
5956         /* Restore WOL flags if they were messed around with. */
5957         if (tp->saved_wolopts)
5958                 __rtl8169_set_wol(tp, tp->saved_wolopts);
5959
5960         if (system_state == SYSTEM_POWER_OFF) {
5961                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5962                         rtl_wol_suspend_quirk(tp);
5963                         rtl_wol_shutdown_quirk(tp);
5964                 }
5965
5966                 pci_wake_from_d3(pdev, true);
5967                 pci_set_power_state(pdev, PCI_D3hot);
5968         }
5969
5970         pm_runtime_put_noidle(d);
5971 }
5972
5973 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5974 {
5975         struct net_device *dev = pci_get_drvdata(pdev);
5976         struct rtl8169_private *tp = netdev_priv(dev);
5977
5978         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5979             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5980             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5981                 rtl8168_driver_stop(tp);
5982         }
5983
5984         cancel_work_sync(&tp->wk.work);
5985
5986         unregister_netdev(dev);
5987
5988         rtl_release_firmware(tp);
5989
5990         if (pci_dev_run_wake(pdev))
5991                 pm_runtime_get_noresume(&pdev->dev);
5992
5993         /* restore original MAC address */
5994         rtl_rar_set(tp, dev->perm_addr);
5995
5996         rtl_disable_msi(pdev, tp);
5997         rtl8169_release_board(pdev, dev, tp->mmio_addr);
5998         pci_set_drvdata(pdev, NULL);
5999 }
6000
6001 static const struct net_device_ops rtl_netdev_ops = {
6002         .ndo_open               = rtl_open,
6003         .ndo_stop               = rtl8169_close,
6004         .ndo_get_stats64        = rtl8169_get_stats64,
6005         .ndo_start_xmit         = rtl8169_start_xmit,
6006         .ndo_tx_timeout         = rtl8169_tx_timeout,
6007         .ndo_validate_addr      = eth_validate_addr,
6008         .ndo_change_mtu         = rtl8169_change_mtu,
6009         .ndo_fix_features       = rtl8169_fix_features,
6010         .ndo_set_features       = rtl8169_set_features,
6011         .ndo_set_mac_address    = rtl_set_mac_address,
6012         .ndo_do_ioctl           = rtl8169_ioctl,
6013         .ndo_set_rx_mode        = rtl_set_rx_mode,
6014 #ifdef CONFIG_NET_POLL_CONTROLLER
6015         .ndo_poll_controller    = rtl8169_netpoll,
6016 #endif
6017
6018 };
6019
6020 static const struct rtl_cfg_info {
6021         void (*hw_start)(struct net_device *);
6022         unsigned int region;
6023         unsigned int align;
6024         u16 event_slow;
6025         unsigned features;
6026         u8 default_ver;
6027 } rtl_cfg_infos [] = {
6028         [RTL_CFG_0] = {
6029                 .hw_start       = rtl_hw_start_8169,
6030                 .region         = 1,
6031                 .align          = 0,
6032                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6033                 .features       = RTL_FEATURE_GMII,
6034                 .default_ver    = RTL_GIGA_MAC_VER_01,
6035         },
6036         [RTL_CFG_1] = {
6037                 .hw_start       = rtl_hw_start_8168,
6038                 .region         = 2,
6039                 .align          = 8,
6040                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6041                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6042                 .default_ver    = RTL_GIGA_MAC_VER_11,
6043         },
6044         [RTL_CFG_2] = {
6045                 .hw_start       = rtl_hw_start_8101,
6046                 .region         = 2,
6047                 .align          = 8,
6048                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6049                                   PCSTimeout,
6050                 .features       = RTL_FEATURE_MSI,
6051                 .default_ver    = RTL_GIGA_MAC_VER_13,
6052         }
6053 };
6054
6055 /* Cfg9346_Unlock assumed. */
6056 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6057                             const struct rtl_cfg_info *cfg)
6058 {
6059         void __iomem *ioaddr = tp->mmio_addr;
6060         unsigned msi = 0;
6061         u8 cfg2;
6062
6063         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6064         if (cfg->features & RTL_FEATURE_MSI) {
6065                 if (pci_enable_msi(tp->pci_dev)) {
6066                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6067                 } else {
6068                         cfg2 |= MSIEnable;
6069                         msi = RTL_FEATURE_MSI;
6070                 }
6071         }
6072         RTL_W8(Config2, cfg2);
6073         return msi;
6074 }
6075
6076 static int __devinit
6077 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6078 {
6079         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6080         const unsigned int region = cfg->region;
6081         struct rtl8169_private *tp;
6082         struct mii_if_info *mii;
6083         struct net_device *dev;
6084         void __iomem *ioaddr;
6085         int chipset, i;
6086         int rc;
6087
6088         if (netif_msg_drv(&debug)) {
6089                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6090                        MODULENAME, RTL8169_VERSION);
6091         }
6092
6093         dev = alloc_etherdev(sizeof (*tp));
6094         if (!dev) {
6095                 rc = -ENOMEM;
6096                 goto out;
6097         }
6098
6099         SET_NETDEV_DEV(dev, &pdev->dev);
6100         dev->netdev_ops = &rtl_netdev_ops;
6101         tp = netdev_priv(dev);
6102         tp->dev = dev;
6103         tp->pci_dev = pdev;
6104         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6105
6106         mii = &tp->mii;
6107         mii->dev = dev;
6108         mii->mdio_read = rtl_mdio_read;
6109         mii->mdio_write = rtl_mdio_write;
6110         mii->phy_id_mask = 0x1f;
6111         mii->reg_num_mask = 0x1f;
6112         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6113
6114         /* disable ASPM completely as that cause random device stop working
6115          * problems as well as full system hangs for some PCIe devices users */
6116         if (aspm_disable) {
6117                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6118                                        PCIE_LINK_STATE_L1 |
6119                                        PCIE_LINK_STATE_CLKPM);
6120                 dprintk("ASPM disabled");
6121         }
6122
6123         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6124         rc = pci_enable_device(pdev);
6125         if (rc < 0) {
6126                 netif_err(tp, probe, dev, "enable failure\n");
6127                 goto err_out_free_dev_1;
6128         }
6129
6130         if (pci_set_mwi(pdev) < 0)
6131                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6132
6133         /* make sure PCI base addr 1 is MMIO */
6134         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6135                 netif_err(tp, probe, dev,
6136                           "region #%d not an MMIO resource, aborting\n",
6137                           region);
6138                 rc = -ENODEV;
6139                 goto err_out_mwi_2;
6140         }
6141
6142         /* check for weird/broken PCI region reporting */
6143         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6144                 netif_err(tp, probe, dev,
6145                           "Invalid PCI region size(s), aborting\n");
6146                 rc = -ENODEV;
6147                 goto err_out_mwi_2;
6148         }
6149
6150         rc = pci_request_regions(pdev, MODULENAME);
6151         if (rc < 0) {
6152                 netif_err(tp, probe, dev, "could not request regions\n");
6153                 goto err_out_mwi_2;
6154         }
6155
6156         tp->cp_cmd = RxChkSum;
6157
6158         if ((sizeof(dma_addr_t) > 4) &&
6159             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6160                 tp->cp_cmd |= PCIDAC;
6161                 dev->features |= NETIF_F_HIGHDMA;
6162         } else {
6163                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6164                 if (rc < 0) {
6165                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6166                         goto err_out_free_res_3;
6167                 }
6168         }
6169
6170         /* ioremap MMIO region */
6171         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6172         if (!ioaddr) {
6173                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6174                 rc = -EIO;
6175                 goto err_out_free_res_3;
6176         }
6177         tp->mmio_addr = ioaddr;
6178
6179         if (!pci_is_pcie(pdev))
6180                 netif_info(tp, probe, dev, "not PCI Express\n");
6181
6182         /* Identify chip attached to board */
6183         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6184
6185         rtl_init_rxcfg(tp);
6186
6187         rtl_irq_disable(tp);
6188
6189         rtl_hw_reset(tp);
6190
6191         rtl_ack_events(tp, 0xffff);
6192
6193         pci_set_master(pdev);
6194
6195         /*
6196          * Pretend we are using VLANs; This bypasses a nasty bug where
6197          * Interrupts stop flowing on high load on 8110SCd controllers.
6198          */
6199         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6200                 tp->cp_cmd |= RxVlan;
6201
6202         rtl_init_mdio_ops(tp);
6203         rtl_init_pll_power_ops(tp);
6204         rtl_init_jumbo_ops(tp);
6205
6206         rtl8169_print_mac_version(tp);
6207
6208         chipset = tp->mac_version;
6209         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6210
6211         RTL_W8(Cfg9346, Cfg9346_Unlock);
6212         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6213         RTL_W8(Config3, 0);
6214         RTL_W8(Config5, PMEStatus);
6215         tp->features |= rtl_try_msi(tp, cfg);
6216         RTL_W8(Cfg9346, Cfg9346_Lock);
6217
6218         if (rtl_tbi_enabled(tp)) {
6219                 tp->set_speed = rtl8169_set_speed_tbi;
6220                 tp->get_settings = rtl8169_gset_tbi;
6221                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6222                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6223                 tp->link_ok = rtl8169_tbi_link_ok;
6224                 tp->do_ioctl = rtl_tbi_ioctl;
6225         } else {
6226                 tp->set_speed = rtl8169_set_speed_xmii;
6227                 tp->get_settings = rtl8169_gset_xmii;
6228                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6229                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6230                 tp->link_ok = rtl8169_xmii_link_ok;
6231                 tp->do_ioctl = rtl_xmii_ioctl;
6232         }
6233
6234         mutex_init(&tp->wk.mutex);
6235
6236         /* Get MAC address */
6237         for (i = 0; i < ETH_ALEN; i++)
6238                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6239         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6240
6241         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6242         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6243
6244         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6245
6246         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6247          * properly for all devices */
6248         dev->features |= NETIF_F_RXCSUM |
6249                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6250
6251         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6252                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6253         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6254                 NETIF_F_HIGHDMA;
6255
6256         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6257                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6258                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6259
6260         dev->hw_features |= NETIF_F_RXALL;
6261         dev->hw_features |= NETIF_F_RXFCS;
6262
6263         tp->hw_start = cfg->hw_start;
6264         tp->event_slow = cfg->event_slow;
6265
6266         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6267                 ~(RxBOVF | RxFOVF) : ~0;
6268
6269         init_timer(&tp->timer);
6270         tp->timer.data = (unsigned long) dev;
6271         tp->timer.function = rtl8169_phy_timer;
6272
6273         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6274
6275         rc = register_netdev(dev);
6276         if (rc < 0)
6277                 goto err_out_msi_4;
6278
6279         pci_set_drvdata(pdev, dev);
6280
6281         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6282                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6283                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6284         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6285                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6286                            "tx checksumming: %s]\n",
6287                            rtl_chip_infos[chipset].jumbo_max,
6288                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6289         }
6290
6291         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6292             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6293             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6294                 rtl8168_driver_start(tp);
6295         }
6296
6297         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6298
6299         if (pci_dev_run_wake(pdev))
6300                 pm_runtime_put_noidle(&pdev->dev);
6301
6302         netif_carrier_off(dev);
6303
6304 out:
6305         return rc;
6306
6307 err_out_msi_4:
6308         rtl_disable_msi(pdev, tp);
6309         iounmap(ioaddr);
6310 err_out_free_res_3:
6311         pci_release_regions(pdev);
6312 err_out_mwi_2:
6313         pci_clear_mwi(pdev);
6314         pci_disable_device(pdev);
6315 err_out_free_dev_1:
6316         free_netdev(dev);
6317         goto out;
6318 }
6319
6320 static struct pci_driver rtl8169_pci_driver = {
6321         .name           = MODULENAME,
6322         .id_table       = rtl8169_pci_tbl,
6323         .probe          = rtl_init_one,
6324         .remove         = __devexit_p(rtl_remove_one),
6325         .shutdown       = rtl_shutdown,
6326         .driver.pm      = RTL8169_PM_OPS,
6327 };
6328
6329 static int __init rtl8169_init_module(void)
6330 {
6331         return pci_register_driver(&rtl8169_pci_driver);
6332 }
6333
6334 static void __exit rtl8169_cleanup_module(void)
6335 {
6336         pci_unregister_driver(&rtl8169_pci_driver);
6337 }
6338
6339 module_init(rtl8169_init_module);
6340 module_exit(rtl8169_cleanup_module);